From patchwork Fri Oct 2 23:51:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 267411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67B51C35257 for ; Fri, 2 Oct 2020 23:51:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1FCD2206A2 for ; Fri, 2 Oct 2020 23:51:33 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="G/pkBZgD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725379AbgJBXvc (ORCPT ); Fri, 2 Oct 2020 19:51:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725283AbgJBXvc (ORCPT ); Fri, 2 Oct 2020 19:51:32 -0400 Received: from mail-pj1-x1041.google.com (mail-pj1-x1041.google.com [IPv6:2607:f8b0:4864:20::1041]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C4C3C0613D0; Fri, 2 Oct 2020 16:51:32 -0700 (PDT) Received: by mail-pj1-x1041.google.com with SMTP id u3so1862844pjr.3; Fri, 02 Oct 2020 16:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=mEj/Snh9xo7eeSA1pUo3LqgpRgSxgfcItY6huejtGkA=; b=G/pkBZgDDYyonMcDNpJmvmCiGpfDuTfA6YacbZEwogdnKU4af9H4SVk9JN2ekfbnqG nrPYaRAMPtxCcogjqBPO6NZfzZlw9MhGtD94s2+NzpiGDjUvyTxmGIbVEItQ0zYoo91j wroR+L276rpEinKqVOaRn8craepoDCJ+wakQWkt93uMb+uRYASh67bkVwheC+cUClF+I mSp1S+vPyy5LXC/T7UopbYPvr2QSJ1mtlmkRsZMeVcvhqGfsA5qj5JxTGZd4uJpXkc+N DlgOPMvKGRhZDD3Qr3KscqhicZ/BSa8HtiDE6b0FjBc94rdnHAMHL9CUYq41Mu4IJ3Gh zVnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=mEj/Snh9xo7eeSA1pUo3LqgpRgSxgfcItY6huejtGkA=; b=YhDc4Rp7ZT3xMv2OVgxgJLHVh8OnJ6jjDR6aA/Mkj+zoL42+OzKQnW6szFHbtsG96a p3ygdpHgI5Fb9mkOuN+WnJCE/b16uXzcby9M4enKY7jzy55KPfmA0HD3OUFI1EVHJseB YafCbdKvo168+57KWh95PIT8hXSwfjQ9f2EgS2D6U/R3WS6aPANnWEUFF+Gf/k3CaVs8 6KnzLMVRSB1kZQCsUslRG9t7r5TvU6SDdGS3wy9Nzq5+Fen6+7T5ckA8SjRU0eflOlva 81QAeOu8dRnn97EUaEJ0bL0zXzsUDa8sWnJzmqqAoB1ziL75hj1/vjqBeHjKC0d5WwKd lmng== X-Gm-Message-State: AOAM532V3z+Jm2DlCCnQzyfNQXCKSC6MG5g3H4nRGVBycCNK81JTDE8k YgRYwxHhqD43Bj1FdfJgU4xxniNUWY2jMg== X-Google-Smtp-Source: ABdhPJxgc2PQYqSvHorH5Vu4JQvD1WFCARVRLhAnxKrw73i41wb+Rq0DR2PH8tqlvKgtAhgNgi/7Ew== X-Received: by 2002:a17:90b:104f:: with SMTP id gq15mr5094263pjb.215.1601682692186; Fri, 02 Oct 2020 16:51:32 -0700 (PDT) Received: from syed.domain.name ([103.201.127.75]) by smtp.gmail.com with ESMTPSA id g4sm2831302pgj.15.2020.10.02.16.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Oct 2020 16:51:31 -0700 (PDT) Date: Sat, 3 Oct 2020 05:21:19 +0530 From: Syed Nayyar Waris To: linus.walleij@linaro.org, akpm@linux-foundation.org Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, rrichter@marvell.com, bgolaszewski@baylibre.com, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 3/4] gpio: thunderx: Utilize for_each_set_clump macro Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch reimplements the thunderx_gpio_set_multiple function in drivers/gpio/gpio-thunderx.c to use the new for_each_set_clump macro. Instead of looping for each bank in thunderx_gpio_set_multiple function, now we can skip bank which is not set and save cycles. Cc: Robert Richter Cc: Bartosz Golaszewski Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v10: - No change. Changes in v9: - No change. Changes in v8: - No change. Changes in v7: - No change. Changes in v6: - No change. Changes in v5: - No change. Changes in v4: - Minor change: Inline value '64' in code for better code readability. Changes in v3: - Change datatype of some variables from u64 to unsigned long in function thunderx_gpio_set_multiple. Changes in v2: - No change. drivers/gpio/gpio-thunderx.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-thunderx.c b/drivers/gpio/gpio-thunderx.c index 9f66deab46ea..58c9bb25a377 100644 --- a/drivers/gpio/gpio-thunderx.c +++ b/drivers/gpio/gpio-thunderx.c @@ -275,12 +275,15 @@ static void thunderx_gpio_set_multiple(struct gpio_chip *chip, unsigned long *bits) { int bank; - u64 set_bits, clear_bits; + unsigned long set_bits, clear_bits, gpio_mask; + unsigned long offset; + struct thunderx_gpio *txgpio = gpiochip_get_data(chip); - for (bank = 0; bank <= chip->ngpio / 64; bank++) { - set_bits = bits[bank] & mask[bank]; - clear_bits = ~bits[bank] & mask[bank]; + for_each_set_clump(offset, gpio_mask, mask, chip->ngpio, 64) { + bank = offset / 64; + set_bits = bits[bank] & gpio_mask; + clear_bits = ~bits[bank] & gpio_mask; writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR); } From patchwork Fri Oct 2 23:52:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Syed Nayyar Waris X-Patchwork-Id: 285649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A9F1C35257 for ; Fri, 2 Oct 2020 23:52:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DD384206B7 for ; Fri, 2 Oct 2020 23:52:42 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Fri, 02 Oct 2020 16:52:41 -0700 (PDT) Date: Sat, 3 Oct 2020 05:22:28 +0530 From: Syed Nayyar Waris To: linus.walleij@linaro.org, akpm@linux-foundation.org Cc: andriy.shevchenko@linux.intel.com, vilhelm.gray@gmail.com, bgolaszewski@baylibre.com, michal.simek@xilinx.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v10 4/4] gpio: xilinx: Utilize generic bitmap_get_value and _set_value Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This patch reimplements the xgpio_set_multiple function in drivers/gpio/gpio-xilinx.c to use the new generic functions: bitmap_get_value and bitmap_set_value. The code is now simpler to read and understand. Moreover, instead of looping for each bit in xgpio_set_multiple function, now we can check each channel at a time and save cycles. Cc: Bartosz Golaszewski Cc: Michal Simek Signed-off-by: Syed Nayyar Waris Signed-off-by: William Breathitt Gray --- Changes in v10: - No change. Changes in v9: - Remove looping of 'for_each_set_clump' and instead process two halves of a 64-bit bitmap separately or individually. Use normal spin_lock call for second inner lock. And take the spin_lock_init call outside the 'if' condition in the 'probe' function of driver. Changes in v8: - No change. Changes in v7: - No change. Changes in v6: - No change. Changes in v5: - Minor change: Inline values '32' and '64' in code for better code readability. Changes in v4: - Minor change: Inline values '32' and '64' in code for better code readability. Changes in v3: - No change. Changes in v2: - No change drivers/gpio/gpio-xilinx.c | 66 +++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c index 67f9f82e0db0..48393d06fb55 100644 --- a/drivers/gpio/gpio-xilinx.c +++ b/drivers/gpio/gpio-xilinx.c @@ -136,39 +136,39 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits) { - unsigned long flags; + unsigned long flag; struct xgpio_instance *chip = gpiochip_get_data(gc); - int index = xgpio_index(chip, 0); - int offset, i; - - spin_lock_irqsave(&chip->gpio_lock[index], flags); - - /* Write to GPIO signals */ - for (i = 0; i < gc->ngpio; i++) { - if (*mask == 0) - break; - /* Once finished with an index write it out to the register */ - if (index != xgpio_index(chip, i)) { - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, - chip->gpio_state[index]); - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); - index = xgpio_index(chip, i); - spin_lock_irqsave(&chip->gpio_lock[index], flags); - } - if (__test_and_clear_bit(i, mask)) { - offset = xgpio_offset(chip, i); - if (test_bit(i, bits)) - chip->gpio_state[index] |= BIT(offset); - else - chip->gpio_state[index] &= ~BIT(offset); - } - } - - xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + - index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]); - - spin_unlock_irqrestore(&chip->gpio_lock[index], flags); + u32 *const state = chip->gpio_state; + unsigned int *const width = chip->gpio_width; + + DECLARE_BITMAP(old, 64); + DECLARE_BITMAP(new, 64); + DECLARE_BITMAP(changed, 64); + + spin_lock_irqsave(&chip->gpio_lock[0], flag); + spin_lock(&chip->gpio_lock[1]); + + bitmap_set_value(old, state[0], 0, width[0]); + bitmap_set_value(old, state[1], width[0], width[1]); + bitmap_replace(new, old, bits, mask, gc->ngpio); + + bitmap_set_value(old, state[0], 0, 32); + bitmap_set_value(old, state[1], 32, 32); + state[0] = bitmap_get_value(new, 0, width[0]); + state[1] = bitmap_get_value(new, width[0], width[1]); + bitmap_set_value(new, state[0], 0, 32); + bitmap_set_value(new, state[1], 32, 32); + bitmap_xor(changed, old, new, 64); + + if (((u32 *)changed)[0]) + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET, + state[0]); + if (((u32 *)changed)[1]) + xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET + + XGPIO_CHANNEL_OFFSET, state[1]); + + spin_unlock(&chip->gpio_lock[1]); + spin_unlock_irqrestore(&chip->gpio_lock[0], flag); } /** @@ -292,6 +292,7 @@ static int xgpio_probe(struct platform_device *pdev) chip->gpio_width[0] = 32; spin_lock_init(&chip->gpio_lock[0]); + spin_lock_init(&chip->gpio_lock[1]); if (of_property_read_u32(np, "xlnx,is-dual", &is_dual)) is_dual = 0; @@ -314,7 +315,6 @@ static int xgpio_probe(struct platform_device *pdev) &chip->gpio_width[1])) chip->gpio_width[1] = 32; - spin_lock_init(&chip->gpio_lock[1]); } chip->gc.base = -1;