From patchwork Fri Oct 27 13:29:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 117352 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp774772qgn; Fri, 27 Oct 2017 06:29:51 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SFzclGxsKgptu/Lr+h1auxRvz1+sFq3b06Wwmn8K7sJjbG+ELWPbCugY9VvFSy1za1HZ3+ X-Received: by 10.98.220.220 with SMTP id c89mr479179pfl.167.1509110991356; Fri, 27 Oct 2017 06:29:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509110991; cv=none; d=google.com; s=arc-20160816; b=JTScudvA/KPiGHFr3amfkJxWUnl4GEM5gyNY3oiOnE1GsPJN5g7UYk4AKkrEVDEAhY BFYYAaxxWDA2mDjKvtM2q9OBqYVyhOwoNBf70bCJ2KxIa1WIfu6zMiz/YLR0bKp2txhs +xytu/xv/P6ecGcXyz4HlROYPMg9noBilGJaOm1v++RlZwKt26WJUYBh8h4qvfZamuIH 2YVNEVvrXbjKJuCmv4CxZjMNPigPLPtkQRjd0h8ZE3QYOB4KYPdMSZs1LIR0Fp/ZEUp6 oQeactGHPNJ9vh5V7uRPwMixM/bS+WDg/PnIkZnoGxp6Hqksv0PVR6VzQ8o8sHLOgfQA GUlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:cc:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=sbrJZxLeh6fmAaa9HXzBPf5EXys30HWq7tpIeQeq0w8=; b=bRhgF9wGgvH1QbciU8AF7O/LyaWUVsWBUJUYxWN3sSmE+JkU6EUOWjLis9vWIR2yN3 iy/R2u3tUaPpljZsZZnpZisWCUyx0VozeY9vD2pYARG0u4gy5thrxZE9/C54yiXA5+HF HVJYy9KZcF2ueRCfTBqbGDYPC1/UbpcamMbG5RqbaSROBgpaJxovJRVCxrQaXV1Szv5x uF25/zzt2+C2/byJpA/JPbLVQZVwvEOpQS+AHiaiI6I4OPxsJZq4Q//aceap+rO/k+Dn q0BbgAP7qqJ/rv6HM2utt1OGvpTiL8rcc99yklO8R+8/ZvmhcPEZALwegIi8Uef+FecR NAEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=P64U3Gu+; spf=pass (google.com: domain of gcc-patches-return-465348-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465348-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id d63si4423951pld.450.2017.10.27.06.29.51 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Oct 2017 06:29:51 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-465348-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=P64U3Gu+; spf=pass (google.com: domain of gcc-patches-return-465348-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465348-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; q=dns; s=default; b=md87b/M3oi1xiF5r C9oYeiLAvGWNuu57496uFp4PbHFmYnlhWkWAGmU9fZ/u+nsv2S5d2bV+KQLYOr9Q wcHbN8j+a0prtgjauD6bV8Fis16CKB1xvgZ4WwIs+T+j1XbHpD9yYazkXW/BAnnq dHIdA/g+1IXd1yO/4WEq4qAqFVg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:references:date:in-reply-to:message-id :mime-version:content-type; s=default; bh=EhAs8eGIiu7YZ3opZAGowm VBpS4=; b=P64U3Gu+jKrTkwHwhGBmhCIxwkrb/LHsVPVlZmTfON7HeCiw7885nE Na6A+g1JDvFnMA7siVSrTW1bkUVCYn2mFzXPj86rU2lIkT5a5lBIsquNlgXmrl98 Gh4TIMXyRwCmDS40dey8JBQ7vkcdwOsjQsRXMi9pUU6HjGm5H49WA= Received: (qmail 50692 invoked by alias); 27 Oct 2017 13:29:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 50682 invoked by uid 89); 27 Oct 2017 13:29:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f43.google.com Received: from mail-wm0-f43.google.com (HELO mail-wm0-f43.google.com) (74.125.82.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Oct 2017 13:29:35 +0000 Received: by mail-wm0-f43.google.com with SMTP id z3so3818646wme.5 for ; Fri, 27 Oct 2017 06:29:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:cc:subject:references :date:in-reply-to:message-id:user-agent:mime-version; bh=sbrJZxLeh6fmAaa9HXzBPf5EXys30HWq7tpIeQeq0w8=; b=hTXpVF/kcqIIW1MMVGBPXMn1wRjWwIeaNu0LvtPJoMr6VUP0apStwYQVZEw91r0zOu 4k1bhn7P228Z8tfdx+/1ctesPB3txlq6+NEw2sanhprfDDmXLMTH9VGlVXR6rxGexoHp g+2aU0YxlPOC/ZWOcLOhE/cWd9uxvDWqqLs3P1tcmXbf6tcd9WkDDMeG3SU+a3uQ2XoC CDjAOZB4nnZJd8yGiTtFpkK9+T5HMj6YeOvCwz9q+W7+xNBVXypDLHWk6tOjCNqlfXig uQ5iuY2Bw1cKgtB/0cxw3Tw1HMxpq/erNDI0LWQeMYFA0i7W7dLPkiMUSiXU32F8aS3z jmkg== X-Gm-Message-State: AMCzsaUS9QMgbE7iMHgI4RDCX8z2z5rT/3C2Ysgq/W0xzNunM7tvRcZ7 BJ0UnvDStuN7w2hYEuMCLFUJxQ== X-Received: by 10.28.229.212 with SMTP id c203mr477059wmh.57.1509110972982; Fri, 27 Oct 2017 06:29:32 -0700 (PDT) Received: from localhost (188.29.164.51.threembb.co.uk. [188.29.164.51]) by smtp.gmail.com with ESMTPSA id n14sm9460294wrg.38.2017.10.27.06.29.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Oct 2017 06:29:32 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com, richard.sandiford@linaro.org Cc: richard.earnshaw@arm.com, james.greenhalgh@arm.com, marcus.shawcroft@arm.com Subject: [09/nn] [AArch64] Pass number of units to aarch64_expand_vec_perm(_const) References: <873764d8y3.fsf@linaro.org> Date: Fri, 27 Oct 2017 14:29:30 +0100 In-Reply-To: <873764d8y3.fsf@linaro.org> (Richard Sandiford's message of "Fri, 27 Oct 2017 14:19:48 +0100") Message-ID: <87wp3gafd1.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 This patch passes the number of units to aarch64_expand_vec_perm and aarch64_expand_vec_perm_const, which avoids a to_constant () once GET_MODE_NUNITS is variable. 2017-10-27 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm) (aarch64_expand_vec_perm_const): Take the number of units too. * config/aarch64/aarch64.c (aarch64_expand_vec_perm) (aarch64_expand_vec_perm_const): Likewise. * config/aarch64/aarch64-simd.md (vec_perm_const) (vec_perm): Update accordingly. Reviewed-by: James Greenhalgh Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:07.203885483 +0100 +++ gcc/config/aarch64/aarch64-protos.h 2017-10-27 14:12:11.042239887 +0100 @@ -484,11 +484,11 @@ tree aarch64_builtin_rsqrt (unsigned int tree aarch64_builtin_vectorized_function (unsigned int, tree, tree); extern void aarch64_split_combinev16qi (rtx operands[3]); -extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); +extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int); extern bool aarch64_madd_needs_nop (rtx_insn *); extern void aarch64_final_prescan_insn (rtx_insn *); extern bool -aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); +aarch64_expand_vec_perm_const (rtx, rtx, rtx, rtx, unsigned int); void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); int aarch64_ccmp_mode_to_code (machine_mode mode); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-10-27 14:12:07.205742901 +0100 +++ gcc/config/aarch64/aarch64.c 2017-10-27 14:12:11.045026014 +0100 @@ -13488,11 +13488,14 @@ aarch64_expand_vec_perm_1 (rtx target, r } } +/* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL. + NELT is the number of elements in the vector. */ + void -aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel) +aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel, + unsigned int nelt) { machine_mode vmode = GET_MODE (target); - unsigned int nelt = GET_MODE_NUNITS (vmode); bool one_vector_p = rtx_equal_p (op0, op1); rtx mask; @@ -13848,13 +13851,15 @@ aarch64_expand_vec_perm_const_1 (struct return false; } -/* Expand a vec_perm_const pattern. */ +/* Expand a vec_perm_const pattern with the operands given by TARGET, + OP0, OP1 and SEL. NELT is the number of elements in the vector. */ bool -aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) +aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel, + unsigned int nelt) { struct expand_vec_perm_d d; - int i, nelt, which; + unsigned int i, which; d.target = target; d.op0 = op0; @@ -13864,12 +13869,11 @@ aarch64_expand_vec_perm_const (rtx targe gcc_assert (VECTOR_MODE_P (d.vmode)); d.testing_p = false; - nelt = GET_MODE_NUNITS (d.vmode); d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { rtx e = XVECEXP (sel, 0, i); - int ei = INTVAL (e) & (2 * nelt - 1); + unsigned int ei = INTVAL (e) & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); d.perm.quick_push (ei); } Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:07.203885483 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-10-27 14:12:11.043168596 +0100 @@ -5238,7 +5238,7 @@ (define_expand "vec_perm_const" "TARGET_SIMD" { if (aarch64_expand_vec_perm_const (operands[0], operands[1], - operands[2], operands[3])) + operands[2], operands[3], )) DONE; else FAIL; @@ -5252,7 +5252,7 @@ (define_expand "vec_perm" "TARGET_SIMD" { aarch64_expand_vec_perm (operands[0], operands[1], - operands[2], operands[3]); + operands[2], operands[3], ); DONE; })