From patchwork Tue Oct 31 13:11:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 117629 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3904427qgn; Tue, 31 Oct 2017 06:17:13 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Tn54j4EuWI6Qh6E9w7T7T+3FFrh3JOoknwxdhCCLqm1+OBQQInjm8DxX7NmUJk/mlRlxiX X-Received: by 10.37.37.75 with SMTP id l72mr1108478ybl.39.1509455833667; Tue, 31 Oct 2017 06:17:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509455833; cv=none; d=google.com; s=arc-20160816; b=eyM/C1OBH/zZCpBnnV01lWX7H5CuXtPJxDPuL07MhgDjY9TVIbhVDv75HViVrhInRy JH/PK6aQS0NBCtBgfX9csUSVe2PWlDMmA4dWpFTQOI3oNU2LtojpWK+D0M7tiGVjtRJt Y4uVEZ1ZTEfREQkx2zWZDM+jTWaRxu9Y0qncJAKbLWIoh7o5sG2OAFZ3x6Q8thZtj4By +5Nmd+RCirXmMfhTkgA9s4wvOh2Y4YPM2EegDZvcMMV0prdCJuBd5sGWIbLtV7+Kju2v /YI59xdJLzcjx5kvMXEcReVEaOu9RTHN8MxeA/vB738OYki8u2HHMWMBalfRaEudAcLr 3CsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=S7B5Xn3HawRBwN3Y4CHwTyNibTe7mWKwy8Lupk7mhpE=; b=EtTIlRD1uiBiDERvC0EbcrX8+ytARxXo8fyjDBGiakb3sotCYE+p6fSTvNNOquLecD 1lWZYGoYLDTaXAo0YtGZ8u/wAk8bOPsudjAJrEXu/QtJncCdIKVZOgpMseRRfmYyIOQX KLYkKTI+vn3hY2M3WvxA5g9HvdjrGey0gL59stLlxKVbGLZpPrOxUFlCY9PbsrHEfS5i L6pLxAvoOiAEnycOZ9Z4MKSnLg3oFBYVdzQw8zyZvAug5c89sOiVRuSYmiC8Hs45+rPe mLwee7hjC/FJDnXqkKe+swV731gDLs9Cb3+2KrqyyekgxcXNCkzynm+4U4w5UfYXpaEj OM8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s7si383588ywd.729.2017.10.31.06.17.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 31 Oct 2017 06:17:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WPp-0005nq-68 for patch@linaro.org; Tue, 31 Oct 2017 09:17:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WKB-0001sq-3B for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK4-0006zu-SS for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK4-0006em-K6 for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJr-0007Gi-Rd for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:25 +0000 Message-Id: <1509455489-14101-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Stefano Stabellini WFI/E are often, but not always, 4 bytes long. When they are, we need to set ARM_EL_IL_SHIFT in the syndrome register. Pass the instruction length to HELPER(wfi), use it to decrement pc appropriately and to pass an is_16bit flag to syn_wfx, which sets ARM_EL_IL_SHIFT if needed. Set dc->insn in both arm_tr_translate_insn and thumb_tr_translate_insn. Signed-off-by: Stefano Stabellini Message-id: alpine.DEB.2.10.1710241055160.574@sstabellini-ThinkPad-X260 [PMM: move setting of dc->insn for Thumb so it is correct for 32 bit insns] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/internals.h | 3 ++- target/arm/op_helper.c | 7 ++++--- target/arm/psci.c | 2 +- target/arm/translate-a64.c | 7 ++++++- target/arm/translate.c | 10 +++++++++- 6 files changed, 23 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.h b/target/arm/helper.h index 2cf6f74..439d228 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -48,7 +48,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_1(setend, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) diff --git a/target/arm/internals.h b/target/arm/internals.h index 43106a2..d9cc75e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -428,9 +428,10 @@ static inline uint32_t syn_breakpoint(int same_el) | ARM_EL_IL | 0x22; } -static inline uint32_t syn_wfx(int cv, int cond, int ti) +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) { return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | (cv << 24) | (cond << 20) | ti; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 138d0df..a40a84a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -463,7 +463,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe) return 0; } -void HELPER(wfi)(CPUARMState *env) +void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { CPUState *cs = CPU(arm_env_get_cpu(env)); int target_el = check_wfx_trap(env, false); @@ -476,8 +476,9 @@ void HELPER(wfi)(CPUARMState *env) } if (target_el) { - env->pc -= 4; - raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el); + env->pc -= insn_len; + raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len == 2), + target_el); } cs->exception_index = EXCP_HLT; diff --git a/target/arm/psci.c b/target/arm/psci.c index fc34b26..eb7b88e 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -189,7 +189,7 @@ void arm_handle_psci_call(ARMCPU *cpu) } else { env->regs[0] = 0; } - helper_wfi(env); + helper_wfi(env, 4); break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e98fbcf..caca05a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11400,17 +11400,22 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_WFI: + { /* This is a special case because we don't want to just halt the CPU * if trying to debug across a WFI. */ + TCGv_i32 tmp = tcg_const_i32(4); + gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); + gen_helper_wfi(cpu_env, tmp); + tcg_temp_free_i32(tmp); /* The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anyway. */ tcg_gen_exit_tb(0); break; } + } } /* Functions above can change dc->pc, so re-align db->pc_next */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 6ba4ae9..df57dbb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12125,6 +12125,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->insn = insn; dc->pc += 4; disas_arm_insn(dc, insn); @@ -12200,6 +12201,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) insn = insn << 16 | insn2; dc->pc += 2; } + dc->insn = insn; if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { uint32_t cond = dc->condexec_cond; @@ -12326,12 +12328,18 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env); + { + TCGv_i32 tmp = tcg_const_i32((dc->thumb && + !(dc->insn & (1U << 31))) ? 2 : 4); + + gen_helper_wfi(cpu_env, tmp); + tcg_temp_free_i32(tmp); /* The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anyway. */ tcg_gen_exit_tb(0); break; + } case DISAS_WFE: gen_helper_wfe(cpu_env); break; From patchwork Tue Oct 31 13:11:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 117630 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3905706qgn; Tue, 31 Oct 2017 06:18:23 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Q5HRzm8UrmEOG2UwyFXJ2G99t6ykeuyTNC09utHWKTrPb7oJFvWEaqtBfVaCqrcXQ08PjC X-Received: by 10.13.201.66 with SMTP id l63mr1220949ywd.83.1509455903549; Tue, 31 Oct 2017 06:18:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509455903; cv=none; d=google.com; s=arc-20160816; b=e/+4S1S2Ids0Lxfg6UO1kvx5v4jO3U0ykiAXB1SXOFDqdCL+vVoNG3ClxGNiKl+Kr8 7Pu6sCH7eGkpZPxUWucPYDGS9YkYb+YLB52jtu5m4DyWR1rPDMdmB2Qay7gCblxvmxqo oZPR96jNquhXZXEzkwuwR1RpEdYlrp1s8GViJsbyWhOUusPjl7+6ayRJNRBJdBTijH4I T08DIGV3njStbPeLscTnFiEVM5HMD69P2vQJ+JNJJnOYHVYYkPLS1eFywGD9BuLNvHYj 65YMa1VZzABltjwJzFFj+Z8LHjWqVhcqNpnfRD7V5LkaScWyjP7f3sOZpda35IXdI7p5 AXMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=bWz3dnRCrrnZhmFAuB0OGw6ntkqJ4jjviVGSvGmbnJg=; b=eNL+Y9PqkQE7b7oNjp85if96mrJX6y2NmbhYrjltjhKlCE6LEC2yWWfdzhXI8mPeSL Tlh8rXmG2AqWz3r7O/zkO/G7Glx19H+k7+LZtifadi9PRp7wC1yMwWAs5Uv+3/TroCaJ k7fE7phyD0SgXOEyKabu3JGrZTBw1tr6AXGZ9P610GaZ24zchazpaddR6r1ZqAClv7Jn /e8WMIJ9mMemo1gD6/hgibPrw/gnAofjhoQTQXTu3k30qgs9sDN8aAuoeQ43gUWacC4N WumlB0vbI/GEwblDfeoq7ViChkFqIxtkAFV2b86EE/P9VvZYpJAXi1p3GhaBLPG1BmiB Yipg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Specify the number of CPUs that can run on ZynqMP. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..e2d15a1 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -240,6 +240,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; + mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; } static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { From patchwork Tue Oct 31 13:11:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 117621 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3897546qgn; Tue, 31 Oct 2017 06:11:40 -0700 (PDT) X-Google-Smtp-Source: ABhQp+ScAb8CxhDbzcQRr3hOGpOGN8gvjZD7Va0cj7yZU3AeWTdKaa4WkFlaN+K2tpiCC6BZrfrK X-Received: by 10.37.176.165 with SMTP id f37mr1224156ybj.80.1509455500128; Tue, 31 Oct 2017 06:11:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509455500; cv=none; d=google.com; s=arc-20160816; b=LkzX8DpML1oiEF8hB7hhTfMOBYc052LItPHz6BwvHIOifqQLmvNHzPZKvREAB0vYC8 pYIVGCCkWxEq7tI3RaSscUMBRK3IafdxPElaEMJ85ZcP1DSgp9GILQ0voksy7mLtdoef AhEh5+l/PHYiSdnxat2wnyeihPCFDAI7ZwxlnZMq2xNnJTeqLUHZMdX1Zuqgut3RQeGz Ni7onB0KV6gmcNt4/CCPR5PNNtAG4GiyHp14Mzayyt+zeft51our3MZ1iPMHnCQFSFaQ z/+VwOg2d2VF+e0GFG8qjmJMi/MT92HbE+VcLDyixl66+5o2RxdbJxAWf6qHXz9gE1U3 ye3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=QklVf+ixk0NQFljxo0XfQeNsFNYfdaMs4nNooWSziP0=; b=fIVZR+WFhcm2uPhd22+OHGFjKfFC3kVLHf+V0AVBffQhRJ2KGQ5uR3TjPHDB5YYXCN j7t4Yb6TcdLspiRqxczLauBwtuSJgCY8/LR0Jmf/JL5HDJOSN7tznptmCxz1Zh8+oDMb aBJRGLNaGrOlMYcFIO9/ZA+9TTvq1WJ1zBYYkL68JA7A747cqT+9bAPOKRTegfmpO2N8 e9kxiMwkWl8oVgfAOpSC625cICEFRqgVHGb96uxqKPcFFI9t2v2xDIJJzx2GWKciCY9e rySfgYwOPW4MPv9atnqnI4XNBbfOF/Vk028yl3/qU+BCRUIFDxI9i8xpJSq0ptN5vQio 3CvQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q9si402452ybd.395.2017.10.31.06.11.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 31 Oct 2017 06:11:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45628 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WKR-0001ph-KR for patch@linaro.org; Tue, 31 Oct 2017 09:11:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK4-0001nz-5q for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK3-0006we-0R for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK2-0006em-PF for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJt-0007Hr-8X for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:27 +0000 Message-Id: <1509455489-14101-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Subbaraya Sundeep Fixed incorrect frame size mask, validated maximum frame size in spi_write and removed dead code. Signed-off-by: Subbaraya Sundeep Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/mss-spi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c index 5a8e308..d60daba 100644 --- a/hw/ssi/mss-spi.c +++ b/hw/ssi/mss-spi.c @@ -76,9 +76,10 @@ #define C_BIGFIFO (1 << 29) #define C_RESET (1 << 31) -#define FRAMESZ_MASK 0x1F +#define FRAMESZ_MASK 0x3F #define FMCOUNT_MASK 0x00FFFF00 #define FMCOUNT_SHIFT 8 +#define FRAMESZ_MAX 32 static void txfifo_reset(MSSSpiState *s) { @@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s) s->fifo_depth = 32; } else if (size <= 16) { s->fifo_depth = 16; - } else if (size <= 32) { - s->fifo_depth = 8; } else { - s->fifo_depth = 4; + s->fifo_depth = 8; } } @@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr, if (s->enabled) { break; } + /* + * [31:6] bits are reserved bits and for future use. + * [5:0] are for frame size. Only [5:0] bits are validated + * during write, [31:6] bits are untouched. + */ + if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided." + "Maximum frame size is %u\n", + __func__, value & FRAMESZ_MASK, FRAMESZ_MAX); + break; + } s->regs[R_SPI_DFSIZE] = value; break; From patchwork Tue Oct 31 13:11:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 117627 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3899765qgn; Tue, 31 Oct 2017 06:13:23 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TH/CHLiBv6D//xKnkXNoVvxtlWAm6E380XZtmHtab219gPGmuKuIx7VJZYVW3KozElcBDn X-Received: by 10.37.46.10 with SMTP id u10mr1097229ybu.491.1509455603663; Tue, 31 Oct 2017 06:13:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509455603; cv=none; d=google.com; s=arc-20160816; b=IOeVW6C8u5g/q/5WRcUuMfe9/BUIFGhNhiY++d0Xljp0Hb94EFsY8ZMI1XB7Mj7QHg hjVWCkkGTU1vnu7ST8EizSALvJL/Xr7qKmsUeutCurYyhGpbhYnxJLdqi0MfWTkypB2i 6Hqm2aOd/W/uoPcJxlUlpkFI7t27/HhNKHWjTVuE3Ij6DSruz+bzNe/lGezCHGwOO4RB ml03EFUtW+V1zBZwpmFzzfBWlprbHB2gviNN9/Pv5vjmESk1cDwx9RbDyhJkq04zCBch ycc3zle4FsTaZQASX/TPFcQBrnJkHfyQVYQQ+YwJ5VaNOu8F3AHu6DftnndUQyqLLTKv 9djg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=+hwoTszkgu3uR4XqN1H6ZKgenm5EG5uWZNNx++KP2XA=; b=NYV+3UXQyUAlaWE0bE281nxIF1qmKrlPvINwN+InIMHjwfOTA69KT0Rj9zZKuTGa8z dA/i4+EhLLXNaOCdgyvUppY972n3lBVwsoOK+cXl09kPyQ587hJ7kyFC9TAvm7h6aApr W8rIIuuhBr5IYyeLpWDycP1tOs/SqYojuAu2FwBLyCXxj2D5CRGYW5RmQkL7m2uYZ2gF qktousoiHfJ8+UiNUZJtg9Fnl1XPbf1LMt4by7mnC5Plfs2waN6PoOTdi7XyBprjjTgz ktiCJPWLAgpVcEl1DzCQ8AZabkYzmTXSUnBXOjnovA2qNpU90fVg1DzGQHHcrZrEoTea 7Iug== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a13si392724ybg.549.2017.10.31.06.13.23 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 31 Oct 2017 06:13:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WM7-0002ol-64 for patch@linaro.org; Tue, 31 Oct 2017 09:13:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK7-0001qT-OT for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK2-0006v1-2a for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:19 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK1-0006em-RU for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJt-0007IH-VM for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:28 +0000 Message-Id: <1509455489-14101-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Subbaraya Sundeep Implemented system reset by creating SYSRESETREQ gpio out from nvic. Signed-off-by: Subbaraya Sundeep Message-id: 1509253165-7434-1-git-send-email-sundeep.lkml@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/msf2-soc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.7.4 diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 6f97fa9..a8ec2cd 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 }; static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 }; +static void do_sys_reset(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + static void m2sxxx_soc_initfn(Object *obj) { MSF2State *s = MSF2_SOC(obj); @@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) error_append_hint(errp, "m3clk can not be zero\n"); return; } + + qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, + qemu_allocate_irq(&do_sys_reset, NULL, 0)); + system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; for (i = 0; i < MSF2_NUM_UARTS; i++) { From patchwork Tue Oct 31 13:11:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 117620 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3897356qgn; Tue, 31 Oct 2017 06:11:31 -0700 (PDT) X-Google-Smtp-Source: ABhQp+SHKLS3ny/HQ/lGRsd9RQJpiwTDaUSuqiFYNQM0nx8HPb9g2k2MPsy+Kd/eUQJWVfx9zkcJ X-Received: by 10.37.173.10 with SMTP id y10mr1170525ybi.249.1509455491192; Tue, 31 Oct 2017 06:11:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509455491; cv=none; d=google.com; s=arc-20160816; b=trxc9aElrhzN7GwUMyYcw1VcAnnlgavhxrP+LZgXYAZNuAsgT643yjurr4eSY1KTuE kbsLlRF1KgqTG2Q0MGsZVOZ0EDf+v5nVElW4QyU0PxXxcPP94w/6nbEDkAaDVMLSGG+9 wJf+qsyfU5BYm9DSxn8epnO4rk0nhnCf7fkPhDLrCfOYTaFTgAyGCxkNov8fHGfOK33R SxIiOxNS6b8r6oIBu3vkRxpwk1v0uYJtJfR+FRXOJDEKQ3H4K94OR+jl4NoU4kZ6cVVQ APNrAiF+DPDNpi5CkTE32JjU2Rih+sYvWnLZtwYusvzdJQGgnij9O6UGHjum66biOaaM 2CaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=M/JwGpeEdl+/OGgmM90OsiXrkDtLCdCbTFeFb2CtfKE=; b=KkRugNIa5T+nJEMCiXsxfWuGiu5rBBI0JhwqVtYO2/gFc2z07VeZEFVo9507fk07Cj 8NybAgduwixNz9mlIMfLkfQIF5gmfUkr7GZOBa4F+IpiBUExIkq3B7BB4FHIEQx1hnyX 8LTS4RS0nTALEXtdYnruI8fPV+jMDx+Y7cXwpnuNuYCCeCACviQuxc/r/LWCXba7JGu+ mYHRGV4gizGX+yh5cgeCEw4sJSd9L+gx/DzVUSPBtxsrWOBAJ3f6Dnx8NzQ2yNqg64hV J1TTZGej0yHEd57ayY7Q/aq6KMKrG1dqXIcDclSXdZyuET5Z5384cNamUVOTzUEH7i8+ untw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k11si400395ywc.4.2017.10.31.06.11.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 31 Oct 2017 06:11:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45627 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WKI-0001ny-LD for patch@linaro.org; Tue, 31 Oct 2017 09:11:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK2-0001nh-3n for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK1-0006tP-4u for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK0-0006em-TW for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJu-0007Ij-LS for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:06 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:29 +0000 Message-Id: <1509455489-14101-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger We exposed gpex_set_irq_num() for machines to set the INTx to GSI routing. However if the machine forgets to call that function we currently do not check the association was properly done. Let's initialize gsi values to -1 and if this value is found in gpex_route_intx_pin_to_irq, set the routing mode as disabled. Signed-off-by: Eric Auger Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pci-host/gpex.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 4090793..edf305b 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) { PCIINTxRoute route; GPEXHost *s = opaque; + int gsi = s->irq_num[pin]; - route.mode = PCI_INTX_ENABLED; - route.irq = s->irq_num[pin]; + route.irq = gsi; + if (gsi < 0) { + route.mode = PCI_INTX_DISABLED; + } else { + route.mode = PCI_INTX_ENABLED; + } return route; } @@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(sbd, &s->io_ioport); for (i = 0; i < GPEX_NUM_IRQS; i++) { sysbus_init_irq(sbd, &s->irq[i]); + s->irq_num[i] = -1; } pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,