From patchwork Fri Nov 3 08:40:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 117861 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3188694qgn; Fri, 3 Nov 2017 01:44:31 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RD/ETwZ7lQv9/Op7KE90hPBwn4YVDCE+MF8BiolzmoP7RpUx/x9/MhqoQnMZ07br7j3MYd X-Received: by 10.37.246.39 with SMTP id t39mr4268793ybd.220.1509698671025; Fri, 03 Nov 2017 01:44:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509698671; cv=none; d=google.com; s=arc-20160816; b=hLTYITDgny8KwvF4sYJEovOMoL7pibvupST2YkkTnRlM7heBVPfANQpGOZPgq4dS69 7w4xTdSPwtLRejHdhTabcHt18A1B0ofr2m2SwTp/XOAJBmfkXRC1hcrOuNdmNMY3rbJO JBOJyS1I9bKw5ojH6qfC6Hus/rX8ZneS9SvFnLuL4la5Ela2i8+bXVDfsdKJSz9pCXqt o8l6Iw/pZP7qy/d8IJ+IPfDkHlxAdediotKyWYsqDcx05l1Mvx5eqI1WRnjFTKhRzU+n CbT6CqHVZIMePQcHB0biW+kj9SP5apSS1eIc6FlCDWw/ZbOBgjs3FfhRSrdy9ttd6HBS NOiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4BDSQzsdDM7Bh+3NBnayvPVdSEpTsHHmQGK53JqNFC4=; b=p+MkYbSxQuFiykK1BaVly8DRksjwsj9iivLSXD1VNbJn7OzKC6M3BquIEs+RwApVoc SaNNCI3ICuXDda5xszc5Keyi2gTvGCY2iqtCAkKHENhEwVC4iAUAn1WNqkRK2H7iq5Kg 8Xw1Kp+kYLOcaRNc2Qif9CbpMO+cKFEjICCSOuj3/ix/cQI10VJ2x5nGb/CGQjEthSQd JluCqEn/+981XVhJSdjOePDwc+Y5kzk1Fvh8CZSctjOKqee3uko7RY/oF6VA9ZdUPgTp a5uBW0pR/NHWfJKWKXJHnQ3ZpgtQbY49iwemtkEfxtN9+0PsF9IjGeXnuTyhbfdkpMT+ OwGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AM9RR2qA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[87.164.81.95]) by smtp.gmail.com with ESMTPSA id e6sm12548347wrg.53.2017.11.03.01.40.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 01:40:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 09:40:44 +0100 Message-Id: <20171103084046.12821-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171103084046.12821-1-richard.henderson@linaro.org> References: <20171103084046.12821-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PULL 1/3] tcg: Allow constant pool entries in the prologue X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Both ARMv6 and AArch64 currently may drop complex guest_base values into the constant pool. But generic code wasn't expecting that, and the pool is not emitted. Correct that. Tested-by: Emilio G. Cota Tested-by: Laurent Desnogues Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson --- tcg/tcg.c | 49 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 7 deletions(-) -- 2.13.6 diff --git a/tcg/tcg.c b/tcg/tcg.c index 683ff4abb7..c22f1c4441 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -771,12 +771,32 @@ void tcg_prologue_init(TCGContext *s) /* Put the prologue at the beginning of code_gen_buffer. */ buf0 = s->code_gen_buffer; + total_size = s->code_gen_buffer_size; s->code_ptr = buf0; s->code_buf = buf0; + s->data_gen_ptr = NULL; s->code_gen_prologue = buf0; + /* Compute a high-water mark, at which we voluntarily flush the buffer + and start over. The size here is arbitrary, significantly larger + than we expect the code generation for any one opcode to require. */ + s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); + +#ifdef TCG_TARGET_NEED_POOL_LABELS + s->pool_labels = NULL; +#endif + /* Generate the prologue. */ tcg_target_qemu_prologue(s); + +#ifdef TCG_TARGET_NEED_POOL_LABELS + /* Allow the prologue to put e.g. guest_base into a pool entry. */ + { + bool ok = tcg_out_pool_finalize(s); + tcg_debug_assert(ok); + } +#endif + buf1 = s->code_ptr; flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1); @@ -785,21 +805,36 @@ void tcg_prologue_init(TCGContext *s) s->code_gen_ptr = buf1; s->code_gen_buffer = buf1; s->code_buf = buf1; - total_size = s->code_gen_buffer_size - prologue_size; + total_size -= prologue_size; s->code_gen_buffer_size = total_size; - /* Compute a high-water mark, at which we voluntarily flush the buffer - and start over. The size here is arbitrary, significantly larger - than we expect the code generation for any one opcode to require. */ - s->code_gen_highwater = s->code_gen_buffer + (total_size - TCG_HIGHWATER); - tcg_register_jit(s->code_gen_buffer, total_size); #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { qemu_log_lock(); qemu_log("PROLOGUE: [size=%zu]\n", prologue_size); - log_disas(buf0, prologue_size); + if (s->data_gen_ptr) { + size_t code_size = s->data_gen_ptr - buf0; + size_t data_size = prologue_size - code_size; + size_t i; + + log_disas(buf0, code_size); + + for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { + if (sizeof(tcg_target_ulong) == 8) { + qemu_log("0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", + (uintptr_t)s->data_gen_ptr + i, + *(uint64_t *)(s->data_gen_ptr + i)); + } else { + qemu_log("0x%08" PRIxPTR ": .long 0x%08x\n", + (uintptr_t)s->data_gen_ptr + i, + *(uint32_t *)(s->data_gen_ptr + i)); + } + } + } else { + log_disas(buf0, prologue_size); + } qemu_log("\n"); qemu_log_flush(); qemu_log_unlock(); From patchwork Fri Nov 3 08:40:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 117859 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3186365qgn; Fri, 3 Nov 2017 01:41:17 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Tjm2Ux0MUXl79fTnOnOdRwJIDbtmW7V6Ju/pYzAKlsvne1Jtdx2QT87Xo8l5Z1GY8tVgGU X-Received: by 10.129.196.12 with SMTP id j12mr969744ywi.393.1509698477650; Fri, 03 Nov 2017 01:41:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509698477; cv=none; d=google.com; s=arc-20160816; b=sSN0QdCn9F2F6NUNth29RUfe95MsuvZ4JvuzB3QddfqAsS/3Vq0rN7ESYUCuNiIk0s oWcj1dUk+JRnS7mvbxYKO4IeP8p041YAaZUb7DZHT6dxK9zUrvYA3aY6ZEj6xRKu1/Z5 LNBEL44Fx1H0ML49iGWqEMaf3yPTrm1dR9JhScpNvG1Q/5gzDuJU3Mxp+tZoyVXpg1GV ivMzefv1QXrsDqsmuRJQSom5af2EdVXXm5QsgjmAtQXAPUHeOvH6IuwtPsc8VErkHfmh NJEW0buu4vgVuygBkM7P7bFjJ6Iiin0pv+0ubitZK8cug2CyEY1hpZ+K4G7TxLc//x8y 5nIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xbCD6ZopTFgQK0anWBQ0BbvGGkrHG3DYaUP6xslNLEU=; b=1FJu1+fTfT2Et22kZWT2JvxE1Pd5Ht/XigvSm1mZcybVsKpmCCehF42XRqO7Tc4Ls2 K5nw7nVSmMEaWpxdl32q8GlhzG2Ng2gIXBo9QYtkuZkGIcYO3dHTfa7zK0Ppley9tXNH W0uHmsnNzVHHY+lJYz6MkzSlahNxmV8ZgenLXJBpxMjRhkZxJXfOf6uUt6ufDM2F4jci 78AaNabHKzBnQG8qb2XIvms3S5+iMFceJWj6HgM7CnLSEJSZ7bgSb+tPIb9jtaISMESj ngMiyOLN174AE2Aw2ifeUxY1BfqLUAArt9kNP0+5h3gWg3cjYYZjDSIZnOlGJUAF0rsh XOPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GVU9HTCs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[87.164.81.95]) by smtp.gmail.com with ESMTPSA id e6sm12548347wrg.53.2017.11.03.01.40.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 01:40:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 09:40:45 +0100 Message-Id: <20171103084046.12821-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171103084046.12821-1-richard.henderson@linaro.org> References: <20171103084046.12821-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PULL 2/3] tcg/s390x: Use constant pool for prologue X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-s390x@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than have separate code only used for guest_base, rely on a recent change to handle constant pool entries. Cc: qemu-s390x@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 44 ++++++++++++-------------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) -- 2.13.6 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 38a7cdab75..9af6dcef05 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -555,9 +555,6 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) static const S390Opcode lli_insns[4] = { RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH }; -static const S390Opcode ii_insns[4] = { - RI_IILL, RI_IILH, RI_IIHL, RI_IIHH -}; static bool maybe_out_small_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long sval) @@ -647,36 +644,19 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } - /* When allowed, stuff it in the constant pool. */ - if (!in_prologue) { - if (USE_REG_TB) { - tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); - new_pool_label(s, sval, R_390_20, s->code_ptr - 2, - -(intptr_t)s->code_gen_ptr); - } else { - tcg_out_insn(s, RIL, LGRL, ret, 0); - new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); - } - return; - } - - /* What's left is for the prologue, loading GUEST_BASE, and because - it failed to match above, is known to be a full 64-bit quantity. - We could try more than this, but it probably wouldn't pay off. */ - if (s390_facilities & FACILITY_EXT_IMM) { - tcg_out_insn(s, RIL, LLILF, ret, uval); - tcg_out_insn(s, RIL, IIHF, ret, uval >> 32); + /* Otherwise, stuff it in the constant pool. */ + if (s390_facilities & FACILITY_GEN_INST_EXT) { + tcg_out_insn(s, RIL, LGRL, ret, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); + } else if (USE_REG_TB && !in_prologue) { + tcg_out_insn(s, RXY, LG, ret, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, sval, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); } else { - const S390Opcode *insns = lli_insns; - int i; - - for (i = 0; i < 4; i++) { - uint16_t part = uval >> (16 * i); - if (part) { - tcg_out_insn_RI(s, insns[i], ret, part); - insns = ii_insns; - } - } + TCGReg base = ret ? ret : TCG_TMP0; + tcg_out_insn(s, RIL, LARL, base, 0); + new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, RXY, LG, ret, base, TCG_REG_NONE, 0); } } From patchwork Fri Nov 3 08:40:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 117860 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3187854qgn; Fri, 3 Nov 2017 01:43:20 -0700 (PDT) X-Google-Smtp-Source: ABhQp+T4o4DjDR6gyivDrA6YRgl/o9tG5RgN0JX+4jdA804fcgicL+yKHx0aamEIugsvTAyR7eZy X-Received: by 10.37.215.147 with SMTP id o141mr4114941ybg.484.1509698600890; Fri, 03 Nov 2017 01:43:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509698600; cv=none; d=google.com; s=arc-20160816; b=UAvHeVsjRZy/1OkPh12UEidSDcDX3PUzIAVZEaXU2AsG5GrU/honxIzFGOZ7SiCNbz 4ZTtBylBGfg5o4A4Wje+Ehy3WuycqeBd/2l3nO72d5a5gBx8rVl2k5+Ekj3zPeSIpAu7 F5LIPc/0XZNLTDubjPMtWxC5ONc6mwROHVOUEP+9VC/lhKJRCZgS0VSvknezY4CFQ50/ QtnMclUO4yfAPdl+SZVe2cc8vFFEenJFlnOMwSYNJ9LSNd7hvZM0oCBW3m+NHTdfokex r3bI0tuTC1906DR1ky+JZF1mGv+fM0gpzvbEmNiRGID6CqM/VE5eOxEdTUyTQBhAVYSc P2Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=qAKXbHRfKP2ype58aUcRZOMoKb9bP3iiBfoCjREvatw=; b=02MPu7VQ+iQ5yypjxcDO3ziDc/1xcN6r24keM47L50893z8GT2dGX8PGVr6r0tmM+A ofgEHMTpg+KroXBSQZoUCS6fajSyeGlYdyqBR0T8hDan6mSMON5/wVCyjHP/t9pQ/D48 VefKdQnLaWnTBHBbftgnGFfVIWX9906olYaXulL9lR6g8D9TZREqS00vz6Kmvlg4mHqX P5J//l6Pz8ScnoaM8hEzGyBM6ks6muvYwDHEFkstydse6zjQAH5BLk3urxleytgoi9SB VsFyOhcSiGw6GxpcDVFtJVwe+QtRw8dVP3oqc3W2/jsGcHxDMDRfkbGVtb4q5KDWjUe1 XWUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YR3uV3sg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[87.164.81.95]) by smtp.gmail.com with ESMTPSA id e6sm12548347wrg.53.2017.11.03.01.40.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Nov 2017 01:40:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 Nov 2017 09:40:46 +0100 Message-Id: <20171103084046.12821-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171103084046.12821-1-richard.henderson@linaro.org> References: <20171103084046.12821-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PULL 3/3] cpu-exec: Exit exclusive region on longjmp from step_atomic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Commit ac03ee5331612e44be narrowed the scope of the exclusive region so it only covers when we're executing the TB, not when we're generating it. However it missed that there is more than one execution path out of cpu_tb_exec -- if the atomic insn causes an exception then the code will longjmp out, skipping the code to end the exclusive region. This causes QEMU to hang the next time the CPU calls start_exclusive(), waiting for itself to exit the region. Move the "end the region" code out to the end of the function so that it is run for both normal exit and also for exit-via-longjmp. We have to use a volatile bool flag to decide whether we need to end the region, because we can longjump out of the codegen as well as the execution. (For some reason this only reproduces for me with a clang optimized build, not a gcc debug build.) Reviewed-by: Emilio G. Cota Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Fixes: ac03ee5331612e44beb393df2b578c951d27dc0d Signed-off-by: Peter Maydell Message-Id: <1509640536-32160-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) -- 2.13.6 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4318441e4c..61297f8f4a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -233,6 +233,8 @@ void cpu_exec_step_atomic(CPUState *cpu) uint32_t flags; uint32_t cflags = 1; uint32_t cf_mask = cflags & CF_HASH_MASK; + /* volatile because we modify it between setjmp and longjmp */ + volatile bool in_exclusive_region = false; if (sigsetjmp(cpu->jmp_env, 0) == 0) { tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); @@ -251,14 +253,12 @@ void cpu_exec_step_atomic(CPUState *cpu) /* Since we got here, we know that parallel_cpus must be true. */ parallel_cpus = false; + in_exclusive_region = true; cc->cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); cpu_tb_exec(cpu, tb); cc->cpu_exec_exit(cpu); - parallel_cpus = true; - - end_exclusive(); } else { /* We may have exited due to another problem here, so we need * to reset any tb_locks we may have taken but didn't release. @@ -270,6 +270,15 @@ void cpu_exec_step_atomic(CPUState *cpu) #endif tb_lock_reset(); } + + if (in_exclusive_region) { + /* We might longjump out of either the codegen or the + * execution, so must make sure we only end the exclusive + * region if we started it. + */ + parallel_cpus = true; + end_exclusive(); + } } struct tb_desc {