From patchwork Tue Nov 7 13:35:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118164 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3987816qgn; Tue, 7 Nov 2017 05:37:42 -0800 (PST) X-Google-Smtp-Source: ABhQp+S82sBzXRW6FKhBeAUnEDDXBFwCOkroxdvRC6rOKwfNRu06bPThuLH70y7ZHzUw7RmV3hw0 X-Received: by 10.129.130.4 with SMTP id s4mr12082447ywf.179.1510061862388; Tue, 07 Nov 2017 05:37:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510061862; cv=none; d=google.com; s=arc-20160816; b=jg+rNecRPc+vpteoMb9k2T7xxazPu+whtiy1QDgZ4kRiHAZsg2ig77oeFGfwAeQt5P 2hWESO97AEcDts4J3+q/m83C1/W/bUpG4+ItKxQ7bw+e0wt5pO0wODVTGAgP2KP3TSTV bMMpmQDZm4RaTZzBw6bzfUgpPL5QHCBuo8NgSH5smHZRzC9NEn16Vv+2dMec2iRCnxIT vr3/xcD8KeK99FLbpYzmqOhioOsc56Upu9hvvi0Ka6DzSvMTZflXxnNSAliK79lVLkxy fEWtqBS9+lzCKZYawoZ9ALoXVuBtromVyQ0E99xoDxSdJW/mojljGBOKctpb3GaSnAwR eJYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=DKZJzXLuUaE0ls9NzW4NfiUI4bJSumjNFcnbmJ3kw+0=; b=tNsVIhByRHzXnrjZ7FFTaORJ3rHYQtOx5f3GCCVS465O+VLNXIklwUbWhIfSgp11b7 eA0OcvUqjswtwwgzb1mhy0P4ICg39eMvRjFEGuobioYSS4VwwHNgA16owgCgZj1XaTwd LFMkN6neIMyM2UWiu0nmYiU8QkeRajs1DxzxxEWmMBPO44aQ2VRlhmesG/2FMsfjYwPP UFTWCIPvQqAr7hz7KSp6WIWobqqgDtOsIbvlu5yMVcIT+f/6lJ2TgzGvzdi/RhxoiGrU D91ao3r0Y67aHKkT946kVJpSnoBDhcCW7oglbv73r/ocsJtmToMrZ/IrL6Q5Frr6hzmc Ar4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a12si265398ybc.297.2017.11.07.05.37.42 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:37:42 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53475 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC44T-0008IK-TB for patch@linaro.org; Tue, 07 Nov 2017 08:37:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36774) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vp-9U for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41j-0005uj-Ga for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41j-0005rx-4q for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:51 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41g-0004ST-Uj for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:48 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:16 +0000 Message-Id: <1510061722-14092-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/7] arm: implement cache/shareability attribute bits for PAR registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Andrew Baumann On a successful address translation instruction, PAR is supposed to contain cacheability and shareability attributes determined by the translation. We previously returned 0 for these bits (in line with the general strategy of ignoring caches and memory attributes), but some guest OSes may depend on them. This patch collects the attribute bits in the page-table walk, and updates PAR with the correct attributes for all LPAE translations. Short descriptor formats still return 0 for these bits, as in the prior implementation. Signed-off-by: Andrew Baumann Message-id: 20171031223830.4608-1-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 178 +++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 164 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 96113fe..f61fb3e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -19,17 +19,23 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #ifndef CONFIG_USER_ONLY +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ +} ARMCacheAttrs; + static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, - ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); /* Security attributes for an address, as returned by v8m_security_lookup. */ typedef struct V8M_SAttributes { @@ -2159,9 +2165,10 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, uint64_t par64; MemTxAttrs attrs = {}; ARMMMUFaultInfo fi = {}; + ARMCacheAttrs cacheattrs = {}; - ret = get_phys_addr(env, value, access_type, mmu_idx, - &phys_addr, &attrs, &prot, &page_size, &fsr, &fi); + ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, + &prot, &page_size, &fsr, &fi, &cacheattrs); if (extended_addresses_enabled(env)) { /* fsr is a DFSR/IFSR value for the long descriptor * translation table format, but with WnR always clear. @@ -2173,7 +2180,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, if (!attrs.secure) { par64 |= (1 << 9); /* NS */ } - /* We don't set the ATTR or SH fields in the PAR. */ + par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ + par64 |= cacheattrs.shareability << 7; /* SH */ } else { par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ @@ -6925,7 +6933,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, return false; } if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, - &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) { + &physaddr, &attrs, &prot, &page_size, &fsr, &fi, NULL)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -8207,7 +8215,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, int ret; ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, fsr, fi); + &txattrs, &s2prot, &s2size, fsr, fi, NULL); if (ret) { fi->s2addr = addr; fi->stage2 = true; @@ -8608,11 +8616,41 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, return true; } +/* Translate from the 4-bit stage 2 representation of + * memory attributes (without cache-allocation hints) to + * the 8-bit representation of the stage 1 MAIR registers + * (which includes allocation hints). + * + * ref: shared/translation/attrs/S2AttrDecode() + * .../S2ConvertAttrsHints() + */ +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +{ + uint8_t hiattr = extract32(s2attrs, 2, 2); + uint8_t loattr = extract32(s2attrs, 0, 2); + uint8_t hihint = 0, lohint = 0; + + if (hiattr != 0) { /* normal memory */ + if ((env->cp15.hcr_el2 & HCR_CD) != 0) { /* cache disabled */ + hiattr = loattr = 1; /* non-cacheable */ + } else { + if (hiattr != 1) { /* Write-through or write-back */ + hihint = 3; /* RW allocate */ + } + if (loattr != 1) { /* Write-through or write-back */ + lohint = 3; /* RW allocate */ + } + } + } + + return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; +} + static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, target_ulong *page_size_ptr, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); @@ -8929,6 +8967,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, */ txattrs->secure = false; } + + if (cacheattrs != NULL) { + if (mmu_idx == ARMMMUIdx_S2NS) { + cacheattrs->attrs = convert_stage2_attrs(env, + extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint8_t attrindx = extract32(attrs, 0, 3); + uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <= 7); + cacheattrs->attrs = extract64(mair, attrindx * 8, 8); + } + cacheattrs->shareability = extract32(attrs, 6, 2); + } + *phys_ptr = descaddr; *page_size_ptr = page_size; return false; @@ -9490,6 +9543,93 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, return false; } +/* Combine either inner or outer cacheability attributes for normal + * memory, according to table D4-42 and pseudocode procedure + * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). + * + * NB: only stage 1 includes allocation hints (RW bits), leading to + * some asymmetry. + */ +static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) +{ + if (s1 == 4 || s2 == 4) { + /* non-cacheable has precedence */ + return 4; + } else if (extract32(s1, 2, 2) == 0 || extract32(s1, 2, 2) == 2) { + /* stage 1 write-through takes precedence */ + return s1; + } else if (extract32(s2, 2, 2) == 2) { + /* stage 2 write-through takes precedence, but the allocation hint + * is still taken from stage 1 + */ + return (2 << 2) | extract32(s1, 0, 2); + } else { /* write-back */ + return s1; + } +} + +/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 + * and CombineS1S2Desc() + * + * @s1: Attributes from stage 1 walk + * @s2: Attributes from stage 2 walk + */ +static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4); + uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4); + ARMCacheAttrs ret; + + /* Combine shareability attributes (table D4-43) */ + if (s1.shareability == 2 || s2.shareability == 2) { + /* if either are outer-shareable, the result is outer-shareable */ + ret.shareability = 2; + } else if (s1.shareability == 3 || s2.shareability == 3) { + /* if either are inner-shareable, the result is inner-shareable */ + ret.shareability = 3; + } else { + /* both non-shareable */ + ret.shareability = 0; + } + + /* Combine memory type and cacheability attributes */ + if (s1hi == 0 || s2hi == 0) { + /* Device has precedence over normal */ + if (s1lo == 0 || s2lo == 0) { + /* nGnRnE has precedence over anything */ + ret.attrs = 0; + } else if (s1lo == 4 || s2lo == 4) { + /* non-Reordering has precedence over Reordering */ + ret.attrs = 4; /* nGnRE */ + } else if (s1lo == 8 || s2lo == 8) { + /* non-Gathering has precedence over Gathering */ + ret.attrs = 8; /* nGRE */ + } else { + ret.attrs = 0xc; /* GRE */ + } + + /* Any location for which the resultant memory type is any + * type of Device memory is always treated as Outer Shareable. + */ + ret.shareability = 2; + } else { /* Normal memory */ + /* Outer/inner cacheability combine independently */ + ret.attrs = combine_cacheattr_nibble(s1hi, s2hi) << 4 + | combine_cacheattr_nibble(s1lo, s2lo); + + if (ret.attrs == 0x44) { + /* Any location for which the resultant memory type is Normal + * Inner Non-cacheable, Outer Non-cacheable is always treated + * as Outer Shareable. + */ + ret.shareability = 2; + } + } + + return ret; +} + + /* get_phys_addr - get the physical address for this virtual address * * Find the physical address corresponding to the given virtual address, @@ -9514,12 +9654,14 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, * @prot: set to the permissions for the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr * @fsr: set to the DFSR/IFSR value on failure + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { /* Call ourselves recursively to do the stage 1 and then stage 2 @@ -9529,10 +9671,11 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, hwaddr ipa; int s2_prot; int ret; + ARMCacheAttrs cacheattrs2 = {}; ret = get_phys_addr(env, address, access_type, stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fsr, fi); + prot, page_size, fsr, fi, cacheattrs); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { @@ -9543,10 +9686,17 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* S1 is done. Now do S2 translation. */ ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, phys_ptr, attrs, &s2_prot, - page_size, fsr, fi); + page_size, fsr, fi, + cacheattrs != NULL ? &cacheattrs2 : NULL); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ *prot &= s2_prot; + + /* Combine the S1 and S2 cache attributes, if needed */ + if (!ret && cacheattrs != NULL) { + *cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2); + } + return ret; } else { /* @@ -9617,7 +9767,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, - attrs, prot, page_size, fsr, fi); + attrs, prot, page_size, fsr, fi, cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi); @@ -9645,7 +9795,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, ret = get_phys_addr(env, address, access_type, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fsr, fi); + &attrs, &prot, &page_size, fsr, fi, NULL); if (!ret) { /* Map a single [sub]page. */ phys_addr &= TARGET_PAGE_MASK; @@ -9674,7 +9824,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, *attrs = (MemTxAttrs) {}; ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fsr, &fi); + attrs, &prot, &page_size, &fsr, &fi, NULL); if (ret) { return -1; From patchwork Tue Nov 7 13:35:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118165 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3989737qgn; Tue, 7 Nov 2017 05:39:29 -0800 (PST) X-Google-Smtp-Source: ABhQp+TPXujCbfAVS7hheieIgAnxOp0oe4N90chUQG5nkohDLtbk+XHlNMBReNjTDcolxBw3ZYO6 X-Received: by 10.37.209.78 with SMTP id i75mr12721769ybg.75.1510061969212; Tue, 07 Nov 2017 05:39:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510061969; cv=none; d=google.com; s=arc-20160816; b=m8+Gn5gc+iW3RmBdl/Ak+EjGJi4s9HWCW0aEm7JbwFJXYCQvtDJ/dooaMRgXi6SQyq 52M2TDM7EHplP5myV2Jl7EehnuweSa90egbkrWbvDofN60POmrSeS6oCZ9eV5HbDNF5W UKqiP/LEOIeG+BrRKRjSpOT0CFVlo/2NIlOYYBjMpdKZTscRzaLjeaesigSdqxh4arcm 3HQKjMEMxeIgbdF/MyUy33t+r4Ga6g2itAR+r2SHc1NKyxqn9LAYogk/aAbmyzhJehKk J1+nvIULEPJcxs5Zsb2lhiK2hRXDHftxwKQXJDNUJtKXzZO875l/t8iLQqlNng0kT7wz xk1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=eKqq7ygDkFcd44v3Z59sN5n7sJDynsM2xWqM8SGhnIU=; b=AaESfNhlnGKzMOS2/vlanAaTtl2hSYBgCFdgJ8XoZXxLMpYy3ignNzRreUeFmiObMp K/3evABFqsPfxykewQyQfAdQe4Nm/mcBuWiZL+Mn2GAPfzTbUP3mzv2zxYWer8J5cyqc cZx5f1qZGwrpQQktu6DDqeT3aJ3j4E4qewumMhrt8TxCGse+6KtA4e6xkbhGmp42WfYF L1Swtgzgii5kRg5jeLI6Q257mFxlLPgZDw72ttm+07WCGgJ0W0vEt6ApcYc8kiq3TO1E 9BAj/k5s/WMMyY9pPKBlkSOgMScx2LYiNcL7lCsi0NXrP36Yo1bN8jP56oGio+xtH/SM wFow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b76si274475ywh.759.2017.11.07.05.39.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:39:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53485 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC46C-00012P-OW for patch@linaro.org; Tue, 07 Nov 2017 08:39:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36800) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41m-0006Wh-9r for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41l-0005y7-Iz for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38240) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41l-0005vT-D6 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41h-0004Sg-J6 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:49 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:17 +0000 Message-Id: <1510061722-14092-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/7] hw/arm: Mark the "fsl, imx6" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth This device causes QEMU to abort if the user tries to instantiate it: $ qemu-system-aarch64 -M sabrelite -smp 1,maxcpus=2 -device fsl,,imx6 Unexpected error in qemu_chr_fe_init() at chardev/char-fe.c:222: qemu-system-aarch64: -device fsl,,imx6: Device 'serial0' is in use Aborted (core dumped) The device uses serial_hds[] directly in its realize function, so it can not be instantiated again by the user. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-2-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx6.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 26fd214..59ef33e 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -440,8 +440,9 @@ static void fsl_imx6_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = fsl_imx6_realize; - dc->desc = "i.MX6 SOC"; + /* Reason: Uses serial_hds[] in the realize() function */ + dc->user_creatable = false; } static const TypeInfo fsl_imx6_type_info = { From patchwork Tue Nov 7 13:35:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118167 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3991452qgn; Tue, 7 Nov 2017 05:41:12 -0800 (PST) X-Google-Smtp-Source: ABhQp+SYgIpkNV6ep1WabZRC0EqQKidU98Guu55Zd0lZfr/j0E9Bk5VXpbZXe7uYK7tu5mzGaKQE X-Received: by 10.129.226.67 with SMTP id z3mr11136486ywl.282.1510062072386; Tue, 07 Nov 2017 05:41:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510062072; cv=none; d=google.com; s=arc-20160816; b=PUJmcVI+3NOleznqzhKiDV254HwmsfLUbqvOuSAG7saEIhaLeWAHEL/h8qxrSuu+up W8MGcGIt38bszwOQFGLot/f6hU/N+pg1tiCbja7CC+EkE/Sp2bHmbjTvhEfpxE/JY0nX +Gw4jBsF/w5AOh2r/5KVctAMhb6v66xWLDhaJpozObFpuUD2m70BC7CiHcN7oE/8qZM6 xAEEVGWpj3j+3RTEGB3Jnal/Fj0wJtTSnNTitjUX3IF0vUPbju/fOWfdlwiORco8EZ4K Yv2qGVUjE8XXqO4J3UZ2s5DOlBOHX5aoE+wozade/uUTOCzyCO5avicUc3oo+sAcZGtT lLtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=3++GEAFIocEXAX2iP/VVcsIN2BlTid0sO6OYAmDHYI4=; b=WmsUcV0Wqm0MlPgSVS897wxtvxTKIVV6kb6FMsZjzhmanK1O81eqytP20UbQaY9GED kaaOmJESOk8gCIfuOm4cYwqKecc+XOb2y1VZvfpBCV/pVCCO52L3XPvVbbDL4IhgVmes VgZMZGAGaVyOQpCNH47X/tYFNuZ2DbbvzA527e8RHsQmpvvO3FRGjAajnNp8wQeCWz/3 zHQR06zC3C4XdCirhUPWHrUeFL1NncvnE90eEBFJ2oswC7Tt7zL0M2KfykIe+WTfhSiA EVu6GfsYlT6dE7/C7xB9k7Z6vJZUkObXdEeW5Hze5B3h0W7wAeZJyXrtT/QDG1sxRBvI Wf5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id x74si277563ywg.625.2017.11.07.05.41.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:41:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53498 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC47s-0002MU-0M for patch@linaro.org; Tue, 07 Nov 2017 08:41:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41r-0006ac-0O for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41l-0005xc-B0 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:58 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41l-0005rx-4E for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41i-0004TU-6d for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:18 +0000 Message-Id: <1510061722-14092-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/7] hw/arm: Mark the "fsl, imx25" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth QEMU currently crashes when the user tries to instantiate the fsl,imx25 device manually: $ aarch64-softmmu/qemu-system-aarch64 -S -M imx25-pdk -device fsl,,imx25 ** ERROR:/home/thuth/devel/qemu/tcg/tcg.c:538:tcg_register_thread: assertion failed: (n < max_cpus) The imx25-pdk board (which is the one that uses this CPU type) only supports one CPU, and the realize function of the "fsl,imx25" device also uses serial_hds[] directly, so this device clearly can not be instantiated twice and thus we should mark it with user_creatable = 0. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-3-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 3b97ece..cb988a6 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -288,8 +288,12 @@ static void fsl_imx25_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = fsl_imx25_realize; - dc->desc = "i.MX25 SOC"; + /* + * Reason: uses serial_hds in realize and the imx25 board does not + * support multiple CPUs + */ + dc->user_creatable = false; } static const TypeInfo fsl_imx25_type_info = { From patchwork Tue Nov 7 13:35:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118160 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3985226qgn; Tue, 7 Nov 2017 05:35:16 -0800 (PST) X-Google-Smtp-Source: ABhQp+RwBLVBBI1ZPGsuQQBABTXrCMRAZoxW57k3cEey2p1E6k8siJmUykMUAfTtt21od4WtLc5U X-Received: by 10.129.116.193 with SMTP id p184mr11840433ywc.131.1510061716663; Tue, 07 Nov 2017 05:35:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510061716; cv=none; d=google.com; s=arc-20160816; b=G4lDwSab4VWY8nYec72ofmzfqxwu+jrgrVEMcl//CXa6NOi4KvGAmM93RLwSCihEnI IM9f9pWw9sUbJfKxhFx5HYtJGQgjA4RntEIhW2XzIV3l3uCRtbHG+4EQWPfaYqwLfcKi Z6reXPO28oI2LPNV5QAFmtAkydo2lcBuRddkFfNAiXxeaksj1F6z285m2kip+VzhPEv8 GVZIvcoBVMM4v+wvUbIiVT77O2wnWWZkJSI28RwzlBnz5QZvDJp+M92ug0ifkfXqS20A qy925NGJjmc+skaXYx+D/UjUuC6BokPglxHKz/Oq9ONEwW4nsJnBvPRQhZ1Jl+qVZssv WDRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=vvwgPN+103kEz0imGRVFO6TBM8JE8rJ8MDlvZFqnifk=; b=P93x8UfJfX6g36Fw7THaCXkvH1yhf4R/tVihjaTwpg2VSoWXLSbaUIoN/7spairXW4 fFd49V9Jm8Ubt0SkCJ67+CfLAwcVnkZ3GvJz/bHmKvUkv8gq76qhPejHLN404yrUe5Ap 4zHyFHmGC7nLZ/4x4LbNEvx8PEQnO9aG28Mp4EwRloCPqkoGhaSTpw4+yqN0tGeY9ges hHLwb1tC3aQcXPxpvTok9KBgnsEs5DGsvSZIWAiEKVNBSiYOslwNUi6tCcC3xHVgjrVo Je43xHZ8yKoDqNCwcNPUMvxlhNaPWcnK1T0mt6CeFm7FBPdJZYgdoElvR9UCKM7AZR7r Og8A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d6si276134ywa.289.2017.11.07.05.35.16 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:35:16 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53462 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC428-0006XO-3O for patch@linaro.org; Tue, 07 Nov 2017 08:35:16 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vq-A3 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41k-0005wK-FX for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41k-0005rx-7f for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41i-0004Tv-PH for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:50 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:19 +0000 Message-Id: <1510061722-14092-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/7] hw/arm: Mark the "fsl, imx31" device with user_creatable = false X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth QEMU currently crashes when the user tries to instantiate the fsl,imx31 device manually: $ aarch64-softmmu/qemu-system-aarch64 -M kzm -device fsl,,imx31 ** ERROR:/home/thuth/devel/qemu/tcg/tcg.c:538:tcg_register_thread: assertion failed: (n < max_cpus) Aborted (core dumped) The kzm board (which is the one that uses this CPU type) only supports one CPU, and the realize function of the "fsl,imx31" device also uses serial_hds[] directly, so this device clearly can not be instantiated twice and thus we should mark it with user_creatable = false. Signed-off-by: Thomas Huth Message-id: 1509519537-6964-4-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/fsl-imx31.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 0f2ebe8..3eee83d 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -260,8 +260,12 @@ static void fsl_imx31_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = fsl_imx31_realize; - dc->desc = "i.MX31 SOC"; + /* + * Reason: uses serial_hds in realize and the kzm board does not + * support multiple CPUs + */ + dc->user_creatable = false; } static const TypeInfo fsl_imx31_type_info = { From patchwork Tue Nov 7 13:35:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118162 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3987456qgn; Tue, 7 Nov 2017 05:37:21 -0800 (PST) X-Google-Smtp-Source: ABhQp+Ta4WcvBGOaGZsyPv1vR4ySVUJuRpwaWQhOe6pcHXhCAdtGPTrN/t8/8G/QuKE9GuUaB/u/ X-Received: by 10.129.1.22 with SMTP id 22mr11738662ywb.472.1510061841332; Tue, 07 Nov 2017 05:37:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510061841; cv=none; d=google.com; s=arc-20160816; b=vuJiPGb2gQuCs2uXmYEDMQCOnYoGU4vbiVHixi+rpztTwz3zHgdCdxEnpbI7XFe+UT o2dQhdxt+z1wZqKemP020YzuqyxXQb7eMFaX2u71BAJOoPUY8XbXjxLeno+Ysj2G/+NZ mvOtYyRV1klQE96rZj191aGXFCrpZG3Cu1okt8MBTZNIe8LvgzPysXMq8psk43lLI4LW bjo19iDWetMMfpdCCMRICZRKW6Rn7uNcYOIyKNjtd2Qj9SCb3WhcVquAx7bLBB3LQsrZ xddGdhD0SuuLELK0d0GoQTfFGSopFFzgdrPCFNKwTvjj2TXdJDR/dWBhIf5piTtlxI3W kkHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=XqHGbfXMPM7Hxi1JVUYydt6Armcd6M7tYwrZ8G/lHo8=; b=yZEXktdR7YBf566z2tWZDRRdGY7ZaIkXEZCg9dERSSmx04PEZWnWdZClDP5jNCVlb4 zxpCgs2nhR1nfnpNdXCKilJ3RbR76sR8KtpgS8Bm6NP44T6n+A59aAOlwYfxAl0MNSU6 fZkBEYvErvYiOwxneDBYBpIX27/2wp5PP0Ue4yZ94etOH0rONKtjdMnglWI2nVP4aiPZ a71xdxTe7LTDNvV4eJ22hKaqEgsFWsZfCR2XL9iHGwkTX7SEFWztltnxMh1Cn1HySlqn T8G9hSHrCuWnYDiNAudHuZKdGUmRQAIW34My1Tb+xKTU7OzkiqR0wg3jUeSox1hHxy8I HNlw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n9si133141ywi.245.2017.11.07.05.37.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:37:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53471 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC448-0007RE-Qz for patch@linaro.org; Tue, 07 Nov 2017 08:37:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41l-0006Vr-Qz for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41k-0005wZ-N7 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:53 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38240) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41k-0005vT-FF for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:52 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41j-0004UP-F3 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:51 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:20 +0000 Message-Id: <1510061722-14092-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/7] translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the lowest address is always Rt and the one at addr+4 is Rt2, even if the CPU is big-endian. Our implementation does these with a single 64-bit store, so if we're big-endian then we need to put the two 32-bit halves together in the opposite order to little-endian, so that they end up in the right places. We were trying to do this with the gen_aa32_frob64() function, but that is not correct for the usermode emulator, because there there is a distinction between "load a 64 bit value" (which does a BE 64-bit access and doesn't need swapping) and "load two 32 bit values as one 64 bit access" (where we still need to do the swapping, like system mode BE32). Fixes: https://bugs.launchpad.net/qemu/+bug/1725267 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1509622400-13351-1-git-send-email-peter.maydell@linaro.org --- target/arm/translate.c | 39 ++++++++++++++++++++++++++++++++++----- 1 file changed, 34 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/target/arm/translate.c b/target/arm/translate.c index df57dbb..4afb0c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7903,9 +7903,27 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i32 tmp2 = tcg_temp_new_i32(); TCGv_i64 t64 = tcg_temp_new_i64(); - gen_aa32_ld_i64(s, t64, addr, get_mem_index(s), opc); + /* For AArch32, architecturally the 32-bit word at the lowest + * address is always Rt and the one at addr+4 is Rt2, even if + * the CPU is big-endian. That means we don't want to do a + * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if + * for an architecturally 64-bit access, but instead do a + * 64-bit access using MO_BE if appropriate and then split + * the two halves. + * This only makes a difference for BE32 user-mode, where + * frob64() must not flip the two halves of the 64-bit data + * but this code must treat BE32 user-mode like BE32 system. + */ + TCGv taddr = gen_aa32_addr(s, addr, opc); + + tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); + tcg_temp_free(taddr); tcg_gen_mov_i64(cpu_exclusive_val, t64); - tcg_gen_extr_i64_i32(tmp, tmp2, t64); + if (s->be_data == MO_BE) { + tcg_gen_extr_i64_i32(tmp2, tmp, t64); + } else { + tcg_gen_extr_i64_i32(tmp, tmp2, t64); + } tcg_temp_free_i64(t64); store_reg(s, rt2, tmp2); @@ -7954,15 +7972,26 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, TCGv_i64 n64 = tcg_temp_new_i64(); t2 = load_reg(s, rt2); - tcg_gen_concat_i32_i64(n64, t1, t2); + /* For AArch32, architecturally the 32-bit word at the lowest + * address is always Rt and the one at addr+4 is Rt2, even if + * the CPU is big-endian. Since we're going to treat this as a + * single 64-bit BE store, we need to put the two halves in the + * opposite order for BE to LE, so that they end up in the right + * places. + * We don't want gen_aa32_frob64() because that does the wrong + * thing for BE32 usermode. + */ + if (s->be_data == MO_BE) { + tcg_gen_concat_i32_i64(n64, t2, t1); + } else { + tcg_gen_concat_i32_i64(n64, t1, t2); + } tcg_temp_free_i32(t2); - gen_aa32_frob64(s, n64); tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64, get_mem_index(s), opc); tcg_temp_free_i64(n64); - gen_aa32_frob64(s, o64); tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val); tcg_gen_extrl_i64_i32(t0, o64); From patchwork Tue Nov 7 13:35:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118161 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3985478qgn; Tue, 7 Nov 2017 05:35:30 -0800 (PST) X-Google-Smtp-Source: ABhQp+S++njKz8xbDJtB2igbbiEPgfjAmcaqD0a/ytXZW+Zd+QenEZHPaht0xebEOBs8dqxkfQXE X-Received: by 10.37.115.70 with SMTP id o67mr552187ybc.303.1510061730016; Tue, 07 Nov 2017 05:35:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510061730; cv=none; d=google.com; s=arc-20160816; b=lrb3cfwtw+TSGMjXuzoSyZL9+5V3NQUWqW7GOAdO+0he7h4Usil5Ca7ayYe12WMwrd /7ZDsfgVyVsbEvGLeoJM+S/NGvPleyNkQn3aaXU20hYlBtRChAuAmlxFa4LvD9AYxw45 9G9osITjsBL1I5of69ljfXWpHQcOUInu2SlqE1nqosyT4QS4z01N5jXXpK2GW/ZXUUrn 53LCCunlxjUiYbUkp/kiSQdGQVrWGzK6XApLeDnCl84mnKGf9pj0O9bdc1GoYcmz0fti SrHST+ilTwtc9FKmi2E03kDu7AnfNHjYrux5kTTwrr2Cf1RkhNMN85QeyRXxAiyDrrLn 08jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=iCZAiAm0lQpqNoMidKvC0FU0boss9KpS4vm7r1UiyW8=; b=WmAdN1nD8aMpyNKmA1ySz90fwDXzVk8D9AOV69NxNR83iI2kUe4xWiWQO2dCQR6yK4 3rhQi3LJOi5q2Wpj7x4lcfEpqnXremeztftDPjeMN+ZizEFsvccVat9pOWl+18g2CXvf VT+ncm/X5inkn/RWh32oNBX4JSFd51jpLOSLfahcgjA4FIMOKd6ROJWeEg6hC49ewOXe AGvT+K0+VtbM7/LwGU+0cMjYQ95sfiR/cWJUp29TNnHJERVqhnlQh4xsmjFCEXxT7YQ2 anWvJfZqSavFC+zkHpmiFTtRxjmUAZUfafTpQS6gwNH5TLpmUzrtnxlp/pGXS9ORVS6w MwzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l31si283366ywh.692.2017.11.07.05.35.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:35:30 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53464 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC42L-0006eZ-Gi for patch@linaro.org; Tue, 07 Nov 2017 08:35:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41n-0006XK-Cr for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41m-0005zG-7z for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41m-0005xq-1Q for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:54 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41l-0004Uq-2o for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:21 +0000 Message-Id: <1510061722-14092-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 6/7] hw/intc/arm_gicv3_its: Fix the VM termination in vm_change_state_handler() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shanker Donthineni The commit cddafd8f353d ("hw/intc/arm_gicv3_its: Implement state save /restore") breaks the backward compatibility with the older kernels where vITS save/restore support is not available. The vmstate function vm_change_state_handler() should not be registered if the running kernel doesn't support ITS save/restore feature. Otherwise VM instance will be killed whenever vmstate callback function is invoked. Observed a virtual machine shutdown with QEMU-2.10+linux-4.11 when testing the reboot command "virsh reboot --mode acpi" instead of reboot. KVM Error: 'KVM_SET_DEVICE_ATTR failed: Group 4 attr 0x00000000000001' Signed-off-by: Shanker Donthineni Reviewed-by: Eric Auger Message-id: 1509712671-16299-1-git-send-email-shankerd@codeaurora.org Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 39903d5..9b00ce5 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -111,13 +111,13 @@ static void kvm_arm_its_realize(DeviceState *dev, Error **errp) error_free(s->migration_blocker); return; } + } else { + qemu_add_vm_change_state_handler(vm_change_state_handler, s); } kvm_msi_use_devid = true; kvm_gsi_direct_mapping = false; kvm_msi_via_irqfd_allowed = kvm_irqfds_enabled(); - - qemu_add_vm_change_state_handler(vm_change_state_handler, s); } /** From patchwork Tue Nov 7 13:35:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118166 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp3991276qgn; Tue, 7 Nov 2017 05:41:01 -0800 (PST) X-Google-Smtp-Source: ABhQp+Sq8JzGUB9pXpkGdUgo4d+FM7a4vMkCwk2s2Xd8IiNqgzEu0UMtsoiQZtGyEKqljkv/MZa0 X-Received: by 10.37.196.69 with SMTP id u66mr11049686ybf.97.1510062061382; Tue, 07 Nov 2017 05:41:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510062061; cv=none; d=google.com; s=arc-20160816; b=X/4qHt+ZtVCikwDrwsrC2241m6XeYR2CrdcQp7fQ8bQkXA7Madp2BWy3+hksOEzouD l9RFq+8Ssfx0Nlhe96MIjEPZYytymjDC3Pg7hmGPLgfXwmGPFdDVPgx3myjMdqrubl2r C2YIbZdiTWA3dw0ksqm8TiXVmezRPsXsQ9/5JONFz6y6VqKThSCpsKPBnfEFiCenVNO+ sIHqE4eJanuhvUGn8Ns/foeLINFiX89R124FuTk1B0zq9YU9ED3l/rvADlv8rwoqKtOt opIF+K6ZT9Zth9XkWVQmBct2dSjZ3+ueyGN5xDbfY/ykl7QAXknhbNeBw9v+67oTum9j HsRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=vwQpo2f9Dr49XV7wj4N8VXoGrpuQQxD0pdKoXF6NOUg=; b=s0GOxVnFAM5YJXSXMxESebIGYhKlnQipkcxnxZnd6hh+dgfyqLR7pN1m61VJoW6eTJ BZV1yGTEjNkif9weCXFUmiip5CxqcoWMFhfs+MxmFqljYOXITsxG0G4EcIb3Tgqx8pnF C8aUGaEEZauVxQZ+0XsQiMLVxXrEZN4t7iVDO7uPanKWGykpR2BNBu04FNmLB3c1mGmb h1xKlrZLm2cqBi39x7ewcDxdFUZ6juboCtDKOb5mhaaRokTJBukrw3nl7Mdp0I3U2CkM VoHy6ybVEhQ+9niPzSBmogiBpTV2tyH3AXaFFxflSDSahqgRh8+5H/BaXFVciJnrbbVs peng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id i3si277904ywf.470.2017.11.07.05.41.01 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Nov 2017 05:41:01 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC47g-0001cB-VA for patch@linaro.org; Tue, 07 Nov 2017 08:41:01 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36867) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eC41r-0006av-DJ for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:35:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eC41n-00060c-3Y for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:59 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38242) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eC41m-0005xq-T1 for qemu-devel@nongnu.org; Tue, 07 Nov 2017 08:34:55 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eC41l-0004VK-Mu for qemu-devel@nongnu.org; Tue, 07 Nov 2017 13:34:53 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Nov 2017 13:35:22 +0000 Message-Id: <1510061722-14092-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> References: <1510061722-14092-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 7/7] hw/intc/arm_gicv3_its: Don't abort on table save failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Eric Auger The ITS is not fully properly reset at the moment. Caches are not emptied. After a reset, in case we attempt to save the state before the bound devices have registered their MSIs and after the 1st level table has been allocated by the ITS driver (device BASER is valid), the first level entries are still invalid. If the device cache is not empty (devices registered before the reset), vgic_its_save_device_tables fails with -EINVAL. This causes a QEMU abort(). Cc: qemu-stable@nongnu.org Signed-off-by: Eric Auger Reported-by: wanghaibin Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 9b00ce5..6fb45df 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -64,20 +64,16 @@ static void vm_change_state_handler(void *opaque, int running, { GICv3ITSState *s = (GICv3ITSState *)opaque; Error *err = NULL; - int ret; if (running) { return; } - ret = kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, - KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); + kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL, + KVM_DEV_ARM_ITS_SAVE_TABLES, NULL, true, &err); if (err) { error_report_err(err); } - if (ret < 0 && ret != -EFAULT) { - abort(); - } } static void kvm_arm_its_realize(DeviceState *dev, Error **errp)