From patchwork Tue Jul 7 18:47:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 278261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AB08C433E0 for ; Tue, 7 Jul 2020 18:51:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3954920738 for ; Tue, 7 Jul 2020 18:51:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="Fc4yKq5s" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3954920738 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jssgG-0005lx-Eg for qemu-devel@archiver.kernel.org; Tue, 07 Jul 2020 14:51:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3S8MEXwsKCuILWOMRRIQSIRKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--hskinnemoen.bounces.google.com>) id 1jssd5-0008Qe-HP for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:43 -0400 Received: from mail-qt1-x849.google.com ([2607:f8b0:4864:20::849]:38340) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3S8MEXwsKCuILWOMRRIQSIRKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--hskinnemoen.bounces.google.com>) id 1jssd3-0007Xi-Rj for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:43 -0400 Received: by mail-qt1-x849.google.com with SMTP id 71so23357268qte.5 for ; Tue, 07 Jul 2020 11:47:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=x4zl2op1cKzABpWzOJ32Kyt+vBmeWcDSoujgoCFMWWI=; b=Fc4yKq5s3Ui3JTvioSaq1D9ezmZeTbO+onO8ukc1LzT6CYfY3bezw1nK6ThlSx99kD DcJJ9ALmT0yZaEoc/ebYuHBooaBkk3d9c1CkSWOD6pkba1rnqR3E2msTmEW0CH7oi1DI jaBqmkNuRd9RAHYZSy4fgV9+5WFrsibBKkic+y3TmH2QYbMQzxo4vG3JV/7fey5joWOg kb4X877wO9vbgI7Z3JvifQcbCEqwrLol/UIu6zi/2g8xbseaPIMQt5FNykh10kF9Bvk7 SAOXluitt8NlE/9NSbIWhts5FG+63GWwaiGn2kORxd6WyBpGvn3rWO9RnjoWc89HXs1f BqbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=x4zl2op1cKzABpWzOJ32Kyt+vBmeWcDSoujgoCFMWWI=; b=sAmqErHhJ1DIFjiwt4G/Sj4DFJEe4DQk+tWLPslkm/tWtgwMRc1hjCHnrOMPDXNjvz SoWpRfCf5YLiZDP8hmQdKklwABgM1AJWVlU1zh7Fuuus63NUXkNXg2Vwq4A5r1w2OrP/ quLLNlh0qyLJ/FGGKShrP3sGnDOj8cLIpkoTz0QrhZlvcyDRyDgUOBC8mtQDNuUvKBqV X+asLjDz2M+a7K0XoRwZELdQjXP2y7OqwWxXmBszw5MtL5jNzuDQ0hMuvGZR9kgaNxe7 assP5ML8r4escFN9MmX5XiiAwnvTjC0I6j1fhJWdIzvwvKFYMk27YTpQIVpDvt0Ishwj ZDUg== X-Gm-Message-State: AOAM530+k+2zsytksCzWpLXeqnKLE5+EkZ61x3xFUti/P6IrP5MYvbTW 6vo+uaQe7xM5aI6O1fROIcGkdVOU0WzXzBTgxA== X-Google-Smtp-Source: ABdhPJx913787MUpkXR+V6fHT/QFz1o2LIIitBWRILmqxq2MlY1FlXELdKXBc1pbZ/IrYQL407vNTOPW66fYI0UjPA== X-Received: by 2002:a0c:b2d1:: with SMTP id d17mr43471302qvf.100.1594147659912; Tue, 07 Jul 2020 11:47:39 -0700 (PDT) Date: Tue, 7 Jul 2020 11:47:19 -0700 In-Reply-To: <20200707184730.3047754-1-hskinnemoen@google.com> Message-Id: <20200707184730.3047754-2-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200707184730.3047754-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v4 01/12] npcm7xx: Add config symbol From: Havard Skinnemoen To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, philmd@redhat.com, Havard Skinnemoen , Joel Stanley Received-SPF: pass client-ip=2607:f8b0:4864:20::849; envelope-from=3S8MEXwsKCuILWOMRRIQSIRKSSKPI.GSQUIQY-HIZIPRSRKRY.SVK@flex--hskinnemoen.bounces.google.com; helo=mail-qt1-x849.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a config symbol for the NPCM7xx BMC SoC family that subsequent patches can use in Makefiles. Reviewed-by: Tyrone Ting Acked-by: Joel Stanley Signed-off-by: Havard Skinnemoen --- default-configs/arm-softmmu.mak | 1 + hw/arm/Kconfig | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak index 8fc09a4a51..9a94ebd0be 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -27,6 +27,7 @@ CONFIG_GUMSTIX=y CONFIG_SPITZ=y CONFIG_TOSA=y CONFIG_Z2=y +CONFIG_NPCM7XX=y CONFIG_COLLIE=y CONFIG_ASPEED_SOC=y CONFIG_NETDUINO2=y diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4a224a6351..a31d0d282f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -354,6 +354,14 @@ config XLNX_VERSAL select VIRTIO_MMIO select UNIMP +config NPCM7XX + bool + select A9MPCORE + select ARM_GIC + select PL310 # cache controller + select SERIAL + select UNIMP + config FSL_IMX25 bool select IMX From patchwork Tue Jul 7 18:47:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 278259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75B6BC433E0 for ; Tue, 7 Jul 2020 18:52:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 35E7E206CD for ; Tue, 7 Jul 2020 18:52:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="WH0d2HX8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 35E7E206CD Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsshx-0000VN-G0 for qemu-devel@archiver.kernel.org; Tue, 07 Jul 2020 14:52:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3U8MEXwsKCuoTeWUZZQYaQZSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--hskinnemoen.bounces.google.com>) id 1jssdD-0000GC-9a for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:51 -0400 Received: from mail-qt1-x849.google.com ([2607:f8b0:4864:20::849]:33474) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3U8MEXwsKCuoTeWUZZQYaQZSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--hskinnemoen.bounces.google.com>) id 1jssdA-0007Yu-OV for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:50 -0400 Received: by mail-qt1-x849.google.com with SMTP id g6so31408560qtr.0 for ; Tue, 07 Jul 2020 11:47:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=wl5Pn+YkkRlcDFzXeH7nsFsUbTPkR52YcN83RD2dFFg=; b=WH0d2HX8Zwv88JcW9nntSyNOV5v/6ZYcdsdVpIdlq3LzBtnuwLSnfbrJivswsaVOQr pNfnEzul6i9beNWqL2VObYcQJz9yzUNvzGbECTH4s/maM3GtkrVdrAtzzTNqXezGif2y Gdzr3gtk+4A7KY3PeepSlByDjDxxLjxE4ZQWSJADVmmFyYJjSsKUQZS7ZEgGoqwn4Zk8 2f/Dd6w829y/Dpx1jf8i0IWKKb9q4NR6B5GD01iu1n8wqiZjoV+eX5Zu3gsBLkkPUaBQ EpoKxopQi4L6ZUuljypd7RqFqm9X+iwRnZsX85KaNhbN7q1H3ZvbbSIE4I3C3Jbe8Ub1 x+Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=wl5Pn+YkkRlcDFzXeH7nsFsUbTPkR52YcN83RD2dFFg=; b=oYCuEhd251wjo1rr5qm7Hmc1U/SnNar/CmVC6xbYxvWVu/u0LlZ7OS6/VXVnpnkjUB YC92nsUI3B4YGkHMBC5V+Ffxg6Yh1vXR38/KoiZc4joeI4bz2MuhRcHJY4eFOXzV0DdH M2PjRbt26IlaYlNbA4stc+ZYlL5r2sZdQoxoaPByOps7p8L4DcD0+DjcHuo4JDRcovwE 0Q6FqhXyX6tDQQh5GR1fQkgBtg9Uwgn/bhKw/aS6eyF2jSnxijMLhvlkswuPTrXfhrSV Zjirb1sioe9z6nxq9wO9TUAzWafxnYaYjjGUHOdmqnnHN5D0miAIi7k5xfGs7ocl2Nvl L4Xg== X-Gm-Message-State: AOAM531307IW5V2zFUWpjUYGE1BXxOIQ19CDqkp+uX7XnYKYAzrngEnS Wi2Fthx6ubAB/AyfbpvWPKc4FYq//89YUq9ZYw== X-Google-Smtp-Source: ABdhPJyySivg+aoJuYwdLTp7DXRCUgQ3jeKLII8nxdMxUoTBS2PTbs81RlAa4OkLkAUYz5GuVGeWIeO5ERDJdxCfYQ== X-Received: by 2002:a05:6214:a0a:: with SMTP id dw10mr54527480qvb.200.1594147667386; Tue, 07 Jul 2020 11:47:47 -0700 (PDT) Date: Tue, 7 Jul 2020 11:47:23 -0700 In-Reply-To: <20200707184730.3047754-1-hskinnemoen@google.com> Message-Id: <20200707184730.3047754-6-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200707184730.3047754-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v4 05/12] hw/arm: Add NPCM730 and NPCM750 SoC models From: Havard Skinnemoen To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, philmd@redhat.com, Havard Skinnemoen , Joel Stanley Received-SPF: pass client-ip=2607:f8b0:4864:20::849; envelope-from=3U8MEXwsKCuoTeWUZZQYaQZSaaSXQ.OaYcQYg-PQhQXZaZSZg.adS@flex--hskinnemoen.bounces.google.com; helo=mail-qt1-x849.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Nuvoton NPCM7xx SoC family are used to implement Baseboard Management Controllers in servers. While the family includes four SoCs, this patch implements limited support for two of them: NPCM730 (targeted for Data Center applications) and NPCM750 (targeted for Enterprise applications). This patch includes little more than the bare minimum needed to boot a Linux kernel built with NPCM7xx support in direct-kernel mode: - Two Cortex-A9 CPU cores with built-in periperhals. - Global Configuration Registers. - Clock Management. - 3 Timer Modules with 5 timers each. - 4 serial ports. The chips themselves have a lot more features, some of which will be added to the model at a later stage. Reviewed-by: Tyrone Ting Reviewed-by: Joel Stanley Signed-off-by: Havard Skinnemoen --- hw/arm/Makefile.objs | 1 + hw/arm/npcm7xx.c | 328 +++++++++++++++++++++++++++++++++++++++ include/hw/arm/npcm7xx.h | 81 ++++++++++ 3 files changed, 410 insertions(+) create mode 100644 hw/arm/npcm7xx.c create mode 100644 include/hw/arm/npcm7xx.h diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 534a6a119e..13d163a599 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -41,6 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o +obj-$(CONFIG_NPCM7XX) += npcm7xx.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c new file mode 100644 index 0000000000..0a9e30f66f --- /dev/null +++ b/hw/arm/npcm7xx.c @@ -0,0 +1,328 @@ +/* + * Nuvoton NPCM7xx SoC family. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "exec/address-spaces.h" +#include "hw/arm/npcm7xx.h" +#include "hw/char/serial.h" +#include "hw/loader.h" +#include "hw/misc/unimp.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "sysemu/sysemu.h" + +/* The first half of the address space is reserved for DDR4 DRAM. */ +#define NPCM7XX_DRAM_BA (0x00000000) +#define NPCM7XX_DRAM_SZ (2 * GiB) + +/* + * This covers the whole MMIO space. We'll use this to catch any MMIO accesses + * that aren't handled by any device. + */ +#define NPCM7XX_MMIO_BA (0x80000000) +#define NPCM7XX_MMIO_SZ (0x7FFD0000) + +/* Core system modules. */ +#define NPCM7XX_L2C_BA (0xF03FC000) +#define NPCM7XX_CPUP_BA (0xF03FE000) +#define NPCM7XX_GCR_BA (0xF0800000) +#define NPCM7XX_CLK_BA (0xF0801000) + +/* Memory blocks at the end of the address space */ +#define NPCM7XX_RAM2_BA (0xFFFD0000) +#define NPCM7XX_RAM2_SZ (128 * KiB) +#define NPCM7XX_ROM_BA (0xFFFF0000) +#define NPCM7XX_ROM_SZ (64 * KiB) + +/* + * Interrupt lines going into the GIC. This does not include internal Cortex-A9 + * interrupts. + */ +enum NPCM7xxInterrupt { + NPCM7XX_UART0_IRQ = 2, + NPCM7XX_UART1_IRQ, + NPCM7XX_UART2_IRQ, + NPCM7XX_UART3_IRQ, + NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */ + NPCM7XX_TIMER1_IRQ, + NPCM7XX_TIMER2_IRQ, + NPCM7XX_TIMER3_IRQ, + NPCM7XX_TIMER4_IRQ, + NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */ + NPCM7XX_TIMER6_IRQ, + NPCM7XX_TIMER7_IRQ, + NPCM7XX_TIMER8_IRQ, + NPCM7XX_TIMER9_IRQ, + NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */ + NPCM7XX_TIMER11_IRQ, + NPCM7XX_TIMER12_IRQ, + NPCM7XX_TIMER13_IRQ, + NPCM7XX_TIMER14_IRQ, +}; + +/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */ +#define NPCM7XX_NUM_IRQ (160) + +/* Register base address for each Timer Module */ +static const hwaddr npcm7xx_tim_addr[] = { + 0xF0008000, + 0xF0009000, + 0xF000A000, +}; + +/* Register base address for each 16550 UART */ +static const hwaddr npcm7xx_uart_addr[] = { + 0xF0001000, + 0xF0002000, + 0xF0003000, + 0xF0004000, +}; + +void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* + * The default smpboot stub halts the secondary CPU with a 'wfi' + * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel + * does not send an IPI to wake it up, so the second CPU fails to boot. So + * we need to provide our own smpboot stub that can not use 'wfi', it has + * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. + */ + uint32_t smpboot[] = { + 0xe59f2018, /* ldr r2, bootreg_addr */ + 0xe3a00000, /* mov r0, #0 */ + 0xe5820000, /* str r0, [r2] */ + 0xe320f002, /* wfe */ + 0xe5921000, /* ldr r1, [r2] */ + 0xe1110001, /* tst r1, r1 */ + 0x0afffffb, /* beq */ + 0xe12fff11, /* bx r1 */ + NPCM7XX_SMP_BOOTREG_ADDR, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(smpboot); i++) { + smpboot[i] = tswap32(smpboot[i]); + } + + rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), + NPCM7XX_SMP_LOADER_START); +} + +static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) +{ + return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); +} + +static void npcm7xx_init(Object *obj) +{ + NPCM7xxState *s = NPCM7XX(obj); + int i; + + for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { + object_initialize_child(obj, "cpu[*]", &s->cpu[i], + ARM_CPU_TYPE_NAME("cortex-a9")); + } + + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); + object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); + object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), + "power-on-straps"); + object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); + + for (i = 0; i < ARRAY_SIZE(s->tim); i++) { + object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); + } +} + +static void npcm7xx_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxState *s = NPCM7XX(dev); + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); + Error *err = NULL; + int i; + + /* I/O space -- unimplemented unless overridden below. */ + create_unimplemented_device("npcm7xx.io", NPCM7XX_MMIO_BA, NPCM7XX_MMIO_SZ); + + /* CPUs */ + for (i = 0; i < nc->num_cpus; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), + arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), + "mp-affinity", &error_abort); + object_property_set_int(OBJECT(&s->cpu[i]), NPCM7XX_GIC_CPU_IF_ADDR, + "reset-cbar", &error_abort); + object_property_set_bool(OBJECT(&s->cpu[i]), true, + "reset-hivecs", &error_abort); + + /* Disable security extensions. */ + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3", NULL)) { + object_property_set_bool(OBJECT(&s->cpu[i]), false, "has_el3", + &error_abort); + } + + qdev_realize(DEVICE(&s->cpu[i]), NULL, &err); + if (err) { + error_propagate(errp, err); + return; + } + } + + /* A9MPCORE peripherals */ + object_property_set_int(OBJECT(&s->a9mpcore), nc->num_cpus, "num-cpu", + &error_abort); + object_property_set_int(OBJECT(&s->a9mpcore), NPCM7XX_NUM_IRQ, "num-irq", + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &err); + if (err) { + error_propagate(errp, err); + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); + + for (i = 0; i < nc->num_cpus; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); + } + + /* L2 cache controller */ + sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); + + /* System Global Control Registers (GCR) */ + object_property_set_int(OBJECT(&s->gcr), nc->disabled_modules, + "disabled-modules", &error_abort); + object_property_set_link(OBJECT(&s->gcr), OBJECT(s->dram), "dram", + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->gcr), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA); + + /* Clock Control Registers (CLK) */ + sysbus_realize(SYS_BUS_DEVICE(&s->clk), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); + + /* Timer Modules (TIM) */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); + for (i = 0; i < ARRAY_SIZE(s->tim); i++) { + SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]); + int first_irq; + int j; + + sysbus_realize(sbd, &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]); + + first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; + for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { + qemu_irq irq = npcm7xx_irq(s, first_irq + j); + sysbus_connect_irq(sbd, j, irq); + } + } + + /* UART0..3 (16550 compatible) */ + for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) { + serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2, + npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200, + serial_hd(i), DEVICE_LITTLE_ENDIAN); + } + + /* RAM2 (SRAM) */ + memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", + NPCM7XX_RAM2_SZ, &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram); + + /* Internal ROM */ + memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ, &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom); + + /* External DDR4 SDRAM */ + memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, s->dram); +} + +static Property npcm7xx_properties[] = { + DEFINE_PROP_LINK("dram", NPCM7xxState, dram, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm7xx_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = npcm7xx_realize; + dc->user_creatable = false; + device_class_set_props(dc, npcm7xx_properties); +} + +static void npcm730_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxClass *nc = NPCM7XX_CLASS(oc); + + /* NPCM730 is optimized for data center use, so no graphics, etc. */ + nc->disabled_modules = 0x00300395; + nc->num_cpus = 2; +} + +static void npcm750_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxClass *nc = NPCM7XX_CLASS(oc); + + /* NPCM750 has 2 cores and a full set of peripherals */ + nc->disabled_modules = 0x00000000; + nc->num_cpus = 2; +} + +static const TypeInfo npcm7xx_soc_types[] = { + { + .name = TYPE_NPCM7XX, + .parent = TYPE_DEVICE, + .instance_size = sizeof(NPCM7xxState), + .instance_init = npcm7xx_init, + .class_size = sizeof(NPCM7xxClass), + .class_init = npcm7xx_class_init, + .abstract = true, + }, { + .name = TYPE_NPCM730, + .parent = TYPE_NPCM7XX, + .class_init = npcm730_class_init, + }, { + .name = TYPE_NPCM750, + .parent = TYPE_NPCM7XX, + .class_init = npcm750_class_init, + }, +}; + +DEFINE_TYPES(npcm7xx_soc_types); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h new file mode 100644 index 0000000000..2ffa573b11 --- /dev/null +++ b/include/hw/arm/npcm7xx.h @@ -0,0 +1,81 @@ +/* + * Nuvoton NPCM7xx SoC family. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_H +#define NPCM7XX_H + +#include "hw/boards.h" +#include "hw/cpu/a9mpcore.h" +#include "hw/misc/npcm7xx_clk.h" +#include "hw/misc/npcm7xx_gcr.h" +#include "hw/timer/npcm7xx_timer.h" +#include "target/arm/cpu.h" + +#define NPCM7XX_MAX_NUM_CPUS (2) + +/* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ +#define NPCM7XX_LOADER_START (0x00000000) /* Start of SDRAM */ +#define NPCM7XX_SMP_LOADER_START (0xFFFF0000) /* Boot ROM */ +#define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */ +#define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */ + +typedef struct NPCM7xxState { + DeviceState parent; + + ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; + A9MPPrivState a9mpcore; + + MemoryRegion sram; + MemoryRegion irom; + MemoryRegion *dram; + + NPCM7xxGCRState gcr; + NPCM7xxCLKState clk; + NPCM7xxTimerCtrlState tim[3]; +} NPCM7xxState; + +#define TYPE_NPCM7XX "npcm7xx" +#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX) + +#define TYPE_NPCM730 "npcm730" +#define TYPE_NPCM750 "npcm750" + +typedef struct NPCM7xxClass { + DeviceClass parent; + + /* Bitmask of modules that are permanently disabled on this chip. */ + uint32_t disabled_modules; + /* Number of CPU cores enabled in this SoC class (may be 1 or 2). */ + uint32_t num_cpus; +} NPCM7xxClass; + +#define NPCM7XX_CLASS(klass) \ + OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX) +#define NPCM7XX_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX) + +/** + * npcm7xx_write_secondary_boot - Write stub for booting secondary CPU. + * @cpu: The CPU to be booted. + * @info: Boot info structure for the board. + * + * This will write a short code stub to the internal ROM that will keep the + * secondary CPU spinning until the primary CPU writes an address to the SCRPAD + * register in the GCR, after which the secondary CPU will jump there. + */ +extern void npcm7xx_write_secondary_boot(ARMCPU *cpu, + const struct arm_boot_info *info); + +#endif /* NPCM7XX_H */ From patchwork Tue Jul 7 18:47:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 278258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-22.4 required=3.0 tests=DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9D27C433E0 for ; Tue, 7 Jul 2020 18:54:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7AC1A206CD for ; Tue, 7 Jul 2020 18:54:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="DqwnYP5q" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7AC1A206CD Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:55744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jssjC-00039v-Og for qemu-devel@archiver.kernel.org; Tue, 07 Jul 2020 14:54:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3VsMEXwsKCu0WhZXccTbdTcVddVaT.RdbfTbj-STkTacdcVcj.dgV@flex--hskinnemoen.bounces.google.com>) id 1jssdG-0000Ng-H6 for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:54 -0400 Received: from mail-qt1-x84a.google.com ([2607:f8b0:4864:20::84a]:38342) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3VsMEXwsKCu0WhZXccTbdTcVddVaT.RdbfTbj-STkTacdcVcj.dgV@flex--hskinnemoen.bounces.google.com>) id 1jssdE-0007ar-33 for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:54 -0400 Received: by mail-qt1-x84a.google.com with SMTP id 71so23357556qte.5 for ; Tue, 07 Jul 2020 11:47:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=VbDO2mkLoftcJxkNlO9sINkU2IM/6wHFBs/gYcP1ZDQ=; b=DqwnYP5q06qqVSvqj+cNub5kNydEGIA5OCMspBQtFQqIOXOD3s5Zd3tCOmf8tfgP8t 8NCXWNZpOUEHsLv7e+7lQqYiz6YY1O5vvplm+NuhBHln3Lk/P2vadJiqriBeCV25YKqS Hw3Kj/L8sYSELg/KugyeAdF7hPTudTqX9IsFgv2Y4h9uPan+gtPccgLgXOmYp+qZUfDA FfZ7Yq3w+krgZRNVrBDvzJH72a04PoTaUGQHJkiiIDUL+c/zlVEi7mVEdLw1t20dlxOH a9uUIrnFaUIXYLWLBMbAT2iq9VvJoeFNvgaeKAFWgecqiX6IJ3BMZScjQ9WRMsm5USl/ G4cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=VbDO2mkLoftcJxkNlO9sINkU2IM/6wHFBs/gYcP1ZDQ=; b=ahIdADl0F6awcMB7kJd47V3KOclqGDkrnk5BGunQtv2yqVIapbStw518T9PZM8Dwen qJt+jZincpayjjKVmfNyhWW/0QAD1rxxfPBAW7TgyP1c+a/7nuy5vOOOwGnaVrH5n0J5 Ur8ifxgBNN9ps3c/CuOdLrCKuBeTWz7BzmF+RRc7j5R6LhUdKRAgogzNt4+AX+tSZerr p0TINLfKQIsxSDilOsxm44shSsfMlgHx/JApt2LUJ7POkr8gOEF5xzYEtY/pVDGZ15Wi JmDaFqsuMPw5NL9WtsEgqQizKNnUvOnCkQyOB8E3habXhInKtBU+DqX6Wfr+vUZzOXL4 U6Xw== X-Gm-Message-State: AOAM533ZtT0WOWDgUs0XKNV8ffCdjvTTrK/CrqrjbEKzfsonCtkN9vKE SYfRk2PWrCXlIFGuNrq7syFjyooqnh3Bt3t84w== X-Google-Smtp-Source: ABdhPJx9Mhu5SqfL9FLfxzy8fWoCnvCz8BdFs1nUMdVziaqhzB59FARX+Q6Hb8e3dxIhPKAjFKpvvcilALZIWhht6g== X-Received: by 2002:ad4:57c4:: with SMTP id y4mr51685670qvx.230.1594147670847; Tue, 07 Jul 2020 11:47:50 -0700 (PDT) Date: Tue, 7 Jul 2020 11:47:25 -0700 In-Reply-To: <20200707184730.3047754-1-hskinnemoen@google.com> Message-Id: <20200707184730.3047754-8-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200707184730.3047754-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v4 07/12] hw/arm: Load -bios image as a boot ROM for npcm7xx From: Havard Skinnemoen To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, philmd@redhat.com, Havard Skinnemoen Received-SPF: pass client-ip=2607:f8b0:4864:20::84a; envelope-from=3VsMEXwsKCu0WhZXccTbdTcVddVaT.RdbfTbj-STkTacdcVcj.dgV@flex--hskinnemoen.bounces.google.com; helo=mail-qt1-x84a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" If a -bios option is specified on the command line, load the image into the internal ROM memory region, which contains the first instructions run by the CPU after reset. A minimal Apache-2.0-licensed boot ROM can be found at https://github.com/google/vbootrom It is by no means feature complete, but it is enough to launch the Nuvoton bootblock[1] from offset 0 in the flash, which in turn will launch u-boot and finally the Linux kernel. [1] https://github.com/Nuvoton-Israel/bootblock Reviewed-by: Tyrone Ting Signed-off-by: Havard Skinnemoen --- hw/arm/npcm7xx_boards.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 205243cde6..de2d2ca786 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -19,8 +19,11 @@ #include "hw/arm/boot.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" +#include "hw/loader.h" #include "qapi/error.h" +#include "qemu-common.h" #include "qemu/units.h" +#include "sysemu/sysemu.h" #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff @@ -34,6 +37,25 @@ static struct arm_boot_info npcm7xx_binfo = { .board_id = -1, }; +static void npcm7xx_load_bootrom(NPCM7xxState *soc) +{ + if (bios_name) { + g_autofree char *filename = NULL; + int ret; + + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); + if (!filename) { + error_report("Could not find ROM image '%s'", bios_name); + exit(1); + } + ret = load_image_mr(filename, &soc->irom); + if (ret < 0) { + error_report("Failed to load ROM image '%s'", filename); + exit(1); + } + } +} + static void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) { NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); @@ -66,7 +88,7 @@ static void npcm750_evb_init(MachineState *machine) NPCM7xxState *soc; soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); - + npcm7xx_load_bootrom(soc); npcm7xx_load_kernel(machine, soc); } @@ -75,7 +97,7 @@ static void quanta_gsj_init(MachineState *machine) NPCM7xxState *soc; soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); - + npcm7xx_load_bootrom(soc); npcm7xx_load_kernel(machine, soc); } From patchwork Tue Jul 7 18:47:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 278260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED698C433E0 for ; Tue, 7 Jul 2020 18:51:02 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0536206CD for ; Tue, 7 Jul 2020 18:51:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="GBEQiYMH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0536206CD Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jssgH-0005pY-U7 for qemu-devel@archiver.kernel.org; Tue, 07 Jul 2020 14:51:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3WMMEXwsKCu8YjbZeeVdfVeXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--hskinnemoen.bounces.google.com>) id 1jssdJ-0000WH-VG for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:57 -0400 Received: from mail-yb1-xb49.google.com ([2607:f8b0:4864:20::b49]:41478) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3WMMEXwsKCu8YjbZeeVdfVeXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--hskinnemoen.bounces.google.com>) id 1jssdG-0007b9-K2 for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:57 -0400 Received: by mail-yb1-xb49.google.com with SMTP id i4so22377859ybh.8 for ; Tue, 07 Jul 2020 11:47:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=UwW/ulHwrSaFkbNaXRtduq4/uqpdDkuDsZbHdM+C1s0=; b=GBEQiYMHqCPtHowEZnV2qQ47gj2XTECTVToOyMi2e8d7DosvOYis7hrGNW0Fey/hdN ZVKNyw38ZuHQgMhDyo69mdM1349CYFm1oc3/N+Vft5WOz+rcbd3Bl9dQu0qLguC/pUJ5 wgD3BkVpOGg3kLnlXy9kOQ+FE0tUsN1POewi3iF5x5G+N7XtWgr8TuCGFGxX4hbavlPv 0aEo1z182zTyIM9PAH+xTAh4CxHPXQ5MKBdqfEz1JPZwDmcLGWOu5fDUtb2em3CQUFCd ztvZShYHiEw0G6ic79S76xKPGgi+n56qaH/ggeTJXliy1/ir9AcaSENu2LeztZQDEDAM sG5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=UwW/ulHwrSaFkbNaXRtduq4/uqpdDkuDsZbHdM+C1s0=; b=Xa8H9rG7OBW1cdONJm7NR26qqmezzbBV4R/ugc8d8fdtNLMXz4wBTOHa4XqGt1iLfm 5gbmpwSe39gKBTr+EnHWkIIDkyfV12mmRRoCpePKawUHg+pnOkMcEL/yp0o6zXMRkK/j POAYpEuyKoXiFwCaiXYxooEpfz3WBVB5zo0jBV+xaLaBfFfBBBgZT4CXpCbv2IKjxJhC I0/or6bIRMoEpuHK5BJrZszKyOOl/1uJKv65jFRagg24MM4HeHBcxzs6TYofuLKEf5dG C35BqGAx7+5Vv9kMnR4Ma7Cg8q/a9uchATNhhZSbgrOP8foyRCP+9it4qUs9sidCwROO FEAA== X-Gm-Message-State: AOAM530EMJo8fDklqclCnaC2X85i6EQILeYQztggnxnJGbkBSA1NLwrY fZzKRS13DLfGp1ZU2Obo+OIX0M0h84mP/GH9Og== X-Google-Smtp-Source: ABdhPJxkUhkuBRcZFbjR+NEKi6lswcHAJa1LSzQ+CDQffRn/v0D4/lHLcFsorBo5GDg1UCWHJeXxKBsCTylLiIF/pg== X-Received: by 2002:a25:70c2:: with SMTP id l185mr28141118ybc.83.1594147672792; Tue, 07 Jul 2020 11:47:52 -0700 (PDT) Date: Tue, 7 Jul 2020 11:47:26 -0700 In-Reply-To: <20200707184730.3047754-1-hskinnemoen@google.com> Message-Id: <20200707184730.3047754-9-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200707184730.3047754-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v4 08/12] hw/nvram: NPCM7xx OTP device model From: Havard Skinnemoen To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, philmd@redhat.com, Havard Skinnemoen , Avi Fishman Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3WMMEXwsKCu8YjbZeeVdfVeXffXcV.TfdhVdl-UVmVcefeXel.fiX@flex--hskinnemoen.bounces.google.com; helo=mail-yb1-xb49.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman Signed-off-by: Havard Skinnemoen --- hw/arm/npcm7xx.c | 32 +++ hw/nvram/Makefile.objs | 1 + hw/nvram/npcm7xx_otp.c | 405 +++++++++++++++++++++++++++++++++ include/hw/arm/npcm7xx.h | 3 + include/hw/nvram/npcm7xx_otp.h | 94 ++++++++ 5 files changed, 535 insertions(+) create mode 100644 hw/nvram/npcm7xx_otp.c create mode 100644 include/hw/nvram/npcm7xx_otp.h diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 0a9e30f66f..71cc141f3c 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -37,6 +37,10 @@ #define NPCM7XX_MMIO_BA (0x80000000) #define NPCM7XX_MMIO_SZ (0x7FFD0000) +/* OTP key storage and fuse strap array */ +#define NPCM7XX_OTP1_BA (0xF0189000) +#define NPCM7XX_OTP2_BA (0xF018A000) + /* Core system modules. */ #define NPCM7XX_L2C_BA (0xF03FC000) #define NPCM7XX_CPUP_BA (0xF03FE000) @@ -123,6 +127,15 @@ void npcm7xx_write_secondary_boot(ARMCPU *cpu, const struct arm_boot_info *info) NPCM7XX_SMP_LOADER_START); } +static void npcm7xx_init_fuses(NPCM7xxState *s) +{ + NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s); + uint32_t value; + + value = tswap32(nc->disabled_modules); + npcm7xx_otp_array_write(&s->fuse_array, &value, 64, sizeof(value)); +} + static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n) { return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n); @@ -143,6 +156,10 @@ static void npcm7xx_init(Object *obj) object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), "power-on-straps"); object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK); + object_initialize_child(obj, "otp1", &s->key_storage, + TYPE_NPCM7XX_KEY_STORAGE); + object_initialize_child(obj, "otp2", &s->fuse_array, + TYPE_NPCM7XX_FUSE_ARRAY); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); @@ -223,6 +240,21 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) } sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA); + /* OTP key storage and fuse strap array */ + sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA); + sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); + npcm7xx_init_fuses(s); + /* Timer Modules (TIM) */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { diff --git a/hw/nvram/Makefile.objs b/hw/nvram/Makefile.objs index f3ad921382..0270f0bbf7 100644 --- a/hw/nvram/Makefile.objs +++ b/hw/nvram/Makefile.objs @@ -4,5 +4,6 @@ common-obj-$(CONFIG_AT24C) += eeprom_at24c.o common-obj-y += fw_cfg.o common-obj-$(CONFIG_CHRP_NVRAM) += chrp_nvram.o common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o +common-obj-$(CONFIG_NPCM7XX) += npcm7xx_otp.o common-obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o obj-$(CONFIG_PSERIES) += spapr_nvram.o diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c new file mode 100644 index 0000000000..18908bc839 --- /dev/null +++ b/hw/nvram/npcm7xx_otp.c @@ -0,0 +1,405 @@ +/* + * Nuvoton NPCM7xx OTP (Fuse Array) Interface + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/nvram/npcm7xx_otp.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +/* Each module has 4 KiB of register space. Only a fraction of it is used. */ +#define NPCM7XX_OTP_REGS_SIZE (4 * KiB) + +/* Register field definitions. */ +#define FST_RIEN BIT(2) +#define FST_RDST BIT(1) +#define FST_RDY BIT(0) +#define FST_RO_MASK (FST_RDST | FST_RDY) + +#define FADDR_BYTEADDR(rv) extract32((rv), 0, 10) +#define FADDR_BITPOS(rv) extract32((rv), 10, 3) + +#define FDATA_CLEAR 0x00000001 + +#define FCFG_FDIS BIT(31) +#define FCFG_FCFGLK_MASK 0x00ff0000 + +#define FCTL_PROG_CMD1 0x00000001 +#define FCTL_PROG_CMD2 0xbf79e5d0 +#define FCTL_READ_CMD 0x00000002 + +static uint8_t ecc_encode_nibble(uint8_t n) +{ + uint8_t result = n; + + result |= (((n >> 0) & 1) ^ ((n >> 1) & 1)) << 4; + result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5; + result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6; + result |= (((n >> 1) & 1) ^ ((n >> 3) & 1)) << 7; + + return result; +} + +void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, + unsigned int offset, unsigned int len) +{ + const uint8_t *src = data; + uint8_t *dst = &s->array[offset]; + + while (len-- > 0) { + uint8_t c = *src++; + + *dst++ = ecc_encode_nibble(extract8(c, 0, 4)); + *dst++ = ecc_encode_nibble(extract8(c, 4, 4)); + } +} + +/* Common register read handler for both OTP classes. */ +static uint64_t npcm7xx_otp_read(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg) +{ + uint32_t value = 0; + + switch (reg) { + case NPCM7XX_OTP_FST: + case NPCM7XX_OTP_FADDR: + case NPCM7XX_OTP_FDATA: + case NPCM7XX_OTP_FCFG: + value = s->regs[reg]; + break; + + case NPCM7XX_OTP_FCTL: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from write-only FCTL register\n", + DEVICE(s)->canonical_path); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: read from invalid offset 0x%zx\n", + DEVICE(s)->canonical_path, reg * sizeof(uint32_t)); + break; + } + + return value; +} + +/* Read a byte from the OTP array into the data register. */ +static void npcm7xx_otp_read_array(NPCM7xxOTPState *s) +{ + uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR]; + + s->regs[NPCM7XX_OTP_FDATA] = s->array[FADDR_BYTEADDR(faddr)]; + s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY; +} + +/* Program a byte from the data register into the OTP array. */ +static void npcm7xx_otp_program_array(NPCM7xxOTPState *s) +{ + uint32_t faddr = s->regs[NPCM7XX_OTP_FADDR]; + + /* Bits can only go 0->1, never 1->0. */ + s->array[FADDR_BYTEADDR(faddr)] |= (1U << FADDR_BITPOS(faddr)); + s->regs[NPCM7XX_OTP_FST] |= FST_RDST | FST_RDY; +} + +/* Compute the next value of the FCFG register. */ +static uint32_t npcm7xx_otp_compute_fcfg(uint32_t cur_value, uint32_t new_value) +{ + uint32_t lock_mask; + uint32_t value; + + /* + * FCFGLK holds sticky bits 16..23, indicating which bits in FPRGLK (8..15) + * and FRDLK (0..7) that are read-only. + */ + lock_mask = (cur_value & FCFG_FCFGLK_MASK) >> 8; + lock_mask |= lock_mask >> 8; + /* FDIS and FCFGLK bits are sticky (write 1 to set; can't clear). */ + value = cur_value & (FCFG_FDIS | FCFG_FCFGLK_MASK); + /* Preserve read-only bits in FPRGLK and FRDLK */ + value |= cur_value & lock_mask; + /* Set all bits that aren't read-only. */ + value |= new_value & ~lock_mask; + + return value; +} + +/* Common register write handler for both OTP classes. */ +static void npcm7xx_otp_write(NPCM7xxOTPState *s, NPCM7xxOTPRegister reg, + uint32_t value) +{ + switch (reg) { + case NPCM7XX_OTP_FST: + /* RDST is cleared by writing 1 to it. */ + if (value & FST_RDST) { + s->regs[NPCM7XX_OTP_FST] &= ~FST_RDST; + } + /* Preserve read-only and write-one-to-clear bits */ + value = + (value & ~FST_RO_MASK) | (s->regs[NPCM7XX_OTP_FST] & FST_RO_MASK); + break; + + case NPCM7XX_OTP_FADDR: + break; + + case NPCM7XX_OTP_FDATA: + /* + * This register is cleared by writing a magic value to it; no other + * values can be written. + */ + if (value == FDATA_CLEAR) { + value = 0; + } else { + value = s->regs[NPCM7XX_OTP_FDATA]; + } + break; + + case NPCM7XX_OTP_FCFG: + value = npcm7xx_otp_compute_fcfg(s->regs[NPCM7XX_OTP_FCFG], value); + break; + + case NPCM7XX_OTP_FCTL: + switch (value) { + case FCTL_READ_CMD: + npcm7xx_otp_read_array(s); + break; + + case FCTL_PROG_CMD1: + /* + * Programming requires writing two separate magic values to this + * register; this is the first one. Just store it so it can be + * verified later when the second magic value is received. + */ + break; + + case FCTL_PROG_CMD2: + /* + * Only initiate programming if we received the first half of the + * command immediately before this one. + */ + if (s->regs[NPCM7XX_OTP_FCTL] == FCTL_PROG_CMD1) { + npcm7xx_otp_program_array(s); + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: unrecognized FCNTL value 0x%" PRIx32 "\n", + DEVICE(s)->canonical_path, value); + break; + } + if (value != FCTL_PROG_CMD1) { + value = 0; + } + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: write to invalid offset 0x%zx\n", + DEVICE(s)->canonical_path, reg * sizeof(uint32_t)); + return; + } + + s->regs[reg] = value; +} + +/* Register read handler specific to the fuse array OTP module. */ +static uint64_t npcm7xx_fuse_array_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t); + NPCM7xxOTPState *s = opaque; + uint32_t value; + + /* + * Only the Fuse Strap register needs special handling; all other registers + * work the same way for both kinds of OTP modules. + */ + if (reg != NPCM7XX_OTP_FUSTRAP) { + value = npcm7xx_otp_read(s, reg); + } else { + /* FUSTRAP is stored as three copies in the OTP array. */ + uint32_t fustrap[3]; + + memcpy(fustrap, &s->array[0], sizeof(fustrap)); + + /* Determine value by a majority vote on each bit. */ + value = (fustrap[0] & fustrap[1]) | (fustrap[0] & fustrap[2]) | + (fustrap[1] & fustrap[2]); + } + + return value; +} + +/* Register write handler specific to the fuse array OTP module. */ +static void npcm7xx_fuse_array_write(void *opaque, hwaddr addr, uint64_t v, + unsigned int size) +{ + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t); + NPCM7xxOTPState *s = opaque; + + /* + * The Fuse Strap register is read-only. Other registers are handled by + * common code. + */ + if (reg != NPCM7XX_OTP_FUSTRAP) { + npcm7xx_otp_write(s, reg, v); + } +} + +static const MemoryRegionOps npcm7xx_fuse_array_ops = { + .read = npcm7xx_fuse_array_read, + .write = npcm7xx_fuse_array_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +/* Register read handler specific to the key storage OTP module. */ +static uint64_t npcm7xx_key_storage_read(void *opaque, hwaddr addr, + unsigned int size) +{ + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t); + NPCM7xxOTPState *s = opaque; + + /* + * Only the Fuse Key Index register needs special handling; all other + * registers work the same way for both kinds of OTP modules. + */ + if (reg != NPCM7XX_OTP_FKEYIND) { + return npcm7xx_otp_read(s, reg); + } + + qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__); + + return s->regs[NPCM7XX_OTP_FKEYIND]; +} + +/* Register write handler specific to the key storage OTP module. */ +static void npcm7xx_key_storage_write(void *opaque, hwaddr addr, uint64_t v, + unsigned int size) +{ + NPCM7xxOTPRegister reg = addr / sizeof(uint32_t); + NPCM7xxOTPState *s = opaque; + + /* + * Only the Fuse Key Index register needs special handling; all other + * registers work the same way for both kinds of OTP modules. + */ + if (reg != NPCM7XX_OTP_FKEYIND) { + npcm7xx_otp_write(s, reg, v); + return; + } + + qemu_log_mask(LOG_UNIMP, "%s: FKEYIND is not implemented\n", __func__); + + s->regs[NPCM7XX_OTP_FKEYIND] = v; +} + +static const MemoryRegionOps npcm7xx_key_storage_ops = { + .read = npcm7xx_key_storage_read, + .write = npcm7xx_key_storage_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void npcm7xx_otp_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxOTPState *s = NPCM7XX_OTP(obj); + + memset(s->regs, 0, sizeof(s->regs)); + + s->regs[NPCM7XX_OTP_FST] = 0x00000001; + s->regs[NPCM7XX_OTP_FCFG] = 0x20000000; +} + +static void npcm7xx_otp_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev); + NPCM7xxOTPState *s = NPCM7XX_OTP(dev); + SysBusDevice *sbd = &s->parent; + + memset(s->array, 0, sizeof(s->array)); + + memory_region_init_io(&s->mmio, OBJECT(s), oc->mmio_ops, s, "regs", + NPCM7XX_OTP_REGS_SIZE); + sysbus_init_mmio(sbd, &s->mmio); +} + +static const VMStateDescription vmstate_npcm7xx_otp = { + .name = "npcm7xx-otp", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, NPCM7xxOTPState, NPCM7XX_OTP_NR_REGS), + VMSTATE_UINT8_ARRAY(array, NPCM7xxOTPState, NPCM7XX_OTP_ARRAY_BYTES), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_otp_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = npcm7xx_otp_realize; + dc->vmsd = &vmstate_npcm7xx_otp; + rc->phases.enter = npcm7xx_otp_enter_reset; +} + +static void npcm7xx_key_storage_class_init(ObjectClass *klass, void *data) +{ + NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass); + + oc->mmio_ops = &npcm7xx_key_storage_ops; +} + +static void npcm7xx_fuse_array_class_init(ObjectClass *klass, void *data) +{ + NPCM7xxOTPClass *oc = NPCM7XX_OTP_CLASS(klass); + + oc->mmio_ops = &npcm7xx_fuse_array_ops; +} + +static const TypeInfo npcm7xx_otp_types[] = { + { + .name = TYPE_NPCM7XX_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxOTPState), + .class_init = npcm7xx_otp_class_init, + .abstract = true, + }, + { + .name = TYPE_NPCM7XX_KEY_STORAGE, + .parent = TYPE_NPCM7XX_OTP, + .class_init = npcm7xx_key_storage_class_init, + }, + { + .name = TYPE_NPCM7XX_FUSE_ARRAY, + .parent = TYPE_NPCM7XX_OTP, + .class_init = npcm7xx_fuse_array_class_init, + }, +}; +DEFINE_TYPES(npcm7xx_otp_types); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index e25f5752d7..2f2d44aad7 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -20,6 +20,7 @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" +#include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "target/arm/cpu.h" @@ -63,6 +64,8 @@ typedef struct NPCM7xxState { NPCM7xxGCRState gcr; NPCM7xxCLKState clk; NPCM7xxTimerCtrlState tim[3]; + NPCM7xxOTPState key_storage; + NPCM7xxOTPState fuse_array; } NPCM7xxState; #define TYPE_NPCM7XX "npcm7xx" diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h new file mode 100644 index 0000000000..b52330dadc --- /dev/null +++ b/include/hw/nvram/npcm7xx_otp.h @@ -0,0 +1,94 @@ +/* + * Nuvoton NPCM7xx OTP (Fuse Array) Interface + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_OTP_H +#define NPCM7XX_OTP_H + +#include "exec/memory.h" +#include "hw/sysbus.h" + +/* Each OTP module holds 8192 bits of one-time programmable storage */ +#define NPCM7XX_OTP_ARRAY_BITS (8192) +#define NPCM7XX_OTP_ARRAY_BYTES (NPCM7XX_OTP_ARRAY_BITS / 8) + +/** + * enum NPCM7xxOTPRegister - 32-bit register indices. + */ +typedef enum NPCM7xxOTPRegister { + NPCM7XX_OTP_FST, + NPCM7XX_OTP_FADDR, + NPCM7XX_OTP_FDATA, + NPCM7XX_OTP_FCFG, + /* Offset 0x10 is FKEYIND in OTP1, FUSTRAP in OTP2 */ + NPCM7XX_OTP_FKEYIND = 0x0010 / sizeof(uint32_t), + NPCM7XX_OTP_FUSTRAP = 0x0010 / sizeof(uint32_t), + NPCM7XX_OTP_FCTL, + NPCM7XX_OTP_NR_REGS, +} NPCM7xxOTPRegister; + +/** + * struct NPCM7xxOTPState - Device state for one OTP module. + * @parent: System bus device. + * @mmio: Memory region through which registers are accessed. + * @regs: Register contents. + * @array: OTP storage array. + */ +typedef struct NPCM7xxOTPState { + SysBusDevice parent; + + MemoryRegion mmio; + uint32_t regs[NPCM7XX_OTP_NR_REGS]; + uint8_t array[NPCM7XX_OTP_ARRAY_BYTES]; +} NPCM7xxOTPState; + +#define TYPE_NPCM7XX_OTP "npcm7xx-otp" +#define NPCM7XX_OTP(obj) OBJECT_CHECK(NPCM7xxOTPState, (obj), TYPE_NPCM7XX_OTP) + +#define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage" +#define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array" + +/** + * struct NPCM7xxOTPClass - OTP module class. + * @parent: System bus device class. + * @mmio_ops: MMIO register operations for this type of module. + * + * The two OTP modules (key-storage and fuse-array) have slightly different + * behavior, so we give them different MMIO register operations. + */ +typedef struct NPCM7xxOTPClass { + SysBusDeviceClass parent; + + const MemoryRegionOps *mmio_ops; +} NPCM7xxOTPClass; + +#define NPCM7XX_OTP_CLASS(klass) \ + OBJECT_CLASS_CHECK(NPCM7xxOTPClass, (klass), TYPE_NPCM7XX_OTP) +#define NPCM7XX_OTP_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NPCM7xxOTPClass, (obj), TYPE_NPCM7XX_OTP) + +/** + * npcm7xx_otp_array_write - ECC encode and write data to OTP array. + * @s: OTP module. + * @data: Data to be encoded and written. + * @offset: Offset of first byte to be written in the OTP array. + * @len: Number of bytes before ECC encoding. + * + * Each nibble of data is encoded into a byte, so the number of bytes written + * to the array will be @len * 2. + */ +extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, + unsigned int offset, unsigned int len); + +#endif /* NPCM7XX_OTP_H */ From patchwork Tue Jul 7 18:47:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 278257 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FE50C433DF for ; Tue, 7 Jul 2020 18:55:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4CD75206CD for ; Tue, 7 Jul 2020 18:55:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="WzyaXhHy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4CD75206CD Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:33432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jsskd-0005YX-JM for qemu-devel@archiver.kernel.org; Tue, 07 Jul 2020 14:55:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3WsMEXwsKCvEaldbggXfhXgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--hskinnemoen.bounces.google.com>) id 1jssdL-0000Zd-CU for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:59 -0400 Received: from mail-yb1-xb4a.google.com ([2607:f8b0:4864:20::b4a]:44961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3WsMEXwsKCvEaldbggXfhXgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--hskinnemoen.bounces.google.com>) id 1jssdI-0007bc-4F for qemu-devel@nongnu.org; Tue, 07 Jul 2020 14:47:59 -0400 Received: by mail-yb1-xb4a.google.com with SMTP id k127so43700376ybk.11 for ; Tue, 07 Jul 2020 11:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=UbC22jahfl+w2uRvEhSFpeDwZfsnpqdU4TMex24g6uU=; b=WzyaXhHy679UIcGYn3w63fKuiuHTp91yg7ugQeY9e/dSc86KSTqypUFG9Sd+qQTm1w 7pMomgbPwDIReol37U3/rPLGCBs4h1HwOVq9FFwzgPsz1AqyUpx8ylT61ZwltJQ9B+w8 IQxhSmRYz5mApwRw9SS8gBjh8y0MsDa2UfEj4PqLmobyJwxCA822OUExhCa5DU4EjTjy foOMyxAeaWILK4h8x+TZWEIqMOZTAPaJk1DrYUG78f5k2YIBIgxkTkaI20xnFWON+1Df Va9khUM49l9OoxpmvzGmyj1zWWTc4FymWSflkuprvkYFBB7EQCWGGnD+SFRwG/mbWhUX oQEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=UbC22jahfl+w2uRvEhSFpeDwZfsnpqdU4TMex24g6uU=; b=gGnr4pMP9j1cf87rCECs7xy9S86RU4ln/wO8hnfnJvrkQmCmJ776deTzO8SIwPkqCq 4GWzSfEVr5l0oi2tNC/DJGtl+/EjnNbY4BO5UH088qoAxVdDy4evB66u/vZCU9uMGne8 DTlh2BSALfE3CFO3rBagESNB/606TMQMLDdfUizqeTPJvGFmclZdOaOcBrn/AJ9aUeba +J3E1rpX99a8iHg1AbXvJelSotI/EWFokmAt1kF7xj4tWtyPeYrSnytaRhHPgwLjpyt5 +/TaEPds+fD1z3C5HHtWGhCyqdByGeBq5B/+BsYRTTO8HxZLk/OvyT6v2otdppkryrfx XO7g== X-Gm-Message-State: AOAM532Gp/2uvhifp5iU/pin+qI/By/2lKEg6XSk+aLcMVPkpLqowdqe otZAhvhKLhoVDOfDNoteV/vIaFBa5kf0wZTWrA== X-Google-Smtp-Source: ABdhPJwsMM07IsTg1wVMrUUJkoySvcGpVvtm+bgWSs9GKWpWAo3Uu73oKHkcvbUCIlBMjV7B2e3Af0t72HEwopryXw== X-Received: by 2002:a05:6902:1002:: with SMTP id w2mr43447327ybt.321.1594147674664; Tue, 07 Jul 2020 11:47:54 -0700 (PDT) Date: Tue, 7 Jul 2020 11:47:27 -0700 In-Reply-To: <20200707184730.3047754-1-hskinnemoen@google.com> Message-Id: <20200707184730.3047754-10-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200707184730.3047754-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v4 09/12] hw/mem: Stubbed out NPCM7xx Memory Controller model From: Havard Skinnemoen To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, philmd@redhat.com, Havard Skinnemoen , "=?UTF-8?q?C=C3=A9dric=20Le=20Goater?=" Received-SPF: pass client-ip=2607:f8b0:4864:20::b4a; envelope-from=3WsMEXwsKCvEaldbggXfhXgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--hskinnemoen.bounces.google.com; helo=mail-yb1-xb4a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This just implements the bare minimum to cause the boot block to skip memory initialization. Reviewed-by: Tyrone Ting Reviewed-by: Cédric Le Goater Signed-off-by: Havard Skinnemoen --- hw/arm/npcm7xx.c | 10 +++++ hw/mem/Makefile.objs | 1 + hw/mem/npcm7xx_mc.c | 84 +++++++++++++++++++++++++++++++++++++ include/hw/arm/npcm7xx.h | 2 + include/hw/mem/npcm7xx_mc.h | 36 ++++++++++++++++ 5 files changed, 133 insertions(+) create mode 100644 hw/mem/npcm7xx_mc.c create mode 100644 include/hw/mem/npcm7xx_mc.h diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 71cc141f3c..5e6d05642e 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -46,6 +46,7 @@ #define NPCM7XX_CPUP_BA (0xF03FE000) #define NPCM7XX_GCR_BA (0xF0800000) #define NPCM7XX_CLK_BA (0xF0801000) +#define NPCM7XX_MC_BA (0xF0824000) /* Memory blocks at the end of the address space */ #define NPCM7XX_RAM2_BA (0xFFFD0000) @@ -160,6 +161,7 @@ static void npcm7xx_init(Object *obj) TYPE_NPCM7XX_KEY_STORAGE); object_initialize_child(obj, "otp2", &s->fuse_array, TYPE_NPCM7XX_FUSE_ARRAY); + object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER); @@ -255,6 +257,14 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA); npcm7xx_init_fuses(s); + /* Fake Memory Controller (MC) */ + sysbus_realize(SYS_BUS_DEVICE(&s->mc), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA); + /* Timer Modules (TIM) */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim)); for (i = 0; i < ARRAY_SIZE(s->tim); i++) { diff --git a/hw/mem/Makefile.objs b/hw/mem/Makefile.objs index 56345befd0..9a33ef7b35 100644 --- a/hw/mem/Makefile.objs +++ b/hw/mem/Makefile.objs @@ -1,3 +1,4 @@ common-obj-$(CONFIG_DIMM) += pc-dimm.o common-obj-y += memory-device.o +common-obj-$(CONFIG_NPCM7XX) += npcm7xx_mc.o common-obj-$(CONFIG_NVDIMM) += nvdimm.o diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c new file mode 100644 index 0000000000..0435d06ab4 --- /dev/null +++ b/hw/mem/npcm7xx_mc.c @@ -0,0 +1,84 @@ +/* + * Nuvoton NPCM7xx Memory Controller stub + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/mem/npcm7xx_mc.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/units.h" + +#define NPCM7XX_MC_REGS_SIZE (4 * KiB) + +static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size) +{ + /* + * If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory + * controller has already been initialized and will skip DDR training. + */ + if (addr == 0) { + return 0x100; + } + + qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__); + + return 0; +} + +static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__); +} + +static const MemoryRegionOps npcm7xx_mc_ops = { + .read = npcm7xx_mc_read, + .write = npcm7xx_mc_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + .unaligned = false, + }, +}; + +static void npcm7xx_mc_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxMCState *s = NPCM7XX_MC(dev); + + memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs", + NPCM7XX_MC_REGS_SIZE); + sysbus_init_mmio(&s->parent, &s->mmio); +} + +static void npcm7xx_mc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->desc = "NPCM7xx Memory Controller stub"; + dc->realize = npcm7xx_mc_realize; +} + +static const TypeInfo npcm7xx_mc_types[] = { + { + .name = TYPE_NPCM7XX_MC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(NPCM7xxMCState), + .class_init = npcm7xx_mc_class_init, + }, +}; +DEFINE_TYPES(npcm7xx_mc_types); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 2f2d44aad7..a6c1d4082b 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -18,6 +18,7 @@ #include "hw/boards.h" #include "hw/cpu/a9mpcore.h" +#include "hw/mem/npcm7xx_mc.h" #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" #include "hw/nvram/npcm7xx_otp.h" @@ -66,6 +67,7 @@ typedef struct NPCM7xxState { NPCM7xxTimerCtrlState tim[3]; NPCM7xxOTPState key_storage; NPCM7xxOTPState fuse_array; + NPCM7xxMCState mc; } NPCM7xxState; #define TYPE_NPCM7XX "npcm7xx" diff --git a/include/hw/mem/npcm7xx_mc.h b/include/hw/mem/npcm7xx_mc.h new file mode 100644 index 0000000000..7ed38be243 --- /dev/null +++ b/include/hw/mem/npcm7xx_mc.h @@ -0,0 +1,36 @@ +/* + * Nuvoton NPCM7xx Memory Controller stub + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_MC_H +#define NPCM7XX_MC_H + +#include "exec/memory.h" +#include "hw/sysbus.h" + +/** + * struct NPCM7xxMCState - Device state for the memory controller. + * @parent: System bus device. + * @mmio: Memory region through which registers are accessed. + */ +typedef struct NPCM7xxMCState { + SysBusDevice parent; + + MemoryRegion mmio; +} NPCM7xxMCState; + +#define TYPE_NPCM7XX_MC "npcm7xx-mc" +#define NPCM7XX_MC(obj) OBJECT_CHECK(NPCM7xxMCState, (obj), TYPE_NPCM7XX_MC) + +#endif /* NPCM7XX_MC_H */