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[209.132.180.67]) by mx.google.com with ESMTP id 60si4254488plc.104.2017.11.08.10.02.00; Wed, 08 Nov 2017 10:02:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Bcfv1hCb; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751495AbdKHSB5 (ORCPT + 7 others); Wed, 8 Nov 2017 13:01:57 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:49657 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbdKHSB4 (ORCPT ); Wed, 8 Nov 2017 13:01:56 -0500 Received: by mail-wr0-f194.google.com with SMTP id o88so3223047wrb.6 for ; Wed, 08 Nov 2017 10:01:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=MxNBrBR+3bHSb1tUnem1JMxzrtzh0Tasr8+Xr71EtYA=; b=Bcfv1hCb3XdvRL+XB1sPjMHgteIMv1qXgx+xBDptGs61KCyjaW/LXR7Gawg4H8VZP6 1CYdYoIYVOugsm3PCC/LoRRKXpoDEdaSlF9iHeDRYmPkvfWuJTWVKNEYYCfba2CCXNXB Dd761a63xv67dmWA2F/Bw0klgMrCDAaA1j+ow= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=MxNBrBR+3bHSb1tUnem1JMxzrtzh0Tasr8+Xr71EtYA=; b=GbOsBzlW+HBrlBgdqsVHne+MrsLZ8+/072fGY5IJIgOjPqRQKyaDnO1rbWaT7X3LSU V3gDNysY8WsqLnj6x+oUE/uKJ0YWFFxzp1rjNw1tjQo4v/cniyFQZIDvlPyzetbACRmA SqS6DRswzG4VsZG+Dqf0IYHkS5QoTEwCW832XyfYqUj35K8+wRnBvs26uzh3p5NPKc51 5+G2xPMfg6da3UsDLn4EvW8T3NjjmBuCk46rmsoKPGD0hsdI5H63hw91YyzeIRjPEfbd xWvgshmYW/XWJ//NFOYiZnQI3YsSxHTITv4lfQbrk1gbb57M7UxI2fDSn0pM4zEaxpWI e8mQ== X-Gm-Message-State: AJaThX7/GD+EhkSB4BVtEDMILyClfgpghxWLxUkMGUNrQtOH2jXyMLOY ssNvEdwn4wQc5IeXjC4sosf9ak+FElXlwQ== X-Received: by 10.223.143.51 with SMTP id p48mr1127658wrb.104.1510164115239; Wed, 08 Nov 2017 10:01:55 -0800 (PST) Received: from localhost.localdomain ([105.146.187.5]) by smtp.gmail.com with ESMTPSA id 10sm4819356wml.27.2017.11.08.10.01.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Nov 2017 10:01:53 -0800 (PST) From: Ard Biesheuvel To: netdev@vger.kernel.org Cc: f.fainelli@gmail.com, andrew@lunn.ch, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel Subject: [RFC PATCH] phy: don't disable and re-enable interrupts in oneshot threaded handler Date: Wed, 8 Nov 2017 18:01:40 +0000 Message-Id: <20171108180140.3817-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The PHY interrupt handling code registers its interrupt as a oneshot threaded interrupt, which guarantees that the interrupt will be masked throughout both the primary and secondary handling stages. However, the handling code still disables the interrupt by calling disable_irq(), and re-enables it by calling enable_irq() after having acked the interrupt in the PHY hardware. This causes problems with hierarchical irqchip implementations built on top of the GIC, because the core threaded interrupt code will only EOI the interrupt if it is still masked after the secondary handler completes. If this is not the case, the EOI is not emitted, and the interrupt remains active, blocking further interrupts from the same source. Disabling and enabling the interrupt will result in the secondary handler completing with the interrupt unmasked, resulting in the above behavior. So remove the disable_irq/enable_irq, and rely on the fact that the interrupt remains masked already. Signed-off-by: Ard Biesheuvel --- drivers/net/phy/phy.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-) -- 2.11.0 diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d0626bf5c540..ce8bba0c1072 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -774,8 +774,8 @@ static void phy_error(struct phy_device *phydev) * @irq: interrupt line * @phy_dat: phy_device pointer * - * Description: When a PHY interrupt occurs, the handler disables - * interrupts, and uses phy_change to handle the interrupt. + * Description: When a PHY interrupt occurs, the handler invokes + * phy_change to handle the interrupt. */ static irqreturn_t phy_interrupt(int irq, void *phy_dat) { @@ -784,9 +784,6 @@ static irqreturn_t phy_interrupt(int irq, void *phy_dat) if (PHY_HALTED == phydev->state) return IRQ_NONE; /* It can't be ours. */ - disable_irq_nosync(irq); - atomic_inc(&phydev->irq_disable); - phy_change(phydev); return IRQ_HANDLED; @@ -891,10 +888,10 @@ void phy_change(struct phy_device *phydev) if (phy_interrupt_is_valid(phydev)) { if (phydev->drv->did_interrupt && !phydev->drv->did_interrupt(phydev)) - goto ignore; + return; if (phy_disable_interrupts(phydev)) - goto phy_err; + goto irq_enable_err; } mutex_lock(&phydev->lock); @@ -903,9 +900,6 @@ void phy_change(struct phy_device *phydev) mutex_unlock(&phydev->lock); if (phy_interrupt_is_valid(phydev)) { - atomic_dec(&phydev->irq_disable); - enable_irq(phydev->irq); - /* Reenable interrupts */ if (PHY_HALTED != phydev->state && phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED)) @@ -916,15 +910,9 @@ void phy_change(struct phy_device *phydev) phy_trigger_machine(phydev, true); return; -ignore: - atomic_dec(&phydev->irq_disable); - enable_irq(phydev->irq); - return; - irq_enable_err: disable_irq(phydev->irq); atomic_inc(&phydev->irq_disable); -phy_err: phy_error(phydev); }