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Thu, 9 Nov 2017 10:28:42 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171109102842eucas1p1cbc3dee63599a443e794bb2a9f9dbdac~1ZBwz_KGK2326523265eucas1p1X; Thu, 9 Nov 2017 10:28:42 +0000 (GMT) X-AuditID: cbfec7f2-f793b6d000003243-55-5a042ddae4a6 Received: from eusync3.samsung.com ( [203.254.199.213]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 3E.79.18832.ADD240A5; Thu, 9 Nov 2017 10:28:42 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OZ500G16BRQABB0@eusync3.samsung.com>; Thu, 09 Nov 2017 10:28:42 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org Subject: [PATCH] drm/bridge/sii8620: filter unsupported modes Date: Thu, 09 Nov 2017 11:28:31 +0100 Message-id: <20171109102831.19844-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.14.2 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrAIsWRmVeSWpSXmKPExsWy7djPc7q3dFmiDA7s1rO4te4cq0VTx1tW iytf37NZdE5cwm6x9shddgdWj8t9vUwesztmsnrc7z7O5NG3ZRVjAEsUl01Kak5mWWqRvl0C V8baR9cZCy7wVJx68ZmpgXEvVxcjB4eEgInEpL1KXYycQKaYxIV769lAbCGBpYwSz9dzdzFy AdmfGSWeHP7IDFP/60QqRHwZo8SMyzeZIJwGJonWWZ1MIN1sAoYSXW+7wCaJCChL/J24ihGk iFlgG6PExQsQRcICthLLXu9jB7FZBFQlHk9+CRbnBYpfOXSXGeIkeYn3C+6DNUsIPGWVWDml iwUi4SIx+ecVqCJhiVfHt7BD2DISnR0HmSDsfkaJplZtCHsGo8S5t7wQtrXE4eMXWUFsZgE+ iUnbpkO9xivR0SYEUeIhsevgTqjxjhJn1jazg5QICcRK3HktNYFRagEjwypGkdTS4tz01GJj veLE3OLSvHS95PzcTYzAeDv97/inHYxfT1gdYhTgYFTi4X2xijlKiDWxrLgy9xCjBAezkgiv yFugEG9KYmVValF+fFFpTmrxIUZpDhYlcV7bqLZIIYH0xJLU7NTUgtQimCwTB6dUA6P+pXqV 4k8G7/Yn3qu3nm98Rr3lzvtqpjuR9zZllIbPnqvC8sqXcUvytKfrlziXJBctXj7Tzlprac/C P+nreH9tusnF2/fH9Xddtuedr0zVitMiJMoeH7p0kuV0vVv9447lXzYvO3/8bqz5cv2bU/+H TksM9PnSmfDt4Cfd9WtKZvws0Ul207BRYinOSDTUYi4qTgQAjTNrfbMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDJMWRmVeSWpSXmKPExsVy+t/xq7q3dFmiDLb8ELa4te4cq0VTx1tW iytf37NZdE5cwm6x9shddgdWj8t9vUwesztmsnrc7z7O5NG3ZRVjAEsUl01Kak5mWWqRvl0C V8baR9cZCy7wVJx68ZmpgXEvVxcjB4eEgInErxOpXYycQKaYxIV769m6GLk4hASWMEq8fb+S BcJpYpL4tW4aM0gVm4ChRNfbLjYQW0RAWeLvxFWMIDazwDZGieM3UkBsYQFbiWWv97GD2CwC qhKPJ79kArF5geJXDt1lhtgmL/F+wX3GCYzcCxgZVjGKpJYW56bnFhvqFSfmFpfmpesl5+du YgSGwbZjPzfvYLy0MfgQowAHoxIP74tVzFFCrIllxZW5hxglOJiVRHhF3gKFeFMSK6tSi/Lj i0pzUosPMUpzsCiJ8/buWR0pJJCeWJKanZpakFoEk2Xi4JRqYGy4P+HXr03pfB3MDpvXv2tS /3+/d+Ur00Clh2E3vj8scW5Q/Vax6uqWnueGy/UufPiwYjH3e+UTp37e4jpr66Bdr5PT2Ph6 U36w3SnH6WxHSs79Y+4p4bU6nqDIdVJk7bFbS8/Pv7/r+5k9Ib3qL7hV/jay/sl91dVQvdRC zWeT3/SvIaVx9YJKLMUZiYZazEXFiQAM7Clp/wEAAA== X-CMS-MailID: 20171109102842eucas1p1cbc3dee63599a443e794bb2a9f9dbdac X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171109102842eucas1p1cbc3dee63599a443e794bb2a9f9dbdac X-RootMTR: 20171109102842eucas1p1cbc3dee63599a443e794bb2a9f9dbdac References: Cc: Laurent Pinchart , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The maximum pixel clock depends on the version of the connected MHL adapter. Add mode_valid callback to filter out modes with too high pixel clock to avoid failure in mode_fixup later. Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/bridge/sil-sii8620.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index b7eb704d0a8a..268d66d99337 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -2191,6 +2191,19 @@ static void sii8620_detach(struct drm_bridge *bridge) rc_unregister_device(ctx->rc_dev); } +static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, + const struct drm_display_mode *mode) +{ + struct sii8620 *ctx = bridge_to_sii8620(bridge); + bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & + MHL_DCAP_VID_LINK_PPIXEL; + unsigned int max_pclk = sii8620_is_mhl3(ctx) ? MHL3_MAX_LCLK : + MHL1_MAX_LCLK; + max_pclk /= can_pack ? 2 : 3; + + return (mode->clock > max_pclk) ? MODE_CLOCK_HIGH : MODE_OK; +} + static bool sii8620_mode_fixup(struct drm_bridge *bridge, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) @@ -2238,6 +2251,7 @@ static const struct drm_bridge_funcs sii8620_bridge_funcs = { .attach = sii8620_attach, .detach = sii8620_detach, .mode_fixup = sii8620_mode_fixup, + .mode_valid = sii8620_mode_valid, }; static int sii8620_probe(struct i2c_client *client,