From patchwork Mon Jan 16 09:26:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91544 Delivered-To: patch@linaro.org Received: by 10.182.3.34 with SMTP id 2csp1197970obz; Mon, 16 Jan 2017 01:31:55 -0800 (PST) X-Received: by 10.55.0.148 with SMTP id t20mr278556qkg.299.1484559115843; Mon, 16 Jan 2017 01:31:55 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l6si2645734qkd.129.2017.01.16.01.31.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:31:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55269 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3dr-00041x-CC for patch@linaro.org; Mon, 16 Jan 2017 04:31:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48696) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3bg-0002yM-44 for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3bb-00023V-RA for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:40 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:11847) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3bb-00022V-1E; Mon, 16 Jan 2017 04:29:35 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50575; Mon, 16 Jan 2017 17:28:10 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:27:58 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:26:56 +0800 Message-ID: <1484558821-15512-2-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.587C9235.0126, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2e144d0b431d9602fd9fcac3d0c00790 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 1/6] headers: update linux headers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao Signed-off-by: Shannon Zhao --- linux-headers/asm-arm64/kvm.h | 1 + linux-headers/linux/kvm.h | 2 ++ 2 files changed, 3 insertions(+) -- 2.0.4 diff --git a/linux-headers/asm-arm64/kvm.h b/linux-headers/asm-arm64/kvm.h index fd5a276..f914eac 100644 --- a/linux-headers/asm-arm64/kvm.h +++ b/linux-headers/asm-arm64/kvm.h @@ -97,6 +97,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */ #define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */ #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */ +#define KVM_ARM_VCPU_CROSS 4 /* Support cross type vCPU */ struct kvm_vcpu_init { __u32 target; diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index bb0ed71..ea9e288 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -870,6 +870,8 @@ struct kvm_ppc_smmu_info { #define KVM_CAP_S390_USER_INSTR0 130 #define KVM_CAP_MSI_DEVID 131 #define KVM_CAP_PPC_HTM 132 +#define KVM_CAP_ARM_CROSS_VCPU 133 +#define KVM_CAP_ARM_HETEROGENEOUS 134 #ifdef KVM_CAP_IRQ_ROUTING From patchwork Mon Jan 16 09:26:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91548 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1337962qgi; Mon, 16 Jan 2017 01:36:31 -0800 (PST) X-Received: by 10.200.37.183 with SMTP id e52mr4212397qte.166.1484559391396; Mon, 16 Jan 2017 01:36:31 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l47si10105128qtc.113.2017.01.16.01.36.31 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:36:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3iJ-0007zF-0b for patch@linaro.org; Mon, 16 Jan 2017 04:36:31 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3c5-0003KU-Ou for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:30:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3c1-0002Cs-1R for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:30:05 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:12057) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3c0-0002BL-8d; Mon, 16 Jan 2017 04:30:00 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50567; Mon, 16 Jan 2017 17:28:09 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:27:59 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:26:57 +0800 Message-ID: <1484558821-15512-3-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.587C922E.01AF, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 55dd8b30267b0e0b4b777f1e06945666 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 2/6] target: arm: Add the qemu target for KVM_ARM_TARGET_GENERIC_V8 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao Signed-off-by: Shannon Zhao --- target/arm/kvm-consts.h | 2 ++ 1 file changed, 2 insertions(+) -- 2.0.4 diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index a2c9518..fc01ac5 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -128,6 +128,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 #define QEMU_KVM_ARM_TARGET_XGENE_POTENZA 3 #define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 +#define QEMU_KVM_ARM_TARGET_GENERIC_V8 5 /* There's no kernel define for this: sentinel value which * matches no KVM target value for either 64 or 32 bit @@ -140,6 +141,7 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POTENZA) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_GENERIC_V8, KVM_ARM_TARGET_GENERIC_V8) #else MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) From patchwork Mon Jan 16 09:26:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91547 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1337919qgi; Mon, 16 Jan 2017 01:36:23 -0800 (PST) X-Received: by 10.55.42.41 with SMTP id q41mr32941355qkh.169.1484559383670; Mon, 16 Jan 2017 01:36:23 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b132si13857658qka.270.2017.01.16.01.36.23 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:36:23 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55297 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3iB-0007rV-5l for patch@linaro.org; Mon, 16 Jan 2017 04:36:23 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3cm-0003z3-LZ for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:30:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3ch-0002Wa-Rr for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:30:48 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:12576) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3cg-0002W8-Kd; Mon, 16 Jan 2017 04:30:43 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50574; Mon, 16 Jan 2017 17:28:10 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:28:00 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:26:58 +0800 Message-ID: <1484558821-15512-4-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.587C9234.0286, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 71191e536b4cceb22c86fc0ed779a1e8 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 3/6] arm: kvm64: Check if kvm supports cross type vCPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao If user requests a specific type vCPU which is not same with the physical ones and if kvm supports cross type vCPU, we set the KVM_ARM_VCPU_CROSS bit and set the CPU ID registers. Signed-off-by: Shannon Zhao --- target/arm/kvm64.c | 182 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) -- 2.0.4 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6111109..70442ea 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -481,7 +481,151 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return true; } +#define ARM_CPU_ID_MIDR 3, 0, 0, 0, 0 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 +/* ID group 1 registers */ +#define ARM_CPU_ID_REVIDR 3, 0, 0, 0, 6 +#define ARM_CPU_ID_AIDR 3, 1, 0, 0, 7 + +/* ID group 2 registers */ +#define ARM_CPU_ID_CCSIDR 3, 1, 0, 0, 0 +#define ARM_CPU_ID_CLIDR 3, 1, 0, 0, 1 +#define ARM_CPU_ID_CSSELR 3, 2, 0, 0, 0 +#define ARM_CPU_ID_CTR 3, 3, 0, 0, 1 + +/* ID group 3 registers */ +#define ARM_CPU_ID_PFR0 3, 0, 0, 1, 0 +#define ARM_CPU_ID_PFR1 3, 0, 0, 1, 1 +#define ARM_CPU_ID_DFR0 3, 0, 0, 1, 2 +#define ARM_CPU_ID_AFR0 3, 0, 0, 1, 3 +#define ARM_CPU_ID_MMFR0 3, 0, 0, 1, 4 +#define ARM_CPU_ID_MMFR1 3, 0, 0, 1, 5 +#define ARM_CPU_ID_MMFR2 3, 0, 0, 1, 6 +#define ARM_CPU_ID_MMFR3 3, 0, 0, 1, 7 +#define ARM_CPU_ID_ISAR0 3, 0, 0, 2, 0 +#define ARM_CPU_ID_ISAR1 3, 0, 0, 2, 1 +#define ARM_CPU_ID_ISAR2 3, 0, 0, 2, 2 +#define ARM_CPU_ID_ISAR3 3, 0, 0, 2, 3 +#define ARM_CPU_ID_ISAR4 3, 0, 0, 2, 4 +#define ARM_CPU_ID_ISAR5 3, 0, 0, 2, 5 +#define ARM_CPU_ID_MMFR4 3, 0, 0, 2, 6 +#define ARM_CPU_ID_MVFR0 3, 0, 0, 3, 0 +#define ARM_CPU_ID_MVFR1 3, 0, 0, 3, 1 +#define ARM_CPU_ID_MVFR2 3, 0, 0, 3, 2 +#define ARM_CPU_ID_AA64PFR0 3, 0, 0, 4, 0 +#define ARM_CPU_ID_AA64PFR1 3, 0, 0, 4, 1 +#define ARM_CPU_ID_AA64DFR0 3, 0, 0, 5, 0 +#define ARM_CPU_ID_AA64DFR1 3, 0, 0, 5, 1 +#define ARM_CPU_ID_AA64AFR0 3, 0, 0, 5, 4 +#define ARM_CPU_ID_AA64AFR1 3, 0, 0, 5, 5 +#define ARM_CPU_ID_AA64ISAR0 3, 0, 0, 6, 0 +#define ARM_CPU_ID_AA64ISAR1 3, 0, 0, 6, 1 +#define ARM_CPU_ID_AA64MMFR0 3, 0, 0, 7, 0 +#define ARM_CPU_ID_AA64MMFR1 3, 0, 0, 7, 1 +#define ARM_CPU_ID_MAX 36 + +static int kvm_arm_set_id_registers(CPUState *cs) +{ + int ret = 0; + uint32_t i; + ARMCPU *cpu = ARM_CPU(cs); + struct kvm_one_reg id_regitsers[ARM_CPU_ID_MAX]; + + memset(id_regitsers, 0, ARM_CPU_ID_MAX * sizeof(struct kvm_one_reg)); + + id_regitsers[0].id = ARM64_SYS_REG(ARM_CPU_ID_MIDR); + id_regitsers[0].addr = (uintptr_t)&cpu->midr; + + id_regitsers[1].id = ARM64_SYS_REG(ARM_CPU_ID_REVIDR); + id_regitsers[1].addr = (uintptr_t)&cpu->revidr; + + id_regitsers[2].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR0); + id_regitsers[2].addr = (uintptr_t)&cpu->mvfr0; + + id_regitsers[3].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR1); + id_regitsers[3].addr = (uintptr_t)&cpu->mvfr1; + + id_regitsers[4].id = ARM64_SYS_REG(ARM_CPU_ID_MVFR2); + id_regitsers[4].addr = (uintptr_t)&cpu->mvfr2; + + id_regitsers[5].id = ARM64_SYS_REG(ARM_CPU_ID_PFR0); + id_regitsers[5].addr = (uintptr_t)&cpu->id_pfr0; + + id_regitsers[6].id = ARM64_SYS_REG(ARM_CPU_ID_PFR1); + id_regitsers[6].addr = (uintptr_t)&cpu->id_pfr1; + + id_regitsers[7].id = ARM64_SYS_REG(ARM_CPU_ID_DFR0); + id_regitsers[7].addr = (uintptr_t)&cpu->id_dfr0; + + id_regitsers[8].id = ARM64_SYS_REG(ARM_CPU_ID_AFR0); + id_regitsers[8].addr = (uintptr_t)&cpu->id_afr0; + + id_regitsers[9].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR0); + id_regitsers[9].addr = (uintptr_t)&cpu->id_mmfr0; + + id_regitsers[10].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR1); + id_regitsers[10].addr = (uintptr_t)&cpu->id_mmfr1; + + id_regitsers[11].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR2); + id_regitsers[11].addr = (uintptr_t)&cpu->id_mmfr2; + + id_regitsers[12].id = ARM64_SYS_REG(ARM_CPU_ID_MMFR3); + id_regitsers[12].addr = (uintptr_t)&cpu->id_mmfr3; + + id_regitsers[13].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR0); + id_regitsers[13].addr = (uintptr_t)&cpu->id_isar0; + + id_regitsers[14].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR1); + id_regitsers[14].addr = (uintptr_t)&cpu->id_isar1; + + id_regitsers[15].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR2); + id_regitsers[15].addr = (uintptr_t)&cpu->id_isar2; + + id_regitsers[16].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR3); + id_regitsers[16].addr = (uintptr_t)&cpu->id_isar3; + + id_regitsers[17].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR4); + id_regitsers[17].addr = (uintptr_t)&cpu->id_isar4; + + id_regitsers[18].id = ARM64_SYS_REG(ARM_CPU_ID_ISAR5); + id_regitsers[18].addr = (uintptr_t)&cpu->id_isar5; + + id_regitsers[19].id = ARM64_SYS_REG(ARM_CPU_ID_AA64PFR0); + id_regitsers[19].addr = (uintptr_t)&cpu->id_aa64pfr0; + + id_regitsers[20].id = ARM64_SYS_REG(ARM_CPU_ID_AA64DFR0); + id_regitsers[20].addr = (uintptr_t)&cpu->id_aa64dfr0; + + id_regitsers[21].id = ARM64_SYS_REG(ARM_CPU_ID_AA64ISAR0); + id_regitsers[21].addr = (uintptr_t)&cpu->id_aa64isar0; + + id_regitsers[22].id = ARM64_SYS_REG(ARM_CPU_ID_AA64MMFR0); + id_regitsers[22].addr = (uintptr_t)&cpu->id_aa64mmfr0; + + id_regitsers[23].id = ARM64_SYS_REG(ARM_CPU_ID_CLIDR); + id_regitsers[23].addr = (uintptr_t)&cpu->clidr; + + id_regitsers[24].id = ARM64_SYS_REG(ARM_CPU_ID_CTR); + id_regitsers[24].addr = (uintptr_t)&cpu->ctr; + + + for (i = 0; i < ARM_CPU_ID_MAX; i++) { + if(id_regitsers[i].id != 0) { + ret = kvm_set_one_reg(cs, id_regitsers[i].id, + (void *)id_regitsers[i].addr); + if (ret) { + fprintf(stderr, "set ID register 0x%llx failed\n", + id_regitsers[i].id); + return ret; + } + } else { + break; + } + } + + /* TODO: Set CCSIDR */ + return ret; +} int kvm_arch_init_vcpu(CPUState *cs) { @@ -489,6 +633,8 @@ int kvm_arch_init_vcpu(CPUState *cs) uint64_t mpidr; ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; + bool heterogeneous = false, cross = false; + struct kvm_vcpu_init init; if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE || !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { @@ -518,12 +664,48 @@ int kvm_arch_init_vcpu(CPUState *cs) unset_feature(&env->features, ARM_FEATURE_PMU); } + /* + * Check if host is a heterogeneous system. It doesn't support -cpu host on + * heterogeneous system. If user requests a specific type VCPU, it should + * set the KVM_ARM_VCPU_CROSS bit to tell KVM that userspace want a specific + * vCPU. If KVM supports cross type vCPU, then set the ID registers. + */ + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_HETEROGENEOUS)) { + heterogeneous = true; + } + + if (strcmp(object_get_typename(OBJECT(cpu)), TYPE_ARM_HOST_CPU) == 0) { + if (heterogeneous) { + fprintf(stderr, "heterogeneous system can't support host guest CPU type\n"); + return -EINVAL; + } + } else if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_CROSS_VCPU)) { + init.features[0] = 1 << KVM_ARM_VCPU_CROSS; + if (kvm_vm_ioctl(cs->kvm_state, KVM_ARM_PREFERRED_TARGET, &init) < 0) { + return -EINVAL; + } + + if (init.target != (cpu->midr & 0xFF00FFF0) || heterogeneous) { + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8; + cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_CROSS; + cross = true; + } + } + /* Do KVM_ARM_VCPU_INIT ioctl */ ret = kvm_arm_vcpu_init(cs); if (ret) { return ret; } + if (cross) { + ret = kvm_arm_set_id_registers(cs); + if (ret) { + fprintf(stderr, "set vcpu ID registers failed\n"); + return ret; + } + } + /* * When KVM is in use, PSCI is emulated in-kernel and not by qemu. * Currently KVM has its own idea about MPIDR assignment, so we From patchwork Mon Jan 16 09:26:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91546 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1337896qgi; Mon, 16 Jan 2017 01:36:20 -0800 (PST) X-Received: by 10.55.33.163 with SMTP id f35mr28554005qki.66.1484559380291; Mon, 16 Jan 2017 01:36:20 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r33si13845116qtc.332.2017.01.16.01.36.20 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:36:20 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55296 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3i7-0007nf-Ra for patch@linaro.org; Mon, 16 Jan 2017 04:36:19 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48753) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3bk-00030M-7Y for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3bj-00028a-4a for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:44 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:11889) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3bi-00023f-C8; Mon, 16 Jan 2017 04:29:43 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50577; Mon, 16 Jan 2017 17:28:10 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:28:01 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:26:59 +0800 Message-ID: <1484558821-15512-5-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.587C9236.00B8, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2045b3cc78378efb16187dc97ef04a60 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 4/6] target: arm: Add a generic type cpu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao Add a generic type cpu, it's useful for migration when running on different hardwares. Signed-off-by: Shannon Zhao --- target/arm/cpu64.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) -- 2.0.4 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 549cb1e..223f31e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -204,6 +204,59 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void aarch64_generic_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,armv8"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8; + cpu->midr = 0x410fd000; /* FIXME: this needs to adjust */ + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x41034070; + cpu->mvfr0 = 0x10110222; + cpu->mvfr1 = 0x12111111; + cpu->mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; /* L1Ip = VIPT */ + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00000131; + cpu->id_pfr1 = 0x00011011; + cpu->id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10101105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02102211; + cpu->id_isar0 = 0x02101110; + cpu->id_isar1 = 0x13112111; + cpu->id_isar2 = 0x21232042; + cpu->id_isar3 = 0x01112131; + cpu->id_isar4 = 0x00011142; + cpu->id_isar5 = 0x00011121; + cpu->id_aa64pfr0 = 0x00002222; + cpu->id_aa64dfr0 = 0x10305106; + cpu->id_aa64isar0 = 0x00011120; + cpu->id_aa64mmfr0 = 0x0f001101; /* only support 4k page, 36 bit physical addr */ + cpu->dbgdidr = 0x3516d000; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x7003e01a; /* 8KB L1 dcache */ + cpu->ccsidr[1] = 0x2007e00a; /* 8KB L1 icache */ + cpu->ccsidr[2] = 0x700fe07a; /* 128KB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); +} + #ifdef CONFIG_USER_ONLY static void aarch64_any_initfn(Object *obj) { @@ -232,6 +285,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "generic", .initfn = aarch64_generic_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif From patchwork Mon Jan 16 09:27:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91545 Delivered-To: patch@linaro.org Received: by 10.182.3.34 with SMTP id 2csp1197983obz; Mon, 16 Jan 2017 01:31:58 -0800 (PST) X-Received: by 10.55.22.219 with SMTP id 88mr28999048qkw.283.1484559118369; Mon, 16 Jan 2017 01:31:58 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t28si13859102qtc.337.2017.01.16.01.31.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:31:58 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55270 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3dt-00043j-TY for patch@linaro.org; Mon, 16 Jan 2017 04:31:57 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3bj-0002z8-13 for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3bi-00027k-9j for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:43 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:11895) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3bg-00023i-PX; Mon, 16 Jan 2017 04:29:42 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50582; Mon, 16 Jan 2017 17:28:13 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:28:02 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:27:00 +0800 Message-ID: <1484558821-15512-6-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.587C9236.0278, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 45da7aec04fc35acc68dd0f7cf52495b X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 5/6] arm: virt: Enable generic type CPU in virt machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao Signed-off-by: Shannon Zhao --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) -- 2.0.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4b301c2..49b7b65 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -166,6 +166,7 @@ static const char *valid_cpus[] = { "cortex-a15", "cortex-a53", "cortex-a57", + "generic", "host", NULL }; From patchwork Mon Jan 16 09:27:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shannon Zhao X-Patchwork-Id: 91543 Delivered-To: patch@linaro.org Received: by 10.182.3.34 with SMTP id 2csp1197968obz; Mon, 16 Jan 2017 01:31:55 -0800 (PST) X-Received: by 10.55.174.130 with SMTP id x124mr5938599qke.63.1484559115473; Mon, 16 Jan 2017 01:31:55 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j66si4010994qkd.306.2017.01.16.01.31.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 16 Jan 2017 01:31:55 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:55268 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3dr-00041V-2V for patch@linaro.org; Mon, 16 Jan 2017 04:31:55 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48694) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cT3bf-0002yL-UY for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cT3bb-00023L-5S for qemu-devel@nongnu.org; Mon, 16 Jan 2017 04:29:39 -0500 Received: from szxga01-in.huawei.com ([58.251.152.64]:11806) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1cT3ba-000227-BC; Mon, 16 Jan 2017 04:29:35 -0500 Received: from 172.24.1.136 (EHLO szxeml426-hub.china.huawei.com) ([172.24.1.136]) by szxrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id DXW50581; Mon, 16 Jan 2017 17:28:12 +0800 (CST) Received: from HGHY1Z002260041.china.huawei.com (10.177.16.142) by szxeml426-hub.china.huawei.com (10.82.67.181) with Microsoft SMTP Server id 14.3.235.1; Mon, 16 Jan 2017 17:28:03 +0800 From: Shannon Zhao To: Date: Mon, 16 Jan 2017 17:27:01 +0800 Message-ID: <1484558821-15512-7-git-send-email-zhaoshenglong@huawei.com> X-Mailer: git-send-email 1.9.0.msysgit.0 In-Reply-To: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> References: <1484558821-15512-1-git-send-email-zhaoshenglong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.16.142] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.587C9236.0149, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 828304195dcbdbde2d71cf49cf75590a X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x-2.6.x [generic] [fuzzy] X-Received-From: 58.251.152.64 Subject: [Qemu-devel] [PATCH RFC 6/6] target-arm: cpu64: Add support for Cortex-A72 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wei@redhat.com, peter.maydell@linaro.org, drjones@redhat.com, qemu-devel@nongnu.org, wu.wubin@huawei.com, zhaoshenglong@huawei.com, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Shannon Zhao Add the ARM Cortex-A72 processor definition. It's similar to A57. Signed-off-by: Shannon Zhao --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) -- 2.0.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 49b7b65..2ba93e3 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -166,6 +166,7 @@ static const char *valid_cpus[] = { "cortex-a15", "cortex-a53", "cortex-a57", + "cortex-a72", "generic", "host", NULL diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 223f31e..4f00ceb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -204,6 +204,61 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +static void aarch64_a72_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a72"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_GENERIC_V8; + cpu->midr = 0x410fd081; + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x41034080; + cpu->mvfr0 = 0x10110222; + cpu->mvfr1 = 0x12111111; + cpu->mvfr2 = 0x00000043; + cpu->ctr = 0x8444c004; + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00000131; + cpu->id_pfr1 = 0x00011011; + cpu->id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02102211; + cpu->id_isar0 = 0x02101110; + cpu->id_isar1 = 0x13112111; + cpu->id_isar2 = 0x21232042; + cpu->id_isar3 = 0x01112131; + cpu->id_isar4 = 0x00011142; + cpu->id_isar5 = 0x00011121; + cpu->id_aa64pfr0 = 0x00002222; + cpu->id_aa64dfr0 = 0x10305106; + cpu->pmceid0 = 0x00000000; + cpu->pmceid1 = 0x00000000; + cpu->id_aa64isar0 = 0x00011120; + cpu->id_aa64mmfr0 = 0x00001124; + cpu->dbgdidr = 0x3516d000; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x71ffe07a; /* 4096KB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); +} + static void aarch64_generic_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -285,6 +340,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "generic", .initfn = aarch64_generic_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn },