From patchwork Mon Nov 13 14:11:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118760 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1841533qgn; Mon, 13 Nov 2017 06:11:54 -0800 (PST) X-Google-Smtp-Source: AGs4zMYsWBFeTsAjqtR/VQrWjeG4xRlmozYd+HKc9d7WiVphONDP52kUVXfpboQafrsiHdfFUSpx X-Received: by 10.37.194.199 with SMTP id s190mr5822700ybf.269.1510582314205; Mon, 13 Nov 2017 06:11:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582314; cv=none; d=google.com; s=arc-20160816; b=xTE+hu0Q/N1bKIUpBToP4psHBQNhTeb8MA82Am9J9/JTi19UnaQdEcvz10d4ebhuAa JaF/J5A+OrlETs7KwagBtIHc3zEs54sBFga2Kl96h+H2GPjcTMRD4F+f8MZC26ujljFv vlTTv7rljdmgzX+tmLo3SI/JvOZ53Wf2HQJUsL9+5EZgHG0Tk/xXFljDs56LTkZG6QF0 7nayxx19UMUXsTV5kayCSEAmk86jWDN7FA4wf/F+n7Vd+mJy6j8EKo+3A+CmTxV4hFxq eKFs9UG87TOJe2ICj+r1YdVizlLGm63LJGQo7QKxaOyyna9shDV507TFoOI4e0xc6ATh w/WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=FHgH6TiSTGxzCv1wk2VV0bPJ6KhOiqgZ545ObZ0Xj48=; b=YIs8+NsO7qXFoK4s7q2qr6U6h4JyXuiB7fP2S6cHzCqKiINarfaZ0WwY0ag9Pj94fu xxR0HSJKh0xmGnpo9LFaBFeSC8cWuZObn0Soc68/8LHRPw/HlHJvQzI3HjCiSoJSWTox rqq14d6YmHRld5el/tYstT5/Vp7CaX/XPy3R25MaFXYO200xDFs/XywDz+8JREX+Na89 HUey3gS7U4fmKT/F1N4ymA9cksU6+6ELV3Uen/zcO1OM+CeneJfr9o091nICEN30Fs/8 oXl2c6uZLFiP7wScjyahrFdzcSP+u8lWrTBiYTugBWynhYUxVZLCedUsBT5zLNEoijeX xHnQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id h3si1169559ybj.211.2017.11.13.06.11.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Nov 2017 06:11:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54608 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSr-0004Hi-Jq for patch@linaro.org; Mon, 13 Nov 2017 09:11:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47477) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSO-0004CQ-5o for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEFSI-0007kj-H1 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:24 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eEFSI-0007Yd-A7 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:18 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eEFS3-00021y-0W for qemu-devel@nongnu.org; Mon, 13 Nov 2017 14:11:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 13 Nov 2017 14:11:36 +0000 Message-Id: <1510582304-27058-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> References: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/9] arm/translate-a64: mark path as unreachable to eliminate warning X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Fixes the following warning when compiling with gcc 5.4.0 with -O1 optimizations and --enable-debug: target/arm/translate-a64.c: In function ‘aarch64_tr_translate_insn’: target/arm/translate-a64.c:2361:8: error: ‘post_index’ may be used uninitialized in this function [-Werror=maybe-uninitialized] if (!post_index) { ^ target/arm/translate-a64.c:2307:10: note: ‘post_index’ was declared here bool post_index; ^ target/arm/translate-a64.c:2386:8: error: ‘writeback’ may be used uninitialized in this function [-Werror=maybe-uninitialized] if (writeback) { ^ target/arm/translate-a64.c:2308:10: note: ‘writeback’ was declared here bool writeback; ^ Note that idx comes from selecting 2 bits, and therefore its value can be at most 3. Signed-off-by: Emilio G. Cota Acked-by: Philippe Mathieu-Daudé Message-id: 1510087611-1851-1-git-send-email-cota@braap.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index caca05a..625ef2d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2351,6 +2351,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, post_index = false; writeback = true; break; + default: + g_assert_not_reached(); } if (rn == 31) { From patchwork Mon Nov 13 14:11:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118764 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1844291qgn; Mon, 13 Nov 2017 06:14:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMbXd0/pmf72bCea0cDCJiuWkF/vuhvchknVe1MT8RmzEWiTunnQxMkRkNe2RJDPFO485Pmx X-Received: by 10.37.48.8 with SMTP id w8mr5918773ybw.520.1510582458222; Mon, 13 Nov 2017 06:14:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582458; cv=none; d=google.com; s=arc-20160816; b=z1LuswtWpzPyWMIVuAIwVsh8TOopyxvZSYuGwyL4m83wO4LnoDAxe2hF+cGtB81RQC YZfO2mPA8LInAowytUJjWM1r7ujyV+Ee8zU43FakQKUORz4zHHqZ1u8Zu+cSdpwteKS/ lSwX16RCPpd32aKviw/bn3Mveun/8IrwSVek5APPy8TdDxu7Nb/j5CNixmfSp7v8TEbx 6wSrIFCv6aGH12AfG7b9L9Vsnvl3EPJd+qRdcItoBJaHoxnj8oVPLSlKwiEvv3xexpNI igfJtPHt5awWBXYKdIy391hH/xFq+CKmHHexIQFutfC1Mc55S/FLS9WOjrigfVJFXt/h hZkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=anR6PthChcXK1NpVTFpo0qHrc8xNahdhAYOwI3oUIWc=; b=JeLnFyJVjw0djKwtDKWb+tiOaampXs2x4iUld+HmkRLT4v7K6eB2ak2/JrLb83y/bV JePbowurpPv9q6L3OgWgkn9l0FNBhNf62B/v/JPiC/Bpvz4EYp1s+YO/4LEhN+cnhrsH BMn8y1e2yf3w3AuKOpaM9hiTsaYRBYuGFQce7UT0d9YOBHupF8SaX8ivx99M0pEFZQ69 Bp6HoaF/aWoqMl1E6wb0i9PWJzrR/SR9E8IW6kc/Az8nGh0S4O21/COxCy9Cqu3UFy4d g9jf8ywhktFE99DSsgf4xCMs4lMUOWNNq0ZIiJE7Fhk6p3+wAJ1Vpjas7NxKCODQ8m4X TNDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/9] highbank: validate register offset before access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Prasad J Pandit An 'offset' parameter sent to highbank register r/w functions could be greater than number(NUM_REGS=0x200) of hb registers, leading to an OOB access issue. Add check to avoid it. Reported-by: Moguofang (Dennis mo) Signed-off-by: Prasad J Pandit Message-id: 20171113062658.9697-1-ppandit@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/highbank.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 354c6b2..287392b 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -34,6 +34,7 @@ #include "hw/ide/ahci.h" #include "hw/cpu/a9mpcore.h" #include "hw/cpu/a15mpcore.h" +#include "qemu/log.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 @@ -117,14 +118,26 @@ static void hb_regs_write(void *opaque, hwaddr offset, } } - regs[offset/4] = value; + if (offset / 4 >= NUM_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset); + return; + } + regs[offset / 4] = value; } static uint64_t hb_regs_read(void *opaque, hwaddr offset, unsigned size) { + uint32_t value; uint32_t *regs = opaque; - uint32_t value = regs[offset/4]; + + if (offset / 4 >= NUM_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset); + return 0; + } + value = regs[offset / 4]; if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) { value |= 0x30000000; From patchwork Mon Nov 13 14:11:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118774 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1850263qgn; Mon, 13 Nov 2017 06:19:29 -0800 (PST) X-Google-Smtp-Source: AGs4zMap5ieyCrl4yQOWGDeyLclHcpVqqVcbKndElBaXKO6KtWMlBIIYHBKBzFIwvDF5H//0Orzr X-Received: by 10.37.88.68 with SMTP id m65mr5624247ybb.516.1510582769137; Mon, 13 Nov 2017 06:19:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582769; cv=none; d=google.com; s=arc-20160816; b=xvFpPdO7zl3IL23wUQHBH26s5A6MbhqWevC8sQ3ICcEY5bTiCnLa5X6j+gbWf2m5p6 sMUIcCtCKyNJRloGay/bVVMq1LstlzXMXhJ1Qd2PRFEXS8WSWMd/b7/ek9+EaIeMPlTm 7Owtm5ZnLs5zQQ+8uXMsUAh29PurYauzfCqfrcG31RGm930dYCF/yqtYr1aQJIhiXUl/ N8EQwdZhbbx9d7m2FeTi6r+VzxaVtQ6viLTD71nj+xnW74o1pNkWCHoRu7UyW3BE3upf Z8Z2M9hWYK0GdZ04Ty4SFE9rvkahkuxjff+FlwJIlkZMjaLo4XwW77Uc2e7/hiXpmHEu sElQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=ojBCnuKGT3hCSQfTuedx62a0HqjQf3ejwUQ7kJ9Yozo=; b=ng9iHsfax94H7JHbE6zSTjz3WrLHM4oreVGKdc9Ay0IhOKkVo3gT0DR2YUFOQ0LKtP q4SXCb/F15bjQnvZSziS3ypaj+WtN1ja+zFGBHDzqUV3R8KTgaJfQUDEW3iRw2/BnfZZ l5LF9MTogltJh1hkyZR8iClkeaS6YmRiOPk0h1f319++AFUZre8NCnQlq5xFjEu29dWf iz34F82ChW3pbolLwlHxW6RfpcSuYzBtGbhg5VXm9E81HELyGd0JLPvYS6UHghvqzdFW j6JAg/7LyZEMztzPs48MCGvqvZkRwRm/JXac5mkZc+LCMg645pSGuk5YOB9BH22YM0+a w/eA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d85si1516928ybh.784.2017.11.13.06.19.29 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Nov 2017 06:19:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54653 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFaC-0002jD-Mu for patch@linaro.org; Mon, 13 Nov 2017 09:19:28 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSK-00048x-Jd for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEFSG-0007jG-N2 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:20 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eEFSG-0007Yd-Ac for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:16 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eEFS4-00022x-Qi for qemu-devel@nongnu.org; Mon, 13 Nov 2017 14:11:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 13 Nov 2017 14:11:38 +0000 Message-Id: <1510582304-27058-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> References: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/9] MAINTAINERS: Add entries for Smartfusion2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Subbaraya Sundeep Voluntarily add myself as maintainer for Smartfusion2 Signed-off-by: Subbaraya Sundeep Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 1510552520-3566-1-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- MAINTAINERS | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.7.4 diff --git a/MAINTAINERS b/MAINTAINERS index 0cd4d02..ffd77b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -564,6 +564,23 @@ M: Alistair Francis S: Maintained F: hw/arm/netduino2.c +SmartFusion2 +M: Subbaraya Sundeep +S: Maintained +F: hw/arm/msf2-soc.c +F: hw/misc/msf2-sysreg.c +F: hw/timer/mss-timer.c +F: hw/ssi/mss-spi.c +F: include/hw/arm/msf2-soc.h +F: include/hw/misc/msf2-sysreg.h +F: include/hw/timer/mss-timer.h +F: include/hw/ssi/mss-spi.h + +Emcraft M2S-FG484 +M: Subbaraya Sundeep +S: Maintained +F: hw/arm/msf2-som.c + CRIS Machines ------------- Axis Dev88 From patchwork Mon Nov 13 14:11:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118780 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1853169qgn; Mon, 13 Nov 2017 06:22:02 -0800 (PST) X-Google-Smtp-Source: AGs4zMZtPuo530vpeT/i/Pz/oBGDtFFLiQGoLony42oIQ7FfyBS/Aterr+AoBop6KrhMr/ItF/5x X-Received: by 10.37.38.133 with SMTP id m127mr5624527ybm.45.1510582922092; Mon, 13 Nov 2017 06:22:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582922; cv=none; d=google.com; s=arc-20160816; b=qFNV6Z+lGy+gPi46Eac0QdX6YLnZXE6cB6B/29NwkK+Xc+4ESGyzoDNP4rSNm9gtd8 uosufQLT3WTCrGXMPDl62t+NHvy5dFMpXQ7foLtBwvCdLTy5SvXKW+BQsd6KWsGUEHvf XIruDtIXpr9O4xudzY+kb7sRutXKgXacXKk9ufzAEaBmdcJHyJOZ7l5ze2O3/X4E7Gua FfBELMass5DTnbSaOZVmu7TqIfaLS4ZmONhPMhZacBfwjx53VehpmmBpIsEUhW9qvSOb 3IhiL5lA+zqAvDnx8eeYAVDN8P0hkMAIkz+D8v50RdmMAUxRqRPiAyeUM9KCq1t3yI1E Ttsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=maML9pDk5IX4x1LoM9HvDddJwiuzqA7uHVkof5BuPR4=; b=UI7lNCpclkMb/8No6c0P488482UmnvAo+uUSbzB6IsW+4n9ljaKflT6L1YD8iQCt+X wAy9MLCUW04zhm4rmIHnIqqBjAqSYUoDEQHZQMZsuc8+FndicihnKij9eiIrA54dC5c6 /qSkGG6yE7rCdd2PnUzErmpv9OgDTgQvi4rbC0aW+So/Vje0XL9OxHt1TFLshohe8Dvg aoiD5hTKe4SFvkIYVRtsiA86HGQ5DA95G+m9v3DjwUbynWuRjPB2wXWCzI9xHzRPHrru oTvCsOp4bzMnFi2beoexL5tXKGlJECb6yQRQRZ6qlVeM7nV5O2T+XnNeObCDCKp+Hm7T /+0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/9] qom: move CPUClass.tcg_initialize to a global X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" 55c3cee ("qom: Introduce CPUClass.tcg_initialize", 2017-10-24) introduces a per-CPUClass bool that we check so that the target CPU is initialized for TCG only once. This works well except when we end up creating more than one CPUClass, in which case we end up incorrectly initializing TCG more than once, i.e. once for each CPUClass. This can be replicated with: $ aarch64-softmmu/qemu-system-aarch64 -machine xlnx-zcu102 -smp 6 \ -global driver=xlnx,,zynqmp,property=has_rpu,value=on In this case the class name of the "RPUs" is prefixed by "cortex-r5-", whereas the "regular" CPUs are prefixed by "cortex-a53-". This results in two CPUClass instances being created. Fix it by introducing a static variable, so that only the first target CPU being initialized will initialize the target-dependent part of TCG, regardless of CPUClass instances. Fixes: 55c3ceef61fcf06fc98ddc752b7cce788ce7680b Signed-off-by: Emilio G. Cota Reviewed-by: Eduardo Habkost Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Tested-by: Alistair Francis Message-id: 1510343626-25861-2-git-send-email-cota@braap.org Signed-off-by: Peter Maydell --- include/qom/cpu.h | 1 - exec.c | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index fa4b0c9..c2fa151 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -209,7 +209,6 @@ typedef struct CPUClass { /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; - bool tcg_initialized; } CPUClass; #ifdef HOST_WORDS_BIGENDIAN diff --git a/exec.c b/exec.c index 97a24a8..8b579c0 100644 --- a/exec.c +++ b/exec.c @@ -792,11 +792,12 @@ void cpu_exec_initfn(CPUState *cpu) void cpu_exec_realizefn(CPUState *cpu, Error **errp) { CPUClass *cc = CPU_GET_CLASS(cpu); + static bool tcg_target_initialized; cpu_list_add(cpu); - if (tcg_enabled() && !cc->tcg_initialized) { - cc->tcg_initialized = true; + if (tcg_enabled() && !tcg_target_initialized) { + tcg_target_initialized = true; cc->tcg_initialize(); } From patchwork Mon Nov 13 14:11:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118772 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1848786qgn; Mon, 13 Nov 2017 06:18:11 -0800 (PST) X-Google-Smtp-Source: AGs4zMZZg7+VqTnaTvJMXs6j/Kh9Bh/nVECX5pywsNv4mbTCWlMKRtwbBm4K/QW/Nw+OHroZ9VJ6 X-Received: by 10.129.28.206 with SMTP id c197mr5849887ywc.328.1510582691455; Mon, 13 Nov 2017 06:18:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582691; cv=none; d=google.com; s=arc-20160816; b=ZBRSioPtwdxQEzDqiVQfQrOnzwotdmvy354953avQkQ7icHOT2goFomxW9G15Wze97 aV8BGBUoBdl/AVJAUDSXiRV47ppztYuvU8oehIGcFdQ0nc3YzrNjQY3JVp0VlqZu0U3E SWwwytdJc4sH12m3TEygzjMyu3JJFhlu2w13MCx3968EVmbPR9DXOETVCqFF3rNGBcFP fsT9Q5deb7ek0cbkd78mIkK51+okZfJqzl2j+LPYe6tfQIGTBOsTNZPc5D8bPoiPPqab wONuquMdA3h0w3CUOxY4P+lOPLKpG5YODkKuAPr/mBEwyKgYGGh4EUfHVwTqauJIOb+M i1gA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=WpK5057nUU0TZmbEPVIGcToPku3rN8ZfY66YkIxKhQc=; b=F9Q4hVmtwsAS/GgP5urVR1CAntBQWkg2bR0mRTXe1xsb3haChH/IAII1IgFeMG/wP/ nPYBQh0tIpazKsdP+klfqMwUOkgUamtwd+K465DrxS9RyILmCMCKP12SC3K2YzPeP6cE G4JTpp5qhnDKfuYU+sMCsq9FhMl9iFbHvAjZ7SfgNeBECu2rTVwYT2ERAfUyioNnU6YA 8bWg/yskGWxcl7I14RyHt1Ayg2uN+PR6Ns4ZrjigzArifYACiLV+C7WWYB7qo4KlpgrM pKtqApGcWlTGsH3PyBXNrnDi3iAIH/MPL9ivpSRf7isBqQ3t9RknrVEj+zPpH8g3BkYW y6QA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b10si140551ywc.241.2017.11.13.06.18.11 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Nov 2017 06:18:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54644 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFYw-0001n8-VX for patch@linaro.org; Mon, 13 Nov 2017 09:18:11 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSJ-000485-6m for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEFSE-0007ge-P7 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:19 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eEFSE-0007Yd-I0 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:14 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eEFS6-00023s-40 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 14:11:06 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 13 Nov 2017 14:11:40 +0000 Message-Id: <1510582304-27058-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> References: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/9] xlnx-zynqmp: Properly support the smp command line option X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Allow the -smp command line option to control the number of CPUs we create. Signed-off-by: Alistair Francis Reviewed-by: Eduardo Habkost Reviewed-by: Emilio G. Cota Tested-by: Emilio G. Cota Message-id: 1510343626-25861-3-git-send-email-cota@braap.org Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 3 ++- hw/arm/xlnx-zynqmp.c | 26 ++++++++++++++++---------- 2 files changed, 18 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index e2d15a1..7ec03da 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -235,7 +235,8 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); - mc->desc = "Xilinx ZynqMP ZCU102 board"; + mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5s based on " \ + "the value of smp"; mc->init = xlnx_zcu102_init; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index d4b6560..c707c66 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -98,8 +98,9 @@ static void xlnx_zynqmp_create_rpu(XlnxZynqMPState *s, const char *boot_cpu, { Error *err = NULL; int i; + int num_rpus = MIN(smp_cpus - XLNX_ZYNQMP_NUM_APU_CPUS, XLNX_ZYNQMP_NUM_RPU_CPUS); - for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { + for (i = 0; i < num_rpus; i++) { char *name; object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), @@ -132,8 +133,9 @@ static void xlnx_zynqmp_init(Object *obj) { XlnxZynqMPState *s = XLNX_ZYNQMP(obj); int i; + int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); - for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + for (i = 0; i < num_apus; i++) { object_initialize(&s->apu_cpu[i], sizeof(s->apu_cpu[i]), "cortex-a53-" TYPE_ARM_CPU); object_property_add_child(obj, "apu-cpu[*]", OBJECT(&s->apu_cpu[i]), @@ -182,6 +184,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) MemoryRegion *system_memory = get_system_memory(); uint8_t i; uint64_t ram_size; + int num_apus = MIN(smp_cpus, XLNX_ZYNQMP_NUM_APU_CPUS); const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; ram_addr_t ddr_low_size, ddr_high_size; qemu_irq gic_spi[GIC_NUM_SPI_INTR]; @@ -233,10 +236,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); - qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", XLNX_ZYNQMP_NUM_APU_CPUS); + qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); /* Realize APUs before realizing the GIC. KVM requires this. */ - for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + for (i = 0; i < num_apus; i++) { char *name; object_property_set_int(OBJECT(&s->apu_cpu[i]), QEMU_PSCI_CONDUIT_SMC, @@ -292,7 +295,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } } - for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) { + for (i = 0; i < num_apus; i++) { qemu_irq irq; sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, @@ -307,11 +310,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } if (s->has_rpu) { - xlnx_zynqmp_create_rpu(s, boot_cpu, &err); - if (err) { - error_propagate(errp, err); - return; - } + info_report("The 'has_rpu' property is no longer required, to use the " + "RPUs just use -smp 6."); + } + + xlnx_zynqmp_create_rpu(s, boot_cpu, &err); + if (err) { + error_propagate(errp, err); + return; } if (!s->boot_cpu_ptr) { From patchwork Mon Nov 13 14:11:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118766 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1845993qgn; Mon, 13 Nov 2017 06:15:47 -0800 (PST) X-Google-Smtp-Source: AGs4zMYMpAex4zCgsabL19VxsaewP7UuJjOk6HWD+oAM8NJZtew9w/ELzPCzUKnRpM6X+29GFqEn X-Received: by 10.37.192.143 with SMTP id c137mr2515447ybf.463.1510582547203; Mon, 13 Nov 2017 06:15:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582547; cv=none; d=google.com; s=arc-20160816; b=VCH89Cu4ulaDXKKLLNFHobdRqc+qr+Bi4R8sJins0LmJQda84rwGvlWTvnio+9GRBC Vi6X9h5cAmnSNeDCTV0NFxvNZqNky6IcDgU9C92WX1KAPsve3GXaM22XPTNORxExPk+H NK4ESgM+fvB7UcEJlMZcum5jciwr4Ho3UNAGOEzXRoQIY/4ZWWvMCyy4giMJz5yqEfws 1Gi6navFQ+mSjyvUSsvYqYGdC8tmx7UibtycYI7NcYHYw7KvIqtxvekh1tfpx/bxj3sC bDCGGwIIsnQ1GWqfcyFX6x984uRpOX8Gjz4U3MiTR/dds9AckAPwsau30meQi2RGCCDj LA3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=tvpDDFXOPsfIU3EqpnaBP2zxzWvjPQa/D9RIAWfAgCc=; b=n1fGynwnHCCKr243/Wtv9uHaWyvyNGPSrwDK5ZCoAQ5oML7W5VlYllrF9ANgckFAB3 p9Gjl7EmjF6lC5zLLaM5nm2VeNoG99qxh29yeoZ8lB3A+I4b0OZ/Wuc3ul9vNLMjMANl dLwTW1okLHSkTMacnvLEEdC8Vx7+bexWmQbr9B/1R8so7gO1StgH59ZcjZohvG1nGAy9 8NWRds5dOlCwCKez1o5eUjUkuWWvfTbdWdUroDoIJsw+04LX4OlLsWrm00VMaWSWtIqj Inb0/owRE2BXF8Po4ToOUmRWNFQVOQR66gRD6ZyLReCoQ1WlHIR9pdvpCxgB8bYSryhZ WnQQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 6/9] xlnx-zcu102: Add an info message deprecating the EP108 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The EP108 was an early access development board that is no longer used. Add an info message to convert any users to the ZCU102 instead. On QEMU they are both identical. This patch also updated the qemu-doc.texi file to indicate that the EP108 has been deprecated. Signed-off-by: Alistair Francis Reviewed-by: Emilio G. Cota Message-id: 1510343626-25861-4-git-send-email-cota@braap.org Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 3 +++ qemu-doc.texi | 7 +++++++ 2 files changed, 10 insertions(+) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 7ec03da..adddd23 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -164,6 +164,9 @@ static void xlnx_ep108_init(MachineState *machine) { XlnxZCU102 *s = EP108_MACHINE(machine); + info_report("The Xilinx EP108 machine is deprecated, please use the " + "ZCU102 machine instead. It has the same features supported."); + xlnx_zynqmp_init(s, machine); } diff --git a/qemu-doc.texi b/qemu-doc.texi index 8c10956..d383ac4 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -2537,6 +2537,13 @@ or ``ivshmem-doorbell`` device types. The ``spapr-pci-vfio-host-bridge'' device type is replaced by the ``spapr-pci-host-bridge'' device type. +@section System emulator machines + +@subsection Xilinx EP108 (since 2.11.0) + +The ``xlnx-ep108'' machine has been replaced by the ``xlnx-zcu102'' machine. +The ``xlnx-zcu102'' machine has the same features and capabilites in QEMU. + @node License @appendix License From patchwork Mon Nov 13 14:11:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118759 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1841457qgn; Mon, 13 Nov 2017 06:11:49 -0800 (PST) X-Google-Smtp-Source: AGs4zMaM2UK26Mmnx8bMxfBcXMcrFXIdCG5CtBuZSq1X9Fp+2tUfRW1LB/P/1X3Fek5ej3z5WtoF X-Received: by 10.37.219.208 with SMTP id g199mr5674544ybf.481.1510582309732; Mon, 13 Nov 2017 06:11:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582309; cv=none; d=google.com; s=arc-20160816; b=KDq9TazHuIkFXHkaBDFd6eyCcKq1UXqKYVGgtoDGIaCLD3xCaD3jv2rkZruTlJLVIB ngywGEm5JWuwTZaGOM0IXQTUqNSyObL9QTbrz9dYtho0vv47SE/frzGO2rOnf4V/rOhZ ZinPkTV8ViSfch02z7lW65xwgSqDro83y9hIU+qPkeisp2sOAI1eRN5idJQKXTYwbKQl 9LrcesUVKgF87hjqGqG1udaVegiVS7P3fHgJuNKhpfXL1upl/mtYHLYeg66pwSUBBAdM Z/mZjzKhctSntdXH5NIQn1FhFmOdjDevLvSfhFBQXaZCL2i3xd8v7a2nFjfUB3QIjPKU iLpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=6jnwq6WaipYCNtN0PeqH3+mEwrbOk1eiKDCCqnpGjVA=; b=XCaCihPr2XF5hBLw7P47pB2nOufv+bAX+XgkSpUzIYYl2mLwtW/e0SDzid9FNbTKKY 6bVt6WpAZ3IvSev0T6GaU2IwtFjksMBw3NaD2Y+qyYiovAhqFT5ra+Iaw4ZzvsSF7qb2 b7MCZG553af5MLdK06ovrPy0evy2sfYwLIPiGcRkrW6rqaGNzgSaY9zfbTpDObiW4rKw VKIvnP2osH27MHtmw2nJj9KEOgBcbrUoCvJ1KcKGiDbKyhai2+q++iXqtZVTMZnQRW+3 Rc18X/3Mi9zEqNydxkI3iGMhAa/VaYzPkLi8ct1UV4DHKnCJuXpugRLfrFWnYyXL677n Fccw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 7/9] xlnx-zcu102: Specify the max number of CPUs for the EP108 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" Just like the zcu102, the ep108 can instantiate several CPUs. Signed-off-by: Emilio G. Cota Reviewed-by: Alistair Francis Message-id: 1510343626-25861-5-git-send-email-cota@braap.org Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index adddd23..190eb69 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -188,6 +188,7 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; + mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; } static const TypeInfo xlnx_ep108_machine_init_typeinfo = { From patchwork Mon Nov 13 14:11:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118758 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1841364qgn; Mon, 13 Nov 2017 06:11:45 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ34mYtfGcEhewoYlfNFcjmsd/C2Kkf3b78yRtNvC464UREwskltDnvjilF5tPl89yQpH9/ X-Received: by 10.37.132.140 with SMTP id v12mr921434ybk.285.1510582305366; Mon, 13 Nov 2017 06:11:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582305; cv=none; d=google.com; s=arc-20160816; b=v3DA94usQxEHLhgviWBXDgN8cuDjoxkh5PgwH/tWZ5E1My56gga/9rpDObLkLsjcO0 46kGBkzLDLaEJf2x/WBffaRMpUNrhRDkyRoBzJzI1BlA3fHGgBJLP0T6zmO6lC5Obq6z frR7Maw9bb5VbWXZt9SvhF8+dz4TnDbZv6DqToEH6Jj0yqjc5IRwdv9ndsd3h0AwkEbw 5c2Tf5WkALu1J+C+oaw2m8va6EzxH6KqjsMRkYLx2rSTSuDtN3ES4sClfGiEieTqsZks 6MYbHdkBvAQTC//2cnh/Vck176kW+2Y6rAInCzMgAsysi5KxgRsNzqkNrUbaFuoUCwx4 ICJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=BR6DJH9jcfalIUtQUMDmWe6Lrpwli6ODQxKRoqlGz+A=; b=0WXHQ+U+9pHp4hwhtmPGq6dDPhg7eRYaK+JJjkct3qoKKRSRIO8PuIfeMO1WMxUdu2 hU2bJhQK6UIk7YyZsYvt8JRy+N6sf7YAJi0KxQZSgpWKpE14ZYZwqzyElI7ACAmeecZ6 dywBotz/CJDHI/U8yTBQ6M7M6Lnjb/fRDouPlhnTlvdY1YCx1s07QNroqUbHffonI3+9 pe0U9cTMFIP54MGxf7aZZCQK98zZIBZWIRwROncSto56dhahYIt1S9DIOSta8A5a3LXP Ysw4UV2WsbTsz5r7fESZJQcUvKwNIsuqCpXlsP64fGRvc5oBZRlUJnqNekUWLX6uxj2m mu/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r66si2769318ywb.381.2017.11.13.06.11.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Nov 2017 06:11:45 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54605 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSi-0004AK-O5 for patch@linaro.org; Mon, 13 Nov 2017 09:11:44 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSD-00043d-Vb for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEFSC-0007e2-3y for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:13 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eEFSB-0007Yd-RM for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:12 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eEFS8-00025A-EQ for qemu-devel@nongnu.org; Mon, 13 Nov 2017 14:11:08 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 13 Nov 2017 14:11:43 +0000 Message-Id: <1510582304-27058-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> References: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 8/9] hw: add .min_cpus and .default_cpus fields to machine_class X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: "Emilio G. Cota" max_cpus needs to be an upper bound on the number of vCPUs initialized; otherwise TCG region initialization breaks. Some boards initialize a hard-coded number of vCPUs, which is not captured by the global max_cpus and therefore breaks TCG initialization. Fix it by adding the .min_cpus field to machine_class. This commit also changes some user-facing behaviour: we now die if -smp is below this hard-coded vCPU minimum instead of silently ignoring the passed -smp value (sometimes announcing this by printing a warning). However, the introduction of .default_cpus lessens the likelihood that users will notice this: if -smp isn't set, we now assign the value in .default_cpus to both smp_cpus and max_cpus. IOW, if a user does not set -smp, they always get a correct number of vCPUs. This change fixes 3468b59 ("tcg: enable multiple TCG contexts in softmmu", 2017-10-24), which broke TCG initialization for some ARM boards. Fixes: 3468b59e18b179bc63c7ce934de912dfa9596122 Reported-by: Thomas Huth Reviewed-by: Eduardo Habkost Reviewed-by: Alistair Francis Signed-off-by: Emilio G. Cota Message-id: 1510343626-25861-6-git-send-email-cota@braap.org Suggested-by: Peter Maydell Signed-off-by: Emilio G. Cota Signed-off-by: Peter Maydell --- include/hw/boards.h | 5 +++++ hw/arm/exynos4_boards.c | 12 ++++-------- hw/arm/raspi.c | 2 ++ hw/arm/xlnx-zcu102.c | 2 ++ vl.c | 21 ++++++++++++++++++--- 5 files changed, 31 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/include/hw/boards.h b/include/hw/boards.h index 191a5b3..62f160e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -102,6 +102,9 @@ typedef struct { /** * MachineClass: + * @max_cpus: maximum number of CPUs supported. Default: 1 + * @min_cpus: minimum number of CPUs supported. Default: 1 + * @default_cpus: number of CPUs instantiated if none are specified. Default: 1 * @get_hotplug_handler: this function is called during bus-less * device hotplug. If defined it returns pointer to an instance * of HotplugHandler object, which handles hotplug operation @@ -167,6 +170,8 @@ struct MachineClass { BlockInterfaceType block_default_type; int units_per_default_bus; int max_cpus; + int min_cpus; + int default_cpus; unsigned int no_serial:1, no_parallel:1, use_virtcon:1, diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index f1441ec..750162c 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -27,7 +27,6 @@ #include "qemu-common.h" #include "cpu.h" #include "sysemu/sysemu.h" -#include "sysemu/qtest.h" #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/arm.h" @@ -129,13 +128,6 @@ exynos4_boards_init_common(MachineState *machine, Exynos4BoardType board_type) { Exynos4BoardState *s = g_new(Exynos4BoardState, 1); - MachineClass *mc = MACHINE_GET_CLASS(machine); - - if (smp_cpus != EXYNOS4210_NCPUS && !qtest_enabled()) { - error_report("%s board supports only %d CPU cores, ignoring smp_cpus" - " value", - mc->name, EXYNOS4210_NCPUS); - } exynos4_board_binfo.ram_size = exynos4_board_ram_size[board_type]; exynos4_board_binfo.board_id = exynos4_board_id[board_type]; @@ -189,6 +181,8 @@ static void nuri_class_init(ObjectClass *oc, void *data) mc->desc = "Samsung NURI board (Exynos4210)"; mc->init = nuri_init; mc->max_cpus = EXYNOS4210_NCPUS; + mc->min_cpus = EXYNOS4210_NCPUS; + mc->default_cpus = EXYNOS4210_NCPUS; mc->ignore_memory_transaction_failures = true; } @@ -205,6 +199,8 @@ static void smdkc210_class_init(ObjectClass *oc, void *data) mc->desc = "Samsung SMDKC210 board (Exynos4210)"; mc->init = smdkc210_init; mc->max_cpus = EXYNOS4210_NCPUS; + mc->min_cpus = EXYNOS4210_NCPUS; + mc->default_cpus = EXYNOS4210_NCPUS; mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 5941c9f..cd5fa8c 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -167,6 +167,8 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->max_cpus = BCM2836_NCPUS; + mc->min_cpus = BCM2836_NCPUS; + mc->default_cpus = BCM2836_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; mc->ignore_memory_transaction_failures = true; }; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 190eb69..9631a53 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -189,6 +189,7 @@ static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; } static const TypeInfo xlnx_ep108_machine_init_typeinfo = { @@ -246,6 +247,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; + mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; } static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { diff --git a/vl.c b/vl.c index ec29909..7372424 100644 --- a/vl.c +++ b/vl.c @@ -160,8 +160,8 @@ Chardev *virtcon_hds[MAX_VIRTIO_CONSOLES]; Chardev *sclp_hds[MAX_SCLP_CONSOLES]; int win2k_install_hack = 0; int singlestep = 0; -int smp_cpus = 1; -unsigned int max_cpus = 1; +int smp_cpus; +unsigned int max_cpus; int smp_cores = 1; int smp_threads = 1; int acpi_enabled = 1; @@ -4327,9 +4327,24 @@ int main(int argc, char **argv, char **envp) exit(0); } + /* machine_class: default to UP */ + machine_class->max_cpus = machine_class->max_cpus ?: 1; + machine_class->min_cpus = machine_class->min_cpus ?: 1; + machine_class->default_cpus = machine_class->default_cpus ?: 1; + + /* default to machine_class->default_cpus */ + smp_cpus = machine_class->default_cpus; + max_cpus = machine_class->default_cpus; + smp_parse(qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); - machine_class->max_cpus = machine_class->max_cpus ?: 1; /* Default to UP */ + /* sanity-check smp_cpus and max_cpus against machine_class */ + if (smp_cpus < machine_class->min_cpus) { + error_report("Invalid SMP CPUs %d. The min CPUs " + "supported by machine '%s' is %d", smp_cpus, + machine_class->name, machine_class->min_cpus); + exit(1); + } if (max_cpus > machine_class->max_cpus) { error_report("Invalid SMP CPUs %d. The max CPUs " "supported by machine '%s' is %d", max_cpus, From patchwork Mon Nov 13 14:11:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 118768 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1846519qgn; Mon, 13 Nov 2017 06:16:12 -0800 (PST) X-Google-Smtp-Source: AGs4zMaHox/LXFj5G/tJkaMLzggBLuW4lnWpNM20fScsS0HEWT7klOHFJ+vSC5oK+8AvHaUl9Xnx X-Received: by 10.37.161.195 with SMTP id a61mr5609583ybi.425.1510582572902; Mon, 13 Nov 2017 06:16:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510582572; cv=none; d=google.com; s=arc-20160816; b=cfgjzet7u1m+TkoQctva6wTqbXZvlOr+VZ3tr8GdItxkkZSpJ3N8W8c2hkrkZGvEmN UZJLDrFN+iITXNpQ+nyHkdj3EFwd5KIIeSMIzt5kziZ/Lr+uF6Cu0J06Z0y3ddzmY4dl idpDfRRIi3fsaqIUZPInFtpOgOJJekY65KnNVe7KG32Bq/GRiGMCuBoXiwG5VrdeIG5x Rb2ONzE8EW530WD9QTRUvV2wRa+odBzkFj55RLNORTAkLcH4osk6RfA7wA4sCL9yXFBB EmuEPqy+pOdWL/hDsmXWi5juXWZQqSa7wOf20Vu4w0VSe9isIdQYY/+XDlo+kiRgWIMY VLUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=aOsumAzTq3uB4QRRjwiwQz8az0NI5CPCPbsXFTyD2QM=; b=MJ84TSUbD5tk64xlmw0YibhJMgoIjMQeKFBkVbc0MIvze0Ytkgbe98Gsq6k/wc8PVZ eiOeLEMHeb6zvgJOao4+2aZe+V458XNa3ILIfdmhfAKfpiPdy5a0cw4m1xLRHLcOgd6V kvgGx4eMfGMOwcWm1rXjqSFt7TfUDFzYnVE7FrqLZ+MUdFCDdn5p78yQz+6LtDhKO080 NeN9Evd+L7hHY4PmOZeJ1VpLqezMPkSfBXlsi4QGWajUeLe8M3BWHHmLrtD6PV7gahIy HS8VxSaOvjDg5auztR4ZDW7gbcyUnV/KAkJxfMN2NA4PDsB1NkHdNq/HAHPSK5l27DEB dqVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id c137si2519178ywa.609.2017.11.13.06.16.12 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 13 Nov 2017 06:16:12 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54639 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFX2-0000J9-9m for patch@linaro.org; Mon, 13 Nov 2017 09:16:12 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eEFSH-00046e-Jm for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eEFSB-0007dQ-5D for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:17 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38322) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eEFSA-0007Yd-T8 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 09:11:11 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eEFS9-00025e-33 for qemu-devel@nongnu.org; Mon, 13 Nov 2017 14:11:09 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 13 Nov 2017 14:11:44 +0000 Message-Id: <1510582304-27058-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> References: <1510582304-27058-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 9/9] accel/tcg/translate-all: expand cpu_restore_state addr check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We are still seeing signals during translation time when we walk over a page protection boundary. This expands the check to ensure the host PC is inside the code generation buffer. The original suggestion was to check versus tcg_ctx.code_gen_ptr but as we now segment the translation buffer we have to settle for just a general check for being inside. I've also fixed up the declaration to make it clear it can deal with invalid addresses. A later patch will fix up the call sites. Signed-off-by: Alex Bennée Reported-by: Peter Maydell Reviewed-by: Laurent Vivier Reviewed-by: Richard Henderson Message-id: 20171108153245.20740-2-alex.bennee@linaro.org Suggested-by: Paolo Bonzini Cc: Richard Henderson Tested-by: Peter Maydell Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 11 ++++++++++ accel/tcg/translate-all.c | 52 ++++++++++++++++++++++++++--------------------- 2 files changed, 40 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 923ece3..0f51c92 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -45,6 +45,17 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, target_ulong *data); void cpu_gen_init(void); + +/** + * cpu_restore_state: + * @cpu: the vCPU state is to be restore to + * @searched_pc: the host PC the fault occurred at + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If the searched_pc is not in translated code no state is + * restored and the function returns false. + */ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); void QEMU_NORETURN cpu_loop_exit_noexc(CPUState *cpu); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 34c5e28..e7f0329 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -352,36 +352,42 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, return 0; } -bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc) { TranslationBlock *tb; bool r = false; + uintptr_t check_offset; - /* A retaddr of zero is invalid so we really shouldn't have ended - * up here. The target code has likely forgotten to check retaddr - * != 0 before attempting to restore state. We return early to - * avoid blowing up on a recursive tb_lock(). The target must have - * previously survived a failed cpu_restore_state because - * tb_find_pc(0) would have failed anyway. It still should be - * fixed though. + /* The host_pc has to be in the region of current code buffer. If + * it is not we will not be able to resolve it here. The two cases + * where host_pc will not be correct are: + * + * - fault during translation (instruction fetch) + * - fault from helper (not using GETPC() macro) + * + * Either way we need return early to avoid blowing up on a + * recursive tb_lock() as we can't resolve it here. + * + * We are using unsigned arithmetic so if host_pc < + * tcg_init_ctx.code_gen_buffer check_offset will wrap to way + * above the code_gen_buffer_size */ - - if (!retaddr) { - return r; - } - - tb_lock(); - tb = tb_find_pc(retaddr); - if (tb) { - cpu_restore_state_from_tb(cpu, tb, retaddr); - if (tb->cflags & CF_NOCACHE) { - /* one-shot translation, invalidate it immediately */ - tb_phys_invalidate(tb, -1); - tb_remove(tb); + check_offset = host_pc - (uintptr_t) tcg_init_ctx.code_gen_buffer; + + if (check_offset < tcg_init_ctx.code_gen_buffer_size) { + tb_lock(); + tb = tb_find_pc(host_pc); + if (tb) { + cpu_restore_state_from_tb(cpu, tb, host_pc); + if (tb->cflags & CF_NOCACHE) { + /* one-shot translation, invalidate it immediately */ + tb_phys_invalidate(tb, -1); + tb_remove(tb); + } + r = true; } - r = true; + tb_unlock(); } - tb_unlock(); return r; }