From patchwork Fri Nov 17 09:24:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu YiPing X-Patchwork-Id: 119136 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp289268qgn; Fri, 17 Nov 2017 01:29:43 -0800 (PST) X-Google-Smtp-Source: AGs4zMaLOT0ngEszSljYsO38meuNMGJM4gGDkcCf7zDg60MXRihk7gPPuZsC93AAFc9ijSsOavgd X-Received: by 10.159.214.140 with SMTP id n12mr4523271plp.4.1510910983500; Fri, 17 Nov 2017 01:29:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510910983; cv=none; d=google.com; s=arc-20160816; b=cI7JX1F9N86WVXU+v2XOS5E8B+gqCvcK67mSmNUWC9j8dj7WO162RH7pFoLzu4lgeJ ngMgthaWywEd3IJcZvM9SGIutJkvOb6JIYAhsHasRzoR0LmNffzygDwtFfFXCQ3p7cgA XXg4kNvs/jkyo3mP0sWtFNvpnIQN1qiA1n8VFhOk1Ige7VNnjEwdfJoNiib5GjyLsvFO n3cqYPQSqVaFQzjGUejvnN9RdUfjKs4Wv1egs8d4DpUN4e9Zgf2wrn1Kyq5bsBQdN8V+ HQY/11+S8YocSfaSSXc81uIrETtX6chOyZYLTu/PC3uqdgJNnVXvDS1yblFDSSLtkd3y p9zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=hb1UPrfynDn+ItjARRC62T49yiTDHtxGCix4Si2dWKo=; b=yerrU8gG7h/kHKLujflbuLRjMh9hS+QmrmPn+S+o5X/P2zCc2oOhJGzfpBJP1+yeCy ezLiOffeB4yDgHapwYAHqByeFqnURN2ndgZ57tDFhhxk5/oxsAwyqXByviOgpAuhGCpu qdwi871GY9ujcjW8/no1UOfqBpNU0S1+XPoOzkaLjUybGvYYHgtm9ID+QImXnnRIYHKa QJCYJvYj0+K7Q+IbcET6QTnXm4ehiEsvMagjoVeoEL41luzP0IM8r+j/q/htQVAcmZb9 SVaqUm72bDEjIBA7fOZe21vcM9Dml8OEdXePHoyGxdZf1cAAoerH+syesbtxs+yKJ6uO YDcw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u70si2668562pfk.350.2017.11.17.01.29.43; Fri, 17 Nov 2017 01:29:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965856AbdKQJ3P (ORCPT + 6 others); Fri, 17 Nov 2017 04:29:15 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10946 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965930AbdKQJ3J (ORCPT ); Fri, 17 Nov 2017 04:29:09 -0500 Received: from 172.30.72.58 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLA22892; Fri, 17 Nov 2017 17:25:22 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:24:34 +0800 From: Xu YiPing To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 1/3] dt-bindings: mailbox: Introduce Hi3660 controller binding Date: Fri, 17 Nov 2017 17:24:30 +0800 Message-ID: <1510910672-1409-2-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> References: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.5A0EAB02.0047, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bb0894d03a288da47192700d16d6f5ab Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Leo Yan Introduce a binding for the Hi3660 mailbox controller, the mailbox is used within application processor (AP), communication processor (CP), HIFI and MCU, etc. Signed-off-by: Leo Yan --- .../bindings/mailbox/hisilicon,hi3660-mailbox.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt new file mode 100644 index 0000000..3e5b453 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/hisilicon,hi3660-mailbox.txt @@ -0,0 +1,51 @@ +Hisilicon Hi3660 Mailbox Controller + +Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages +are passed between processors, including application & communication +processors, MCU, HIFI, etc. Each channel is unidirectional and accessed +by using MMIO registers; it supports maximum to 8 words message. + +Controller +---------- + +Required properties: +- compatible: : Shall be "hisilicon,hi3660-mbox" +- reg: : Offset and length of the device's register set +- #mbox-cells: : Must be 3 + <&phandle channel dst_irq ack_irq> + phandle : Label name of controller + channel : Channel number + dst_irq : Remote interrupt vector + ack_irq : Local interrupt vector + +- interrupts: : Contains the two IRQ lines for mailbox. + +Example: + +mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = <0x0 0xc0 0x4>, + <0x0 0xc1 0x4>; + #mbox-cells = <3>; +}; + +Client +------ + +Required properties: +- compatible : See the client docs +- mboxes : Standard property to specify a Mailbox (See ./mailbox.txt) + Cells must match 'mbox-cells' (See Controller docs above) + +Optional properties +- mbox-names : Name given to channels seen in the 'mboxes' property. + +Example: + +stub_clock: stub_clock@e896b500 { + compatible = "hisilicon,hi3660-stub-clk"; + reg = <0x0 0xe896b500 0x0 0x0100>; + #clock-cells = <1>; + mboxes = <&mailbox 13 3 0>; +}; From patchwork Fri Nov 17 09:24:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu YiPing X-Patchwork-Id: 119139 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp290070qgn; Fri, 17 Nov 2017 01:30:32 -0800 (PST) X-Google-Smtp-Source: AGs4zMZkXGU4Hb5xlDri/QdyJOCN+wFJ0VFcZozT1BQGZfZdHWTqdtPncdY/2ZWOTQxYv1DwV7Xq X-Received: by 10.159.205.130 with SMTP id v2mr4641988plo.105.1510911032844; Fri, 17 Nov 2017 01:30:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510911032; cv=none; d=google.com; s=arc-20160816; b=WlRoQ0NNk1TSHYqXSk/ZMN1ofCveXh4WrFeutjE4csxTf17WhPWmrIR/ZYhDLcideB yvMMTNeAAcGv6cRKJJax1iH/+QslJ9mpfnCWTx/FvZe+0ELDyh1CRJPCM5LvO/nbpQeJ cJememLuVvv+83YwGENZf/98zGyMDo0tQ3mwuR6nZ6A7e3zz1+/pYkDdghrO8slj1WCN C88ObkosZG8G1TCsr9K0N983hZEfgqLLFuD+YRkHMtnW90NeiX0Svpnvi2IqyC3yft0m ddkoscYznrnOZ4w7TaAwrk/tjo2uxfXrzCMajwcArqXMw+RQlt06z0gfWJ4YdI7VIWnF jPMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=bxPi9KeF5ze8dkjatvPkg4X02Zwf9uxz3f2+sXcufv0=; b=Hsz+P5O0CqdLPO5ktsJLfI4Kyk9c/A/G49Ptk3HzKc3L+4Y76HmY9qWONT3rJPHX90 QGqwqSCmOK4bLdlf09QYN+6L87BVM0n8eNjKAg4fdoKbiHwW9/5docv63L0WBYXoMXjo vLKBf4rhClv7hX3oe0QUJ4stTgmP4avmNlb0ekl3QO5V9GqimARj9SVvmMf3jLKcX8Ui klhP0dHKKPU0RUEIFiv7ZE6TnQr6wBJVVf+PPgljHEF33J9NO4WbuZTwzeZ7T79scfYe UlSOv7sgZW912UOaA5WangLKcBNoBWvUtsVWLtyZWLhWQE3SCqpBbruSHKy0QqxLsVA8 u/UQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k75si2710902pfg.360.2017.11.17.01.30.32; Fri, 17 Nov 2017 01:30:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757481AbdKQJab (ORCPT + 6 others); Fri, 17 Nov 2017 04:30:31 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10949 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965391AbdKQJ3R (ORCPT ); Fri, 17 Nov 2017 04:29:17 -0500 Received: from 172.30.72.58 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLA22888; Fri, 17 Nov 2017 17:25:21 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:24:34 +0800 From: Xu YiPing To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 2/3] mailbox: Add support for Hi3660 mailbox Date: Fri, 17 Nov 2017 17:24:31 +0800 Message-ID: <1510910672-1409-3-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> References: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.5A0EAB01.0099, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 06d5037821e1e3a19b7796815a27a9ab Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kaihua Zhong Hi3660 mailbox controller is used to send message within multiple processors, MCU, HIFI, etc. It supports 32 mailbox channels and every channel can only be used for single transferring direction. Once the channel is enabled, it needs to specify the destination interrupt and acknowledge interrupt, these two interrupt vectors are used to create the connection between the mailbox and interrupt controllers. The data transferring supports two modes, one is named as "automatic acknowledge" mode so after send message the kernel doesn't need to wait for acknowledge from remote and directly return; there have another mode is to rely on handling interrupt for acknowledge. This commit is for initial version driver, which only supports "automatic acknowledge" mode to support CPU clock, which is the only one consumer to use mailbox and has been verified. Later may enhance this driver for interrupt mode (e.g. for supporting HIFI). Signed-off-by: Leo Yan Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 2 + drivers/mailbox/hi3660-mailbox.c | 322 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 332 insertions(+) create mode 100644 drivers/mailbox/hi3660-mailbox.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index c5731e5..4b5d6e9 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -108,6 +108,14 @@ config TI_MESSAGE_MANAGER multiple processors within the SoC. Select this driver if your platform has support for the hardware block. +config HI3660_MBOX + tristate "Hi3660 Mailbox" + depends on ARCH_HISI && OF + help + An implementation of the hi3660 mailbox. It is used to send message + between application processors and other processors/MCU/DSP. Select + Y here if you want to use Hi3660 mailbox controller. + config HI6220_MBOX tristate "Hi6220 Mailbox" depends on ARCH_HISI diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d54e412..7d1bd51 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -26,6 +26,8 @@ obj-$(CONFIG_TI_MESSAGE_MANAGER) += ti-msgmgr.o obj-$(CONFIG_XGENE_SLIMPRO_MBOX) += mailbox-xgene-slimpro.o +obj-$(CONFIG_HI3660_MBOX) += hi3660-mailbox.o + obj-$(CONFIG_HI6220_MBOX) += hi6220-mailbox.o obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c new file mode 100644 index 0000000..ba80834 --- /dev/null +++ b/drivers/mailbox/hi3660-mailbox.c @@ -0,0 +1,322 @@ +/* + * Hisilicon's Hi3660 mailbox controller driver + * + * Copyright (c) 2017 Hisilicon Limited. + * Copyright (c) 2017 Linaro Limited. + * + * Author: Leo Yan + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mailbox.h" + +#define MBOX_CHAN_MAX 32 + +#define MBOX_RX (0x0) +#define MBOX_TX (0x1) + +#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x40)) +#define MBOX_SRC_REG (0x00) +#define MBOX_DST_REG (0x04) +#define MBOX_DCLR_REG (0x08) +#define MBOX_DSTAT_REG (0x0c) +#define MBOX_MODE_REG (0x10) +#define MBOX_IMASK_REG (0x14) +#define MBOX_ICLR_REG (0x18) +#define MBOX_SEND_REG (0x1c) +#define MBOX_DATA_REG (0x20) + +#define MBOX_IPC_LOCK_REG (0xa00) +#define MBOX_IPC_UNLOCK (0x1acce551) + +#define MBOX_AUTOMATIC_ACK (1) + +#define MBOX_STATE_IDLE BIT(4) +#define MBOX_STATE_ACK BIT(7) + +#define MBOX_MSG_LEN 8 + +/** + * Hi3660 mailbox channel device data + * + * A channel can be used for TX or RX, it can trigger remote + * processor interrupt to notify remote processor and can receive + * interrupt if has incoming message. + * + * @dst_irq: Interrupt vector for remote processor + * @ack_irq: Interrupt vector for local processor + */ +struct hi3660_mbox_dev { + unsigned int dst_irq; + unsigned int ack_irq; +}; + +/** + * Hi3660 mailbox controller data + * + * Mailbox controller includes 32 channels and can allocate + * channel for message transferring. + * + * @dev: Device to which it is attached + * @base: Base address of the register mapping region + * @chan: Representation of channels in mailbox controller + * @mdev: Representation of channel device data + * @controller: Representation of a communication channel controller + */ +struct hi3660_mbox { + struct device *dev; + void __iomem *base; + struct mbox_chan chan[MBOX_CHAN_MAX]; + struct hi3660_mbox_dev mdev[MBOX_CHAN_MAX]; + struct mbox_controller controller; +}; + +static inline struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox) +{ + return container_of(mbox, struct hi3660_mbox, controller); +} + +static int hi3660_mbox_check_state(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_mbox_dev *mdev = &mbox->mdev[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned long val; + unsigned int state, ret; + + /* Mailbox is idle so directly bail out */ + state = readl_relaxed(base + MBOX_MODE_REG); + if (state & MBOX_STATE_IDLE) + return 0; + + /* Wait for acknowledge from remote */ + ret = readx_poll_timeout_atomic(readl_relaxed, base + MBOX_MODE_REG, + val, (val & MBOX_STATE_ACK), 1000, 300000); + if (ret) { + dev_err(mbox->dev, "%s: timeout for receiving ack\n", __func__); + return ret; + } + + /* Ensure channel is released */ + writel_relaxed(0xffffffff, base + MBOX_IMASK_REG); + writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SRC_REG); + + return 0; +} + +static int hi3660_mbox_unlock(struct mbox_chan *chan) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + unsigned int val, retry = 3; + + do { + writel_relaxed(MBOX_IPC_UNLOCK, mbox->base + MBOX_IPC_LOCK_REG); + + val = readl_relaxed(mbox->base + MBOX_IPC_LOCK_REG); + if (!val) + break; + + udelay(10); + } while (retry--); + + return (!val) ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_acquire_channel(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_mbox_dev *mdev = &mbox->mdev[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned int val, retry; + + for (retry = 10; retry; retry--) { + /* Check if channel has been acquired */ + if (readl_relaxed(base + MBOX_MODE_REG) & MBOX_STATE_IDLE) { + writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SRC_REG); + val = readl_relaxed(base + MBOX_SRC_REG); + if (val & BIT(mdev->ack_irq)) + break; + } + } + + return retry ? 0 : -ETIMEDOUT; +} + +static int hi3660_mbox_send(struct mbox_chan *chan, u32 *msg) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + struct hi3660_mbox_dev *mdev = &mbox->mdev[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + unsigned int i; + + /* Clear mask for destination interrupt */ + writel_relaxed(~BIT(mdev->dst_irq), base + MBOX_IMASK_REG); + + /* Config destination for interrupt vector */ + writel_relaxed(BIT(mdev->dst_irq), base + MBOX_DST_REG); + + /* Automatic acknowledge mode */ + writel_relaxed(MBOX_AUTOMATIC_ACK, base + MBOX_MODE_REG); + + /* Fill message data */ + for (i = 0; i < MBOX_MSG_LEN; i++) + writel_relaxed(msg[i], base + MBOX_DATA_REG + i * 4); + + /* Trigger data transferring */ + writel_relaxed(BIT(mdev->ack_irq), base + MBOX_SEND_REG); + return 0; +} + +static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(chan->mbox); + int err; + + err = hi3660_mbox_check_state(chan); + if (err) { + dev_err(mbox->dev, "checking state failed\n"); + return err; + } + + err = hi3660_mbox_unlock(chan); + if (err) { + dev_err(mbox->dev, "unlocking mailbox failed\n"); + return err; + } + + err = hi3660_mbox_acquire_channel(chan); + if (err) { + dev_err(mbox->dev, "acquiring channel failed\n"); + return err; + } + + return hi3660_mbox_send(chan, msg); +} + +static struct mbox_chan_ops hi3660_mbox_ops = { + .send_data = hi3660_mbox_send_data, +}; + +static struct mbox_chan *hi3660_mbox_xlate(struct mbox_controller *controller, + const struct of_phandle_args *spec) +{ + struct hi3660_mbox *mbox = to_hi3660_mbox(controller); + struct hi3660_mbox_dev *mdev; + unsigned int ch = spec->args[0]; + + if (ch >= MBOX_CHAN_MAX) { + dev_err(mbox->dev, "Invalid channel idx %d\n", ch); + return ERR_PTR(-EINVAL); + } + + mdev = &mbox->mdev[ch]; + mdev->dst_irq = spec->args[1]; + mdev->ack_irq = spec->args[2]; + + return &mbox->chan[ch]; +} + +static const struct of_device_id hi3660_mbox_of_match[] = { + { .compatible = "hisilicon,hi3660-mbox", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, hi3660_mbox_of_match); + +static int hi3660_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct hi3660_mbox *mbox; + struct mbox_chan *chan; + struct resource *res; + unsigned long ch; + int err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->base = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->base)) + return PTR_ERR(mbox->base); + + mbox->dev = dev; + mbox->controller.dev = dev; + mbox->controller.chans = mbox->chan; + mbox->controller.num_chans = MBOX_CHAN_MAX; + mbox->controller.ops = &hi3660_mbox_ops; + mbox->controller.of_xlate = hi3660_mbox_xlate; + + /* Initialize mailbox channel data */ + chan = mbox->chan; + for (ch = 0; ch < MBOX_CHAN_MAX; ch++) + chan[ch].con_priv = (void *)ch; + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + return 0; +} + +static int hi3660_mbox_remove(struct platform_device *pdev) +{ + struct hi3660_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + return 0; +} + +static struct platform_driver hi3660_mbox_driver = { + .probe = hi3660_mbox_probe, + .remove = hi3660_mbox_remove, + .driver = { + .name = "hi3660-mbox", + .of_match_table = hi3660_mbox_of_match, + }, +}; + +static int __init hi3660_mbox_init(void) +{ + return platform_driver_register(&hi3660_mbox_driver); +} +core_initcall(hi3660_mbox_init); + +static void __exit hi3660_mbox_exit(void) +{ + platform_driver_unregister(&hi3660_mbox_driver); +} +module_exit(hi3660_mbox_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Hisilicon Hi3660 Mailbox Controller"); +MODULE_AUTHOR("Leo Yan "); From patchwork Fri Nov 17 09:24:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu YiPing X-Patchwork-Id: 119137 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp289926qgn; Fri, 17 Nov 2017 01:30:23 -0800 (PST) X-Google-Smtp-Source: AGs4zMYsZP/ObylRc+eVqkx1CJGJkrY8xaUb1L0D//fiP8GQye+VWBM5bmy+p/1WoxH9qd4fMQ4J X-Received: by 10.98.70.132 with SMTP id o4mr1436240pfi.102.1510911023804; Fri, 17 Nov 2017 01:30:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1510911023; cv=none; d=google.com; s=arc-20160816; b=ZlpzQfRBLNb/zSrYGgy5+OpSN5/xsRWz5YE0Y04uw0tBGasV66Tr1Zqi3gUpvLcHmq /ubXPVqA0A+jpYbeZYVcxh0WaQULodcyZZex8fDUh/uFOQ0aKdr2Po8bFxym8bz52QuO t3M6C53sAZc28hB9b3RSzmdhDc9qBpI2uk2aZBMJGkgYK28NAdRjKlj9vE219McEsGZd zFsuQu4LslR2KtAoAgN8ns0ii5e5INWray5sJa0x8Nxzh/WaqFWZ3TW3N9yMHGH49g10 ovQ5hY9xMEGjXZ4GFd138cZ0+HTP/i73nafUtI4wy9K10rnDqVHiFBFcbAkHsId65xL0 dBZQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id u70si2668562pfk.350.2017.11.17.01.30.23; Fri, 17 Nov 2017 01:30:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965492AbdKQJ3Y (ORCPT + 6 others); Fri, 17 Nov 2017 04:29:24 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10947 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965928AbdKQJ3K (ORCPT ); Fri, 17 Nov 2017 04:29:10 -0500 Received: from 172.30.72.58 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLA22890; Fri, 17 Nov 2017 17:25:21 +0800 (CST) Received: from vm167-7.huawei.com (10.177.167.7) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.361.1; Fri, 17 Nov 2017 17:24:35 +0800 From: Xu YiPing To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 3/3] dts: arm64: Add mailbox binding for hi3660 Date: Fri, 17 Nov 2017 17:24:32 +0800 Message-ID: <1510910672-1409-4-git-send-email-xuyiping@hisilicon.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> References: <1510910672-1409-1-git-send-email-xuyiping@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.177.167.7] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0205.5A0EAB01.0140, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b305f9f5be18260eb19a0c881cb90643 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kaihua Zhong Add DT binding for mailbox driver. Signed-off-by: Leo Yan Signed-off-by: Ruyi Wang Signed-off-by: Kaihua Zhong --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 610990f..451b6bf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -285,6 +285,14 @@ #reset-cells = <2>; }; + mailbox: mailbox@e896b000 { + compatible = "hisilicon,hi3660-mbox"; + reg = <0x0 0xe896b000 0x0 0x1000>; + interrupts = , + ; + #mbox-cells = <3>; + }; + dual_timer0: timer@fff14000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x0 0xfff14000 0x0 0x1000>;