From patchwork Wed Nov 29 14:14:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 120015 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3115095qgn; Wed, 29 Nov 2017 06:19:42 -0800 (PST) X-Google-Smtp-Source: AGs4zMZD+97eJ9LlV83ZH3/DTqkH3K3cVlgCFM4TAyakvaMy+joc8uy0S/qLLfkFzj9IZZGflS4A X-Received: by 10.84.174.1 with SMTP id q1mr3155305plb.220.1511965182321; Wed, 29 Nov 2017 06:19:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511965182; cv=none; d=google.com; s=arc-20160816; b=Arg7L0pTiRHTloYI/MlQODi8tA368e76OR6kclYOGtUyhmDzxg9nsZVXeMsi8B9bZk BzbyhVklA2lqlN0Awcead+Yv7dPg4BEhsf9/mscY5jhnlJwhZ1GAeArdHY4RWkxi0WMw dZNZrWe4rKXMbhVYLYuQRdxcMNUX5/sCtVBUfJ+ZfBZ3SMQm9tufQbJq00eRZd+wVpXq Qm0fTDOC8DmK7mDyTbOPam2JvS2qHBtheHiOt6NfcFsDhu0FR9o3oast7ra5CA+E640D wGs9qJL80OUywwyeekr2wQ/LtofgfVzMe29S1f38HsCfDohUScukgRLBrJ1oYANVtO/4 Ur2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=WKXD5dJwyt7AgDbSkfo/DBIWif7kGibgp/bLlLb+2fQ=; b=gGTfMeijDcYvGTSPY5wDp3N3TJSTknPm+HGWuMyfvUkPF4dTNwvOX2pn0yXeCG8DRf FJbixmhatS2j5UwmNlvmgmADiNOnfpi+mETDnvze0ISXvBUKw0xph9EQd7KP1BhDOeMS vjCb5+AnuMC39z2wz6Tf7BOASLK5CASP2yVgsbSxWjPIr5bl56MMw0sY2H1iPwpvk4/U /ra2pXFOYdktGkM0nD/AaO+agdC6m1VXbV3G5IIkiQDMVD844eKz1jnAXcHUfhawiRtp VdMxnXJPW0k9YPP3IIZOoepQSDbeQr685w2lQ2hAiSZQpZwVh0LWtYEZ0+EcZbU1PE0A cEjw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i3si1321734pgc.833.2017.11.29.06.19.42; Wed, 29 Nov 2017 06:19:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752344AbdK2OTk (ORCPT + 7 others); Wed, 29 Nov 2017 09:19:40 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11474 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753759AbdK2ORb (ORCPT ); Wed, 29 Nov 2017 09:17:31 -0500 Received: from 172.30.72.60 (EHLO DGGEMS411-HUB.china.huawei.com) ([172.30.72.60]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DLR92804; Wed, 29 Nov 2017 22:16:39 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Wed, 29 Nov 2017 22:16:32 +0800 From: Shameer Kolothum To: , , , , CC: , , , , , , , , Shameer Kolothum Subject: [PATCH v10 2/3] iommu/dma: Add HW MSI(GICv3 ITS) address regions reservation Date: Wed, 29 Nov 2017 14:14:48 +0000 Message-ID: <20171129141449.120316-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171129141449.120316-1-shameerali.kolothum.thodi@huawei.com> References: <20171129141449.120316-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.5A1EC148.0083, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 511c57110f51f5fa2ef97a3f28a66b1f Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Modified iommu_dma_get_resv_regions() to include GICv3 ITS region on ACPI based ARM platfiorms which may require HW MSI reservations. Signed-off-by: Shameer Kolothum --- drivers/iommu/dma-iommu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Robin Murphy diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 25914d3..f05f3cf 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -19,6 +19,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -167,13 +168,18 @@ void iommu_put_dma_cookie(struct iommu_domain *domain) * * IOMMU drivers can use this to implement their .get_resv_regions callback * for general non-IOMMU-specific reservations. Currently, this covers host - * bridge windows for PCI devices. + * bridge windows for PCI devices and GICv3 ITS region reservation on ACPI + * based ARM platforms that may require HW MSI reservation. */ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) { struct pci_host_bridge *bridge; struct resource_entry *window; + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode) && + iort_iommu_msi_get_resv_regions(dev, list) < 0) + return; + if (!dev_is_pci(dev)) return; From patchwork Wed Nov 29 14:14:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 120010 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3111744qgn; Wed, 29 Nov 2017 06:16:52 -0800 (PST) X-Google-Smtp-Source: AGs4zMZVOVizX28oJxI06NvKDX16qkW3aZviomwB6YOsnkKy5/tL663GUSHZZIfAn/pJInCFp1AY X-Received: by 10.159.253.73 with SMTP id b9mr3023156plx.357.1511965012163; Wed, 29 Nov 2017 06:16:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511965012; cv=none; d=google.com; s=arc-20160816; b=Ia0sxQdZdkagPktFXccJv6HkBG65okbUmN/gzCPhDPv/9gJBR1d7bkg4vCFV+s1FmH FAIV4xPfOfWtspbrbrG46/ztD/uoLsJkeuBs2MoEnzvi9oHaVKAp+b3GXnyvNinHCeeR feHcE3kFY0O9WJkNOzsDPqaUC5ybX1vQmt2kLFCGpOUbzZwbDS5g99FAwX+zlLTwJjuH CH5SUZ7iuBsRfhKmK+pUh5NHjVLUtYbA4DX+GJzyKeSV0MAlXAJyiVJ5ZqJL0U0+t4DM wzy8BrPTPI+Lgv98Qi0Or64h7ZmsR0zlT97DIFPLMJlF1U1YAS6ftYrn5mDg4M5lBKgf Ad5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=o19kW1wLU8MDIujGimkwGPqEQv4H208yUdU1wSK/zyc=; b=YpVJD7AqOHuZVNv92lKP1gtG7Lq5UtBSbIP4TkvEAjmFoEXolJJuVwYLlEGM2jX0AJ fmTTy3PIu3CQVyfddGi+Smq3c4K8lXDD2M2UN+E0oEbw/f2fD7fXrszFJzae+dFlTuzz jkrPmPRExFVCaWbwwIyQLUCO9uu2v6bDGrZdi+uzuWYN6XsmooBN0U8ZT/LB9woSJGnG TPeN5YeZ6bYXjgm0Ryq25CvbgYSaMYEQQbNpfRlK6mlRl/oDuawK358mqvZ+Sh2wRK8d eJBCTi79Mmv2vtj+xNCOYltIEVa/P2Ekwu7A2r9oAefSz301Gwl1mjMPcYeKuV7ssZzB OXXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si1318931pgo.205.2017.11.29.06.16.52; Wed, 29 Nov 2017 06:16:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932764AbdK2OQu (ORCPT + 7 others); Wed, 29 Nov 2017 09:16:50 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:48972 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932321AbdK2OQr (ORCPT ); Wed, 29 Nov 2017 09:16:47 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 04B0046791DC8; Wed, 29 Nov 2017 22:16:42 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Wed, 29 Nov 2017 22:16:36 +0800 From: Shameer Kolothum To: , , , , CC: , , , , , , , , Shameer Kolothum Subject: [PATCH v10 3/3] arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 Date: Wed, 29 Nov 2017 14:14:49 +0000 Message-ID: <20171129141449.120316-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171129141449.120316-1-shameerali.kolothum.thodi@huawei.com> References: <20171129141449.120316-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it difficult for these platforms to have SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to explicitly disable the hip06/hip07 smmu entries in dts. Signed-off-by: Shameer Kolothum Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 55 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 24 ++++++++++++++ 2 files changed, 79 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a049b64..d0d5933 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -291,6 +291,13 @@ #interrupt-cells = <2>; num-pins = <128>; }; + + mbigen_pcie0: intc_pcie0 { + msi-parent = <&its_dsa 0x40085>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; }; mbigen_dsa@c0080000 { @@ -312,6 +319,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -676,6 +707,30 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + pcie0: pcie@a0090000 { + compatible = "hisilicon,hip06-pcie-ecam"; + reg = <0 0xb0000000 0 0x2000000>, + <0 0xa0090000 0 0x10000>; + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 + 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 + 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21..58fe013 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1083,6 +1083,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;