From patchwork Mon Dec 4 01:29:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 120469 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3864749qgn; Sun, 3 Dec 2017 17:30:52 -0800 (PST) X-Google-Smtp-Source: AGs4zMa1Y/SfJH0mvdIw3/fHeO3qem/GCGImkixOnz5Zxp+u2boXqU9DIGbXY8a5Sggg8Du2j68z X-Received: by 10.101.96.213 with SMTP id r21mr12137430pgv.395.1512351051963; Sun, 03 Dec 2017 17:30:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512351051; cv=none; d=google.com; s=arc-20160816; b=s3KKk+8KWSPtZgrcMGFSCmTw4giagqJlZkBpvvldhH2Fcfzjm0IvP3G6uBkehsupHG 91mcW23pTxy+OvYZv/fFKEQ3mRU5e8jfXN3YVZfIe1WhKUY60ss7QzdJkFvOmQH6CAJ9 uAW7H3ysw4bdcWMIHZ7Y4CxLQ4Yj/gLbVtUVE+5pkgYpbrfOmqOxzHjKbhGhd1hU103W 2uOY22VygvIrToxmG7fpJh+cMvuJ4YknZAswCKd5PapruSMEtJqCjrqpk3qZYHMMjCZO B0KoAA5YLi1TsPtXQnxtjM0uGYQLVawIy0XCltbv8hCOCuBxi8mRI1rriP8ped1X3Zpk CUBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=SmErqrhBjgrjL0bIH6mYazwuQspMQad/ceI1KT3aUlc=; b=A6GqgUmgpW53GmJbh/mRKtsV/2II2UVC+nQCyxSRYEHObK6Kg+qV091r/R/PyRyL6+ Y0KX9wpsTbsT8TFSTusR7PGjBGAeUc7hvpLJLo0xya/1pNmzSB5pEPIzj/O/3VVVPNl4 iQlbBreD3Y5Vu0yuyQWwpQyY4G69kC4feFfj3V/H27lH5osNgTqrH5a8cRCZfY9Nyp36 +Z8CZECkstBURABj4m74s40U6fVbOkNW4yFVZuG8wKZxBeY7uJOSCDDyKlBPAqibmXbb PRJlyURxOMCtUuin/JBDynd9fdkmdACjJWdTEcUb5peoTP0z/UzwZG5U9fLR1C6r4gvW fiVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n1si8822615pld.460.2017.12.03.17.30.51; Sun, 03 Dec 2017 17:30:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752488AbdLDBat (ORCPT + 7 others); Sun, 3 Dec 2017 20:30:49 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2249 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751111AbdLDBar (ORCPT ); Sun, 3 Dec 2017 20:30:47 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9520BCE93FEBC; Mon, 4 Dec 2017 09:30:42 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.47.83.141) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Mon, 4 Dec 2017 09:30:36 +0800 From: Salil Mehta To: CC: , , , , , , , Subject: [PATCH V2 net-next 2/3] net: hns3: Add reset service task for handling reset requests Date: Mon, 4 Dec 2017 01:29:54 +0000 Message-ID: <20171204012955.17560-3-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20171204012955.17560-1-salil.mehta@huawei.com> References: <20171204012955.17560-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.141] X-CFilter-Loop: Reflected Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Existing common service task was being used to service the reset requests. This patch tries to make the handling of reset cleaner by separating task to handle the reset requests. This might in turn help in adapting similar handling approach for other interrupt events like mailbox, sharing vector 0 interrupt. Signed-off-by: Salil Mehta Signed-off-by: lipeng --- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 41 ++++++++++++++++------ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 4 +++ 2 files changed, 34 insertions(+), 11 deletions(-) -- 2.11.0 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 0c0543e84957..345868470201 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -2226,6 +2226,12 @@ static int hclge_mac_init(struct hclge_dev *hdev) return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc); } +static void hclge_reset_task_schedule(struct hclge_dev *hdev) +{ + if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) + schedule_work(&hdev->rst_service_task); +} + static void hclge_task_schedule(struct hclge_dev *hdev) { if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && @@ -2421,7 +2427,7 @@ static irqreturn_t hclge_misc_irq_handle(int irq, void *data) */ switch (event_cause) { case HCLGE_VECTOR0_EVENT_RST: - /* reset task to be scheduled here */ + hclge_reset_task_schedule(hdev); break; default: dev_dbg(&hdev->pdev->dev, @@ -2584,6 +2590,9 @@ static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type) case HNAE3_FUNC_RESET: dev_info(&pdev->dev, "PF Reset requested\n"); hclge_func_reset_cmd(hdev, 0); + /* schedule again to check later */ + set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); + hclge_reset_task_schedule(hdev); break; default: dev_warn(&pdev->dev, @@ -2605,14 +2614,9 @@ static void hclge_reset_event(struct hnae3_handle *handle, case HNAE3_FUNC_RESET: case HNAE3_CORE_RESET: case HNAE3_GLOBAL_RESET: - if (test_bit(HCLGE_STATE_RESET_INT, &hdev->state)) { - dev_err(&hdev->pdev->dev, "Already in reset state"); - return; - } - hdev->reset_type = reset; - set_bit(HCLGE_STATE_RESET_INT, &hdev->state); - set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); - schedule_work(&hdev->service_task); + /* request reset & schedule reset task */ + set_bit(reset, &hdev->reset_request); + hclge_reset_task_schedule(hdev); break; default: dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset); @@ -2658,9 +2662,19 @@ static void hclge_reset_subtask(struct hclge_dev *hdev) hdev->reset_type = HNAE3_NONE_RESET; } -static void hclge_misc_irq_service_task(struct hclge_dev *hdev) +static void hclge_reset_service_task(struct work_struct *work) { + struct hclge_dev *hdev = + container_of(work, struct hclge_dev, rst_service_task); + + if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) + return; + + clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); + hclge_reset_subtask(hdev); + + clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); } static void hclge_service_task(struct work_struct *work) @@ -2668,7 +2682,6 @@ static void hclge_service_task(struct work_struct *work) struct hclge_dev *hdev = container_of(work, struct hclge_dev, service_task); - hclge_misc_irq_service_task(hdev); hclge_update_speed_duplex(hdev); hclge_update_link_status(hdev); hclge_update_stats_for_all(hdev); @@ -4699,6 +4712,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) hdev->pdev = pdev; hdev->ae_dev = ae_dev; hdev->reset_type = HNAE3_NONE_RESET; + hdev->reset_request = 0; hdev->reset_pending = 0; ae_dev->priv = hdev; @@ -4811,12 +4825,15 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) timer_setup(&hdev->service_timer, hclge_service_timer, 0); INIT_WORK(&hdev->service_task, hclge_service_task); + INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); /* Enable MISC vector(vector0) */ hclge_enable_vector(&hdev->misc_vector, true); set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); set_bit(HCLGE_STATE_DOWN, &hdev->state); + clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); + clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); return 0; @@ -4928,6 +4945,8 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) del_timer_sync(&hdev->service_timer); if (hdev->service_task.func) cancel_work_sync(&hdev->service_task); + if (hdev->rst_service_task.func) + cancel_work_sync(&hdev->rst_service_task); if (mac->phydev) mdiobus_unregister(mac->mdio_bus); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index d4429496f4b5..fd04fd23b76a 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -99,6 +99,8 @@ enum HCLGE_DEV_STATE { HCLGE_STATE_REMOVING, HCLGE_STATE_SERVICE_INITED, HCLGE_STATE_SERVICE_SCHED, + HCLGE_STATE_RST_SERVICE_SCHED, + HCLGE_STATE_RST_HANDLING, HCLGE_STATE_MBX_HANDLING, HCLGE_STATE_MBX_IRQ, HCLGE_STATE_RESET_INT, @@ -426,6 +428,7 @@ struct hclge_dev { unsigned long state; enum hnae3_reset_type reset_type; + unsigned long reset_request; /* reset has been requested */ unsigned long reset_pending; /* client rst is pending to be served */ u32 fw_version; u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ @@ -476,6 +479,7 @@ struct hclge_dev { unsigned long service_timer_previous; struct timer_list service_timer; struct work_struct service_task; + struct work_struct rst_service_task; bool cur_promisc; int num_alloc_vfs; /* Actual number of VFs allocated */ From patchwork Mon Dec 4 01:29:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 120471 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3864911qgn; Sun, 3 Dec 2017 17:31:07 -0800 (PST) X-Google-Smtp-Source: AGs4zMagjB7oN8kN97nOq37+bfdNN/6zz3c1VJvo1omyqJvhyzEP84zZOARDa/+EdNMU14ObPiFP X-Received: by 10.98.76.90 with SMTP id z87mr17860558pfa.194.1512351067616; Sun, 03 Dec 2017 17:31:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512351067; cv=none; d=google.com; s=arc-20160816; b=WT6hjtkmWu76XjvKuJtyl/iKoZBriV0oinDGGP+ABlacB4xDBsY2/weq3NgIqSPrLm hpDnrf9S8/5gLD1H53cNgmPmd33n5tG0YXaL7mTj9iqRSeh/YNlO5RnEJBKj+0eB2w9Z q/2I9jevDRDs7jqT+ssJDXkbQUS9gYtVWijQEP014U2qgxRpgoyEwHvmI4qWvZHa/NRt FrpQrFyMseBFwW/xeRLJj3m85t2rYzV7dRwAMht9VlBb3vTq0Uy/ln7w/FsX7+/tSzs9 ndZW8ukjB2MO1uqSOea4h3FH/A0OsAQU5KKhoKDJK8LvgrGiRXK1coKtiee1LlJ1Do2N WCHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=z6nxRnmTYJYS+GsTx3Cj1KHcSctaJTS7y1FUE7b1oIw=; b=uzpqp2NEQZVCQ11MWmAhR6tBJSAbdrRowla59WO2VKzI38vOLsinvq2NAODA02Sg30 R7VgjiPVD3KM9cl8/SQKvWTt42LdsRVQD7G0b918mbQONHGDDYxsDxk5QMkBhs6DneVi iBHu8Xoq8ezQFyo8reVuto2OPkgOGdX0OLqqswgOidMrhThh8Ke2550Q5yR2of2Grpc4 WhU96d3ImfV246EfR2gaj8yA0dGVNpf37bHEoywX766QRxzCPU8iGeBLp5b+MQ8OX6Ud r+F30vUrtYcldhaW1He5pPqw7cWIDeP2rGB1mEHq2GZ5xYx9rmBkLuma86BP1esJetF2 JCgA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n6si8762892pla.772.2017.12.03.17.31.07; Sun, 03 Dec 2017 17:31:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752935AbdLDBbF (ORCPT + 7 others); Sun, 3 Dec 2017 20:31:05 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2200 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752919AbdLDBbD (ORCPT ); Sun, 3 Dec 2017 20:31:03 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 536FA3878AD5F; Mon, 4 Dec 2017 09:30:48 +0800 (CST) Received: from S00293818-DELL1.china.huawei.com (10.47.83.141) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Mon, 4 Dec 2017 09:30:39 +0800 From: Salil Mehta To: CC: , , , , , , , Subject: [PATCH V2 net-next 3/3] net: hns3: Refactors the requested reset & pending reset handling code Date: Mon, 4 Dec 2017 01:29:55 +0000 Message-ID: <20171204012955.17560-4-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20171204012955.17560-1-salil.mehta@huawei.com> References: <20171204012955.17560-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.141] X-CFilter-Loop: Reflected Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org In exisiting code, the way to detect if driver/client reset should be executed or if hardware should be be soft resetted was overly complex. Existing code use to read the interrupt status register from task context to figure out if the interrupt source event was reset and then use clear the interrupt source for reset while waiting for the hardware to finish the reset. This behaviour again was confusing and overly complex in terms of the flow. This patch simplifies the handling of the requested reset and the pending reset(i.e. reset which have already been asserted by the software and hardware has acknowledged back to driver that it is processing the hardware reset through interrupt) Signed-off-by: Salil Mehta Signed-off-by: lipeng --- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 100 +++++++++++++-------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 1 - 2 files changed, 65 insertions(+), 36 deletions(-) -- 2.11.0 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 345868470201..d07c700c7ff8 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -17,7 +17,7 @@ #include #include #include - +#include #include "hclge_cmd.h" #include "hclge_dcb.h" #include "hclge_main.h" @@ -2569,12 +2569,12 @@ static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) return ret; } -static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type) +static void hclge_do_reset(struct hclge_dev *hdev) { struct pci_dev *pdev = hdev->pdev; u32 val; - switch (type) { + switch (hdev->reset_type) { case HNAE3_GLOBAL_RESET: val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); @@ -2596,11 +2596,56 @@ static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type) break; default: dev_warn(&pdev->dev, - "Unsupported reset type: %d\n", type); + "Unsupported reset type: %d\n", hdev->reset_type); break; } } +static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, + unsigned long *addr) +{ + enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; + + /* return the highest priority reset level amongst all */ + if (test_bit(HNAE3_GLOBAL_RESET, addr)) + rst_level = HNAE3_GLOBAL_RESET; + else if (test_bit(HNAE3_CORE_RESET, addr)) + rst_level = HNAE3_CORE_RESET; + else if (test_bit(HNAE3_IMP_RESET, addr)) + rst_level = HNAE3_IMP_RESET; + else if (test_bit(HNAE3_FUNC_RESET, addr)) + rst_level = HNAE3_FUNC_RESET; + + /* now, clear all other resets */ + clear_bit(HNAE3_GLOBAL_RESET, addr); + clear_bit(HNAE3_CORE_RESET, addr); + clear_bit(HNAE3_IMP_RESET, addr); + clear_bit(HNAE3_FUNC_RESET, addr); + + return rst_level; +} + +static void hclge_reset(struct hclge_dev *hdev) +{ + /* perform reset of the stack & ae device for a client */ + + hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); + + if (!hclge_reset_wait(hdev)) { + rtnl_lock(); + hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); + hclge_reset_ae_dev(hdev->ae_dev); + hclge_notify_client(hdev, HNAE3_INIT_CLIENT); + rtnl_unlock(); + } else { + /* schedule again to check pending resets later */ + set_bit(hdev->reset_type, &hdev->reset_pending); + hclge_reset_task_schedule(hdev); + } + + hclge_notify_client(hdev, HNAE3_UP_CLIENT); +} + static void hclge_reset_event(struct hnae3_handle *handle, enum hnae3_reset_type reset) { @@ -2626,39 +2671,24 @@ static void hclge_reset_event(struct hnae3_handle *handle, static void hclge_reset_subtask(struct hclge_dev *hdev) { - bool do_reset; - - do_reset = hdev->reset_type != HNAE3_NONE_RESET; - - - if (hdev->reset_type == HNAE3_NONE_RESET) - return; - - switch (hdev->reset_type) { - case HNAE3_FUNC_RESET: - case HNAE3_CORE_RESET: - case HNAE3_GLOBAL_RESET: - case HNAE3_IMP_RESET: - hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); + /* check if there is any ongoing reset in the hardware. This status can + * be checked from reset_pending. If there is then, we need to wait for + * hardware to complete reset. + * a. If we are able to figure out in reasonable time that hardware + * has fully resetted then, we can proceed with driver, client + * reset. + * b. else, we can come back later to check this status so re-sched + * now. + */ + hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); + if (hdev->reset_type != HNAE3_NONE_RESET) + hclge_reset(hdev); - if (do_reset) - hclge_do_reset(hdev, hdev->reset_type); - else - set_bit(HCLGE_STATE_RESET_INT, &hdev->state); + /* check if we got any *new* reset requests to be honored */ + hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); + if (hdev->reset_type != HNAE3_NONE_RESET) + hclge_do_reset(hdev); - if (!hclge_reset_wait(hdev)) { - hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); - hclge_reset_ae_dev(hdev->ae_dev); - hclge_notify_client(hdev, HNAE3_INIT_CLIENT); - clear_bit(HCLGE_STATE_RESET_INT, &hdev->state); - } - hclge_notify_client(hdev, HNAE3_UP_CLIENT); - break; - default: - dev_err(&hdev->pdev->dev, "Unsupported reset type:%d\n", - hdev->reset_type); - break; - } hdev->reset_type = HNAE3_NONE_RESET; } diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index fd04fd23b76a..aacec438b933 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -103,7 +103,6 @@ enum HCLGE_DEV_STATE { HCLGE_STATE_RST_HANDLING, HCLGE_STATE_MBX_HANDLING, HCLGE_STATE_MBX_IRQ, - HCLGE_STATE_RESET_INT, HCLGE_STATE_MAX };