From patchwork Tue Dec 5 15:46:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120700 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5906614qgn; Tue, 5 Dec 2017 07:47:52 -0800 (PST) X-Google-Smtp-Source: AGs4zMaR1/YEw2HL3vzXm9l2l0gDVS3MKSw4Sq2LmINlRN6RTHBLWA9whkY+gC2VKOsFEpoXmYTQ X-Received: by 10.159.254.6 with SMTP id r6mr19006272pls.144.1512488872151; Tue, 05 Dec 2017 07:47:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512488872; cv=none; d=google.com; s=arc-20160816; b=001fz4Ep9XVvqFOMB9FhOxQ0qlscLxXX3pcSldEYEoJbwimlNV1G2F362oiHZb/VLP M0PM6aHEtcIO3wABOV+Kn9aXxS0cOfD7ZUCCtuyEd9bQov8Jifk1csBDXCZb74V35A/m QMB3z5nhBdc44c+v4I6zUKfZ+RAXt2tEjdmmFwP0C/vPNKpH8VylBGfiFOjjcAXxXPZf a1WtKglH3IbwbuSYIhrGxeSpYCcIGgS2rf2LPjAsbPI+QrvhjSwo7wQHnvztuCGtR+1T dhG3wOCX5xTqxXEGbLsi5Zoyy8MedJYGEyZko4Beg3ihOuC4YB4o/xkTXngbJ4P7oLh3 muuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=M1ZktkenVPhWAklFkRkUr8MNJX7MrhwJ+2Hr5xd1K5s=; b=cBW/phWt83sg7wqxkp0AEWjbfnNTBIf3E60nTDa8k/ZSTPrNnJ/lXSOMuP7p0S0H3x AgBsUjn0a3gqtEFTTna9aqBSDWPfg29fdrR1bKgrp2S6DytY3WORuZqK5VrTCVMi75Kf 9cN7LLimg8UmWiy1MLrzz/S9LEBvydTu8rlVrBBFlfsQA01g+/kyAfbokxT4ZZV7hE5K lumK6QtbY+XLX4x1VnMbppS24TfpRi62lGaPok/8NufeEsOqFxL+mD1qkg0NgOAyQKjB 1rbhKM0/GMTvgV7/mzbAusA4ncgmFXtBpNmZL+D7L0Q1jTxAY6JG6CSPmsLVBpZ05xRU L5Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RK/9XmgW; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o2si235836pll.585.2017.12.05.07.47.51; Tue, 05 Dec 2017 07:47:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RK/9XmgW; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753189AbdLEPru (ORCPT + 10 others); Tue, 5 Dec 2017 10:47:50 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:38764 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752996AbdLEPrI (ORCPT ); Tue, 5 Dec 2017 10:47:08 -0500 Received: by mail-wr0-f193.google.com with SMTP id o2so784838wro.5 for ; Tue, 05 Dec 2017 07:47:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J54cUz8cByVAIC1R7usxpO0FFrUQJouk4nlZHfLBoEQ=; b=RK/9XmgW1YBL2G4ez09+JjMJcsSYCYwn2JOtvTp8vGciEIaI4/KD4KzUE97zEQEzVM 9JtVaHzJqyHr9oEhvW5nTlepB1La3VGP2T1H2/mK3RCJSjD3CbSw8ZT6NF27XYsoMv0y 8c/Mx/1D4Q9EkgM9uiUD9aycBSfsh7WmLtOXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J54cUz8cByVAIC1R7usxpO0FFrUQJouk4nlZHfLBoEQ=; b=UgYJr+5XRUz9hVV8P3vqm7E737HCLa09mtggGMps8lEWq015XLjsnmSxtNybCM7ItS g+41NclHxNqicRdb3+43enN7VRBYCITw68ng2DAvRaEAHKxDayqNbl0BlNKrJlrdBgFK lMo1pPykh7mAHNK0Jr1DIiwX3dPMiLpE5/rVU257E0VhgfgdefX+XANuCdSX7j6UVUSb j50FpDvMWzo/qXb+G8jwUxgHKF2FCxj+h7jQx5rYamqtMNtwJqqYQacGRyRB7zxiZbUX IO2mHUnM6/ZvNlAwVZ5oohDto5LFq+XCZG1eJSPOaYoITD2j62aVwDnlMzaeUz36RY6A tZog== X-Gm-Message-State: AJaThX5M7KGoMWUrqzccUkGIvVVYDnJo5f8j8u+MpFmLSv4Ve5Lickvf cc1NHqYGTt6jRJOVgPFzYcNEaQ== X-Received: by 10.223.150.68 with SMTP id c4mr16359458wra.255.1512488826943; Tue, 05 Dec 2017 07:47:06 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id v47sm500946wrc.13.2017.12.05.07.47.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Dec 2017 07:47:05 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org Cc: mturquette@baylibre.com, robh@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v11 2/6] mailbox: qcom: Create APCS child device for clock controller Date: Tue, 5 Dec 2017 17:46:57 +0200 Message-Id: <20171205154701.27730-3-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171205154701.27730-1-georgi.djakov@linaro.org> References: <20171205154701.27730-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is a clock controller functionality provided by the APCS hardware block of msm8916 devices. The device-tree would represent an APCS node with both mailbox and clock provider properties. Create a platform child device for the clock controller functionality so the driver can probe and use APCS as parent. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index ab344bc6fa63..57bde0dfd12f 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -29,6 +29,7 @@ struct qcom_apcs_ipc { struct regmap *regmap; unsigned long offset; + struct platform_device *clk; }; static const struct regmap_config apcs_regmap_config = { @@ -96,6 +97,14 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) return ret; } + if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) { + apcs->clk = platform_device_register_data(&pdev->dev, + "qcom-apcs-msm8916-clk", + -1, NULL, 0); + if (IS_ERR(apcs->clk)) + dev_err(&pdev->dev, "failed to register APCS clk\n"); + } + platform_set_drvdata(pdev, apcs); return 0; @@ -104,8 +113,10 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) static int qcom_apcs_ipc_remove(struct platform_device *pdev) { struct qcom_apcs_ipc *apcs = platform_get_drvdata(pdev); + struct platform_device *clk = apcs->clk; mbox_controller_unregister(&apcs->mbox); + platform_device_unregister(clk); return 0; } From patchwork Tue Dec 5 15:46:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120697 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5906008qgn; Tue, 5 Dec 2017 07:47:17 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ+sxSi58IOOt3Nwykc8TcyhNGzACTK6MSY1mdTtBmukVxYs25LcwpPLPhS/7BSR2eS5LsX X-Received: by 10.159.246.7 with SMTP id b7mr18118729pls.81.1512488837624; Tue, 05 Dec 2017 07:47:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512488837; cv=none; d=google.com; s=arc-20160816; b=GzwTRFoUel2/nHCgBdA/31GNXnrlbHE/KFCRhxVVACot/27BAly5WaCoLjTLgMCDFW 1rbBnABgOlLwLY/i1jq2vkYDSaahrLOT+ODdXwSn/KtJtOpCxAnCWeS19JcO+eDfDptt kaxTlRUWXbVtqECaHaoutn80yGnewj3DX3A4VXH+ppwSAPPevkWhHix5jGCS5KK6I2/Y peHVjDpYDFssKjzkM0r6PAUkp0un8FiHzqyDOFbgXvSnnQwOcJkdGSuT0/2e7AAJwlEG 1Fo7sMS2mz3oY9tzwDZuVtazT8CRgQC8sJx5nU6FI3IF7TMYbL5PnLMFKjkGhFvwLfuX gqbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lZKWFcv8Ah/nvCcZNe5Xgnr0L8SB44b62DaUCit33rA=; b=Zx5Eg0v834yYutLpCrpUAm2ZP1yGcKxM9+4I2h4B0ukLhIfcw2H7Up764xx4c4lxWe q0tCQARagBFwSokUG8wHMYZlVa0y5Stwa0S9xFx1xgbrghLSScROfOiLpqyqcC8cyecH 9ZjnCG7egYa0TlBWlPr7EUkfQhHD4wc6IvfeOI5513D/Ikfs+jFGzbGvowDRKogGAdqk IDH4G8eeE0JOgXgM+KA83iFnOY5SnCEXm39RTTViN/5dkbya+xy59UNSO4T0LpoHD3i0 fPdPvUbx5JrD1I+QdD4qvPaaV3iCXlTRhajM4HNm5YbsQmFaeXAvRJtGT47PNNl7JsGy KhIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Obpm+9Bw; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j23si238495pll.748.2017.12.05.07.47.17; Tue, 05 Dec 2017 07:47:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Obpm+9Bw; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752977AbdLEPrP (ORCPT + 10 others); Tue, 5 Dec 2017 10:47:15 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:40707 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753050AbdLEPrJ (ORCPT ); Tue, 5 Dec 2017 10:47:09 -0500 Received: by mail-wm0-f65.google.com with SMTP id f206so2067140wmf.5 for ; Tue, 05 Dec 2017 07:47:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SAMVO+dOf8LdSV5eqwOijQZV7TffAdH+tZur48Tw+Q8=; b=Obpm+9BwPYa/Pm/2I9KF+eovPG9Aw4ZuXcJKrJ6CXBKT/8iIDLbBWaZHWVc7aFB4gs 1w28iZKg+fjd3A0lONbjIVP4fBZGtH8HIY9T9mBuyk0HOFURlBJ6yEer1Nj6d8As0v/K xKjLRonP5GhGgmqIvrZxSkq+KVARZVRJ6lk34= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SAMVO+dOf8LdSV5eqwOijQZV7TffAdH+tZur48Tw+Q8=; b=GGzcYdeZ6H2L7btqJRzfxskoifxd+hs3FIsR6g+6Wf0SoEK6iLC5ex+WSg9+bJwF/t IYtmflyHkuuaxUH73RvO3qzHdhgQ5PDrZngbPe/X7LEMENl3QwTZeT+BfsrdGAqVgkOb 0iROb9srXEQ9Y4erGQ0zSsul6y43wCRhX0nC1iE27VZE82QownRkAeCwEA6IBYz3+MOu SEyeQMKKiBJzBLzS4JON4H76lvO4zhzV3TYSRQj/nR2SY+PAOWUWVND9lLg+FN1P7Xw7 XADp4HAHDs5Rw1CC8KN2XvztqN1t6wk6G3g7iGNKktaf7GT5bB3HSmUjsL0yxTF4kR6V EWWg== X-Gm-Message-State: AKGB3mJwT3XVK91xZa9bIvC/dEZqPFkw7uycZ8mdcHNsZXyEUwSNPzP5 D8drsE+FcH2BJiqp0yd464/Edw== X-Received: by 10.28.232.220 with SMTP id f89mr8563076wmi.57.1512488828320; Tue, 05 Dec 2017 07:47:08 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id v47sm500946wrc.13.2017.12.05.07.47.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Dec 2017 07:47:07 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org Cc: mturquette@baylibre.com, robh@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v11 3/6] clk: qcom: Add A53 PLL support Date: Tue, 5 Dec 2017 17:46:58 +0200 Message-Id: <20171205154701.27730-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171205154701.27730-1-georgi.djakov@linaro.org> References: <20171205154701.27730-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs, a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources are connected to a mux and half-integer divider, which is feeding the CPU cores. This patch adds support for the primary CPU PLL which generates the higher range of frequencies above 1GHz. Signed-off-by: Georgi Djakov Acked-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++ drivers/clk/qcom/Kconfig | 10 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 110 +++++++++++++++++++++ 4 files changed, 143 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..e3fa8118eaee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,22 @@ +Qualcomm MSM8916 A53 PLL Binding +-------------------------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,msm8916-a53pll" + +- reg : shall contain base register location and length + +- #clock-cells : must be set to <0> + +Example: + + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; + diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9f6c278deead..81ac7b9378fe 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -12,6 +12,16 @@ config COMMON_CLK_QCOM select REGMAP_MMIO select RESET_CONTROLLER +config QCOM_A53PLL + bool "MSM8916 A53 PLL" + depends on COMMON_CLK_QCOM + default ARCH_QCOM + help + Support for the A53 PLL on MSM8916 devices. It provides + the CPU with frequencies above 1GHz. + Say Y if you want to support higher CPU frequencies on MSM8916 + devices. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 26410d31446b..e767c60c24ec 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..c18cb7614e42 --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm A53 PLL driver + * + * Copyright (c) 2017, Linaro Limited + * Author: Georgi Djakov + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, + { 1248000000, 65, 0x0, 0x1, 0 }, + { 1363200000, 71, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, +}; + +static int qcom_a53pll_remove(struct platform_device *pdev) +{ + of_clk_del_provider(pdev->dev.of_node); + return 0; +} + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct clk_pll *pll; + void __iomem *base; + struct clk_init_data init = { }; + int ret; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + ret = devm_clk_register_regmap(dev, &pll->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + &pll->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,msm8916-a53pll" }, + { } +}; + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .remove = qcom_a53pll_remove, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver); From patchwork Tue Dec 5 15:47:00 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id o2si235836pll.585.2017.12.05.07.47.48; Tue, 05 Dec 2017 07:47:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QQvbrzLN; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753082AbdLEPrq (ORCPT + 10 others); Tue, 5 Dec 2017 10:47:46 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:37826 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753015AbdLEPrN (ORCPT ); Tue, 5 Dec 2017 10:47:13 -0500 Received: by mail-wm0-f66.google.com with SMTP id f140so2093664wmd.2 for ; Tue, 05 Dec 2017 07:47:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=enFYRy2WVA6WKyNMd65JxPCGNUhh/eiRtU+6DrOvK1w=; b=QQvbrzLNPWrbGpMrD5LG1YV5Q1lXCTrXrlcIUfo8nH15ArGtzg3GI7r8voKCIgmjIG o4WLzXXV3IteOzH97U6fjCY3gK8YAbs9D2RNwttZppyTBU7bDP57dOeUkVhdrf6rONYT 61qUS+rhBIxZmn9F9yaOHJK/KLrFq7TxFyAx0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=enFYRy2WVA6WKyNMd65JxPCGNUhh/eiRtU+6DrOvK1w=; b=nTJCY/SCtaOTLm4qJgLxsWmDnQIh49XF0H7fEaeu6ElYBJw0Cr+Pf9iJjeVoubg6lD IUC+GT9T4PyMKGfVYu33xhlPyzCcNbZM90R6tHj8uU38ythnX/YEiJ9JyBomT1IihrmH sWzuLi1ZlVjJuuUxQvTjxacQ2D37dgyWPdK3wM9nQZnzNWd8731o6RgCBINc0zHC6thP i0e70I/c0FLrDA4pKk/D9rVBOsUA2eveiiAhSg4JgPkJnLi0Ckq92YeNY7TkrdlBfTY1 4S5PRlZB04UQJeNjGbhzCQjkVi/SBg43mUzi0gVXR8SKLbpXibsxYY1MoQZfL3XON2kx y5sQ== X-Gm-Message-State: AKGB3mJWl6iQINt7KrQaE1M6S56uBHpOrR/hDvrE5MH0KtwgBvAIkV19 Z86u4boxRq90vUfXj9JAIGQNgA== X-Received: by 10.28.151.7 with SMTP id z7mr6452333wmd.5.1512488831205; Tue, 05 Dec 2017 07:47:11 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id v47sm500946wrc.13.2017.12.05.07.47.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Dec 2017 07:47:10 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org Cc: mturquette@baylibre.com, robh@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v11 5/6] dt-bindings: mailbox: qcom: Document the APCS clock binding Date: Tue, 5 Dec 2017 17:47:00 +0200 Message-Id: <20171205154701.27730-6-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171205154701.27730-1-georgi.djakov@linaro.org> References: <20171205154701.27730-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Update the binding documentation for APCS to mention that the APCS hardware block also expose a clock controller functionality. The APCS clock controller is a mux and half-integer divider. It has the main CPU PLL as an input and provides the clock for the application CPU. Signed-off-by: Georgi Djakov Reviewed-by: Rob Herring Acked-by: Bjorn Andersson --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index fb961c310f44..16964f0c1773 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -15,12 +15,21 @@ platforms. Usage: required Value type: Definition: must specify the base address and size of the global block +- clocks: + Usage: required if #clocks-cells property is present + Value type: + Definition: phandle to the input PLL, which feeds the APCS mux/divider - #mbox-cells: Usage: required Value type: Definition: as described in mailbox.txt, must be 1 +- #clock-cells: + Usage: optional + Value type: + Definition: as described in clock.txt, must be 0 + = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -44,3 +53,12 @@ GLINK RPM referencing the "rpm_hlos" doorbell therein. mbox-names = "rpm_hlos"; }; +Below is another example of the APCS binding on MSM8916 platforms: + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll>; + #clock-cells = <0>; + }; From patchwork Tue Dec 5 15:47:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120698 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5906508qgn; Tue, 5 Dec 2017 07:47:46 -0800 (PST) X-Google-Smtp-Source: AGs4zMZuhia6A+JPOWJyFtpoiFY6oJW2h6zpqthRRNIY+hwqud3d7QIH4xeNkDE7yXExgHVvyisK X-Received: by 10.84.196.131 with SMTP id l3mr18556664pld.194.1512488866054; Tue, 05 Dec 2017 07:47:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512488866; cv=none; d=google.com; s=arc-20160816; b=0C6abka4hWeRg1bmR3hpwfAwMboKEhCRc/GQxZR5YZwoePhFO5xrbbgld9gj3cAH4p Ot7iiAYM+sjewbmh9tlKDTd3clnM2ZfkZuRAoZtsKetFRN8MF23V7rvGMEatPaaZO5V6 mkabWYAaqSl87wVktbSMC4LXcy3BXnTcmJCS5Qlk1uqm2+CH4IwSR2iRFVkDz72/Ht9H OHaszfAb+578OM12hBQCKcj/gdVbXrApMkL5Igry9ikF+pwG+W8myOD8+OeIyMoVLhiF Du+QiaIAZhLL/gn5eW6ohwKBy6FjDCHaRx4oXcIJfEuGwRFTtjr5kjql2nJ2bDRq1WI7 eaIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=sLiHYlrdmOvPNh5ad8pAQT+f1eJO0MEZXul9iptpvtU=; b=DnWzEGJgvAJO7gmaMuXvnHgE2UnnIAxBxCd57d2KzT50zV6+L0x2oWwUZUuu1YgA7u L93FR/B3yXYlCkJh/Ac9wLMImo8bvsNrnxy+xFxzPvpPsnmyFpy+a1+mXw9YWUUjZnIN 9Xvet6NUoSgqH8ZkF7h+C22tpa1IcG7Ydj4qbq5nIRK7LiiTO87TYxTu66mAlnG5FTVJ 7t484fQR7vOwIQmdEQHGA79RcyugT3yvXsrFWw1bmvwnKpo8/0qXOeWQZLIwuoKFTmiD Kd3baHDbqqdrIb7LgbV4MuHUUyNN5LmdRJM+C4RdO1yppWPXdoNu66BGBq3fjq3TjY0G cVdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ej075zrk; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-msm8916.c | 149 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/clk/qcom/apcs-msm8916.c -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 81ac7b9378fe..255023b439c9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -22,6 +22,17 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_CLK_APCS_MSM8916 + bool "MSM8916 APCS Clock Controller" + depends on COMMON_CLK_QCOM + depends on QCOM_APCS_IPC + default ARCH_QCOM + help + Support for the APCS Clock Controller on msm8916 devices. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as msm8916. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 7c51d877f967..0408cebf38d4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -34,5 +34,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c new file mode 100644 index 000000000000..832172c2fc8b --- /dev/null +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm APCS clock controller driver + * + * Copyright (c) 2017, Linaro Limited + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A53 PLL is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = __mux_div_set_src_div(md, 4, 3); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + struct clk_regmap_mux_div *a53cc; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret; + + regmap = dev_get_regmap(parent, NULL); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + init.name = "a53mux"; + init.parent_names = gpll0_a53cc; + init.num_parents = ARRAY_SIZE(gpll0_a53cc); + init.ops = &clk_regmap_mux_div_ops; + init.flags = CLK_SET_RATE_PARENT; + + a53cc->clkr.hw.init = &init; + a53cc->clkr.regmap = regmap; + a53cc->reg_offset = 0x50; + a53cc->hid_width = 5; + a53cc->hid_shift = 0; + a53cc->src_width = 3; + a53cc->src_shift = 8; + a53cc->parent_map = gpll0_a53cc_map; + + a53cc->pclk = devm_clk_get(parent, NULL); + if (IS_ERR(a53cc->pclk)) { + ret = PTR_ERR(a53cc->pclk); + dev_err(dev, "failed to get clk: %d\n", ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a53cc); + + return 0; + +err: + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + return ret; +} + +static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) +{ + struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); + struct device *parent = pdev->dev.parent; + + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + of_clk_del_provider(parent->of_node); + + return 0; +} + +static struct platform_driver qcom_apcs_msm8916_clk_driver = { + .probe = qcom_apcs_msm8916_clk_probe, + .remove = qcom_apcs_msm8916_clk_remove, + .driver = { + .name = "qcom-apcs-msm8916-clk", + }, +}; +module_platform_driver(qcom_apcs_msm8916_clk_driver); + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");