From patchwork Tue Dec 5 19:46:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120742 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168175qgn; Tue, 5 Dec 2017 11:46:39 -0800 (PST) X-Google-Smtp-Source: AGs4zMYZrRqWRXqZTyJY6WT6vs8o70klDzthYJZq/QRiTcgguvqdxzBsf/0yoyxjv8nlMafC38S7 X-Received: by 10.101.93.8 with SMTP id e8mr18631644pgr.214.1512503199143; Tue, 05 Dec 2017 11:46:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503199; cv=none; d=google.com; s=arc-20160816; b=acbsiaqbonSHdFBBTSgG2ZZ5qi7+im2PV8lMc5L/tzCtJFV4To5iCe9AYcslMvZs1B i6M7VZEHwsIzfIO06ULV80nfcsGO6Ojf+ypIxag0OS/QqNSh4EInnEEwWup31Sd5j5/+ v86q6Rwm91Y/39Wpo5dG4L8p9B4gMjV0hYSt8qbFTvShXgyMxl4Ib/P73MuavgZiH7TG 0QAntK9vsJQcIVVmkvkYrkiWZ5sNwUPQ+qulXQrIhf1TAn8EhpA7sWJH9FREqXLv4kHl av9EzPJVO5oFOMkMcNBZx0CokQfBbsrtjbqaESTgnRdeHWNM9lpj9sMu6Wl0XuMAoJyw NFGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=sWCNMmZlk7oJBJqZF3oGZiW7WZkh+NCdzBVJiEpZRok=; b=nK21nmEVEoBCBmv33kS6Hft3rJd8Fr6+yGdeTewMZJSiOynp1/rZRMBQoxOi6d/IhT 3Y1gINnUGM+ILcbn96sUcRme4NnrKzpZoJlgop+7lcSRgd609REf9Ys3VGUKb5k0srFw Q+MPDqb9VCDWDvS79A3CRtiJL6DKPi6HsY3ajyDBbvCIlLMWLsLQ1flbjfQM0m7fFIeW ogpcTw3PVYdbo9/+JOgADTX0xVNnnb+tWdn9Bkow5rRNbJjwyZKsnSYOIsRmYAQ2+Bk/ E5J7uhWyS/FN4Fy/MD2w9/wy+i814+hIUeHzSSqcQlp6XA3EJjHb5/y474fJmc5S8kg/ MavA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id f7si539315pgc.324.2017.12.05.11.46.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAo-00058p-Dp; Tue, 05 Dec 2017 19:46:34 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 01/12] target/arm: Provide fault type enum and FSR conversion functions Date: Tue, 5 Dec 2017 19:46:21 +0000 Message-Id: <1512503192-2239-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Currently get_phys_addr() and its various subfunctions return a hard-coded fault status register value for translation failures. This is awkward because FSR values these days may be either long-descriptor format or short-descriptor format. Worse, the right FSR type to use doesn't depend only on the translation table being walked -- some cases, like fault info reported to AArch32 EL2 for some kinds of ATS operation, must be in long-descriptor format even if the translation table being walked was short format. We can't get those cases right with our current approach. Provide fields in the ARMMMUFaultInfo struct which allow get_phys_addr() to provide sufficient information for a caller to construct an FSR value themselves, and utility functions which do this for both long and short format FSR values, as a first step in switching get_phys_addr() and its children to only returning the failure cause in the ARMMMUFaultInfo struct. Signed-off-by: Peter Maydell --- target/arm/internals.h | 185 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) -- 2.7.4 diff --git a/target/arm/internals.h b/target/arm/internals.h index aa9c91b..67b9a52 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -488,7 +488,39 @@ static inline void arm_clear_exclusive(CPUARMState *env) } /** + * ARMFaultType: type of an ARM MMU fault + * This corresponds to the v8A pseudocode's Fault enumeration, + * with extensions for QEMU internal conditions. + */ +typedef enum ARMFaultType { + ARMFault_None, + ARMFault_AccessFlag, + ARMFault_Alignment, + ARMFault_Background, + ARMFault_Domain, + ARMFault_Permission, + ARMFault_Translation, + ARMFault_AddressSize, + ARMFault_SyncExternal, + ARMFault_SyncExternalOnWalk, + ARMFault_SyncParity, + ARMFault_SyncParityOnWalk, + ARMFault_AsyncParity, + ARMFault_AsyncExternal, + ARMFault_Debug, + ARMFault_TLBConflict, + ARMFault_Lockdown, + ARMFault_Exclusive, + ARMFault_ICacheMaint, + ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ + ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ +} ARMFaultType; + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault + * @type: Type of fault + * @level: Table walk level (for translation, access flag and permission faults) + * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk @@ -496,12 +528,165 @@ static inline void arm_clear_exclusive(CPUARMState *env) */ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { + ARMFaultType type; target_ulong s2addr; + int level; + int domain; bool stage2; bool s1ptw; bool ea; }; +/** + * arm_fi_to_sfsc: Convert fault info struct to short-format FSC + * Compare pseudocode EncodeSDFSC(), though unlike that function + * we set up a whole FSR-format code including domain field and + * putting the high bit of the FSC into bit 10. + */ +static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi) +{ + uint32_t fsc; + + switch (fi->type) { + case ARMFault_None: + return 0; + case ARMFault_AccessFlag: + fsc = fi->level == 1 ? 0x3 : 0x6; + break; + case ARMFault_Alignment: + fsc = 0x1; + break; + case ARMFault_Permission: + fsc = fi->level == 1 ? 0xd : 0xf; + break; + case ARMFault_Domain: + fsc = fi->level == 1 ? 0x9 : 0xb; + break; + case ARMFault_Translation: + fsc = fi->level == 1 ? 0x5 : 0x7; + break; + case ARMFault_SyncExternal: + fsc = 0x8 | (fi->ea << 12); + break; + case ARMFault_SyncExternalOnWalk: + fsc = fi->level == 1 ? 0xc : 0xe; + fsc |= (fi->ea << 12); + break; + case ARMFault_SyncParity: + fsc = 0x409; + break; + case ARMFault_SyncParityOnWalk: + fsc = fi->level == 1 ? 0x40c : 0x40e; + break; + case ARMFault_AsyncParity: + fsc = 0x408; + break; + case ARMFault_AsyncExternal: + fsc = 0x406 | (fi->ea << 12); + break; + case ARMFault_Debug: + fsc = 0x2; + break; + case ARMFault_TLBConflict: + fsc = 0x400; + break; + case ARMFault_Lockdown: + fsc = 0x404; + break; + case ARMFault_Exclusive: + fsc = 0x405; + break; + case ARMFault_ICacheMaint: + fsc = 0x4; + break; + case ARMFault_Background: + fsc = 0x0; + break; + case ARMFault_QEMU_NSCExec: + fsc = M_FAKE_FSR_NSC_EXEC; + break; + case ARMFault_QEMU_SFault: + fsc = M_FAKE_FSR_SFAULT; + break; + default: + /* Other faults can't occur in a context that requires a + * short-format status code. + */ + g_assert_not_reached(); + } + + fsc |= (fi->domain << 4); + return fsc; +} + +/** + * arm_fi_to_lfsc: Convert fault info struct to long-format FSC + * Compare pseudocode EncodeLDFSC(), though unlike that function + * we fill in also the LPAE bit 9 of a DFSR format. + */ +static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) +{ + uint32_t fsc; + + switch (fi->type) { + case ARMFault_None: + return 0; + case ARMFault_AddressSize: + fsc = fi->level & 3; + break; + case ARMFault_AccessFlag: + fsc = (fi->level & 3) | (0x2 << 2); + break; + case ARMFault_Permission: + fsc = (fi->level & 3) | (0x3 << 2); + break; + case ARMFault_Translation: + fsc = (fi->level & 3) | (0x1 << 2); + break; + case ARMFault_SyncExternal: + fsc = 0x10 | (fi->ea << 12); + break; + case ARMFault_SyncExternalOnWalk: + fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12); + break; + case ARMFault_SyncParity: + fsc = 0x18; + break; + case ARMFault_SyncParityOnWalk: + fsc = (fi->level & 3) | (0x7 << 2); + break; + case ARMFault_AsyncParity: + fsc = 0x19; + break; + case ARMFault_AsyncExternal: + fsc = 0x11 | (fi->ea << 12); + break; + case ARMFault_Alignment: + fsc = 0x21; + break; + case ARMFault_Debug: + fsc = 0x22; + break; + case ARMFault_TLBConflict: + fsc = 0x30; + break; + case ARMFault_Lockdown: + fsc = 0x34; + break; + case ARMFault_Exclusive: + fsc = 0x35; + break; + default: + /* Other faults can't occur in a context that requires a + * long-format status code. + */ + g_assert_not_reached(); + } + + fsc |= 1 << 9; + return fsc; +} + /* Do a page table walk and add page to TLB if possible */ bool arm_tlb_fill(CPUState *cpu, vaddr address, MMUAccessType access_type, int mmu_idx, From patchwork Tue Dec 5 19:46:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120737 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168129qgn; Tue, 5 Dec 2017 11:46:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ83c7XVPFF2uilJO+u5tu8PpFmEIrPqeb9fyUGyVkBcTlBBa09eJx3Wt/7Yp7FXB7MHkZ8 X-Received: by 10.46.1.231 with SMTP id f100mr10587183lji.132.1512503196518; Tue, 05 Dec 2017 11:46:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503196; cv=none; d=google.com; s=arc-20160816; b=pSHW94KZbDrpMok2N6CtRlN+n4MWWtsyp1lkMbeSh6eXs5PMpRr6GKjYUk95DAvtHR JDkR84xtKKksn8scmg/nNgZHLVvevGv1p2XuvpoSPXEymagetwRxDhh/k0YPuGoECh5I 7eMB5XYcEvvYReODWUSjp1b1U881a5I/FpZURYkuXv3rG6F0sZTxxOyM5Sa6jVR0fUPW 6EHocmL/OceAb8Dp/BRFp0oJzUr16KtmPVd4D7Mgx5HFi/sVIHOa8lbx0CHeV0Z0BpaI m+29TE0pivx4NeBwBfYP4znjOSxmFQG5D+QSun9t34qHPm0j9jh+wzQB7BVvgGzlnx4D cEIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=s1wmZesBd4JYiEqRo7OWALVgsaLL3wuGTfX2B+sLcp0=; b=b3Jh/GToBavF9XbltAM5ueS9KYIqmAi/0ZL/2ong1SNACMBP49xTYFkd+nN8P9cYj2 jMaSEZwF7AxyVA2SQygwWZASGi3H6qrqaKaLbXWNPd07YQCsSfSsf5jD7o+ubfjYF0au TXlLk3q/XVZRySU5NpSaxScCN6nVUyQefJX/gSp80580sneWMpx9mSRB9erLx7NV0Jqq vJEJAx++/pK1iyp1awEu9SfatHrDZ/uKTVu9WwOx6WIreDtNoYxZBzKvdsEcWJ8aUQWm TzEOY6bjuWjokA/1RAfDhX3ytYJT00R1PH9d5yKkW6hwpkM/5vK1JA6FE850V8s/DEU3 gyHQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g1si376007ljb.354.2017.12.05.11.46.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAp-000597-1N; Tue, 05 Dec 2017 19:46:35 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 02/12] target/arm: Remove fsr argument from arm_ld*_ptw() Date: Tue, 5 Dec 2017 19:46:22 +0000 Message-Id: <1512503192-2239-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> All the callers of arm_ldq_ptw() and arm_ldl_ptw() ignore the value that those functions store in the fsr argument on failure: if they return failure to their callers they will always overwrite the fsr value with something else. Remove the argument from these functions and S1_ptw_translate(). This will simplify removing fsr from the calling functions. Signed-off-by: Peter Maydell --- target/arm/helper.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 5368ad8..30616d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8269,7 +8269,6 @@ static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, - uint32_t *fsr, ARMMMUFaultInfo *fi) { if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && @@ -8278,9 +8277,10 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; + uint32_t fsr; ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, fsr, fi, NULL); + &txattrs, &s2prot, &s2size, &fsr, fi, NULL); if (ret) { fi->s2addr = addr; fi->stage2 = true; @@ -8300,8 +8300,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, * (but not if it was for a debug access). */ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -8310,7 +8309,7 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, attrs.secure = is_secure; as = arm_addressspace(cs, attrs); - addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); + addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } @@ -8322,8 +8321,7 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, } static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, uint32_t *fsr, - ARMMMUFaultInfo *fi) + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; @@ -8332,7 +8330,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, attrs.secure = is_secure; as = arm_addressspace(cs, attrs); - addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); + addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fi); if (fi->s1ptw) { return 0; } @@ -8368,7 +8366,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, goto do_fault; } desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fsr, fi); + mmu_idx, fi); type = (desc & 3); domain = (desc >> 5) & 0x0f; if (regime_el(env, mmu_idx) == 1) { @@ -8405,7 +8403,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); } desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fsr, fi); + mmu_idx, fi); switch (desc & 3) { case 0: /* Page translation fault. */ code = 7; @@ -8487,7 +8485,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, goto do_fault; } desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fsr, fi); + mmu_idx, fi); type = (desc & 3); if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) { /* Section translation fault, or attempt to use the encoding @@ -8539,7 +8537,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, /* Lookup l2 entry. */ table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fsr, fi); + mmu_idx, fi); ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); switch (desc & 3) { case 0: /* Page translation fault. */ @@ -8950,7 +8948,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr |= (address >> (stride * (4 - level))) & indexmask; descaddr &= ~7ULL; nstable = extract32(tableattrs, 4, 1); - descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi); + descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); if (fi->s1ptw) { goto do_fault; } From patchwork Tue Dec 5 19:46:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120736 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168126qgn; Tue, 5 Dec 2017 11:46:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMYKEMZT6CbGsriCEE4PoR/C9bVNosd8F8jXn/klbb9Kd3o3Zi4aGu62yI9JDV4dXCdHugoS X-Received: by 10.28.130.208 with SMTP id e199mr10734725wmd.75.1512503196381; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r4si70441wrc.78.2017.12.05.11.46.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAp-00059Q-Lv; Tue, 05 Dec 2017 19:46:35 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 03/12] target/arm: Convert get_phys_addr_v5() to not return FSC values Date: Tue, 5 Dec 2017 19:46:23 +0000 Message-Id: <1512503192-2239-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_v5() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 30616d9..6aed681 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8344,11 +8344,11 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, - target_ulong *page_size, uint32_t *fsr, + target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs = CPU(arm_env_get_cpu(env)); - int code; + int level = 1; uint32_t table; uint32_t desc; int type; @@ -8362,7 +8362,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Lookup l1 descriptor. */ if (!get_level1_table_address(env, mmu_idx, &table, address)) { /* Section translation fault if page walk is disabled by PD0 or PD1 */ - code = 5; + fi->type = ARMFault_Translation; goto do_fault; } desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), @@ -8377,21 +8377,20 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, domain_prot = (dacr >> (domain * 2)) & 3; if (type == 0) { /* Section translation fault. */ - code = 5; + fi->type = ARMFault_Translation; goto do_fault; } + if (type != 2) { + level = 2; + } if (domain_prot == 0 || domain_prot == 2) { - if (type == 2) - code = 9; /* Section domain fault. */ - else - code = 11; /* Page domain fault. */ + fi->type = ARMFault_Domain; goto do_fault; } if (type == 2) { /* 1Mb section. */ phys_addr = (desc & 0xfff00000) | (address & 0x000fffff); ap = (desc >> 10) & 3; - code = 13; *page_size = 1024 * 1024; } else { /* Lookup l2 entry. */ @@ -8406,7 +8405,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, mmu_idx, fi); switch (desc & 3) { case 0: /* Page translation fault. */ - code = 7; + fi->type = ARMFault_Translation; goto do_fault; case 1: /* 64k page. */ phys_addr = (desc & 0xffff0000) | (address & 0xffff); @@ -8429,7 +8428,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* UNPREDICTABLE in ARMv5; we choose to take a * page translation fault. */ - code = 7; + fi->type = ARMFault_Translation; goto do_fault; } } else { @@ -8442,18 +8441,19 @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, /* Never happens, but compiler isn't smart enough to tell. */ abort(); } - code = 15; } *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot); *prot |= *prot ? PAGE_EXEC : 0; if (!(*prot & (1 << access_type))) { /* Access permission fault. */ + fi->type = ARMFault_Permission; goto do_fault; } *phys_ptr = phys_addr; return false; do_fault: - *fsr = code | (domain << 4); + fi->domain = domain; + fi->level = level; return true; } @@ -9863,8 +9863,11 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi); } else { - return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, - prot, page_size, fsr, fi); + bool ret = get_phys_addr_v5(env, address, access_type, mmu_idx, + phys_ptr, prot, page_size, fi); + + *fsr = arm_fi_to_sfsc(fi); + return ret; } } From patchwork Tue Dec 5 19:46:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120738 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168137qgn; Tue, 5 Dec 2017 11:46:36 -0800 (PST) X-Google-Smtp-Source: AGs4zMa9LZY7i5J04dvJIBxTGfTAEw3fJwzOTl6KCuDIou00ZxQHjgeSFhc+oHuEm2aL88Ne9vi5 X-Received: by 10.28.144.10 with SMTP id s10mr9942433wmd.103.1512503196897; Tue, 05 Dec 2017 11:46:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503196; cv=none; d=google.com; s=arc-20160816; b=CbaFr//vsg5RzhiY+jcq/sSIanedd/ZEl8JoYfLpOL9YZBSTRreOYGK3u0G55jzv+f BIHLGFSS4xNBPDCQrVgWqsYBdjh8UlHsCGlBimMZFicoPVesj+v/Vz6KDRG1PMjCPFXb FXdYTHyG5HRLHisjQhL4irj26MUUk/ICie+UIDOh8rS6lmLjU+1NHXEVgrJwdgzdpgqL DE9/MfhNvnQ9HNcklVTLC1nZZ/cTZBNSTZR8qSF7iXa5BL4yU0otFi1AfFgl3MqoCz0r /6zpp6qOzJO7cQJRxrp3Wn4bSheqd02PbpT7JXSncERZezIAr2K8iCzi1tUSOMPqOJ1s /EpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=STN5vTcg/SboN05Lx7HnUig3E1TU3wJDcdGs575ZO5Y=; b=Ne62p3L3vUbUiFPI5zM6e6jI0Oi14vNKrSOhkKeva20Rk1GRhaNgWaKKVog+4NmL5d GC/VkzkGFv68CTy1sAHXWWlU/gc5rW/mzoPr3wCu80nY12p9uzmwL3pexW1NrODuUEjB 9UInx3bR+3I1iZOGnZVVtXBRn1Ezc6m4DQW118G6VzCB0xBcNQMAQCb5YD5BMuUw4jnE ypVLxczhUiI5h+HXIHCAt+mHj1RJpSSrqh5UGXu/ssSUc6yZFceGZEjgbQG35KzcvC1S NCcoMAk3reqPU7FEzIoDXDHHh20qR2z/YST2muPi/SBCx/CG1PoxX4Wf3yo4IIZOC5KU tjwQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id e191si744748wme.68.2017.12.05.11.46.36 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAq-00059h-9b; Tue, 05 Dec 2017 19:46:36 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 04/12] target/arm: Convert get_phys_addr_v6() to not return FSC values Date: Tue, 5 Dec 2017 19:46:24 +0000 Message-Id: <1512503192-2239-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 6aed681..1e95e3d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8460,11 +8460,10 @@ do_fault: static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, - ARMMMUFaultInfo *fi) + target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs = CPU(arm_env_get_cpu(env)); - int code; + int level = 1; uint32_t table; uint32_t desc; uint32_t xn; @@ -8481,7 +8480,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, /* Lookup l1 descriptor. */ if (!get_level1_table_address(env, mmu_idx, &table, address)) { /* Section translation fault if page walk is disabled by PD0 or PD1 */ - code = 5; + fi->type = ARMFault_Translation; goto do_fault; } desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), @@ -8491,7 +8490,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, /* Section translation fault, or attempt to use the encoding * which is Reserved on implementations without PXN. */ - code = 5; + fi->type = ARMFault_Translation; goto do_fault; } if ((type == 1) || !(desc & (1 << 18))) { @@ -8503,13 +8502,13 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, } else { dacr = env->cp15.dacr_s; } + if (type == 1) { + level = 2; + } domain_prot = (dacr >> (domain * 2)) & 3; if (domain_prot == 0 || domain_prot == 2) { - if (type != 1) { - code = 9; /* Section domain fault. */ - } else { - code = 11; /* Page domain fault. */ - } + /* Section or Page domain fault */ + fi->type = ARMFault_Domain; goto do_fault; } if (type != 1) { @@ -8527,7 +8526,6 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ap = ((desc >> 10) & 3) | ((desc >> 13) & 4); xn = desc & (1 << 4); pxn = desc & 1; - code = 13; ns = extract32(desc, 19, 1); } else { if (arm_feature(env, ARM_FEATURE_PXN)) { @@ -8541,7 +8539,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, ap = ((desc >> 4) & 3) | ((desc >> 7) & 4); switch (desc & 3) { case 0: /* Page translation fault. */ - code = 7; + fi->type = ARMFault_Translation; goto do_fault; case 1: /* 64k page. */ phys_addr = (desc & 0xffff0000) | (address & 0xffff); @@ -8557,7 +8555,6 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, /* Never happens, but compiler isn't smart enough to tell. */ abort(); } - code = 15; } if (domain_prot == 3) { *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -8565,15 +8562,17 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, if (pxn && !regime_is_user(env, mmu_idx)) { xn = 1; } - if (xn && access_type == MMU_INST_FETCH) + if (xn && access_type == MMU_INST_FETCH) { + fi->type = ARMFault_Permission; goto do_fault; + } if (arm_feature(env, ARM_FEATURE_V6K) && (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { /* The simplified model uses AP[0] as an access control bit. */ if ((ap & 1) == 0) { /* Access flag fault. */ - code = (code == 15) ? 6 : 3; + fi->type = ARMFault_AccessFlag; goto do_fault; } *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); @@ -8585,6 +8584,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, } if (!(*prot & (1 << access_type))) { /* Access permission fault. */ + fi->type = ARMFault_Permission; goto do_fault; } } @@ -8598,7 +8598,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, *phys_ptr = phys_addr; return false; do_fault: - *fsr = code | (domain << 4); + fi->domain = domain; + fi->level = level; return true; } @@ -9860,8 +9861,11 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fsr, fi, cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, - attrs, prot, page_size, fsr, fi); + bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); + + *fsr = arm_fi_to_sfsc(fi); + return ret; } else { bool ret = get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, prot, page_size, fi); From patchwork Tue Dec 5 19:46:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120739 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168146qgn; Tue, 5 Dec 2017 11:46:37 -0800 (PST) X-Google-Smtp-Source: AGs4zMZvzbQJK/Qceh6ENz1t0ZPaFe+aAdobt5ZHqHAnZaHfRkqF5EfRmDFeYtroMekQ4G4RFGYE X-Received: by 10.223.161.210 with SMTP id v18mr15924717wrv.170.1512503197522; Tue, 05 Dec 2017 11:46:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503197; cv=none; d=google.com; s=arc-20160816; b=SF/Ynlg95KLJnLCBaz6GsaEsiGPzefoUrcla528fbvchH0PqUdyiVlvR4+5R6HHWiD vFIXIATW3pxH+qNaeRahf5M+J9f8VSjblkGlPFQb6fIuGMUtkCT2xgeDn2HOwJutPjq5 iDgnrHvt3ySbUMLTSzrfUC/KEmNix8sLyxavLPTqPFRjVlwqicOkzPCkLIoP04XUEALk Com9DAMPiEDRTNmXod/1D2ZKOeMV5+5TfZPmmabV2hA7ryp1NuSXfx8FliYtU9L2BKcP v3s/UDESCZ8136KddCTv3j8dmf2Ed8n9Yr2cLkHwreDm7HATOo0/HIS9l2pU4JbGXzE3 zU2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=RSqqLoMHm8ToV87W23DTughwrSw0FE0JmhihawNa4NU=; b=UseSK77FL9vDShsqCfghbQFue6o8jautvQisrA1GTwnqkAAbzZB1armX41/SAAZHU8 yYNKHdr0LAtO0w1oyRJ5exx67J0uSzRdwt62cxZuCSWyXE9MidBcnKDhs6W4745MqMAa d96cz3BaxLSx/aVdLG35mVssBpKvsHdR3pRlOfPnpxmaMUKQ3xSPvTFi35WdiTTqWnG8 nHKFLNapbaUWqTByzcNj7ZME/5F3v0jJk9bjhl2LR6NUj4XvbLCTVSp7/IILcanDcne1 1rPqGDJtezF219F5DkMkC6iqMuvAfLagXC6rAyjfLKY3JWbMmMwb8rOUCr+6wHYlR4vi y9RA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 41si638004wrc.108.2017.12.05.11.46.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAq-0005AF-U6; Tue, 05 Dec 2017 19:46:36 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 05/12] target/arm: Convert get_phys_addr_lpae() to not return FSC values Date: Tue, 5 Dec 2017 19:46:25 +0000 Message-Id: <1512503192-2239-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 1e95e3d..a2a0784 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,7 +34,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); /* Security attributes for an address, as returned by v8m_security_lookup. */ @@ -8277,10 +8277,9 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr s2pa; int s2prot; int ret; - uint32_t fsr; ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa, - &txattrs, &s2prot, &s2size, &fsr, fi, NULL); + &txattrs, &s2prot, &s2size, fi, NULL); if (ret) { fi->s2addr = addr; fi->stage2 = true; @@ -8603,15 +8602,6 @@ do_fault: return true; } -/* Fault type for long-descriptor MMU fault reporting; this corresponds - * to bits [5..2] in the STATUS field in long-format DFSR/IFSR. - */ -typedef enum { - translation_fault = 1, - access_fault = 2, - permission_fault = 3, -} MMUFaultType; - /* * check_s2_mmu_setup * @cpu: ARMCPU @@ -8713,13 +8703,13 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, - target_ulong *page_size_ptr, uint32_t *fsr, + target_ulong *page_size_ptr, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { ARMCPU *cpu = arm_env_get_cpu(env); CPUState *cs = CPU(cpu); /* Read an LPAE long-descriptor translation table. */ - MMUFaultType fault_type = translation_fault; + ARMFaultType fault_type = ARMFault_Translation; uint32_t level; uint32_t epd = 0; int32_t t0sz, t1sz; @@ -8829,7 +8819,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, ttbr_select = 1; } else { /* in the gap between the two regions, this is a Translation fault */ - fault_type = translation_fault; + fault_type = ARMFault_Translation; goto do_fault; } @@ -8915,7 +8905,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, ok = check_s2_mmu_setup(cpu, aarch64, startlevel, inputsize, stride); if (!ok) { - fault_type = translation_fault; + fault_type = ARMFault_Translation; goto do_fault; } level = startlevel; @@ -9001,7 +8991,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Here descaddr is the final physical address, and attributes * are all in attrs. */ - fault_type = access_fault; + fault_type = ARMFault_AccessFlag; if ((attrs & (1 << 8)) == 0) { /* Access flag */ goto do_fault; @@ -9019,7 +9009,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); } - fault_type = permission_fault; + fault_type = ARMFault_Permission; if (!(*prot & (1 << access_type))) { goto do_fault; } @@ -9051,8 +9041,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, return false; do_fault: - /* Long-descriptor format IFSR/DFSR value */ - *fsr = (1 << 9) | (fault_type << 2) | level; + fi->type = fault_type; + fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS); return true; @@ -9778,8 +9768,9 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* S1 is done. Now do S2 translation. */ ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS, phys_ptr, attrs, &s2_prot, - page_size, fsr, fi, + page_size, fi, cacheattrs != NULL ? &cacheattrs2 : NULL); + *fsr = arm_fi_to_lfsc(fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ *prot &= s2_prot; @@ -9858,8 +9849,12 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr, - attrs, prot, page_size, fsr, fi, cacheattrs); + bool ret = get_phys_addr_lpae(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); + + *fsr = arm_fi_to_lfsc(fi); + return ret; } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, page_size, fi); From patchwork Tue Dec 5 19:46:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120740 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168154qgn; Tue, 5 Dec 2017 11:46:38 -0800 (PST) X-Google-Smtp-Source: AGs4zMZJzfeDw2lllISBU5kZVGNqIp1w4kQv4B0ufgx8C9HbvcYk3PLvifYaIZ4dSkHU/9jlXXxN X-Received: by 10.223.155.131 with SMTP id d3mr18960193wrc.29.1512503198130; Tue, 05 Dec 2017 11:46:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503198; cv=none; d=google.com; s=arc-20160816; b=vID++pFMSWwi6NUSb0gqTXFtf/VuZ5s8HnlHy1fJoHtXoKbYyhjc13Bc77KaD1rM6v eXlja8J7+qqYqZm1IpkBC6r52/wTj3Df6hyJfrQcrI+gYHS3nD5m4z7+Ni6XusNUITpA VofKTAs91vBDZO74MoIXWROM9aAJvLn73ie2l1auLhC5Syk2czna6mZJyox5Q4Ogluez 9s7pCKUfiCH/HUQVAvxNn+N9fapfmcjhS61eGl+5lwZuJWt0iziW0Rgn4n1wBJ+ZFvPd AZLzEv9eHxWBIN17j9HFdVtVFY1no9olyNhrCcg9iIiQSHiz1xdO4tF/2/E7XlyneRi9 Tm5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=NmrjrdkPZ/DZlu3dbyTWJaSvflCpEaGCi1hAlSTE4T4=; b=BLuhE6gsfZUW9i7ffldNE8oMWm7XET1V0vwkE1Z9PvReoLf99qnxmJ0pEIMvsdedJi 9wZdQjFdXQDJzmt7B0S1t0KrRhrsdU74sktdZ16uODzNiJbBbK4SxntocQW5bAX5UOc+ i/NLJYpcgzxZQmq+uyiOuDy/bKmHEDZ4kttS6xNLiJ0QELmBTZFTE2Ak9eb10pYpWiOh gojBLWKPFdx9N5uO8qz+LijbNRj2Y1u9UaHk6aKgFWIOHyrTDfRh6Qam60A1Db80FOTB 5MDJQ94H+eOkbV7n+EWSnn/MNCmy3Nye/MlqQ5RIPc9jcBhcO9KHmJ5g8ToyBFUkEuWf gbuQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o1si640093wra.114.2017.12.05.11.46.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAr-0005Al-I6; Tue, 05 Dec 2017 19:46:37 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 06/12] target/arm: Convert get_phys_addr_pmsav5() to not return FSC values Date: Tue, 5 Dec 2017 19:46:26 +0000 Message-Id: <1512503192-2239-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Note that PMSAv5 does not define any guest-visible fault status register, so the different "fsr" values we were previously returning are entirely arbitrary. So we can just switch to using the most appropriae fi->type values without worrying that we need to special-case FaultInfo->FSC conversion for PMSAv5. Signed-off-by: Peter Maydell --- target/arm/helper.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index a2a0784..57286a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9547,7 +9547,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, uint32_t *fsr) + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) { int n; uint32_t mask; @@ -9576,7 +9577,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, } } if (n < 0) { - *fsr = 2; + fi->type = ARMFault_Background; return true; } @@ -9588,11 +9589,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, mask = (mask >> (n * 4)) & 0xf; switch (mask) { case 0: - *fsr = 1; + fi->type = ARMFault_Permission; + fi->level = 1; return true; case 1: if (is_user) { - *fsr = 1; + fi->type = ARMFault_Permission; + fi->level = 1; return true; } *prot = PAGE_READ | PAGE_WRITE; @@ -9608,7 +9611,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, break; case 5: if (is_user) { - *fsr = 1; + fi->type = ARMFault_Permission; + fi->level = 1; return true; } *prot = PAGE_READ; @@ -9618,7 +9622,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, break; default: /* Bad permission. */ - *fsr = 1; + fi->type = ARMFault_Permission; + fi->level = 1; return true; } *prot |= PAGE_EXEC; @@ -9823,7 +9828,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); + phys_ptr, prot, fi); + *fsr = arm_fi_to_sfsc(fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", From patchwork Tue Dec 5 19:46:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120741 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168174qgn; Tue, 5 Dec 2017 11:46:39 -0800 (PST) X-Google-Smtp-Source: AGs4zMYAzhPRJWcKuoJ1AbkoQxm54OPk1X9imJ3DfquMWpWsyfB/Wk+VkMENG/RlWHZy7RFSAWQF X-Received: by 10.28.15.11 with SMTP id 11mr5038055wmp.0.1512503199043; Tue, 05 Dec 2017 11:46:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503199; cv=none; d=google.com; s=arc-20160816; b=bd0QI8gxfCn1k0c49Ar6q6ecQJP6wlbpNyIvySSsk2GXQ6TIvMlxK5Twwx7s/CyFSI Lmz4uzav+Yg2yzgJVjdPQwTgLzYGYEOjrTHvmpCieSlAuxlxm09oxG9Nh2gCr+7l1y7E hOr4f9gpQ8zmVmEvqMOvBfUy3DiF/w4+r9nqTsus8RaFzx5dvqK950jwbaz6Ogs6gGOq BOsIq4Y3odb9KnScX2/9Krjqc2PidrMQkTJAi9HKc4w8bGA6dZQiL7gKNg87P8nxkxaw kL5OIa8tdcdQRWVRY134JWSqZeIQh3PiPOTy/9FF0zddKT5a71bbZ6RJff6CV3AEYYWq /q0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=XL8N80p1ka0KUdeN/YgCJ+DBBr+n3rgMsA145Bsez2s=; b=xmVOAmD8HcbyLhZ2RQTkwiWzAlmMmj12XK/8qVgyx4K5A2EStaQ3KclaMJ1sVVcMrh 2Dq7dyHcJQjpEuSSpAIyrL8LG76HXVUYkEFq1o+IsasweUqDIvf1felix/NAG19ApGyd MXh4t8X8/4KwTy0Q41Q/R7fw9BnsmczQOPBgkk5suuB/X3B0ZMAYI5ZEChD59jFzcj9s jH7noQmp0GqA4m1KpQq+8cP4Idu051rbvM0rZIjz41Rwhy6EciK6F2z9JipuAKWaA7Vf 2yl+9XgjjsLpLcTm8k8Sffsi474oNmnmdb8fEa94odNCSso41CCgT3Fc15zsFIvo8d6J u1fg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c24si646382wra.32.2017.12.05.11.46.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAs-0005BS-Ez; Tue, 05 Dec 2017 19:46:38 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 07/12] target/arm: Convert get_phys_addr_pmsav7() to not return FSC values Date: Tue, 5 Dec 2017 19:46:27 +0000 Message-Id: <1512503192-2239-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_pmsav7() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 57286a7..0f5b161 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9126,7 +9126,8 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address) static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, uint32_t *fsr) + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) { ARMCPU *cpu = arm_env_get_cpu(env); int n; @@ -9221,7 +9222,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, if (n == -1) { /* no hits */ if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { /* background fault */ - *fsr = 0; + fi->type = ARMFault_Background; return true; } get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); @@ -9279,7 +9280,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } } - *fsr = 0x00d; /* Permission fault */ + fi->type = ARMFault_Permission; + fi->level = 1; return !(*prot & (1 << access_type)); } @@ -9824,7 +9826,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); + phys_ptr, prot, fi); + *fsr = arm_fi_to_sfsc(fi); } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, From patchwork Tue Dec 5 19:46:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120743 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168183qgn; Tue, 5 Dec 2017 11:46:39 -0800 (PST) X-Google-Smtp-Source: AGs4zMaAp7xTBBp1sXTZYBBwEgrya+jgGVRemPTIhh3fJlMiiRflvTBQJC5cVyr9MQy/kUwSkmA/ X-Received: by 10.223.188.81 with SMTP id a17mr18521522wrh.146.1512503199634; Tue, 05 Dec 2017 11:46:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503199; cv=none; d=google.com; s=arc-20160816; b=ss9IkYTIuweWVbqiRdLXRymbG83s3hUYwBuX6pUdDZcC3w6t9QGjrG87jYIYjmnmq3 gf8g3ALDifA3lv33qBbEN82BZhbDgf96fyJ735Sb5EI3JZPhormEf+oI3otWHDMLF8PX 1VH3MZfjov/zkjKC9QF6n7G7ASteAnyifNOVs7JNXMdBNaM5zIAuNTBJI9nLYG941Irr KPkNENp3HIpVuwf3scyKo9uMss9kJ9l55P3KPz6LCwVuwIlPnbyX54tNeGQJc04FLk6U WtIJRUKNKx1qgP96gg4ruv7kI3Y8XcBVEiCsKed58dAHwhc3Y+w6GWdQ4mun/LsvhOq0 t6YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=vv1GP02Hm6hr/5fqJm6xXDe5E3FL+LaPtVNO5ia++YA=; b=0aUrBx1Egv19/zKmluvCcVvpl9wHEWwUuRFmoZD7AmW+gBKK99DJgOs5mLzlJdMHbB 1efsnSDo3D0BY36tdQjGTUFALQIxSb7Y8KTGE/mGD4Xu00jqT9C6UfjF+GMGMnGpG0XN Y94p++e4Ml9r8pJc6+qGc4EY8Lh+9mA91pF5/Mo77MDH8i2aiHgwoPAlgj1kcTTYSYZm 2bvJavgx3uoZCnP+ucmdvhtuMy3+HuFmZsJTEP2uDlx91tgYqGXcdTHGaZeDOzP2Ywjt sxNs7LstfGg56s5Hyz0eI/IJzw0/xX9aXW+yTCcYsOWymIO1QJVNP3FNfVihs/8GHKRP ssQg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g130si731254wme.96.2017.12.05.11.46.39 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAt-0005By-3H; Tue, 05 Dec 2017 19:46:39 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 08/12] target/arm: Convert get_phys_addr_pmsav8() to not return FSC values Date: Tue, 5 Dec 2017 19:46:28 +0000 Message-Id: <1512503192-2239-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Make get_phys_addr_pmsav8() return a fault type in the ARMMMUFaultInfo structure, which we convert to the FSC at the callsite. Signed-off-by: Peter Maydell --- target/arm/helper.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index 0f5b161..fad4923 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9367,7 +9367,7 @@ static void v8m_security_lookup(CPUARMState *env, uint32_t address, static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, uint32_t *fsr, uint32_t *mregion) + int *prot, ARMMMUFaultInfo *fi, uint32_t *mregion) { /* Perform a PMSAv8 MPU lookup (without also doing the SAU check * that a full phys-to-virt translation does). @@ -9423,7 +9423,8 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, /* Multiple regions match -- always a failure (unlike * PMSAv7 where highest-numbered-region wins) */ - *fsr = 0x00d; /* permission fault */ + fi->type = ARMFault_Permission; + fi->level = 1; return true; } @@ -9451,7 +9452,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, if (!hit) { /* background fault */ - *fsr = 0; + fi->type = ARMFault_Background; return true; } @@ -9479,7 +9480,8 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } } - *fsr = 0x00d; /* Permission fault */ + fi->type = ARMFault_Permission; + fi->level = 1; return !(*prot & (1 << access_type)); } @@ -9487,7 +9489,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, uint32_t *fsr) + int *prot, ARMMMUFaultInfo *fi) { uint32_t secure = regime_is_secure(env, mmu_idx); V8M_SAttributes sattrs = {}; @@ -9513,7 +9515,11 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * (including possibly emulating an SG instruction). */ if (sattrs.ns != !secure) { - *fsr = sattrs.nsc ? M_FAKE_FSR_NSC_EXEC : M_FAKE_FSR_SFAULT; + if (sattrs.nsc) { + fi->type = ARMFault_QEMU_NSCExec; + } else { + fi->type = ARMFault_QEMU_SFault; + } *phys_ptr = address; *prot = 0; return true; @@ -9535,7 +9541,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, * If we added it we would need to do so as a special case * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). */ - *fsr = M_FAKE_FSR_SFAULT; + fi->type = ARMFault_QEMU_SFault; *phys_ptr = address; *prot = 0; return true; @@ -9544,7 +9550,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, } return pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, fsr, NULL); + txattrs, prot, fi, NULL); } static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, @@ -9822,7 +9828,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, fsr); + phys_ptr, attrs, prot, fi); + *fsr = arm_fi_to_sfsc(fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, @@ -10183,9 +10190,9 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) uint32_t tt_resp; bool r, rw, nsr, nsrw, mrvalid; int prot; + ARMMMUFaultInfo fi = {}; MemTxAttrs attrs = {}; hwaddr phys_addr; - uint32_t fsr; ARMMMUIdx mmu_idx; uint32_t mregion; bool targetpriv; @@ -10219,7 +10226,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) if (arm_current_el(env) != 0 || alt) { /* We can ignore the return value as prot is always set */ pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &phys_addr, &attrs, &prot, &fsr, &mregion); + &phys_addr, &attrs, &prot, &fi, &mregion); if (mregion == -1) { mrvalid = false; mregion = 0; From patchwork Tue Dec 5 19:46:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120744 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168204qgn; Tue, 5 Dec 2017 11:46:40 -0800 (PST) X-Google-Smtp-Source: AGs4zMbr0DsaY5FDj1Yz5A11oOjQ6h9bzx07GPRL9kFweXRSubWuT7vv63Poaxb0vMnWW18/7UiG X-Received: by 10.28.67.2 with SMTP id q2mr10300793wma.38.1512503200653; Tue, 05 Dec 2017 11:46:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503200; cv=none; d=google.com; s=arc-20160816; b=C1Br05xW2NE2e5MJ2Cn+SVnRiQcEx9ph+rA0oB+BLOgYFvqWB3X/YMITsH8ebtujns vxW8QZlcLI1x05KGXROZ5znmQpbMypiAN7eSD8A11J5b56OprZq4Ss2P582z/gsmfn8e BUy2ZrFFBfi/s+pJGSt4NlLlwb2osvo3b5sx1e8olzylflXn++R4LHKdtIfa7YTv/0Z/ KA4X8KEhPMPmlRGKFoORg5GERKx7LFdYyrU9jEXTDMs9xnxQK+zOIoT+Iqxf2J+yy6dW 03HqX4dGwy0hVl6yCmRfhxySuH8g4mZMFuisv8xj/CIDVLX/Jh3fBPP9+IPGNMMpKFzK MJNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=CwhYfMOiSAZu0iD7QYDviMwVBzN6EUTqx08eX+sAN+s=; b=p/+bKnnCRxcLCiyo8mhaYnNSd9A6oQj191s8oI5JNys6MqiWiAOKsWfmfedoF8aZSi 091FUBxu2dq3+ybF82cUXnK4R3IxvWgEbGYas7bJFAqAxC5NbQuPEz/I6oqHTjhkrBps 7ZH02oMr1oaQnS9/VVqDNZOGsZZX5ybkO2vaTfsrW8+cXBav9ub4M6DGsX94NMvOlzEM TcKTaiX7lNcJiZOvbm26u2ydwtncWuPlApDbTiL7u0kxxxkCuOItUS931hWcvlIGa+vS 2d1VhJS7prAvfvBQLcBeDdJLCioGllQODmLDeJjASJNdl7+uA0toj3ZQ2bXAYcWJQHy3 2wow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id x14si615934wrg.146.2017.12.05.11.46.40 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAt-0005CG-OZ; Tue, 05 Dec 2017 19:46:39 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 09/12] target/arm: Use ARMMMUFaultInfo in deliver_fault() Date: Tue, 5 Dec 2017 19:46:29 +0000 Message-Id: <1512503192-2239-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> Now that ARMMMUFaultInfo is guaranteed to have enough information to construct a fault status code, we can pass it in to the deliver_fault() function and let it generate the correct type of FSR for the destination, rather than relying on the value provided by get_phys_addr(). I don't think there are any cases the old code was getting wrong, but this is more obviously correct. Signed-off-by: Peter Maydell --- target/arm/op_helper.c | 79 ++++++++++++++------------------------------------ 1 file changed, 22 insertions(+), 57 deletions(-) -- 2.7.4 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index a40a84a..38e6993 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -116,12 +116,13 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, } static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, - uint32_t fsr, uint32_t fsc, ARMMMUFaultInfo *fi) + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; int target_el; bool same_el; - uint32_t syn, exc; + uint32_t syn, exc, fsr, fsc; + ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); target_el = exception_target_el(env); if (fi->stage2) { @@ -130,14 +131,21 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, } same_el = (arm_current_el(env) == target_el); - if (fsc == 0x3f) { - /* Caller doesn't have a long-format fault status code. This - * should only happen if this fault will never actually be reported - * to an EL that uses a syndrome register. Check that here. - * 0x3f is a (currently) reserved FSC code, in case the constructed - * syndrome does leak into the guest somehow. + if (target_el == 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* LPAE format fault status register : bottom 6 bits are + * status code in the same form as needed for syndrome + */ + fsr = arm_fi_to_lfsc(fi); + fsc = extract32(fsr, 0, 6); + } else { + fsr = arm_fi_to_sfsc(fi); + /* Short format FSR : this fault will never actually be reported + * to an EL that uses a syndrome register. Use a (currently) + * reserved FSR code in case the constructed syndrome does leak + * into the guest somehow. */ - assert(target_el != 2 && !arm_el_is_aa64(env, target_el)); + fsc = 0x3f; } if (access_type == MMU_INST_FETCH) { @@ -174,29 +182,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); - uint32_t fsc; if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } - if (fsr & (1 << 9)) { - /* LPAE format fault status register : bottom 6 bits are - * status code in the same form as needed for syndrome - */ - fsc = extract32(fsr, 0, 6); - } else { - /* Short format FSR : this fault will never actually be reported - * to an EL that uses a syndrome register. Use a (currently) - * reserved FSR code in case the constructed syndrome does leak - * into the guest somehow. deliver_fault will assert that - * we don't target an EL using the syndrome. - */ - fsc = 0x3f; - } - - deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); + deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } } @@ -206,27 +198,15 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int mmu_idx, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint32_t fsr, fsc; ARMMMUFaultInfo fi = {}; - ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } - /* the DFSR for an alignment fault depends on whether we're using - * the LPAE long descriptor format, or the short descriptor format - */ - if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - fsr = (1 << 9) | 0x21; - } else { - fsr = 0x1; - } - fsc = 0x21; - - deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); + fi.type = ARMFault_Alignment; + deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } /* arm_cpu_do_transaction_failed: handle a memory system error response @@ -240,10 +220,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs); - CPUARMState *env = &cpu->env; - uint32_t fsr, fsc; ARMMMUFaultInfo fi = {}; - ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); if (retaddr) { /* now we have a real cpu fault */ @@ -256,20 +233,8 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, * Slave error (1); in QEMU we follow that. */ fi.ea = (response != MEMTX_DECODE_ERROR); - - /* The fault status register format depends on whether we're using - * the LPAE long descriptor format, or the short descriptor format. - */ - if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - /* long descriptor form, STATUS 0b010000: synchronous ext abort */ - fsr = (fi.ea << 12) | (1 << 9) | 0x10; - } else { - /* short descriptor form, FSR 0b01000 : synchronous ext abort */ - fsr = (fi.ea << 12) | 0x8; - } - fsc = 0x10; - - deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); + fi.type = ARMFault_SyncExternal; + deliver_fault(cpu, addr, access_type, mmu_idx, &fi); } #endif /* !defined(CONFIG_USER_ONLY) */ From patchwork Tue Dec 5 19:46:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120745 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168224qgn; Tue, 5 Dec 2017 11:46:41 -0800 (PST) X-Google-Smtp-Source: AGs4zMbE0xDT+AvqfEzumGnLF3nbPlZXRLjZ+stdEoJJ8HXPnmXC6nyd//pFJmnG66oF4Rwylo81 X-Received: by 10.46.17.153 with SMTP id 25mr11890293ljr.36.1512503201335; Tue, 05 Dec 2017 11:46:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503201; cv=none; d=google.com; s=arc-20160816; b=NofuYHe3DCBQg2DKchYDOhebeVmcJNvkYYF5HaofYAPEspB3/G7QzD7NWUa4TgZemi oUhV4IoW6Q8WkbFzmMjbMMA0+4Gm8Tq4nSonlHxRESPP+rdmUAu+Pt0BWNCGAQUKrOwB Cs1UslQWf6Nko5bOiNO60KO0KCzTSQv4VzFWThmTy94YA0K6Oxx9HTZEvd4kHGiukpdp yJYA99oPpNgjW9kKfRTi5h/aGTTD/3ErNskBk+Ce+XGswtAf1u6YJ+ClvoZmfSUa6rzR kjRyDZMutJtdwbnIXJpX7EwQmge7nwnPgILhqGblmXE/nEWWH3c1/uXYFHvMuy9H1vNT tkkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=qB9RN9afNeI8kCNbWloE9IdDxroG41xi0OTHqDEVoV8=; b=LFCUrm2Jm0haItjJ61ObQOrFdqkq3k7RX4uyb21+xv+rb0BGec4avwNNu3fEcRfQWU svuIBVrE2iJ8R4nVr07koO6jsVvdCEP8b1SoM2/5Ssa9FJIHg8SsZr7BtDFPWK2ayZds EfkbLF6B+mtqgpkaeXb7K0ajeizrTwvNmun6QxpV0Rx7T3zR6R+imvMlLV3aD8yq+ORm LugXtLHfhFDppK0CMTc3spGH3+JaRV1072OxzbtkyddFTA2kyMODA7CXq+kpmfmCH0Cm BgGdH1AO4zRvgCizMpglQzz9TmoCQc+PyuF3UQG3+uqpZ4gBd7MvLrhZUni+eSXD61R+ PcgQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s63si365293lja.82.2017.12.05.11.46.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAu-0005Ck-E7; Tue, 05 Dec 2017 19:46:40 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 10/12] target/arm: Ignore fsr from get_phys_addr() in do_ats_write() Date: Tue, 5 Dec 2017 19:46:30 +0000 Message-Id: <1512503192-2239-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> In do_ats_write(), rather than using the FSR value from get_phys_addr(), construct the PAR values using the information in the ARMMMUFaultInfo struct. This allows us to create a PAR of the correct format regardless of what the translation table format is. For the moment we leave the condition for "when should this be a 64 bit PAR" as it was previously; this will need to be fixed to properly support AArch32 Hyp mode. Signed-off-by: Peter Maydell --- target/arm/helper.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index fad4923..17192f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2160,7 +2160,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, hwaddr phys_addr; target_ulong page_size; int prot; - uint32_t fsr; + uint32_t fsr_unused; bool ret; uint64_t par64; MemTxAttrs attrs = {}; @@ -2168,12 +2168,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMCacheAttrs cacheattrs = {}; ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, - &prot, &page_size, &fsr, &fi, &cacheattrs); + &prot, &page_size, &fsr_unused, &fi, &cacheattrs); + /* TODO: this is not the correct condition to use to decide whether + * to report a PAR in 64-bit or 32-bit format. + */ if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { - /* fsr is a DFSR/IFSR value for the long descriptor - * translation table format, but with WnR always clear. - * Convert it to a 64-bit PAR. - */ + /* Create a 64-bit PAR */ par64 = (1 << 11); /* LPAE bit always set */ if (!ret) { par64 |= phys_addr & ~0xfffULL; @@ -2183,6 +2183,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (uint64_t)cacheattrs.attrs << 56; /* ATTR */ par64 |= cacheattrs.shareability << 7; /* SH */ } else { + uint32_t fsr = arm_fi_to_lfsc(&fi); + par64 |= 1; /* F */ par64 |= (fsr & 0x3f) << 1; /* FS */ /* Note that S2WLK and FSTAGE are always zero, because we don't @@ -2207,6 +2209,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (1 << 9); /* NS */ } } else { + uint32_t fsr = arm_fi_to_sfsc(&fi); + par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | ((fsr & 0xf) << 1) | 1; } From patchwork Tue Dec 5 19:46:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120746 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168235qgn; Tue, 5 Dec 2017 11:46:41 -0800 (PST) X-Google-Smtp-Source: AGs4zMb996mZhC+zlPZj+fmRW9vJKdwmMPOlayRIYLFnYB6cmu5ctC47NWFUXwVw/qGiXs43Z8hX X-Received: by 10.28.26.139 with SMTP id a133mr6629418wma.90.1512503201720; Tue, 05 Dec 2017 11:46:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503201; cv=none; d=google.com; s=arc-20160816; b=CqUPIO08x3/lhH6YBeN9IzcYQiE/V+UgC66qw2vGXTXtJAyB9gpp84P6adI4FeBJnd nOaQx4x5ccFce03tkqe7K3wo9YToouFMSZE3KEE4S/EJHbJTcI4qecidVUv4+tsif+mo UoW6/Xjqam/yofrWc8Ih2FauwpIcEdTiPLZ9UUf9Y9zqnUs68LuD0glTHpCHRBG5ocC1 r53Z5Wb264jUqojk1+Qego5nNQJzJcGXeGd1ZE9bcVbPLZwBOh5Eo+oIIuHPn8LTvbmG aRR2Xoo1xOE9WfJZLt+UYT0elQ31BFSHf+1p5j2IU3qP9IjWtQ4ZxvYgp011fMZZBVHA nfWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=TlyvEuyqgl5E8P79AcvnO6U6mRsPf+tD2jityEylgTA=; b=yT8iNfk8SIG3jIs+nPFBZAl0dequroO4tKWfhxRmrtVFHS7I2/TxvwY5jOle04MHe4 M+WlQCgxHF+qW8PZfvTu1cIM4Y5/SnTmvlSPRI5ZoCKFAp88404WkFQjZ7PVKUs9+lvQ Lkt0GCTtnx69FwQBFSSEwGM9fBcQPMPyQ+UePWn8OeokXVEd7LgSofewHUSjPnEafjD6 3qQsWBA8AkAi4zlnKPDO7fSuZdun2vem9yFMrbb57jFJK/2aYP4MKA4JT+vx4zJQZIZI 7/8mnTqSL57uHTBXyNe+ThCLDCgea9rmyn5iYwz2Owxi+yZiTruvZhdseY2RD2lG1OF3 KyMw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id k4si621818wrg.162.2017.12.05.11.46.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAv-0005DV-38; Tue, 05 Dec 2017 19:46:41 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 11/12] target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill() Date: Tue, 5 Dec 2017 19:46:31 +0000 Message-Id: <1512503192-2239-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> All of the callers of get_phys_addr() and arm_tlb_fill() now ignore the FSR values they return, so we can just remove the argument entirely. Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 +- target/arm/helper.c | 45 ++++++++++++++------------------------------- target/arm/op_helper.c | 3 +-- 3 files changed, 16 insertions(+), 34 deletions(-) -- 2.7.4 diff --git a/target/arm/internals.h b/target/arm/internals.h index 67b9a52..876854d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -690,7 +690,7 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi) /* Do a page table walk and add page to TLB if possible */ bool arm_tlb_fill(CPUState *cpu, vaddr address, MMUAccessType access_type, int mmu_idx, - uint32_t *fsr, ARMMMUFaultInfo *fi); + ARMMMUFaultInfo *fi); /* Return true if the stage 1 translation regime is using LPAE format page * tables */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 17192f8..c23e424 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -28,7 +28,7 @@ typedef struct ARMCacheAttrs { static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, + target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, @@ -2160,7 +2160,6 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, hwaddr phys_addr; target_ulong page_size; int prot; - uint32_t fsr_unused; bool ret; uint64_t par64; MemTxAttrs attrs = {}; @@ -2168,7 +2167,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, ARMCacheAttrs cacheattrs = {}; ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, - &prot, &page_size, &fsr_unused, &fi, &cacheattrs); + &prot, &page_size, &fi, &cacheattrs); /* TODO: this is not the correct condition to use to decide whether * to report a PAR in 64-bit or 32-bit format. */ @@ -6981,7 +6980,6 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, target_ulong page_size; hwaddr physaddr; int prot; - uint32_t fsr; v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); if (!sattrs.nsc || sattrs.ns) { @@ -6995,7 +6993,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, return false; } if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, - &physaddr, &attrs, &prot, &page_size, &fsr, &fi, NULL)) { + &physaddr, &attrs, &prot, &page_size, &fi, NULL)) { /* the MPU lookup failed */ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_IACCVIOL_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secure); @@ -9752,14 +9750,13 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) * @attrs: set to the memory transaction attributes to use * @prot: set to the permissions for the page containing phys_ptr * @page_size: set to the size of the page containing phys_ptr - * @fsr: set to the DFSR/IFSR value on failure * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ static bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, uint32_t *fsr, + target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { @@ -9774,7 +9771,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, ret = get_phys_addr(env, address, access_type, stage_1_mmu_idx(mmu_idx), &ipa, attrs, - prot, page_size, fsr, fi, cacheattrs); + prot, page_size, fi, cacheattrs); /* If S1 fails or S2 is disabled, return early. */ if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) { @@ -9787,7 +9784,6 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, phys_ptr, attrs, &s2_prot, page_size, fi, cacheattrs != NULL ? &cacheattrs2 : NULL); - *fsr = arm_fi_to_lfsc(fi); fi->s2addr = ipa; /* Combine the S1 and S2 perms. */ *prot &= s2_prot; @@ -9833,17 +9829,14 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, /* PMSAv8 */ ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, phys_ptr, attrs, prot, fi); - *fsr = arm_fi_to_sfsc(fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, phys_ptr, prot, fi); - *fsr = arm_fi_to_sfsc(fi); } else { /* Pre-v7 MPU */ ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, phys_ptr, prot, fi); - *fsr = arm_fi_to_sfsc(fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -9869,24 +9862,15 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, } if (regime_using_lpae_format(env, mmu_idx)) { - bool ret = get_phys_addr_lpae(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); - - *fsr = arm_fi_to_lfsc(fi); - return ret; + return get_phys_addr_lpae(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - bool ret = get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); - - *fsr = arm_fi_to_sfsc(fi); - return ret; + return get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); } else { - bool ret = get_phys_addr_v5(env, address, access_type, mmu_idx, + return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr, prot, page_size, fi); - - *fsr = arm_fi_to_sfsc(fi); - return ret; } } @@ -9895,7 +9879,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, * fsr with ARM DFSR/IFSR fault register format value on failure. */ bool arm_tlb_fill(CPUState *cs, vaddr address, - MMUAccessType access_type, int mmu_idx, uint32_t *fsr, + MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu = ARM_CPU(cs); @@ -9908,7 +9892,7 @@ bool arm_tlb_fill(CPUState *cs, vaddr address, ret = get_phys_addr(env, address, access_type, core_to_arm_mmu_idx(env, mmu_idx), &phys_addr, - &attrs, &prot, &page_size, fsr, fi, NULL); + &attrs, &prot, &page_size, fi, NULL); if (!ret) { /* Map a single [sub]page. */ phys_addr &= TARGET_PAGE_MASK; @@ -9930,14 +9914,13 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, target_ulong page_size; int prot; bool ret; - uint32_t fsr; ARMMMUFaultInfo fi = {}; ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); *attrs = (MemTxAttrs) {}; ret = get_phys_addr(env, addr, 0, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fsr, &fi, NULL); + attrs, &prot, &page_size, &fi, NULL); if (ret) { return -1; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 38e6993..c2bb4f3 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -176,10 +176,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { bool ret; - uint32_t fsr = 0; ARMMMUFaultInfo fi = {}; - ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); + ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fi); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs); From patchwork Tue Dec 5 19:46:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 120747 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6168253qgn; Tue, 5 Dec 2017 11:46:42 -0800 (PST) X-Google-Smtp-Source: AGs4zMZiRa8JWnRfCzCA6HXf5UmnKk9caHeIXlHhhIqunbS3a+siAHRZ2s08oDcXd2UeJ4+5/K8N X-Received: by 10.28.215.74 with SMTP id o71mr10012596wmg.46.1512503202281; Tue, 05 Dec 2017 11:46:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512503202; cv=none; d=google.com; s=arc-20160816; b=QEiXw4HNiCXuGY/Xu74gkKbVLUJX1zUQOD+nOfu++akLkRXt+gt/GFkLhEbO70d9fX Ee7w5zRCZJPuiEPU/wD+dW5IB7CEp0XJBkDp2tCjNcgP0niT/hZz/iBeE1VYt78vnHSJ SIdGpP77UZTmN7Qralk9dbVBFA8IYozQvxunWu1iQFV//ZLGeJN0Ml7CExsGpdCsXxXt kR0iHL+6jJ2XJTI41S0jpJFnX1CNHonazxmJLp5XdtIBAUGNGopulW8zdSsC7gA+xSUs BZvbnu/ly5SQ3Nv+ood7qVVu4AnA3tGFM1qAMXk6gcpLwEEL5CFRmxJ6QmEaiCsus7Uy rmZQ== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l11si632683wrh.161.2017.12.05.11.46.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 05 Dec 2017 11:46:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eMJAv-0005Dm-NG; Tue, 05 Dec 2017 19:46:41 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, "Edgar E . Iglesias" , Stefano Stabellini Subject: [PATCH 12/12] target/arm: Extend PAR format determination Date: Tue, 5 Dec 2017 19:46:32 +0000 Message-Id: <1512503192-2239-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> References: <1512503192-2239-1-git-send-email-peter.maydell@linaro.org> From: "Edgar E. Iglesias" Now that do_ats_write() is entirely in control of whether to generate a 32-bit PAR or a 64-bit PAR, we can make it use the correct (complicated) condition for doing so. Signed-off-by: Edgar E. Iglesias [PMM: Rebased Edgar's patch on top of get_phys_addr() refactoring; use arm_s1_regime_using_lpae_format() rather than regime_using_lpae_format() because the latter will assert if passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1; updated commit message appropriately] Signed-off-by: Peter Maydell --- target/arm/helper.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/target/arm/helper.c b/target/arm/helper.c index c23e424..d526db4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2162,16 +2162,41 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, int prot; bool ret; uint64_t par64; + bool format64 = false; MemTxAttrs attrs = {}; ARMMMUFaultInfo fi = {}; ARMCacheAttrs cacheattrs = {}; ret = get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &attrs, &prot, &page_size, &fi, &cacheattrs); - /* TODO: this is not the correct condition to use to decide whether - * to report a PAR in 64-bit or 32-bit format. - */ - if (arm_s1_regime_using_lpae_format(env, mmu_idx)) { + + if (is_a64(env)) { + format64 = true; + } else if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* + * ATS1Cxx: + * * TTBCR.EAE determines whether the result is returned using the + * 32-bit or the 64-bit PAR format + * * Instructions executed in Hyp mode always use the 64bit format + * + * ATS1S2NSOxx uses the 64bit format if any of the following is true: + * * The Non-secure TTBCR.EAE bit is set to 1 + * * The implementation includes EL2, and the value of HCR.VM is 1 + * + * ATS1Hx always uses the 64bit format (not supported yet). + */ + format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { + format64 |= env->cp15.hcr_el2 & HCR_VM; + } else { + format64 |= arm_current_el(env) == 2; + } + } + } + + if (format64) { /* Create a 64-bit PAR */ par64 = (1 << 11); /* LPAE bit always set */ if (!ret) {