From patchwork Thu Dec 7 10:27:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 120954 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8179878qgn; Thu, 7 Dec 2017 02:32:06 -0800 (PST) X-Google-Smtp-Source: AGs4zMZMDdfiVR2+NhlXqqo3zA+D7qSHhviHTWQdknKsiWQhRpvjI5OJj7sAivKiYI1cFX33C8LS X-Received: by 10.84.212.151 with SMTP id e23mr25477096pli.449.1512642726563; Thu, 07 Dec 2017 02:32:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512642726; cv=none; d=google.com; s=arc-20160816; b=AlT2Vg0HUqdw8tNEYYnHNGH83vuGl4UZ7RmirXp42zz72BzU9TktKHtj4XjWkKTlMf LjiuiFhc4SpanBOXYmhv+5PN1ahh05paIUK7ZvlHt8j44JAudtS+bcylUm3GOFrebzd9 bnogLAlXDWie/eztFZ8rg8eRjfXoTW3gvzu8n2zlOOnpKZmU+igvjMBNBkmnnO9nl4Yp bN+BSWiCEvPvd+FlJXund+cMxL6Qd7pu8i4jJ6R+7ycy0v/LkcI5ZIzJ/lhz3cbw1ms2 XhwnD6ZY04JrgQxYUospifzsUiYuIXxb3Po9a6YeQmdN+XQeDXpwdrnMpHi6jOlS56vd 2ilw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=HZYbyrD9ze1PZ+q2JHZiocYridKvauK/rrLWoYJTwSg=; b=0K8/9c3FFa7ucuUs8TzBMRBjodYzVvgl0lglHltxjJNb0+18wlsMFjUpiJpLIyFrb1 2VmvercTTnpFip63k3kVVOOohZN17ztF9YWv6mcvWWptLUUNN0+xkC59/WaGPeEhjvtB ZR32fM8kZOtbfxECiZuXaWWhSK8HLrDdfgCnODGCXQK4Egy+wfP+Awr+bgwjK5JHI5sz BcPDkY9u8or/1SSkzvxx5gfsX4Gueu6K9Li3oMh0nvcfkOqJet+QdM4PNw7dcAww6XBr +e2APXQ1qJd6CFJePIExi+zpRkKEcMl3EqNK+WA7Ve9k6eT19hw9DQ5dOfOj9HBA4u6S 6pEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NVD4zrtM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id k2sm4837734wrg.4.2017.12.07.02.30.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:30:36 -0800 (PST) From: srinivas.kandagatla@linaro.org To: Mark Brown , Greg Kroah-Hartman , alsa-devel@alsa-project.org Cc: sdharia@codeaurora.org, Rob Herring , Mark Rutland , Jonathan Corbet , pombredanne@nexb.com, j.neuschaefer@gmx.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v9 02/13] dt-bindings: Add SLIMbus bindings Date: Thu, 7 Dec 2017 10:27:09 +0000 Message-Id: <20171207102720.21071-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> References: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sagar Dharia SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by MIPI (Mobile Industry Processor Interface) alliance. SLIMbus is a 2-wire implementation, which is used to communicate with peripheral components like audio-codec. This patch adds device tree bindings for the slimbus. Signed-off-by: Sagar Dharia Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/slimbus/bus.txt | 50 +++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/slimbus/bus.txt -- 2.15.0 diff --git a/Documentation/devicetree/bindings/slimbus/bus.txt b/Documentation/devicetree/bindings/slimbus/bus.txt new file mode 100644 index 000000000000..52fa6426388c --- /dev/null +++ b/Documentation/devicetree/bindings/slimbus/bus.txt @@ -0,0 +1,50 @@ +SLIM(Serial Low Power Interchip Media Bus) bus + +SLIMbus is a 2-wire bus, and is used to communicate with peripheral +components like audio-codec. + +Required property for SLIMbus controller node: +- compatible - name of SLIMbus controller + +Child nodes: +Every SLIMbus controller node can contain zero or more child nodes +representing slave devices on the bus. Every SLIMbus slave device is +uniquely determined by the enumeration address containing 4 fields: +Manufacturer ID, Product code, Device index, and Instance value for +the device. +If child node is not present and it is instantiated after device +discovery (slave device reporting itself present). + +In some cases it may be necessary to describe non-probeable device +details such as non-standard ways of powering up a device. In +such cases, child nodes for those devices will be present as +slaves of the SLIMbus controller, as detailed below. + +Required property for SLIMbus child node if it is present: +- reg - Should be ('Device index', 'Instance ID') from SLIMbus + Enumeration Address. + Device Index Uniquely identifies multiple Devices within + a single Component. + Instance ID Is for the cases where multiple Devices of the + same type or Class are attached to the bus. + +- compatible -"slimMID,PID". The textual representation of Manufacturer ID, + Product Code, shall be in lower case hexadecimal with leading + zeroes suppressed + +SLIMbus example for Qualcomm's slimbus manager component: + + slim@28080000 { + compatible = "qcom,apq8064-slim", "qcom,slim"; + reg = <0x28080000 0x2000>, + interrupts = <0 33 0>; + clocks = <&lcc SLIMBUS_SRC>, <&lcc AUDIO_SLIMBUS_CLK>; + clock-names = "iface", "core"; + #address-cells = <2>; + #size-cell = <0>; + + codec: wcd9310@1,0{ + compatible = "slim217,60"; + reg = <1 0>; + }; + }; From patchwork Thu Dec 7 10:27:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 120961 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8183230qgn; Thu, 7 Dec 2017 02:35:33 -0800 (PST) X-Google-Smtp-Source: AGs4zMahAwfb3vmWta4t3AUQ3ErE+ygSjNamMpHe+DRQde/g1XAnrgysr9EyZhR99h7VKwYf9JOe X-Received: by 10.159.250.143 with SMTP id k15mr12977865pls.336.1512642933825; Thu, 07 Dec 2017 02:35:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512642933; cv=none; d=google.com; s=arc-20160816; b=jEa7JqaNgB8HTGRHMw5vf+U434jo1Xqm5S92vDFqz0bzi2mjerUwK+E4FoGxAmnsY3 PAt1ntORSR/X2ylCbytg7IQHVC5bHH8cHUNwyD3gqwfzRqQvd+FaINar8L/wPp3qcdu/ 2P/mJsgYbH3RVmzZ5UOBW4j/cwvJB6W3Cm6CshfKpMnCI187edzlN4koSqRyMJCdxzl8 UHvgQzJeQPWF0qwCSUwzSLSo2A0NZPLFydVz+25o+IlAyeggaf9Ibr8agPnc3g0bnSDs 9pTPNwvcynCRojttGowpwOw80BGtmJ++90cK7bmknwQZZhdfRvDD4tOG8M99n7upQ33+ Mx5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=baXZINT5NXXZVjgVmEu9nTnl6BEclj/wZveGtDlEkKg=; b=AdjMVA6Z46cLvPn+nD+yQZ/OWLZXzklJIa58PmrpTcMLGhDiBwRHd9YcrtdlRd8qyz bPKKHXJeyMcDK8Bx8Cgqa9Lb2UjmfV8Jy807Yi8MH6v0d9FRhTEBWs5CqSlWTiZAKbq3 0hGny3zwV3B1GqPGocFeAEEDG9UULlxVpLhSdiSLlgDymzagvhQ2ViK8eXmp+UJW8MR1 93iZ7B5ZOxPAhwYeWPtmpg0MHJjnseKPhbgyG/KvgP6nC2zAuZl3U7hN42KGSg7deqoJ /7iXIOsKMY+pW7cPO3qSnmVUGYTkI8FPoTQv07y39EnTNP+fBs6PL96CKsCmwqM6pELa DIBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WYmfFbMd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id k2sm4837734wrg.4.2017.12.07.02.30.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:30:40 -0800 (PST) From: srinivas.kandagatla@linaro.org To: Mark Brown , Greg Kroah-Hartman , alsa-devel@alsa-project.org Cc: sdharia@codeaurora.org, Rob Herring , Mark Rutland , Jonathan Corbet , pombredanne@nexb.com, j.neuschaefer@gmx.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v9 05/13] slimbus: core: add support to device tree helper Date: Thu, 7 Dec 2017 10:27:12 +0000 Message-Id: <20171207102720.21071-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> References: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Srinivas Kandagatla This patch adds support to parse slim devices from device tree. Signed-off-by: Srinivas Kandagatla --- drivers/slimbus/core.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.15.0 diff --git a/drivers/slimbus/core.c b/drivers/slimbus/core.c index a59a88a7a52d..cd2a47dec635 100644 --- a/drivers/slimbus/core.c +++ b/drivers/slimbus/core.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "slimbus.h" @@ -111,6 +112,9 @@ static int slim_add_device(struct slim_controller *ctrl, sbdev->dev.driver = NULL; sbdev->ctrl = ctrl; + if (node) + sbdev->dev.of_node = of_node_get(node); + dev_set_name(&sbdev->dev, "%x:%x:%x:%x", sbdev->e_addr.manf_id, sbdev->e_addr.prod_code, @@ -141,6 +145,50 @@ static struct slim_device *slim_alloc_device(struct slim_controller *ctrl, return sbdev; } +static void of_register_slim_devices(struct slim_controller *ctrl) +{ + struct device *dev = ctrl->dev; + struct device_node *node; + + if (!ctrl->dev->of_node) + return; + + for_each_child_of_node(ctrl->dev->of_node, node) { + struct slim_device *sbdev; + struct slim_eaddr e_addr; + const char *compat = NULL; + int reg[2], ret; + int manf_id, prod_code; + + compat = of_get_property(node, "compatible", NULL); + if (!compat) + continue; + + ret = sscanf(compat, "slim%x,%x", &manf_id, &prod_code); + if (ret != 2) { + dev_err(dev, "Manf ID & Product code not found %s\n", + compat); + continue; + } + + ret = of_property_read_u32_array(node, "reg", reg, 2); + if (ret) { + dev_err(dev, "Device and Instance id not found:%d\n", + ret); + continue; + } + + e_addr.dev_index = reg[0]; + e_addr.instance = reg[1]; + e_addr.manf_id = manf_id; + e_addr.prod_code = prod_code; + + sbdev = slim_alloc_device(ctrl, &e_addr, node); + if (!sbdev) + continue; + } +} + /* * slim_register_controller() - Controller bring-up and registration. * @@ -172,6 +220,8 @@ int slim_register_controller(struct slim_controller *ctrl) dev_dbg(ctrl->dev, "Bus [%s] registered:dev:%p\n", ctrl->name, ctrl->dev); + of_register_slim_devices(ctrl); + return 0; } EXPORT_SYMBOL_GPL(slim_register_controller); From patchwork Thu Dec 7 10:27:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 120959 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8181202qgn; Thu, 7 Dec 2017 02:33:25 -0800 (PST) X-Google-Smtp-Source: AGs4zMYDzi+AsSdwi6wzqv0Dm6SQkodne1zAlIfJfAs3oYhZ6S51QmdgKufn6qUx5P1y1Cyx8xnb X-Received: by 10.99.136.198 with SMTP id l189mr25475965pgd.307.1512642805416; Thu, 07 Dec 2017 02:33:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512642805; cv=none; d=google.com; s=arc-20160816; b=WpLELD0jOrp+4BqxTtElmxDcJgheUABNj0vzn8WnrHorQQBQSZK+pQJeLueoTLclpy KLYNBD2B7T7tiZduw5d1YXRMe5aAJH/NAiGnFPRtDCQwcQUMsi0adYVCH4KARBab20mG 5hrsHOAX4l07BgUpKXw1GrpLpzC5dCnJ2MefwzGtWGZb7t9NV4TI0Cq8ATchKUxWqA4y GJamq2Ne8t2fkpOqrRvREyuB4lm/yIqHtow7+V35oT9mdNcHf+4bhtuOdZHovfT1s9gS sWviw9CmT9lc2TK+k7WoXxY+FsPxIQ6WCO6p+QK5oYzHBYjBfeODj08pztPrAGVXLSZx nLMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SZXq628LwAI/zssq5oA1vcFcJ1pJBiBd9MS5mT7xUDU=; b=QI+UGKA0WdwvuPZ6+O1jA4endA1OpZf7SH3dqIhmzaDah3iG2WiRoh05loUHF489qs 9wNK4NrLFFU5XksRuvc7IC/up4uxCkuAfV55BbJXvsuKDbdwzD6jMDnAFBBT0xDXdD6y 6xOMivgEDfhgFzF6v0txgnouFc4Rlq8bQyuu50XHS7kC44FKDWWCjurpFvPbVVvM9Wf5 LxCeltY0LJwk0U7jfqlBhCSVm2n4jZSNXfj4MZiWWXCy8zmMuqcqM987HjVi+cjwM4Iw H42wWq6m6wMy/Mp+KvKr3L6OV/WHOcsRsUUp6Y7L5kOSIfREgYHst7bLcHorRyJBuI6Q I0Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O/U5Rt6t; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id k2sm4837734wrg.4.2017.12.07.02.30.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:30:43 -0800 (PST) From: srinivas.kandagatla@linaro.org To: Mark Brown , Greg Kroah-Hartman , alsa-devel@alsa-project.org Cc: sdharia@codeaurora.org, Rob Herring , Mark Rutland , Jonathan Corbet , pombredanne@nexb.com, j.neuschaefer@gmx.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v9 08/13] regmap: add SLIMbus support Date: Thu, 7 Dec 2017 10:27:15 +0000 Message-Id: <20171207102720.21071-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> References: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Srinivas Kandagatla This patch adds support to read/write SLIMbus value elements. Currently it only supports byte read/write. Adding this support in regmap would give codec drivers more flexibility when there are more than 2 control interfaces like SLIMbus, i2c. Without this patch each codec driver has to directly call SLIMbus value element apis, and this could would get messy once we want to add i2c interface to it. Signed-off-by: Srinivas Kandagatla --- drivers/base/regmap/Kconfig | 4 ++ drivers/base/regmap/Makefile | 1 + drivers/base/regmap/regmap-slimbus.c | 80 ++++++++++++++++++++++++++++++++++++ include/linux/regmap.h | 18 ++++++++ 4 files changed, 103 insertions(+) create mode 100644 drivers/base/regmap/regmap-slimbus.c -- 2.15.0 diff --git a/drivers/base/regmap/Kconfig b/drivers/base/regmap/Kconfig index 3a1535d812d8..cc162b48c6d7 100644 --- a/drivers/base/regmap/Kconfig +++ b/drivers/base/regmap/Kconfig @@ -21,6 +21,10 @@ config REGMAP_I2C tristate depends on I2C +config REGMAP_SLIMBUS + tristate + depends on SLIMBUS + config REGMAP_SPI tristate depends on SPI diff --git a/drivers/base/regmap/Makefile b/drivers/base/regmap/Makefile index 0d298c446108..63dec9222892 100644 --- a/drivers/base/regmap/Makefile +++ b/drivers/base/regmap/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_REGCACHE_COMPRESSED) += regcache-lzo.o obj-$(CONFIG_DEBUG_FS) += regmap-debugfs.o obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o obj-$(CONFIG_REGMAP_I2C) += regmap-i2c.o +obj-$(CONFIG_REGMAP_SLIMBUS) += regmap-slimbus.o obj-$(CONFIG_REGMAP_SPI) += regmap-spi.o obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o diff --git a/drivers/base/regmap/regmap-slimbus.c b/drivers/base/regmap/regmap-slimbus.c new file mode 100644 index 000000000000..c90bee81d954 --- /dev/null +++ b/drivers/base/regmap/regmap-slimbus.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017, Linaro Ltd. + +#include +#include +#include + +#include "internal.h" + +static int regmap_slimbus_byte_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct slim_device *sdev = context; + int v; + + v = slim_readb(sdev, reg); + + if (v < 0) + return v; + + *val = v; + + return 0; +} + +static int regmap_slimbus_byte_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct slim_device *sdev = context; + + return slim_writeb(sdev, reg, val); +} + +static struct regmap_bus regmap_slimbus_bus = { + .reg_write = regmap_slimbus_byte_reg_write, + .reg_read = regmap_slimbus_byte_reg_read, + .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, + .val_format_endian_default = REGMAP_ENDIAN_LITTLE, +}; + +static const struct regmap_bus *regmap_get_slimbus(struct slim_device *slim, + const struct regmap_config *config) +{ + if (config->val_bits == 8 && config->reg_bits == 8) + return ®map_slimbus_bus; + + return ERR_PTR(-ENOTSUPP); +} + +struct regmap *__regmap_init_slimbus(struct slim_device *slimbus, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name) +{ + const struct regmap_bus *bus = regmap_get_slimbus(slimbus, config); + + if (IS_ERR(bus)) + return ERR_CAST(bus); + + return __regmap_init(&slimbus->dev, bus, &slimbus->dev, config, + lock_key, lock_name); +} +EXPORT_SYMBOL_GPL(__regmap_init_slimbus); + +struct regmap *__devm_regmap_init_slimbus(struct slim_device *slimbus, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name) +{ + const struct regmap_bus *bus = regmap_get_slimbus(slimbus, config); + + if (IS_ERR(bus)) + return ERR_CAST(bus); + + return __devm_regmap_init(&slimbus->dev, bus, &slimbus, config, + lock_key, lock_name); +} +EXPORT_SYMBOL_GPL(__devm_regmap_init_slimbus); + +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 15eddc1353ba..b2207737a159 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -24,6 +24,7 @@ struct module; struct device; struct i2c_client; struct irq_domain; +struct slim_device; struct spi_device; struct spmi_device; struct regmap; @@ -499,6 +500,10 @@ struct regmap *__regmap_init_i2c(struct i2c_client *i2c, const struct regmap_config *config, struct lock_class_key *lock_key, const char *lock_name); +struct regmap *__regmap_init_slimbus(struct slim_device *slimbus, + const struct regmap_config *config, + struct lock_class_key *lock_key, + const char *lock_name); struct regmap *__regmap_init_spi(struct spi_device *dev, const struct regmap_config *config, struct lock_class_key *lock_key, @@ -615,6 +620,19 @@ int regmap_attach_dev(struct device *dev, struct regmap *map, __regmap_lockdep_wrapper(__regmap_init_i2c, #config, \ i2c, config) +/** + * regmap_init_slimbus() - Initialise register map + * + * @slimbus: Device that will be interacted with + * @config: Configuration for register map + * + * The return value will be an ERR_PTR() on error or a valid pointer to + * a struct regmap. + */ +#define regmap_init_slimbus(slimbus, config) \ + __regmap_lockdep_wrapper(__regmap_init_slimbus, #config, \ + slimbus, config) + /** * regmap_init_spi() - Initialise register map * From patchwork Thu Dec 7 10:27:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 120956 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8180309qgn; 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id k2sm4837734wrg.4.2017.12.07.02.30.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:30:44 -0800 (PST) From: srinivas.kandagatla@linaro.org To: Mark Brown , Greg Kroah-Hartman , alsa-devel@alsa-project.org Cc: sdharia@codeaurora.org, Rob Herring , Mark Rutland , Jonathan Corbet , pombredanne@nexb.com, j.neuschaefer@gmx.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v9 09/13] slimbus: core: add common defines required for controllers Date: Thu, 7 Dec 2017 10:27:16 +0000 Message-Id: <20171207102720.21071-10-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> References: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Srinivas Kandagatla This patch adds some common constant defines which are required for qcom slim controller driver. Signed-off-by: Srinivas Kandagatla --- drivers/slimbus/slimbus.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) -- 2.15.0 diff --git a/drivers/slimbus/slimbus.h b/drivers/slimbus/slimbus.h index e002763e7f6e..4b71b6434549 100644 --- a/drivers/slimbus/slimbus.h +++ b/drivers/slimbus/slimbus.h @@ -9,9 +9,38 @@ #include #include +/* Standard values per SLIMbus spec needed by controllers and devices */ +#define SLIM_CL_PER_SUPERFRAME 6144 +#define SLIM_CL_PER_SUPERFRAME_DIV8 (SLIM_CL_PER_SUPERFRAME >> 3) + /* SLIMbus message types. Related to interpretation of message code. */ #define SLIM_MSG_MT_CORE 0x0 +/* + * SLIM Broadcast header format + * BYTE 0: MT[7:5] RL[4:0] + * BYTE 1: RSVD[7] MC[6:0] + * BYTE 2: RSVD[7:6] DT[5:4] PI[3:0] + */ +#define SLIM_MSG_MT_MASK GENMASK(2, 0) +#define SLIM_MSG_MT_SHIFT 5 +#define SLIM_MSG_RL_MASK GENMASK(4, 0) +#define SLIM_MSG_RL_SHIFT 0 +#define SLIM_MSG_MC_MASK GENMASK(6, 0) +#define SLIM_MSG_MC_SHIFT 0 +#define SLIM_MSG_DT_MASK GENMASK(1, 0) +#define SLIM_MSG_DT_SHIFT 4 + +#define SLIM_HEADER_GET_MT(b) ((b >> SLIM_MSG_MT_SHIFT) & SLIM_MSG_MT_MASK) +#define SLIM_HEADER_GET_RL(b) ((b >> SLIM_MSG_RL_SHIFT) & SLIM_MSG_RL_MASK) +#define SLIM_HEADER_GET_MC(b) ((b >> SLIM_MSG_MC_SHIFT) & SLIM_MSG_MC_MASK) +#define SLIM_HEADER_GET_DT(b) ((b >> SLIM_MSG_DT_SHIFT) & SLIM_MSG_DT_MASK) + +/* Device management messages used by this framework */ +#define SLIM_MSG_MC_REPORT_PRESENT 0x1 +#define SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS 0x2 +#define SLIM_MSG_MC_REPORT_ABSENT 0xF + /* Clock pause Reconfiguration messages */ #define SLIM_MSG_MC_BEGIN_RECONFIGURATION 0x40 #define SLIM_MSG_MC_NEXT_PAUSE_CLOCK 0x4A @@ -92,6 +121,10 @@ struct slim_msg_txn { #define DEFINE_SLIM_BCAST_TXN(name, mc, rl, la, msg) \ struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_BROADCAST, 0,\ 0, la, msg, } + +#define DEFINE_SLIM_EDEST_TXN(name, mc, rl, la, msg) \ + struct slim_msg_txn name = { rl, 0, mc, SLIM_MSG_DEST_ENUMADDR, 0,\ + 0, la, msg, } /** * enum slim_clk_state: SLIMbus controller's clock state used internally for * maintaining current clock state. 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[86.26.100.93]) by smtp.gmail.com with ESMTPSA id k2sm4837734wrg.4.2017.12.07.02.30.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Dec 2017 02:30:46 -0800 (PST) From: srinivas.kandagatla@linaro.org To: Mark Brown , Greg Kroah-Hartman , alsa-devel@alsa-project.org Cc: sdharia@codeaurora.org, Rob Herring , Mark Rutland , Jonathan Corbet , pombredanne@nexb.com, j.neuschaefer@gmx.net, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v9 11/13] slimbus: qcom: Add Qualcomm Slimbus controller driver Date: Thu, 7 Dec 2017 10:27:18 +0000 Message-Id: <20171207102720.21071-12-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> References: <20171207102720.21071-1-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sagar Dharia This controller driver programs manager, interface, and framer devices for Qualcomm's slimbus HW block. Manager component currently implements logical address setting, and messaging interface. Interface device reports bus synchronization information, and framer device clocks the bus from the time it's woken up, until clock-pause is executed by the manager device. Signed-off-by: Sagar Dharia Signed-off-by: Srinivas Kandagatla --- drivers/slimbus/Kconfig | 6 + drivers/slimbus/Makefile | 4 + drivers/slimbus/qcom-ctrl.c | 653 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 663 insertions(+) create mode 100644 drivers/slimbus/qcom-ctrl.c -- 2.15.0 diff --git a/drivers/slimbus/Kconfig b/drivers/slimbus/Kconfig index 9b6bb84d66ed..78bdd4808282 100644 --- a/drivers/slimbus/Kconfig +++ b/drivers/slimbus/Kconfig @@ -13,5 +13,11 @@ menuconfig SLIMBUS if SLIMBUS # SLIMbus controllers +config SLIM_QCOM_CTRL + tristate "Qualcomm SLIMbus Manager Component" + depends on SLIMBUS + help + Select driver if Qualcomm's SLIMbus Manager Component is + programmed using Linux kernel. endif diff --git a/drivers/slimbus/Makefile b/drivers/slimbus/Makefile index cd6833ed521a..a35a3da4eb78 100644 --- a/drivers/slimbus/Makefile +++ b/drivers/slimbus/Makefile @@ -4,3 +4,7 @@ # obj-$(CONFIG_SLIMBUS) += slimbus.o slimbus-y := core.o messaging.o sched.o + +#Controllers +obj-$(CONFIG_SLIM_QCOM_CTRL) += slim-qcom-ctrl.o +slim-qcom-ctrl-y := qcom-ctrl.o diff --git a/drivers/slimbus/qcom-ctrl.c b/drivers/slimbus/qcom-ctrl.c new file mode 100644 index 000000000000..36e828b703b4 --- /dev/null +++ b/drivers/slimbus/qcom-ctrl.c @@ -0,0 +1,653 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2011-2017, The Linux Foundation + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "slimbus.h" + +/* Manager registers */ +#define MGR_CFG 0x200 +#define MGR_STATUS 0x204 +#define MGR_INT_EN 0x210 +#define MGR_INT_STAT 0x214 +#define MGR_INT_CLR 0x218 +#define MGR_TX_MSG 0x230 +#define MGR_RX_MSG 0x270 +#define MGR_IE_STAT 0x2F0 +#define MGR_VE_STAT 0x300 +#define MGR_CFG_ENABLE 1 + +/* Framer registers */ +#define FRM_CFG 0x400 +#define FRM_STAT 0x404 +#define FRM_INT_EN 0x410 +#define FRM_INT_STAT 0x414 +#define FRM_INT_CLR 0x418 +#define FRM_WAKEUP 0x41C +#define FRM_CLKCTL_DONE 0x420 +#define FRM_IE_STAT 0x430 +#define FRM_VE_STAT 0x440 + +/* Interface registers */ +#define INTF_CFG 0x600 +#define INTF_STAT 0x604 +#define INTF_INT_EN 0x610 +#define INTF_INT_STAT 0x614 +#define INTF_INT_CLR 0x618 +#define INTF_IE_STAT 0x630 +#define INTF_VE_STAT 0x640 + +/* Interrupt status bits */ +#define MGR_INT_TX_NACKED_2 BIT(25) +#define MGR_INT_MSG_BUF_CONTE BIT(26) +#define MGR_INT_RX_MSG_RCVD BIT(30) +#define MGR_INT_TX_MSG_SENT BIT(31) + +/* Framer config register settings */ +#define FRM_ACTIVE 1 +#define CLK_GEAR 7 +#define ROOT_FREQ 11 +#define REF_CLK_GEAR 15 +#define INTR_WAKE 19 + +#define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \ + ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16)) + +#define SLIM_ROOT_FREQ 24576000 + +/* MAX message size over control channel */ +#define SLIM_MSGQ_BUF_LEN 40 +#define QCOM_TX_MSGS 2 +#define QCOM_RX_MSGS 8 +#define QCOM_BUF_ALLOC_RETRIES 10 + +#define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r)) + +/* V2 Component registers */ +#define CFG_PORT_V2(r) ((r ## _V2)) +#define COMP_CFG_V2 4 +#define COMP_TRUST_CFG_V2 0x3000 + +/* V1 Component registers */ +#define CFG_PORT_V1(r) ((r ## _V1)) +#define COMP_CFG_V1 0 +#define COMP_TRUST_CFG_V1 0x14 + +/* Resource group info for manager, and non-ported generic device-components */ +#define EE_MGR_RSC_GRP (1 << 10) +#define EE_NGD_2 (2 << 6) +#define EE_NGD_1 0 + +struct slim_ctrl_buf { + void *base; + phys_addr_t phy; + spinlock_t lock; + int head; + int tail; + int sl_sz; + int n; +}; + +struct qcom_slim_ctrl { + struct slim_controller ctrl; + struct slim_framer framer; + struct device *dev; + void __iomem *base; + void __iomem *slew_reg; + + struct slim_ctrl_buf rx; + struct slim_ctrl_buf tx; + + struct completion **wr_comp; + int irq; + struct workqueue_struct *rxwq; + struct work_struct wd; + struct clk *rclk; + struct clk *hclk; +}; + +static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf, + u8 len, u32 tx_reg) +{ + int count = (len + 3) >> 2; + + __iowrite32_copy(ctrl->base + tx_reg, buf, count); + + /* Ensure Oder of subsequent writes */ + mb(); +} + +static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl) +{ + unsigned long flags; + int idx; + + spin_lock_irqsave(&ctrl->rx.lock, flags); + if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) { + spin_unlock_irqrestore(&ctrl->rx.lock, flags); + dev_err(ctrl->dev, "RX QUEUE full!"); + return NULL; + } + idx = ctrl->rx.tail; + ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n; + spin_unlock_irqrestore(&ctrl->rx.lock, flags); + + return ctrl->rx.base + (idx * ctrl->rx.sl_sz); +} + +void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err) +{ + struct completion *comp; + unsigned long flags; + int idx; + + spin_lock_irqsave(&ctrl->tx.lock, flags); + idx = ctrl->tx.head; + ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n; + spin_unlock_irqrestore(&ctrl->tx.lock, flags); + + comp = ctrl->wr_comp[idx]; + ctrl->wr_comp[idx] = NULL; + + complete(comp); +} + +static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl, + u32 stat) +{ + int err = 0; + + if (stat & MGR_INT_TX_MSG_SENT) + writel_relaxed(MGR_INT_TX_MSG_SENT, + ctrl->base + MGR_INT_CLR); + + if (stat & MGR_INT_TX_NACKED_2) { + u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS); + u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT); + u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT); + u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG); + u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT); + u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT); + u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT); + u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT); + u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT); + + writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR); + + dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n", + stat, mgr_stat); + dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat); + dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n", + frm_intr_stat, frm_stat); + dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n", + frm_cfg, frm_ie_stat); + dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n", + intf_intr_stat, intf_stat); + dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n", + intf_ie_stat); + err = -ENOTCONN; + } + + slim_ack_txn(ctrl, err); + + return IRQ_HANDLED; +} + +static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl, + u32 stat) +{ + u32 *rx_buf, pkt[10]; + bool q_rx = false; + u8 mc, mt, len; + + pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG); + mt = SLIM_HEADER_GET_MT(pkt[0]); + len = SLIM_HEADER_GET_RL(pkt[0]); + mc = SLIM_HEADER_GET_MC(pkt[0]>>8); + + /* + * this message cannot be handled by ISR, so + * let work-queue handle it + */ + if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) { + rx_buf = (u32 *)slim_alloc_rxbuf(ctrl); + if (!rx_buf) { + dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n", + pkt[0]); + goto rx_ret_irq; + } + rx_buf[0] = pkt[0]; + + } else { + rx_buf = pkt; + } + + __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4, + DIV_ROUND_UP(len, 4)); + + switch (mc) { + + case SLIM_MSG_MC_REPORT_PRESENT: + q_rx = true; + break; + case SLIM_MSG_MC_REPLY_INFORMATION: + case SLIM_MSG_MC_REPLY_VALUE: + slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1), + (u8)(*rx_buf >> 24), (len - 4)); + break; + default: + dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n", + mc, mt); + break; + } +rx_ret_irq: + writel(MGR_INT_RX_MSG_RCVD, ctrl->base + + MGR_INT_CLR); + if (q_rx) + queue_work(ctrl->rxwq, &ctrl->wd); + + return IRQ_HANDLED; +} + +static irqreturn_t qcom_slim_interrupt(int irq, void *d) +{ + struct qcom_slim_ctrl *ctrl = d; + u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT); + int ret = IRQ_NONE; + + if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2) + ret = qcom_slim_handle_tx_irq(ctrl, stat); + + if (stat & MGR_INT_RX_MSG_RCVD) + ret = qcom_slim_handle_rx_irq(ctrl, stat); + + return ret; +} + +void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl, struct slim_msg_txn *txn, + struct completion *done) +{ + unsigned long flags; + int idx; + + spin_lock_irqsave(&ctrl->tx.lock, flags); + if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) { + spin_unlock_irqrestore(&ctrl->tx.lock, flags); + dev_err(ctrl->dev, "controller TX buf unavailable"); + return NULL; + } + idx = ctrl->tx.tail; + ctrl->wr_comp[idx] = done; + ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n; + + spin_unlock_irqrestore(&ctrl->tx.lock, flags); + + return ctrl->tx.base + (idx * ctrl->tx.sl_sz); +} + + +static int qcom_xfer_msg(struct slim_controller *sctrl, + struct slim_msg_txn *txn) +{ + struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); + DECLARE_COMPLETION_ONSTACK(done); + void *pbuf = slim_alloc_txbuf(ctrl, txn, &done); + unsigned long ms = txn->rl + HZ; + u8 *puc; + int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES; + u8 la = txn->la; + u32 *head; + /* HW expects length field to be excluded */ + txn->rl--; + + /* spin till buffer is made available */ + if (!pbuf) { + while (retries--) { + usleep_range(10000, 15000); + pbuf = slim_alloc_txbuf(ctrl, txn, &done); + if (pbuf) + break; + } + } + + if (!retries && !pbuf) + return -ENOMEM; + + puc = (u8 *)pbuf; + head = (u32 *)pbuf; + + if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) { + *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, + txn->mc, 0, la); + puc += 3; + } else { + *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt, + txn->mc, 1, la); + puc += 2; + } + + if (slim_tid_txn(txn->mt, txn->mc)) + *(puc++) = txn->tid; + + if (slim_ec_txn(txn->mt, txn->mc)) { + *(puc++) = (txn->ec & 0xFF); + *(puc++) = (txn->ec >> 8) & 0xFF; + } + + if (txn->msg && txn->msg->wbuf) + memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes); + + qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG); + timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms)); + + if (!timeout) { + dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc, + txn->mt); + ret = -ETIMEDOUT; + } + + return ret; + +} + +static int qcom_set_laddr(struct slim_controller *sctrl, + struct slim_eaddr *ead, u8 laddr) +{ + struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev); + struct { + __be16 manf_id; + __be16 prod_code; + u8 dev_index; + u8 instance; + u8 laddr; + } __packed p; + struct slim_val_inf msg = {0}; + DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS, + 10, laddr, &msg); + int ret; + + p.manf_id = cpu_to_be16(ead->manf_id); + p.prod_code = cpu_to_be16(ead->prod_code); + p.dev_index = ead->dev_index; + p.instance = ead->instance; + p.laddr = laddr; + + msg.wbuf = (void *)&p; + msg.num_bytes = 7; + ret = slim_do_transfer(&ctrl->ctrl, &txn); + + if (ret) + dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n", + laddr, ret); + return ret; +} + +static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf) +{ + unsigned long flags; + + spin_lock_irqsave(&ctrl->rx.lock, flags); + if (ctrl->rx.tail == ctrl->rx.head) { + spin_unlock_irqrestore(&ctrl->rx.lock, flags); + return -ENODATA; + } + memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz), + ctrl->rx.sl_sz); + + ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n; + spin_unlock_irqrestore(&ctrl->rx.lock, flags); + + return 0; +} + +static void qcom_slim_rxwq(struct work_struct *work) +{ + u8 buf[SLIM_MSGQ_BUF_LEN]; + u8 mc, mt, len; + int ret; + struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl, + wd); + + while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) { + len = SLIM_HEADER_GET_RL(buf[0]); + mt = SLIM_HEADER_GET_MT(buf[0]); + mc = SLIM_HEADER_GET_MC(buf[1]); + if (mt == SLIM_MSG_MT_CORE && + mc == SLIM_MSG_MC_REPORT_PRESENT) { + struct slim_eaddr ea; + u8 laddr; + + ea.manf_id = be16_to_cpup((__be16 *)&buf[2]); + ea.prod_code = be16_to_cpup((__be16 *)&buf[4]); + ea.dev_index = buf[6]; + ea.instance = buf[7]; + + ret = slim_device_report_present(&ctrl->ctrl, &ea, + &laddr); + if (ret < 0) + dev_err(ctrl->dev, "assign laddr failed:%d\n", + ret); + } else { + dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n", + mc, mt); + } + } +} + +static void qcom_slim_prg_slew(struct platform_device *pdev, + struct qcom_slim_ctrl *ctrl) +{ + struct resource *slew_mem; + + if (!ctrl->slew_reg) { + /* SLEW RATE register for this SLIMbus */ + slew_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "slew"); + ctrl->slew_reg = devm_ioremap(&pdev->dev, slew_mem->start, + resource_size(slew_mem)); + if (!ctrl->slew_reg) + return; + } + + writel_relaxed(1, ctrl->slew_reg); + /* Make sure SLIMbus-slew rate enabling goes through */ + wmb(); +} + +static int qcom_slim_probe(struct platform_device *pdev) +{ + struct qcom_slim_ctrl *ctrl; + struct slim_controller *sctrl; + struct resource *slim_mem; + int ret, ver; + + ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return -ENOMEM; + + ctrl->hclk = devm_clk_get(&pdev->dev, "iface"); + if (IS_ERR(ctrl->hclk)) + return PTR_ERR(ctrl->hclk); + + ctrl->rclk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(ctrl->rclk)) + return PTR_ERR(ctrl->rclk); + + ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ); + if (ret) { + dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret); + return ret; + } + + ctrl->irq = platform_get_irq(pdev, 0); + if (!ctrl->irq) { + dev_err(&pdev->dev, "no slimbus IRQ\n"); + return -ENODEV; + } + + sctrl = &ctrl->ctrl; + sctrl->dev = &pdev->dev; + ctrl->dev = &pdev->dev; + platform_set_drvdata(pdev, ctrl); + dev_set_drvdata(ctrl->dev, ctrl); + + slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); + ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem); + if (!ctrl->base) { + dev_err(&pdev->dev, "IOremap failed\n"); + return -ENOMEM; + } + + sctrl->set_laddr = qcom_set_laddr; + sctrl->xfer_msg = qcom_xfer_msg; + ctrl->tx.n = QCOM_TX_MSGS; + ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN; + ctrl->rx.n = QCOM_RX_MSGS; + ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN; + ctrl->wr_comp = kzalloc(sizeof(struct completion *) * QCOM_TX_MSGS, + GFP_KERNEL); + if (!ctrl->wr_comp) + return -ENOMEM; + + spin_lock_init(&ctrl->rx.lock); + spin_lock_init(&ctrl->tx.lock); + INIT_WORK(&ctrl->wd, qcom_slim_rxwq); + ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx"); + if (!ctrl->rxwq) { + dev_err(ctrl->dev, "Failed to start Rx WQ\n"); + return -ENOMEM; + } + + ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8; + ctrl->framer.superfreq = + ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8; + sctrl->a_framer = &ctrl->framer; + sctrl->clkgear = SLIM_MAX_CLK_GEAR; + + qcom_slim_prg_slew(pdev, ctrl); + + ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt, + IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl); + if (ret) { + dev_err(&pdev->dev, "request IRQ failed\n"); + goto err_request_irq_failed; + } + + ret = clk_prepare_enable(ctrl->hclk); + if (ret) + goto err_hclk_enable_failed; + + ret = clk_prepare_enable(ctrl->rclk); + if (ret) + goto err_rclk_enable_failed; + + ctrl->tx.base = dmam_alloc_coherent(&pdev->dev, + (ctrl->tx.sl_sz * ctrl->tx.n), + &ctrl->tx.phy, GFP_KERNEL); + if (!ctrl->tx.base) { + ret = -ENOMEM; + goto err; + } + + ctrl->rx.base = dmam_alloc_coherent(&pdev->dev, + (ctrl->rx.sl_sz * ctrl->rx.n), + &ctrl->rx.phy, GFP_KERNEL); + if (!ctrl->rx.base) { + ret = -ENOMEM; + goto err; + } + + /* Register with framework before enabling frame, clock */ + ret = slim_register_controller(&ctrl->ctrl); + if (ret) { + dev_err(ctrl->dev, "error adding controller\n"); + goto err; + } + + ver = readl_relaxed(ctrl->base); + /* Version info in 16 MSbits */ + ver >>= 16; + /* Component register initialization */ + writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); + writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1), + ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver)); + + writel((MGR_INT_TX_NACKED_2 | + MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD | + MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN); + writel(1, ctrl->base + MGR_CFG); + /* Framer register initialization */ + writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) | + (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1, + ctrl->base + FRM_CFG); + writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG); + writel(1, ctrl->base + INTF_CFG); + writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver)); + + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND); + pm_runtime_set_active(&pdev->dev); + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver); + return 0; + +err: + clk_disable_unprepare(ctrl->rclk); +err_rclk_enable_failed: + clk_disable_unprepare(ctrl->hclk); +err_hclk_enable_failed: +err_request_irq_failed: + destroy_workqueue(ctrl->rxwq); + return ret; +} + +static int qcom_slim_remove(struct platform_device *pdev) +{ + struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev); + + disable_irq(ctrl->irq); + clk_disable_unprepare(ctrl->hclk); + clk_disable_unprepare(ctrl->rclk); + slim_unregister_controller(&ctrl->ctrl); + destroy_workqueue(ctrl->rxwq); + return 0; +} + +static const struct dev_pm_ops qcom_slim_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume) + SET_RUNTIME_PM_OPS( + qcom_slim_runtime_suspend, + qcom_slim_runtime_resume, + NULL + ) +}; + +static const struct of_device_id qcom_slim_dt_match[] = { + { .compatible = "qcom,slim", }, + { .compatible = "qcom,apq8064-slim", }, + {} +}; + +static struct platform_driver qcom_slim_driver = { + .probe = qcom_slim_probe, + .remove = qcom_slim_remove, + .driver = { + .name = "qcom_slim_ctrl", + .of_match_table = qcom_slim_dt_match, + }, +}; +module_platform_driver(qcom_slim_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");