From patchwork Thu Dec 7 18:14:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121046 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688687qgn; Thu, 7 Dec 2017 10:15:00 -0800 (PST) X-Google-Smtp-Source: AGs4zMZmrLrNPBFx/jljUyb4RfVNCdB1p9sNT3z2gRbuzTyURNA/PllQunjDBCtArEBZ8oJTDGJg X-Received: by 10.99.165.75 with SMTP id r11mr26415649pgu.331.1512670500537; Thu, 07 Dec 2017 10:15:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670500; cv=none; d=google.com; s=arc-20160816; b=OUuZduEN0vxGrckqv9Bf6SRgCSzVE1bu1pkHf/34LMFnvfkRQ8ItVAhbos0qQvUlwL dWiZnA2v5p1R5RHWvZBnJPodd94M/EsqpDehP44ZzNgFYYUwSe4x0Pk8LIVjvrP9tCor V1Di+mgux0s9iqssvXH7+XKYunCW//HJik1pMYtN4jlIWMIl2r5VukkIOmiypNGgt4Ov J+U2PTfmeHBISlhcuPJmmIWDtAmTGwLNb+Z4axokmrLQafkt/YHF2vhCAgG6RBGfeDOg 5FN97OG0THUAtqe2jfc9DwzT3H2MhWiercZC2Ic8N028mO8BNNyQHwlI/uRpwHUHh3ty du6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=MrnPMjcCFVbIPfwGsqGrqBOkH4LEvn4+mJn/CWsa2MI=; b=n8v+XPg/EmTRFrGUefhsv8DeSI9zCK+4GjPOR6n+tJtmZbY4zdodQWwRmJppW0nSaH hN7OnU3pUGuupyjzUFIlpCZ7/HsSDLZjyWIHvmmIMw1llHlIsJ1UF4CDEQ4eWyc8etOS UpP7af+Y4q1XVSZmmWC5ET60txkl1Iqoyi3VBrFBU/+3QYdPENW2LBzZCjig4Ehxu+bD rNca+ZeCOSub2v8hygSivvQ+pStXM7C2uLUKlBe42Bg6asjSjb6/Bk9oOKMq5X9+VLQ8 CoVR8XHljVnDDT0BJyWVOoWEHcVXSonnrQCFJAzNx1cE4s0Rb6ZgkBzf7EuL1jHWjovF 3TOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id y188si4008733pgb.829.2017.12.07.10.14.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:15:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hD-00081H-4c; Thu, 07 Dec 2017 18:14:55 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 1/6] hw/arm/virt: Check that the CPU realize method succeeded Date: Thu, 7 Dec 2017 18:14:48 +0000 Message-Id: <1512670493-18114-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> We were passing a NULL error pointer to the object_property_set_bool() call that realizes the CPU object. This meant that we wouldn't detect failure, and would plough blindly on to crash later trying to use a NULL CPU object pointer. Detect errors and fail instead. In particular, this will be necessary to detect the user error of using "-cpu host" without "-enable-kvm" once we make the host CPU type be registered unconditionally rather than only in kvm_arch_init(). Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Eduardo Habkost Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 151592b..62af013 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1402,7 +1402,7 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } - object_property_set_bool(cpuobj, true, "realized", NULL); + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } fdt_add_timer_nodes(vms); From patchwork Thu Dec 7 18:14:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121043 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688619qgn; Thu, 7 Dec 2017 10:14:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMb9W2CmhGQV1jz7LunA7bUSruL6ybN6+7zbTPAcIDJtMZSHA9ugt/cs8x2JNmuM8FiRxPRq X-Received: by 10.46.91.75 with SMTP id p72mr15642933ljb.95.1512670497340; Thu, 07 Dec 2017 10:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670497; cv=none; d=google.com; s=arc-20160816; b=yoizwpgRGR2BI2P1y6gPT1n4VIFRaoG1sJiDdTtQ37YB81R4pD05r13AXVGU0kKVPG 813Dg9DBWU4n69cDP8cwYJG/64KlQZ58u4jxkXthg2rzDJwdyB70+QQX+Nsyco5foJZJ lcq0lPFrXb2HwZz+daK6pc0pvjIK2osnlvHAlngXqapSzGQchutGf21sKIQ/XZDPYnAv ImzCTWNDsg2+Xh4p3VjWrJgJnBd82mDTY7EUDw2vMIcyTO3Uo05WdcFP+nxU99boCEEU J4ef2TGmBhrwUpFO2ZKc0tO/KJ/xXP1m7/1pbjUxPrRp6j8/R98PD1kfHqJcEblF3dhG hPdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=95CtNHaTIvqmexIEVk5uhKlOG1juOy3Tks+4VC4ZhII=; b=l4cpiY1HtScuiegUqIv/OVOfuAs/X0eXA9ZhhByt6evGmiCxlTZD+WD9T+cUN26hdB 1vlgtFvfkjrxcMpzcpq7rqWXnIVfsWBiJMgNj1YctnQyPI9oVdywbchcLPO/NIPyV2yz x0xzhAVCUgNcn/Y2CQYh3ApngmKiVrbqkzlV4tGv+fyPAYVeEgn2cjaboNtZg4F9QEdr 9sACYfcgaXCv56B+NG8gBTt2A55E5LL0SKaT5gD1Kt0trVf12wt/jxT/Ls2c+JLbgUu1 gO9zkGXAeN+905ej/cmZ4zkKHNb/ESnesDeVIwUBIkDFfCiCH4R3j2AasQl6pc4SV6+n LFEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id f17si2417065ljb.73.2017.12.07.10.14.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hD-00081U-Qz; Thu, 07 Dec 2017 18:14:55 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 2/6] target/arm: Query host CPU features on-demand at instance init Date: Thu, 7 Dec 2017 18:14:49 +0000 Message-Id: <1512670493-18114-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Currently we query the host CPU features in the class init function for the TYPE_ARM_HOST_CPU class, so that we can later copy them from the class object into the instance object in the object instance init function. This is awkward for implementing "-cpu max", which should work like "-cpu host" for KVM but like "cpu with all implemented features" for TCG. Move the place where we store the information about the host CPU from a class object to static variables in kvm.c, and then in the instance init function call a new kvm_arm_set_cpu_features_from_host() function which will query the host kernel if necessary and then fill in the CPU instance fields. This allows us to drop the special class struct and class init function for TYPE_ARM_HOST_CPU entirely. We can't delay the probe until realize, because the ARM instance_post_init hook needs to look at the feature bits we set, so we need to do it in the initfn. This is safe because the probing doesn't affect the actual VM state (it creates a separate scratch VM to do its testing), but the probe might fail. Because we can't report errors in retrieving the host features in the initfn, we check this belatedly in the realize function (the intervening code will be able to cope with the relevant fields in the CPU structure being zero). Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ target/arm/kvm_arm.h | 35 ++++++++++++++++++++++++----------- target/arm/cpu.c | 13 +++++++++++++ target/arm/kvm.c | 36 +++++++++++++++++++----------------- target/arm/kvm32.c | 8 ++++---- target/arm/kvm64.c | 8 ++++---- 6 files changed, 69 insertions(+), 36 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cd..5b01cf9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -690,6 +690,11 @@ struct ARMCPU { /* Uniprocessor system with MP extensions */ bool mp_is_up; + /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init + * and the probe failed (so we need to report the error in realize) + */ + bool host_cpu_probe_failed; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ff53e9f..89d1b67 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -152,20 +152,16 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU -#define ARM_HOST_CPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(ARMHostCPUClass, (klass), TYPE_ARM_HOST_CPU) -#define ARM_HOST_CPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(ARMHostCPUClass, (obj), TYPE_ARM_HOST_CPU) - -typedef struct ARMHostCPUClass { - /*< private >*/ - ARMCPUClass parent_class; - /*< public >*/ +/** + * ARMHostCPUFeatures: information about the host CPU (identified + * by asking the host kernel) + */ +typedef struct ARMHostCPUFeatures { uint64_t features; uint32_t target; const char *dtb_compatible; -} ARMHostCPUClass; +} ARMHostCPUFeatures; /** * kvm_arm_get_host_cpu_features: @@ -174,8 +170,16 @@ typedef struct ARMHostCPUClass { * Probe the capabilities of the host kernel's preferred CPU and fill * in the ARMHostCPUClass struct accordingly. */ -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc); +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); +/** + * kvm_arm_set_cpu_features_from_host: + * @cpu: ARMCPU to set the features for + * + * Set up the ARMCPU struct fields up to match the information probed + * from the host CPU. + */ +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); /** * kvm_arm_sync_mpstate_to_kvm @@ -200,6 +204,15 @@ void kvm_arm_pmu_init(CPUState *cs); #else +static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + /* This should never actually be called in the "not KVM" case, + * but set up the fields to indicate an error anyway. + */ + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + cpu->host_cpu_probe_failed = true; +} + static inline int kvm_arm_vgic_probe(void) { return 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7f7a3d1..a7deb10 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -709,6 +709,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) AddressSpace *as; #endif + /* If we needed to query the host kernel for the CPU features + * then it's possible that might have failed in the initfn, but + * this is the first point where we can report it. + */ + if (cpu->host_cpu_probe_failed) { + if (!kvm_enabled()) { + error_setg(errp, "The 'host' CPU type can only be used with KVM"); + } else { + error_setg(errp, "Failed to retrieve host CPU features"); + } + return; + } + cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 211a7bf..945696c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -33,6 +33,8 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static bool cap_has_mp_state; +static ARMHostCPUFeatures arm_host_cpu_features; + int kvm_arm_vcpu_init(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); @@ -129,30 +131,32 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } -static void kvm_arm_host_cpu_class_init(ObjectClass *oc, void *data) +void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { - ARMHostCPUClass *ahcc = ARM_HOST_CPU_CLASS(oc); + CPUARMState *env = &cpu->env; - /* All we really need to set up for the 'host' CPU - * is the feature bits -- we rely on the fact that the - * various ID register values in ARMCPU are only used for - * TCG CPUs. - */ - if (!kvm_arm_get_host_cpu_features(ahcc)) { - fprintf(stderr, "Failed to retrieve host CPU features!\n"); - abort(); + if (!arm_host_cpu_features.dtb_compatible) { + if (!kvm_enabled() || + !kvm_arm_get_host_cpu_features(&arm_host_cpu_features)) { + /* We can't report this error yet, so flag that we need to + * in arm_cpu_realizefn(). + */ + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + cpu->host_cpu_probe_failed = true; + return; + } } + + cpu->kvm_target = arm_host_cpu_features.target; + cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; + env->features = arm_host_cpu_features.features; } static void kvm_arm_host_cpu_initfn(Object *obj) { - ARMHostCPUClass *ahcc = ARM_HOST_CPU_GET_CLASS(obj); ARMCPU *cpu = ARM_CPU(obj); - CPUARMState *env = &cpu->env; - cpu->kvm_target = ahcc->target; - cpu->dtb_compatible = ahcc->dtb_compatible; - env->features = ahcc->features; + kvm_arm_set_cpu_features_from_host(cpu); } static const TypeInfo host_arm_cpu_type_info = { @@ -163,8 +167,6 @@ static const TypeInfo host_arm_cpu_type_info = { .parent = TYPE_ARM_CPU, #endif .instance_init = kvm_arm_host_cpu_initfn, - .class_init = kvm_arm_host_cpu_class_init, - .class_size = sizeof(ARMHostCPUClass), }; int kvm_arch_init(MachineState *ms, KVMState *s) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f925a21..cc326ea 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -28,7 +28,7 @@ static inline void set_feature(uint64_t *features, int feature) *features |= 1ULL << feature; } -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -74,13 +74,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return false; } - ahcc->target = init.target; + ahcf->target = init.target; /* This is not strictly blessed by the device tree binding docs yet, * but in practice the kernel does not care about this string so * there is no point maintaining an KVM_ARM_TARGET_* -> string table. */ - ahcc->dtb_compatible = "arm,arm-v7"; + ahcf->dtb_compatible = "arm,arm-v7"; for (i = 0; i < ARRAY_SIZE(idregs); i++) { ret = ioctl(fdarray[2], KVM_GET_ONE_REG, &idregs[i]); @@ -132,7 +132,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) set_feature(&features, ARM_FEATURE_VFP4); } - ahcc->features = features; + ahcf->features = features; return true; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6554c30..8f8f828 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -443,7 +443,7 @@ static inline void unset_feature(uint64_t *features, int feature) *features &= ~(1ULL << feature); } -bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) +bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { /* Identify the feature bits corresponding to the host CPU, and * fill out the ARMHostCPUClass fields accordingly. To do this @@ -471,8 +471,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) return false; } - ahcc->target = init.target; - ahcc->dtb_compatible = "arm,arm-v8"; + ahcf->target = init.target; + ahcf->dtb_compatible = "arm,arm-v8"; kvm_arm_destroy_scratch_host_vcpu(fdarray); @@ -486,7 +486,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); - ahcc->features = features; + ahcf->features = features; return true; } From patchwork Thu Dec 7 18:14:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121041 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688614qgn; Thu, 7 Dec 2017 10:14:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMaynoLzp+9aNgCdM9IMuL4UkrVNEkKrAUmMUjqdeu8ymRRe83F+YuW8YPfNncCNyK/EPKQY X-Received: by 10.28.214.145 with SMTP id n139mr2054044wmg.59.1512670497100; Thu, 07 Dec 2017 10:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670497; cv=none; d=google.com; s=arc-20160816; b=Q95B7SyZy8ydsyBKQ5p7Sm/CurnbbKcFV8mAS0z4csTLO3tvBOKm78ujV4IdV9o3lp 9uhHHTJAznxF1K/ZWAff+JB4zQOwL6z/DaFu7+C7Y+uwdAsLq+v5aD/wjEvmLwNvu/P1 AhhB6xbF3EEj+ToxpFQ4tqUQcMciqNTJ/w/d7rpXIsDIEl1kljc8nEbs0U4vUEm7K+RO YHWK5rFvnteWnSuAczl6KuGBuMLGRmQ3ELv82RbGkaqnNK3LBfRaG/Bx3mRUAqUjc5+n TBPqiSXGBx2wyq8rlpLsVCk0JdaY7EwmzxcsmiaINIrwacrek5lCQWmm5Wfub8A9sz1J H/oQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=gdamzciN9oYeOnQEXtDEInhoS4qKKlsZvZNP31PgOHQ=; b=TQJHcjDzoHZBO9zXiJKHS+slvmIWm/sty47kOdQc3K/mBaaViIBybVMgSHEM7QuOuk 3/p0IW3AuV+gSu6vRGdI5gI8/+62R6NwaPrHKV5PUCVQjrOqrAEaA4pQ63xGoKCF7cAx Mj848i+730x3niNafeoxdlAY17qxcumUXROLTx5wDK02ImiCbxTBGmjurhZLuvri+1+l qs4mbwmG8AsgGgrzo3spg3Rs2YwVYbA3j1Vf2VqzT/XLKwPW4PbIwXkw3lq9O4aWRwuD 1BiYQPIV5fr8MVnkcpdJu/PGz7YTxcRiTkQWKzZoKH5szHoKGvd+v9StB48tmfxWahAt 7ZdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 103si4255711wrc.215.2017.12.07.10.14.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hE-00081p-Ew; Thu, 07 Dec 2017 18:14:56 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 3/6] target/arm: Move definition of 'host' cpu type into cpu.c Date: Thu, 7 Dec 2017 18:14:50 +0000 Message-Id: <1512670493-18114-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Move the definition of the 'host' cpu type into cpu.c, where all the other CPU types are defined. We can do this now we've decoupled it from the KVM-specific host feature probing. This means we now create the type unconditionally (assuming we were built with KVM support at all), but if you try to use it without -enable-kvm this will end up in the "host cpu probe failed and KVM not enabled" path in arm_cpu_realizefn(), for an appropriate error message. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/kvm.c | 19 ------------------- 2 files changed, 24 insertions(+), 19 deletions(-) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a7deb10..9304277 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1785,6 +1785,26 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) #endif } +#ifdef CONFIG_KVM +static void arm_host_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + kvm_arm_set_cpu_features_from_host(cpu); +} + +static const TypeInfo host_arm_cpu_type_info = { + .name = TYPE_ARM_HOST_CPU, +#ifdef TARGET_AARCH64 + .parent = TYPE_AARCH64_CPU, +#else + .parent = TYPE_ARM_CPU, +#endif + .instance_init = arm_host_initfn, +}; + +#endif + static void cpu_register(const ARMCPUInfo *info) { TypeInfo type_info = { @@ -1822,6 +1842,10 @@ static void arm_cpu_register_types(void) cpu_register(info); info++; } + +#ifdef CONFIG_KVM + type_register_static(&host_arm_cpu_type_info); +#endif } type_init(arm_cpu_register_types) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 945696c..6bdc027 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -152,23 +152,6 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) env->features = arm_host_cpu_features.features; } -static void kvm_arm_host_cpu_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - kvm_arm_set_cpu_features_from_host(cpu); -} - -static const TypeInfo host_arm_cpu_type_info = { - .name = TYPE_ARM_HOST_CPU, -#ifdef TARGET_AARCH64 - .parent = TYPE_AARCH64_CPU, -#else - .parent = TYPE_ARM_CPU, -#endif - .instance_init = kvm_arm_host_cpu_initfn, -}; - int kvm_arch_init(MachineState *ms, KVMState *s) { /* For ARM interrupt delivery is always asynchronous, @@ -184,8 +167,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE); - type_register_static(&host_arm_cpu_type_info); - return 0; } From patchwork Thu Dec 7 18:14:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121042 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688625qgn; Thu, 7 Dec 2017 10:14:57 -0800 (PST) X-Google-Smtp-Source: AGs4zMYdDHumRWETl4N8jGk3zOZJ7jaP9rJ/ScI6GdN6zPtNsdR9GOgnP5Hb8lmW47VybI8Lgsj2 X-Received: by 10.28.150.20 with SMTP id y20mr1802371wmd.118.1512670497707; Thu, 07 Dec 2017 10:14:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670497; cv=none; d=google.com; s=arc-20160816; b=FepojQjaDjroo0XjfPJyhAim5P01C4h+yaVZGTA1Sq4kw0wh4e0vD9vorIGrYWPu1G hgfFl3Td2QsRKA316amBuenMIiDuPyI+jxEgL4/yJsb0z8u6REABID0DngdyRrXVYXTD tJ/w3v0xffayASGJITAwXajXFOeSgfe9O9X8+0toC0qcHk+Besjf9DoIjkjjP4VB8Xxl CnY1lNoPYB4Dfn+1srz7KjAc/LS1XeEInraXcOsbjv2c819XXlQjBS0yKn51ah4lfr/+ zUUU8HuLfqBJqilGD1V9i53S1DuI90JtC7lSJ6FXXfJKbWJOyrGnDEb471GR7n+qI6TH nnMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=AycHsIRaG0/Tbl3bGwvTv1KREHsLLnG8IgJjSRf9kao=; b=CDoPRdP4i73834nJIm5uwxW/5vxWWVXBaCgt2wmewZYG3vS6hDEbI5yOnBTNfb84h6 /ZALYqxGlhUtxwBzx4D4dd4MptbEBMwOHgrdIYN1FoJNiS3AfiEBHD6W6IvgeafNWY2H J7nbe4sSkWU+jP9XynYv5CzwfO+vVMuCVwriJeCP5bjCPPq/FEXhWf/QoDx1KFvHKOdN ZyOWTXF8MF2T/j68dVsq/CdpNLZdjld5UfIYyiHHNUVhSk9tU4tnXjf9L7LANhDiur4X qxEE39j3vYydnFWtAdB+ScgDjg/U2StQxfA/c3FGpFyQac2AhV0VbGzubdKS9XviL9wp sJXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l25si4322848wra.368.2017.12.07.10.14.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hF-000825-4U; Thu, 07 Dec 2017 18:14:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 4/6] target/arm: Add "-cpu max" support Date: Thu, 7 Dec 2017 18:14:51 +0000 Message-Id: <1512670493-18114-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Add support for "-cpu max" for ARM guests. This CPU type behaves like "-cpu host" when KVM is enabled, and like a system CPU with the maximum possible feature set otherwise. (Note that this means it won't be migratable across versions, as we will likely add features to it in future.) Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 2 ++ target/arm/cpu.c | 24 ++++++++++++++++++++++++ target/arm/cpu64.c | 21 +++++++++++++++++++++ 3 files changed, 47 insertions(+) -- 2.7.4 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a42495b..d135ff8 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,6 +33,8 @@ struct arm_boot_info; #define ARM_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU) +#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU + /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9304277..190da97 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1628,6 +1628,27 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } +#ifndef TARGET_AARCH64 +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; + * this only needs to handle 32 bits. + */ +static void arm_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + cortex_a15_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A15 doesn't implement them. + */ + } +} +#endif + #ifdef CONFIG_USER_ONLY static void arm_any_initfn(Object *obj) { @@ -1691,6 +1712,9 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, +#ifndef TARGET_AARCH64 + { .name = "max", .initfn = arm_max_initfn }, +#endif #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = arm_any_initfn }, #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07a..38dcf32 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -28,6 +28,7 @@ #include "hw/arm/arm.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "kvm_arm.h" static inline void set_feature(CPUARMState *env, int feature) { @@ -212,6 +213,25 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } +/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); + * otherwise, a CPU with as many features enabled as our emulation supports. + * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; + * this only needs to handle 64 bits. + */ +static void aarch64_max_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + kvm_arm_set_cpu_features_from_host(cpu); + } else { + aarch64_a57_initfn(obj); + /* In future we might add feature bits here even if the + * real-world A57 doesn't implement them. + */ + } +} + #ifdef CONFIG_USER_ONLY static void aarch64_any_initfn(Object *obj) { @@ -240,6 +260,7 @@ typedef struct ARMCPUInfo { static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, + { .name = "max", .initfn = aarch64_max_initfn }, #ifdef CONFIG_USER_ONLY { .name = "any", .initfn = aarch64_any_initfn }, #endif From patchwork Thu Dec 7 18:14:52 2017 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id u7si4391268wru.419.2017.12.07.10.14.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hF-00082d-RZ; Thu, 07 Dec 2017 18:14:57 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 5/6] hw/arm/virt: Add "max" to the list of CPU types "virt" supports Date: Thu, 7 Dec 2017 18:14:52 +0000 Message-Id: <1512670493-18114-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Allow the virt board to support '-cpu max' in the same way it already handles '-cpu host'. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 62af013..92bd776 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -167,6 +167,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), }; static bool cpu_type_valid(const char *cpu) From patchwork Thu Dec 7 18:14:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121045 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp8688656qgn; Thu, 7 Dec 2017 10:14:59 -0800 (PST) X-Google-Smtp-Source: AGs4zMa+8N77c00l16VCc1twkVPZFBdbA/YiFfhKBtnmuuG2pAiY4E9FrZyJXMWTxAK75cafiXu/ X-Received: by 10.223.150.46 with SMTP id b43mr24139408wra.5.1512670499204; Thu, 07 Dec 2017 10:14:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512670499; cv=none; d=google.com; s=arc-20160816; b=JVl2UcM6u4GXsCK8BtFxYuX9oqEWtVD8aPED8DVsGVpBlJnah2avBdEXyrKR2dZYGZ MIQPoOOkmhSyX42er8ZYVnNeq4vrI2LKJzBa2vptLqBCOM9gNkcNcfWiHBJ9UQ16o21T 5ClYSdXoET7q50ksAyFyByAJ66gLHrkzpnMcsHT1v3qCw+gyeKafsdDSTAw6oBzl3S0h kGPu4+GXcc8QBtMwYMhU2oPQTdECC3yk9XntwqsiJQHfLQfT8ytN75m5d3wHg8mGIQSI zE3hjlgph8xKsJWvwbGJ8katNNs0K8SRNr14HlrhddgABZk939CwAR9N++VbQ55U28T4 8Tug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=TdebkGqS8kSAy121qHa0qfoa5/4I+I/q5ImO+eNsURk=; b=yn6MwNzewtCMuBkq3MJTJKVHIDJfFNrdrvgVqRZ/bs+meQe2gkoZFmA8txJqbAFH8G 1Im895VzBNwJ6vDbgCeyx5X5xWqP3JSVUe00+Szua7SpyEjDV0m9jND4Z1xDHK8wQgz4 CVK373DPQmRLR8A+F6AbKr4tULGoA+qyqQhvPLotBbAgUR1rpqRklrwJVyzYrkGf0EGq VsugjEKpM7xwWnXcW6pn+AVDsVmwg69pujsy25rCesSu69JbRdyUcE0/Vj4hNBPY00PN DWFll9bczBh80uNQqzTm1XgfNvu3VhE2bVnoLoRaiC8RgWBQbsYBuI7NOrbDzZK84Wk9 gBbA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 203si3999045wmn.160.2017.12.07.10.14.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Dec 2017 10:14:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1eN0hG-000836-IH; Thu, 07 Dec 2017 18:14:58 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Eduardo Habkost , "Richard W . M . Jones" Subject: [PATCH 6/6] hw/arm/virt: Support -machine gic-version=max Date: Thu, 7 Dec 2017 18:14:53 +0000 Message-Id: <1512670493-18114-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> References: <1512670493-18114-1-git-send-email-peter.maydell@linaro.org> Add support for passing 'max' to -machine gic-version. By analogy with the -cpu max option, this picks the "best available" GIC version whether you're using KVM or TCG, so it behaves like 'host' when using KVM, and gives you GICv3 when using TCG. Also like '-cpu host', using -machine gic-version=max' means there is no guarantee of migration compatibility between QEMU versions; in future 'max' might mean '4'. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 92bd776..603ba56 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1265,16 +1265,23 @@ static void machvirt_init(MachineState *machine) /* We can probe only here because during property set * KVM is not available yet */ - if (!vms->gic_version) { + if (vms->gic_version <= 0) { + /* "host" or "max" */ if (!kvm_enabled()) { - error_report("gic-version=host requires KVM"); - exit(1); - } - - vms->gic_version = kvm_arm_vgic_probe(); - if (!vms->gic_version) { - error_report("Unable to determine GIC version supported by host"); - exit(1); + if (vms->gic_version == 0) { + error_report("gic-version=host requires KVM"); + exit(1); + } else { + /* "max": currently means 3 for TCG */ + vms->gic_version = 3; + } + } else { + vms->gic_version = kvm_arm_vgic_probe(); + if (!vms->gic_version) { + error_report( + "Unable to determine GIC version supported by host"); + exit(1); + } } } @@ -1539,9 +1546,11 @@ static void virt_set_gic_version(Object *obj, const char *value, Error **errp) vms->gic_version = 2; } else if (!strcmp(value, "host")) { vms->gic_version = 0; /* Will probe later */ + } else if (!strcmp(value, "max")) { + vms->gic_version = -1; /* Will probe later */ } else { error_setg(errp, "Invalid gic-version value"); - error_append_hint(errp, "Valid values are 3, 2, host.\n"); + error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); } }