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[209.132.180.131]) by mx.google.com with ESMTPS id j2si7702919pgn.690.2017.12.09.15.08.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:08:31 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468851-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Yt08ebDo; spf=pass (google.com: domain of gcc-patches-return-468851-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468851-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=JmDR/n/XdIRjeqO6j10ZJp/Zzif9g 4J2EpuiDZ2wShQ2HRy45rxovjHsGT4DEYI10zKzLhCw4mZpdi9WbDUIt9PMQyObF bMkweMvJZDs7Qz4uHSR9loSHBeLvnWyAoQTQaemUTsupVIYR2IJJORquRCBWmr66 yUFyYMKSOWUDBs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=Xj+/j48Cp+orungWXj9c3oX4xMg=; b=Yt0 8ebDoivSG7keCPrkGxZsr2q7QnhOPZmZXCfFBPmW4xwC/GvTp6bVHgfVwJRQUX0V BAvBNr/Lu2nnu9t6rx7sMAxV7dJ5DGj6gAgHVlCP2dRIyQocNkxjvEDT6ZLVo2rf 6hJwgkCYuxntPxld9pf0v/jz/Uj4vMAVuvSabhIg= Received: (qmail 73235 invoked by alias); 9 Dec 2017 23:08:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 73223 invoked by uid 89); 9 Dec 2017 23:08:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f44.google.com Received: from mail-wm0-f44.google.com (HELO mail-wm0-f44.google.com) (74.125.82.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:08:18 +0000 Received: by mail-wm0-f44.google.com with SMTP id y82so8692549wmg.1 for ; Sat, 09 Dec 2017 15:08:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=IkATfMeoK51th1afG+HL9Uek4ezpnhyoZXBFj6psWE8=; b=Z6sisVTIWP6AFAQmEJy7KVnuyin6+qfWCYw5g+Tr1IYk3Q5kWwtbcJSzCWxjgYQBXN DfH+3WdG26AxGoVbHrHJCz/KKaR15z/xXUfzd/HaFpt0ulWDsxMJPU19Jr3TA0mEWAe4 aE5rU0wWfGmV5KCQV/Ku6XJWqJ/SPgU67deEzM1OJtAkJqNZmErTJv9K8Y6gvzAV4iZ8 bGRW3lLqC0Exs5+2smrgwO3axQTRxW4FDD5orXcqF/cXVCjXADlKg2okr+B5T9bD2a/B 9HDlRQfSu1Ft/L9RUIR3i+zjTbrCf6FlQbTzWBrPvY87CltOWUkNNgoK8q1Qd0nPqKj+ t0RA== X-Gm-Message-State: AKGB3mId7XDLduBrioQghBKH3YVcpwgWMq0w20Pku34ErORsWq8py2pr YxsgbvKft5Y93RAp4WZXVt9SejNi9FY= X-Received: by 10.28.92.146 with SMTP id q140mr7868964wmb.41.1512860896581; Sat, 09 Dec 2017 15:08:16 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id 43sm12958978wru.81.2017.12.09.15.08.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:08:15 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [01/13] Add a qimode_for_vec_perm helper function References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:08:15 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87efo3mrds.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 The vec_perm code falls back to doing byte-level permutes if element-level permutes aren't supported. There were two copies of the code to calculate the mode, and later patches add another, so this patch splits it out into a helper function. 2017-12-09 Richard Sandiford gcc/ * optabs-query.h (qimode_for_vec_perm): Declare. * optabs-query.c (can_vec_perm_p): Split out qimode search to... (qimode_for_vec_perm): ...this new function. * optabs.c (expand_vec_perm): Use qimode_for_vec_perm. Index: gcc/optabs-query.h =================================================================== --- gcc/optabs-query.h 2017-12-09 22:47:12.476364764 +0000 +++ gcc/optabs-query.h 2017-12-09 22:47:14.730310076 +0000 @@ -174,6 +174,7 @@ enum insn_code can_extend_p (machine_mod enum insn_code can_float_p (machine_mode, machine_mode, int); enum insn_code can_fix_p (machine_mode, machine_mode, int, bool *); bool can_conditionally_move_p (machine_mode mode); +opt_machine_mode qimode_for_vec_perm (machine_mode); bool can_vec_perm_p (machine_mode, bool, vec_perm_indices *); /* Find a widening optab even if it doesn't widen as much as we want. */ #define find_widening_optab_handler(A, B, C) \ Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:47:12.476364764 +0000 +++ gcc/optabs-query.c 2017-12-09 22:47:14.729310075 +0000 @@ -345,6 +345,22 @@ can_conditionally_move_p (machine_mode m return direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing; } +/* If a target doesn't implement a permute on a vector with multibyte + elements, we can try to do the same permute on byte elements. + If this makes sense for vector mode MODE then return the appropriate + byte vector mode. */ + +opt_machine_mode +qimode_for_vec_perm (machine_mode mode) +{ + machine_mode qimode; + if (GET_MODE_INNER (mode) != QImode + && mode_for_vector (QImode, GET_MODE_SIZE (mode)).exists (&qimode) + && VECTOR_MODE_P (qimode)) + return qimode; + return opt_machine_mode (); +} + /* Return true if VEC_PERM_EXPR of arbitrary input vectors can be expanded using SIMD extensions of the CPU. SEL may be NULL, which stands for an unknown constant. Note that additional permutations @@ -375,9 +391,7 @@ can_vec_perm_p (machine_mode mode, bool return true; /* We allow fallback to a QI vector mode, and adjust the mask. */ - if (GET_MODE_INNER (mode) == QImode - || !mode_for_vector (QImode, GET_MODE_SIZE (mode)).exists (&qimode) - || !VECTOR_MODE_P (qimode)) + if (!qimode_for_vec_perm (mode).exists (&qimode)) return false; /* ??? For completeness, we ought to check the QImode version of Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:47:12.476364764 +0000 +++ gcc/optabs.c 2017-12-09 22:47:14.731310077 +0000 @@ -5452,9 +5452,7 @@ expand_vec_perm (machine_mode mode, rtx /* Set QIMODE to a different vector mode with byte elements. If no such mode, or if MODE already has byte elements, use VOIDmode. */ - if (GET_MODE_INNER (mode) == QImode - || !mode_for_vector (QImode, w).exists (&qimode) - || !VECTOR_MODE_P (qimode)) + if (!qimode_for_vec_perm (mode).exists (&qimode)) qimode = VOIDmode; /* If the input is a constant, expand it specially. */ From patchwork Sat Dec 9 23:09:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121292 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1157224qgn; Sat, 9 Dec 2017 15:09:32 -0800 (PST) X-Google-Smtp-Source: AGs4zMZMNyiWCy2zQvvoDhXVfA/W5Cn5wxWZqJ2L5Pd2q9k0dSecvDbTANJadpUof/mCkxv0sqiJ X-Received: by 10.101.101.211 with SMTP id y19mr33982786pgv.191.1512860972448; Sat, 09 Dec 2017 15:09:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512860972; cv=none; d=google.com; s=arc-20160816; b=xuwZPvXa7E5FEWGcw7IIfWrBeWBqkn9lzKJGIbiDVUuyPcfZoOHCcIDCaiHQa3CACr DgvGmX4u4bMEzI5wQ6GOvGb/qf4Ugu/o5GyJYrM4QnhtaJekyLKj6drB2mERo5GM3+X1 d6tjSQInXsESPFreDztMBKCMjp9rvXs1GpR0CydIqhRkcQ+wjAlzeELAZHtOtBIzeMw9 ZKkP01kU1rKZEy0LDWrXjclu4FhSzVTnIqob0M3oA1G0cdHRUmbPdBbAMcHFBxshoElW 7ehMvMqPi4ipV7JCgJCPPh9+hnaRhhQG8A3QT289C5SYM620aHhbCEr893os+vrQv4M+ y5/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=kOiy3sBijV2cPEjID66c4w6VRfK0yGtxPUxXabtbvPE=; b=AHZOTzaug422/gq3vxqAkTBmkjEcyVsLPLCubnDlB9CiGz84NCm3Yph8671tuQxadi JaDZn/ZBa60XMobNC3HdS7bPRC+d2cG7ChKsH4HlvHZiF4u5FKgkuZKoQB8pipSDYZxL FTwjiyA7QiUpRoKzxUFhKd2Rs939wwahucDTmvZtie4QwtlXthGkVhKfDrwdCzEezkUh bGWyIOtdkxUuqvRSFqRrhj1HGyTlJ3Lg6rG0PLNZmH0S9nL1jj8WrBOCs38oyMjutml+ xZknbwLgBO1OORBS6KOuSxTJShwfpSwgtUsgtlvDKt5MuEbS3a04FWW6W1NFE01sJIqY Ws9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Xc77CHGJ; spf=pass (google.com: domain of gcc-patches-return-468852-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468852-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. 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Sat, 09 Dec 2017 15:09:16 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [02/13] Pass vec_perm_indices by reference References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:09:15 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87a7yrmrc4.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch makes functions take vec_perm_indices by reference rather than value, since a later patch will turn vec_perm_indices into a class that would be more expensive to copy. 2017-12-06 Richard Sandiford gcc/ * fold-const.c (fold_vec_perm): Take a const vec_perm_indices & instead of vec_perm_indices. * tree-vectorizer.h (vect_gen_perm_mask_any): Likewise, (vect_gen_perm_mask_checked): Likewise, * tree-vect-stmts.c (vect_gen_perm_mask_any): Likewise, (vect_gen_perm_mask_checked): Likewise, Index: gcc/fold-const.c =================================================================== --- gcc/fold-const.c 2017-12-09 22:47:11.840391388 +0000 +++ gcc/fold-const.c 2017-12-09 22:47:19.119312754 +0000 @@ -8801,7 +8801,7 @@ vec_cst_ctor_to_array (tree arg, unsigne NULL_TREE otherwise. */ static tree -fold_vec_perm (tree type, tree arg0, tree arg1, vec_perm_indices sel) +fold_vec_perm (tree type, tree arg0, tree arg1, const vec_perm_indices &sel) { unsigned int i; bool need_ctor = false; Index: gcc/tree-vectorizer.h =================================================================== --- gcc/tree-vectorizer.h 2017-12-09 22:47:11.840391388 +0000 +++ gcc/tree-vectorizer.h 2017-12-09 22:47:19.120312754 +0000 @@ -1204,8 +1204,8 @@ extern void vect_get_load_cost (struct d extern void vect_get_store_cost (struct data_reference *, int, unsigned int *, stmt_vector_for_cost *); extern bool vect_supportable_shift (enum tree_code, tree); -extern tree vect_gen_perm_mask_any (tree, vec_perm_indices); -extern tree vect_gen_perm_mask_checked (tree, vec_perm_indices); +extern tree vect_gen_perm_mask_any (tree, const vec_perm_indices &); +extern tree vect_gen_perm_mask_checked (tree, const vec_perm_indices &); extern void optimize_mask_stores (struct loop*); /* In tree-vect-data-refs.c. */ Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:47:11.840391388 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:47:19.119312754 +0000 @@ -6506,7 +6506,7 @@ vectorizable_store (gimple *stmt, gimple vect_gen_perm_mask_checked. */ tree -vect_gen_perm_mask_any (tree vectype, vec_perm_indices sel) +vect_gen_perm_mask_any (tree vectype, const vec_perm_indices &sel) { tree mask_elt_type, mask_type; @@ -6527,7 +6527,7 @@ vect_gen_perm_mask_any (tree vectype, ve i.e. that the target supports the pattern _for arbitrary input vectors_. */ tree -vect_gen_perm_mask_checked (tree vectype, vec_perm_indices sel) +vect_gen_perm_mask_checked (tree vectype, const vec_perm_indices &sel) { gcc_assert (can_vec_perm_p (TYPE_MODE (vectype), false, &sel)); return vect_gen_perm_mask_any (vectype, sel); From patchwork Sat Dec 9 23:10:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121293 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1158284qgn; Sat, 9 Dec 2017 15:11:18 -0800 (PST) X-Google-Smtp-Source: AGs4zMbZylSML6wa2jjN0gmuabDuh80b4rHA/q2ZKxQLFX0ZlOX4oLcRXHd4hr6MFer+8dQzil1r X-Received: by 10.101.82.203 with SMTP id z11mr33954752pgp.404.1512861078315; Sat, 09 Dec 2017 15:11:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861078; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.131]) by mx.google.com with ESMTPS id l3si7652304pgo.729.2017.12.09.15.11.18 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:11:18 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468853-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=xgMr7lbT; spf=pass (google.com: domain of gcc-patches-return-468853-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468853-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=v07LH1Qo3Ql7Orsecxa6CkH6G1s4J zr4CQ/LVbc44NWiZApYQF43lcXRYlxXXeiHDK+y4Q3MKlU0AoVCx+b8Cvv1vQpmL gdENIjbuH9IuFMJODg720B5xlE9jyKUIJ7HciKN2iyKk2vefC0oFT3YOVbX12hc8 wkS72nxiQ3w/z4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=s8zpPttKPQBlTqpTyfsUSW5ePwQ=; b=xgM r7lbTSgG9wU8k8vaCTapYwC9+ZCN2h8xcPP6xy7xk9JKYpy2WMs7Yqa4A9mlMOTF 1KWJoPP1Q1G/mmsul+ZOEkryfjdWNaBcpANFm0QW1GofghWR/3/J/0ytR+ycSQ77 edLrY/ZdF4vI7Mqxy6IVlTLqceVJAHE5GUJfqn9w= Received: (qmail 77274 invoked by alias); 9 Dec 2017 23:11:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77265 invoked by uid 89); 9 Dec 2017 23:11:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:fold_te, UD:tree-vect-generic.c X-HELO: mail-wm0-f54.google.com Received: from mail-wm0-f54.google.com (HELO mail-wm0-f54.google.com) (74.125.82.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:11:02 +0000 Received: by mail-wm0-f54.google.com with SMTP id f140so8310142wmd.2 for ; Sat, 09 Dec 2017 15:11:01 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=O0KeYPvNey5xBvYQX6jdIIWVW2gYZ9rbF000IKQMXfw=; b=iHdD5cwZ3qE0R3nkMJoZA8H3d61dM7Tc+Z2AHp+ExzyOnGlMABThY+5NAGUGp4QbCa NpIJTrLQUGeQdbyPR+IAjHS59cMET7Un2URqMTOTIqBRPofBWRnsLOzbXdK0qTBAPO0g wsmZB5ZiU0I/K5EY/u7rGxdVzl6D4ku/cSi9qN+VtXHzKMj2BCRA+cYGDgRD2agpVOjt OP4odRUakiU+s4WTp7mL3sF4/quY4b8j4/Wx061QwqRYedVzsi0LO1exhHoeR+9tlsOK l+tx3Mq6ismvF8pOPPvyaWResAgcR/bnLhPLSY7/m4/0eB0T4Uub1ip7OVEuYdgJ+QI6 FztA== X-Gm-Message-State: AKGB3mItKcImXbw0iSJ/k1/m4dKfNKYJEreOXKlYrZBCuSC2LO/be4j4 Z5Av3oMPJuwKQG+xlzWqornk0rRuWVM= X-Received: by 10.28.236.28 with SMTP id k28mr6843889wmh.120.1512861059546; Sat, 09 Dec 2017 15:10:59 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id c2sm13084221wrg.57.2017.12.09.15.10.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:10:58 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [03/13] Split can_vec_perm_p into can_vec_perm_{var,const}_p References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:10:57 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <874lozmr9a.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch splits can_vec_perm_p into two functions: can_vec_perm_var_p for testing permute operations with variable selection vectors, and can_vec_perm_const_p for testing permute operations with specific constant selection vectors. This means that we can pass the constant selection vector by reference. Constant permutes can still use a variable permute as a fallback. A later patch adds a check to make sure that we don't truncate the vector indices when doing this. However, have_whole_vector_shift checked: if (direct_optab_handler (vec_perm_const_optab, mode) == CODE_FOR_nothing) return false; which had the effect of disallowing the fallback to variable permutes. I'm not sure whether that was the intention or whether it was just supposed to short-cut the loop on targets that don't support permutes. (But then why bother? The first check in the loop would fail and we'd bail out straightaway.) The patch adds a parameter for disallowing the fallback. I think it makes sense to do this for the following code in the VEC_PERM_EXPR folder: /* Some targets are deficient and fail to expand a single argument permutation while still allowing an equivalent 2-argument version. */ if (need_mask_canon && arg2 == op2 && !can_vec_perm_p (TYPE_MODE (type), false, &sel) && can_vec_perm_p (TYPE_MODE (type), false, &sel2)) since it's really testing whether the expand_vec_perm_const code expects a particular form. 2017-12-09 Richard Sandiford gcc/ * optabs-query.h (can_vec_perm_p): Delete. (can_vec_perm_var_p, can_vec_perm_const_p): Declare. * optabs-query.c (can_vec_perm_p): Split into... (can_vec_perm_var_p, can_vec_perm_const_p): ...these two functions. (can_mult_highpart_p): Use can_vec_perm_const_p to test whether a particular selector is valid. * tree-ssa-forwprop.c (simplify_vector_constructor): Likewise. * tree-vect-data-refs.c (vect_grouped_store_supported): Likewise. (vect_grouped_load_supported): Likewise. (vect_shift_permute_load_chain): Likewise. * tree-vect-slp.c (vect_build_slp_tree_1): Likewise. (vect_transform_slp_perm_load): Likewise. * tree-vect-stmts.c (perm_mask_for_reverse): Likewise. (vectorizable_bswap): Likewise. (vect_gen_perm_mask_checked): Likewise. * fold-const.c (fold_ternary_loc): Likewise. Don't take implementations of variable permutation vectors into account when deciding which selector to use. * tree-vect-loop.c (have_whole_vector_shift): Don't check whether vec_perm_const_optab is supported; instead use can_vec_perm_const_p with a false third argument. * tree-vect-generic.c (lower_vec_perm): Use can_vec_perm_const_p to test whether the constant selector is valid and can_vec_perm_var_p to test whether a variable selector is valid. Index: gcc/optabs-query.h =================================================================== --- gcc/optabs-query.h 2017-12-09 22:47:14.730310076 +0000 +++ gcc/optabs-query.h 2017-12-09 22:47:21.534314227 +0000 @@ -175,7 +175,9 @@ enum insn_code can_float_p (machine_mode enum insn_code can_fix_p (machine_mode, machine_mode, int, bool *); bool can_conditionally_move_p (machine_mode mode); opt_machine_mode qimode_for_vec_perm (machine_mode); -bool can_vec_perm_p (machine_mode, bool, vec_perm_indices *); +bool can_vec_perm_var_p (machine_mode); +bool can_vec_perm_const_p (machine_mode, const vec_perm_indices &, + bool = true); /* Find a widening optab even if it doesn't widen as much as we want. */ #define find_widening_optab_handler(A, B, C) \ find_widening_optab_handler_and_mode (A, B, C, NULL) Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:47:14.729310075 +0000 +++ gcc/optabs-query.c 2017-12-09 22:47:21.534314227 +0000 @@ -361,58 +361,75 @@ qimode_for_vec_perm (machine_mode mode) return opt_machine_mode (); } -/* Return true if VEC_PERM_EXPR of arbitrary input vectors can be - expanded using SIMD extensions of the CPU. SEL may be NULL, which - stands for an unknown constant. Note that additional permutations - representing whole-vector shifts may also be handled via the vec_shr - optab, but only where the second input vector is entirely constant - zeroes; this case is not dealt with here. */ +/* Return true if VEC_PERM_EXPRs with variable selector operands can be + expanded using SIMD extensions of the CPU. MODE is the mode of the + vectors being permuted. */ bool -can_vec_perm_p (machine_mode mode, bool variable, vec_perm_indices *sel) +can_vec_perm_var_p (machine_mode mode) { - machine_mode qimode; - /* If the target doesn't implement a vector mode for the vector type, then no operations are supported. */ if (!VECTOR_MODE_P (mode)) return false; - if (!variable) - { - if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing - && (sel == NULL - || targetm.vectorize.vec_perm_const_ok == NULL - || targetm.vectorize.vec_perm_const_ok (mode, *sel))) - return true; - } - if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing) return true; /* We allow fallback to a QI vector mode, and adjust the mask. */ + machine_mode qimode; if (!qimode_for_vec_perm (mode).exists (&qimode)) return false; - /* ??? For completeness, we ought to check the QImode version of - vec_perm_const_optab. But all users of this implicit lowering - feature implement the variable vec_perm_optab. */ if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing) return false; /* In order to support the lowering of variable permutations, we need to support shifts and adds. */ - if (variable) + if (GET_MODE_UNIT_SIZE (mode) > 2 + && optab_handler (ashl_optab, mode) == CODE_FOR_nothing + && optab_handler (vashl_optab, mode) == CODE_FOR_nothing) + return false; + if (optab_handler (add_optab, qimode) == CODE_FOR_nothing) + return false; + + return true; +} + +/* Return true if the target directly supports VEC_PERM_EXPRs on vectors + of mode MODE using the selector SEL. ALLOW_VARIABLE_P is true if it + is acceptable to force the selector into a register and use a variable + permute (if the target supports that). + + Note that additional permutations representing whole-vector shifts may + also be handled via the vec_shr optab, but only where the second input + vector is entirely constant zeroes; this case is not dealt with here. */ + +bool +can_vec_perm_const_p (machine_mode mode, const vec_perm_indices &sel, + bool allow_variable_p) +{ + /* If the target doesn't implement a vector mode for the vector type, + then no operations are supported. */ + if (!VECTOR_MODE_P (mode)) + return false; + + /* It's probably cheaper to test for the variable case first. */ + if (allow_variable_p && can_vec_perm_var_p (mode)) + return true; + + if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing) { - if (GET_MODE_UNIT_SIZE (mode) > 2 - && optab_handler (ashl_optab, mode) == CODE_FOR_nothing - && optab_handler (vashl_optab, mode) == CODE_FOR_nothing) - return false; - if (optab_handler (add_optab, qimode) == CODE_FOR_nothing) - return false; + if (targetm.vectorize.vec_perm_const_ok == NULL + || targetm.vectorize.vec_perm_const_ok (mode, sel)) + return true; + + /* ??? For completeness, we ought to check the QImode version of + vec_perm_const_optab. But all users of this implicit lowering + feature implement the variable vec_perm_optab. */ } - return true; + return false; } /* Find a widening optab even if it doesn't widen as much as we want. @@ -472,7 +489,7 @@ can_mult_highpart_p (machine_mode mode, sel.quick_push (!BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0)); - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) return 2; } } @@ -486,7 +503,7 @@ can_mult_highpart_p (machine_mode mode, auto_vec_perm_indices sel (nunits); for (i = 0; i < nunits; ++i) sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) return 3; } } Index: gcc/tree-ssa-forwprop.c =================================================================== --- gcc/tree-ssa-forwprop.c 2017-12-09 22:47:11.145420483 +0000 +++ gcc/tree-ssa-forwprop.c 2017-12-09 22:47:21.534314227 +0000 @@ -2108,7 +2108,7 @@ simplify_vector_constructor (gimple_stmt { tree mask_type; - if (!can_vec_perm_p (TYPE_MODE (type), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (type), sel)) return false; mask_type = build_vector_type (build_nonstandard_integer_type (elem_size, 1), Index: gcc/tree-vect-data-refs.c =================================================================== --- gcc/tree-vect-data-refs.c 2017-12-09 22:47:11.145420483 +0000 +++ gcc/tree-vect-data-refs.c 2017-12-09 22:47:21.535314227 +0000 @@ -4587,11 +4587,11 @@ vect_grouped_store_supported (tree vecty if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = 0; } - if (!can_vec_perm_p (mode, false, &sel)) + if (!can_vec_perm_const_p (mode, sel)) { if (dump_enabled_p ()) dump_printf (MSG_MISSED_OPTIMIZATION, - "permutaion op not supported by target.\n"); + "permutation op not supported by target.\n"); return false; } @@ -4604,11 +4604,11 @@ vect_grouped_store_supported (tree vecty if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = nelt + j2++; } - if (!can_vec_perm_p (mode, false, &sel)) + if (!can_vec_perm_const_p (mode, sel)) { if (dump_enabled_p ()) dump_printf (MSG_MISSED_OPTIMIZATION, - "permutaion op not supported by target.\n"); + "permutation op not supported by target.\n"); return false; } } @@ -4624,11 +4624,11 @@ vect_grouped_store_supported (tree vecty sel[i * 2] = i; sel[i * 2 + 1] = i + nelt; } - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) { for (i = 0; i < nelt; i++) sel[i] += nelt / 2; - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) return true; } } @@ -5166,7 +5166,7 @@ vect_grouped_load_supported (tree vectyp sel[i] = 3 * i + k; else sel[i] = 0; - if (!can_vec_perm_p (mode, false, &sel)) + if (!can_vec_perm_const_p (mode, sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5179,7 +5179,7 @@ vect_grouped_load_supported (tree vectyp sel[i] = i; else sel[i] = nelt + ((nelt + k) % 3) + 3 * (j++); - if (!can_vec_perm_p (mode, false, &sel)) + if (!can_vec_perm_const_p (mode, sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5196,11 +5196,11 @@ vect_grouped_load_supported (tree vectyp gcc_assert (pow2p_hwi (count)); for (i = 0; i < nelt; i++) sel[i] = i * 2; - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) { for (i = 0; i < nelt; i++) sel[i] = i * 2 + 1; - if (can_vec_perm_p (mode, false, &sel)) + if (can_vec_perm_const_p (mode, sel)) return true; } } @@ -5527,7 +5527,7 @@ vect_shift_permute_load_chain (vec sel[i] = i * 2; for (i = 0; i < nelt / 2; ++i) sel[nelt / 2 + i] = i * 2 + 1; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5541,7 +5541,7 @@ vect_shift_permute_load_chain (vec sel[i] = i * 2 + 1; for (i = 0; i < nelt / 2; ++i) sel[nelt / 2 + i] = i * 2; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5555,7 +5555,7 @@ vect_shift_permute_load_chain (vec For vector length 8 it is {4 5 6 7 8 9 10 11}. */ for (i = 0; i < nelt; i++) sel[i] = nelt / 2 + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5570,7 +5570,7 @@ vect_shift_permute_load_chain (vec sel[i] = i; for (i = nelt / 2; i < nelt; i++) sel[i] = nelt + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5633,7 +5633,7 @@ vect_shift_permute_load_chain (vec sel[i] = 3 * k + (l % 3); k++; } - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5647,7 +5647,7 @@ vect_shift_permute_load_chain (vec For vector length 8 it is {6 7 8 9 10 11 12 13}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + (nelt % 3) + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5660,7 +5660,7 @@ vect_shift_permute_load_chain (vec For vector length 8 it is {5 6 7 8 9 10 11 12}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + 1 + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5673,7 +5673,7 @@ vect_shift_permute_load_chain (vec For vector length 8 it is {3 4 5 6 7 8 9 10}. */ for (i = 0; i < nelt; i++) sel[i] = (nelt / 3) + (nelt % 3) / 2 + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5686,7 +5686,7 @@ vect_shift_permute_load_chain (vec For vector length 8 it is {5 6 7 8 9 10 11 12}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + (nelt % 3) / 2 + i; - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, Index: gcc/tree-vect-slp.c =================================================================== --- gcc/tree-vect-slp.c 2017-12-09 22:47:11.145420483 +0000 +++ gcc/tree-vect-slp.c 2017-12-09 22:47:21.536314228 +0000 @@ -901,7 +901,7 @@ vect_build_slp_tree_1 (vec_info *vinfo, elt += count; sel.quick_push (elt); } - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) { for (i = 0; i < group_size; ++i) if (gimple_assign_rhs_code (stmts[i]) == alt_stmt_code) @@ -3646,7 +3646,7 @@ vect_transform_slp_perm_load (slp_tree n if (index == nunits) { if (! noop_p - && ! can_vec_perm_p (mode, false, &mask)) + && ! can_vec_perm_const_p (mode, mask)) { if (dump_enabled_p ()) { Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:47:19.119312754 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:47:21.537314229 +0000 @@ -1720,7 +1720,7 @@ perm_mask_for_reverse (tree vectype) for (i = 0; i < nunits; ++i) sel.quick_push (nunits - 1 - i); - if (!can_vec_perm_p (TYPE_MODE (vectype), false, &sel)) + if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) return NULL_TREE; return vect_gen_perm_mask_checked (vectype, sel); } @@ -2502,7 +2502,7 @@ vectorizable_bswap (gimple *stmt, gimple for (unsigned j = 0; j < word_bytes; ++j) elts.quick_push ((i + 1) * word_bytes - j - 1); - if (! can_vec_perm_p (TYPE_MODE (char_vectype), false, &elts)) + if (!can_vec_perm_const_p (TYPE_MODE (char_vectype), elts)) return false; if (! vec_stmt) @@ -6502,7 +6502,7 @@ vectorizable_store (gimple *stmt, gimple /* Given a vector type VECTYPE, turns permutation SEL into the equivalent VECTOR_CST mask. No checks are made that the target platform supports the - mask, so callers may wish to test can_vec_perm_p separately, or use + mask, so callers may wish to test can_vec_perm_const_p separately, or use vect_gen_perm_mask_checked. */ tree @@ -6523,13 +6523,13 @@ vect_gen_perm_mask_any (tree vectype, co return mask_elts.build (); } -/* Checked version of vect_gen_perm_mask_any. Asserts can_vec_perm_p, +/* Checked version of vect_gen_perm_mask_any. Asserts can_vec_perm_const_p, i.e. that the target supports the pattern _for arbitrary input vectors_. */ tree vect_gen_perm_mask_checked (tree vectype, const vec_perm_indices &sel) { - gcc_assert (can_vec_perm_p (TYPE_MODE (vectype), false, &sel)); + gcc_assert (can_vec_perm_const_p (TYPE_MODE (vectype), sel)); return vect_gen_perm_mask_any (vectype, sel); } Index: gcc/fold-const.c =================================================================== --- gcc/fold-const.c 2017-12-09 22:47:19.119312754 +0000 +++ gcc/fold-const.c 2017-12-09 22:47:21.534314227 +0000 @@ -11620,8 +11620,8 @@ fold_ternary_loc (location_t loc, enum t argument permutation while still allowing an equivalent 2-argument version. */ if (need_mask_canon && arg2 == op2 - && !can_vec_perm_p (TYPE_MODE (type), false, &sel) - && can_vec_perm_p (TYPE_MODE (type), false, &sel2)) + && !can_vec_perm_const_p (TYPE_MODE (type), sel, false) + && can_vec_perm_const_p (TYPE_MODE (type), sel2, false)) { need_mask_canon = need_mask_canon2; sel = sel2; Index: gcc/tree-vect-loop.c =================================================================== --- gcc/tree-vect-loop.c 2017-12-09 22:47:11.145420483 +0000 +++ gcc/tree-vect-loop.c 2017-12-09 22:47:21.536314228 +0000 @@ -3730,9 +3730,6 @@ have_whole_vector_shift (machine_mode mo if (optab_handler (vec_shr_optab, mode) != CODE_FOR_nothing) return true; - if (direct_optab_handler (vec_perm_const_optab, mode) == CODE_FOR_nothing) - return false; - unsigned int i, nelt = GET_MODE_NUNITS (mode); auto_vec_perm_indices sel (nelt); @@ -3740,7 +3737,7 @@ have_whole_vector_shift (machine_mode mo { sel.truncate (0); calc_vec_perm_mask_for_shift (i, nelt, &sel); - if (!can_vec_perm_p (mode, false, &sel)) + if (!can_vec_perm_const_p (mode, sel, false)) return false; } return true; Index: gcc/tree-vect-generic.c =================================================================== --- gcc/tree-vect-generic.c 2017-12-09 22:47:11.145420483 +0000 +++ gcc/tree-vect-generic.c 2017-12-09 22:47:21.535314227 +0000 @@ -1306,7 +1306,7 @@ lower_vec_perm (gimple_stmt_iterator *gs sel_int.quick_push (TREE_INT_CST_LOW (VECTOR_CST_ELT (mask, i)) & (2 * elements - 1)); - if (can_vec_perm_p (TYPE_MODE (vect_type), false, &sel_int)) + if (can_vec_perm_const_p (TYPE_MODE (vect_type), sel_int)) { gimple_assign_set_rhs3 (stmt, mask); update_stmt (stmt); @@ -1337,7 +1337,7 @@ lower_vec_perm (gimple_stmt_iterator *gs } } } - else if (can_vec_perm_p (TYPE_MODE (vect_type), true, NULL)) + else if (can_vec_perm_var_p (TYPE_MODE (vect_type))) return; warning_at (loc, OPT_Wvector_operation_performance, From patchwork Sat Dec 9 23:13:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121294 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1159558qgn; Sat, 9 Dec 2017 15:13:24 -0800 (PST) X-Google-Smtp-Source: AGs4zMYBaYiKGCRkcH4BW1LUmv8JPHS5wyAOQaXDyGffRv7hc/VRhFkJ7IvU1UFjh4MOhLIll0P3 X-Received: by 10.98.192.202 with SMTP id g71mr7106353pfk.33.1512861204782; Sat, 09 Dec 2017 15:13:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861204; cv=none; d=google.com; s=arc-20160816; b=srzd2Z0Ft2F/AcCeuEh0b9kTht8XGjO4D5JBBp60RgzKaieTp+Tc03F12uhAbQ+l1x jpN/4ZmYGKxAuKKlgEClCscGx3V4qhE2PWimDNza1hbSCi+LzmK9WCDOpYmoNtp3eDBe eMAkAwWHZWUR/ceTDIPGuKcSrUa5iFTlQGQc2aAYP2+C6tId2k6WtWAlGmj1+l5/x5P3 aRVdApcgWwVnQAof5SMSk4MMdDJZeSGoAChLOGxmUcCtuoyHmr5zlNBBJcqyRLbKzrzF Gie+TXU6vUvlJKsv4AAzZVbu+TORag94ESb0HraDeodia5rVlWg/xjwROw37IdW7jr5E mDWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=ACLQhSRxSJ6EoSNETN06xwRUP8yLFDqDdQzvraMBcI8=; b=TKvAgg3WprdRK46PRikL7OAsyO/iONzp7BtAOvAwgoqxOjMRt7byLEF4PhcdKovLU5 YAGXcJRf8PPuoDNb8sCspPVEYkgwJ+j6hiYqOAohK2L8bRQWlNWmqfhZ9jATZMx5JXJM qaTJI0w3r7V40leDmsp0PP01MkHnLNM1bvTZSqBJdtRDyYe8clXv2k9djsRsjmx0yxTZ SeqeQz0kLw2CawnGvAVAs42iUKyUYT8KFCDr+PXBxvfz34sCvsyETOOS1H+HPKmxDbKW mZbYxHLV3RQkdBI45asLplw/Jhchd28oop0UkSAVbNsV8VdZTaeTXZatMgCD6TR6XGtn lXjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=aw9g3jHA; spf=pass (google.com: domain of gcc-patches-return-468854-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468854-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. 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Handling CONST_VECTORs includes handling the fallback to variable permutes. The patch also adds an assert for valid optab modes to expand_vec_perm_1, so that we get it when using optabs for CONST_VECTORs. The MODE_VECTOR_INT part was previously in expand_vec_perm and the mode_for_int_vector part is new. Most of the patch is just reindentation, so I've attached a -b version. 2017-12-06 Richard Sandiford gcc/ * optabs.c (expand_vec_perm_1): Assert that SEL has an integer vector mode and that that mode matches the mode of the data being permuted. (expand_vec_perm): Split handling of non-CONST_VECTOR selectors out into expand_vec_perm_var. Do all CONST_VECTOR handling here, directly using expand_vec_perm_1 when forcing selectors into registers. (expand_vec_perm_var): New function, split out from expand_vec_perm. Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 23:06:57.167722990 +0000 +++ gcc/optabs.c 2017-12-09 23:11:09.452859833 +0000 @@ -5405,6 +5405,8 @@ expand_vec_perm_1 (enum insn_code icode, machine_mode smode = GET_MODE (sel); struct expand_operand ops[4]; + gcc_assert (GET_MODE_CLASS (smode) == MODE_VECTOR_INT + || mode_for_int_vector (tmode).require () == smode); create_output_operand (&ops[0], target, tmode); create_input_operand (&ops[3], sel, smode); @@ -5431,8 +5433,13 @@ expand_vec_perm_1 (enum insn_code icode, return NULL_RTX; } -/* Generate instructions for vec_perm optab given its mode - and three operands. */ +static rtx expand_vec_perm_var (machine_mode, rtx, rtx, rtx, rtx); + +/* Implement a permutation of vectors v0 and v1 using the permutation + vector in SEL and return the result. Use TARGET to hold the result + if nonnull and convenient. + + MODE is the mode of the vectors being permuted (V0 and V1). */ rtx expand_vec_perm (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) @@ -5443,6 +5450,9 @@ expand_vec_perm (machine_mode mode, rtx rtx tmp, sel_qi = NULL; rtvec vec; + if (GET_CODE (sel) != CONST_VECTOR) + return expand_vec_perm_var (mode, v0, v1, sel, target); + if (!target || GET_MODE (target) != mode) target = gen_reg_rtx (mode); @@ -5455,22 +5465,18 @@ expand_vec_perm (machine_mode mode, rtx if (!qimode_for_vec_perm (mode).exists (&qimode)) qimode = VOIDmode; - /* If the input is a constant, expand it specially. */ - gcc_assert (GET_MODE_CLASS (GET_MODE (sel)) == MODE_VECTOR_INT); - if (GET_CODE (sel) == CONST_VECTOR) - { /* See if this can be handled with a vec_shr. We only do this if the second vector is all zeroes. */ - enum insn_code shift_code = optab_handler (vec_shr_optab, mode); - enum insn_code shift_code_qi = ((qimode != VOIDmode && qimode != mode) + insn_code shift_code = optab_handler (vec_shr_optab, mode); + insn_code shift_code_qi = ((qimode != VOIDmode && qimode != mode) ? optab_handler (vec_shr_optab, qimode) : CODE_FOR_nothing); - rtx shift_amt = NULL_RTX; + if (v1 == CONST0_RTX (GET_MODE (v1)) && (shift_code != CODE_FOR_nothing || shift_code_qi != CODE_FOR_nothing)) { - shift_amt = shift_amt_for_vec_perm_mask (sel); + rtx shift_amt = shift_amt_for_vec_perm_mask (sel); if (shift_amt) { struct expand_operand ops[3]; @@ -5478,19 +5484,16 @@ expand_vec_perm (machine_mode mode, rtx { create_output_operand (&ops[0], target, mode); create_input_operand (&ops[1], v0, mode); - create_convert_operand_from_type (&ops[2], shift_amt, - sizetype); + create_convert_operand_from_type (&ops[2], shift_amt, sizetype); if (maybe_expand_insn (shift_code, 3, ops)) return ops[0].value; } if (shift_code_qi != CODE_FOR_nothing) { - tmp = gen_reg_rtx (qimode); + rtx tmp = gen_reg_rtx (qimode); create_output_operand (&ops[0], tmp, qimode); - create_input_operand (&ops[1], gen_lowpart (qimode, v0), - qimode); - create_convert_operand_from_type (&ops[2], shift_amt, - sizetype); + create_input_operand (&ops[1], gen_lowpart (qimode, v0), qimode); + create_convert_operand_from_type (&ops[2], shift_amt, sizetype); if (maybe_expand_insn (shift_code_qi, 3, ops)) return gen_lowpart (mode, ops[0].value); } @@ -5525,16 +5528,62 @@ expand_vec_perm (machine_mode mode, rtx icode = direct_optab_handler (vec_perm_const_optab, qimode); if (icode != CODE_FOR_nothing) { - tmp = mode != qimode ? gen_reg_rtx (qimode) : target; + tmp = gen_reg_rtx (qimode); tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), gen_lowpart (qimode, v1), sel_qi); if (tmp) return gen_lowpart (mode, tmp); } } - } /* Otherwise expand as a fully variable permuation. */ + + icode = direct_optab_handler (vec_perm_optab, mode); + if (icode != CODE_FOR_nothing) + { + rtx tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); + if (tmp) + return tmp; + } + + if (qimode != VOIDmode) + { + icode = direct_optab_handler (vec_perm_optab, qimode); + if (icode != CODE_FOR_nothing) + { + rtx tmp = gen_reg_rtx (qimode); + tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), + gen_lowpart (qimode, v1), sel_qi); + if (tmp) + return gen_lowpart (mode, tmp); + } + } + + return NULL_RTX; +} + +/* Implement a permutation of vectors v0 and v1 using the permutation + vector in SEL and return the result. Use TARGET to hold the result + if nonnull and convenient. + + MODE is the mode of the vectors being permuted (V0 and V1). + SEL must have the integer equivalent of MODE and is known to be + unsuitable for permutes with a constant permutation vector. */ + +static rtx +expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) +{ + enum insn_code icode; + unsigned int i, w, u; + rtx tmp, sel_qi; + rtvec vec; + + w = GET_MODE_SIZE (mode); + u = GET_MODE_UNIT_SIZE (mode); + + if (!target || GET_MODE (target) != mode) + target = gen_reg_rtx (mode); + icode = direct_optab_handler (vec_perm_optab, mode); if (icode != CODE_FOR_nothing) { @@ -5545,22 +5594,20 @@ expand_vec_perm (machine_mode mode, rtx /* As a special case to aid several targets, lower the element-based permutation to a byte-based permutation and try again. */ - if (qimode == VOIDmode) + machine_mode qimode; + if (!qimode_for_vec_perm (mode).exists (&qimode)) return NULL_RTX; icode = direct_optab_handler (vec_perm_optab, qimode); if (icode == CODE_FOR_nothing) return NULL_RTX; - if (sel_qi == NULL) - { /* Multiply each element by its byte size. */ machine_mode selmode = GET_MODE (sel); if (u == 2) sel = expand_simple_binop (selmode, PLUS, sel, sel, NULL, 0, OPTAB_DIRECT); else - sel = expand_simple_binop (selmode, ASHIFT, sel, - GEN_INT (exact_log2 (u)), + sel = expand_simple_binop (selmode, ASHIFT, sel, GEN_INT (exact_log2 (u)), NULL, 0, OPTAB_DIRECT); gcc_assert (sel != NULL); @@ -5588,7 +5635,6 @@ expand_vec_perm (machine_mode mode, rtx sel_qi = expand_simple_binop (qimode, PLUS, sel, tmp, sel, 0, OPTAB_DIRECT); gcc_assert (sel_qi != NULL); - } tmp = mode != qimode ? gen_reg_rtx (qimode) : target; tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), From patchwork Sat Dec 9 23:16:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121295 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1162440qgn; Sat, 9 Dec 2017 15:17:32 -0800 (PST) X-Google-Smtp-Source: AGs4zMaPYDZUgwyARUbOoXEZGpFf2s7u44JyyvYDnHIkySFD0xRFH0NQmreMdlcO44t6qky6QELf X-Received: by 10.84.216.26 with SMTP id m26mr11097076pli.432.1512861452314; Sat, 09 Dec 2017 15:17:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861452; cv=none; d=google.com; s=arc-20160816; b=q6SoP+qA6g7iUfnmWAEFXYpqTFs17hTYWWDuik9VfdMtGeQ9wvK6LTArnROeuBUmq6 jZXIuvQTlVUe5+5C3PBGrGuzeYhuNdaG5pgkpJxtu2/adImIR7PMEilQxKOxb3WAm5xT L6HHVOT3y9WZ6neImPgmasc9azZuet5fS3XcKZxwf2+O/tnXdd46A0t+YgKaSm89an6y mQ2MdSTK41cxOvF4wjV0eD7Tc57WA4UklJS8gPtfwqU5uH9qxHcwV6CBpm/oS/ay/V+a Tw+2FlWIBHdmSgFkiLBgjw0rJuhILTOWOeP/NqwbKpRiszkHsQ33ifC249IxzFTPY1VO u7Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=8AiVb01/m/d4lhmueJDqK8zXM2w/hazr8YbOj5I4Plk=; b=oF+OYpzGu3hp+JT7EOTDYNsRa0NSn8ssi17ejRaBVEuvJgdUVmEOz1IK+f1yC6LUz4 msucISt0JeF6z38VyEOKbxPc4HUNdItXhIUark9/J6+PNcbn6PPHakWkM3pLILZcZfoc +m60mDwfj9vpRFW4tq0O2eK1zUMV3tR1ARC/7YfcKKYFUa9wVQ7LNT7NHL3/UGOWrhZ+ rTDkFEbd3zbT8XMLST5Mi2OsdUduw8Lg/7vu/N/87RquQyvKGm5u8LG7W8/qiyrCrOr1 DgInCUX1FczBjOORfd4NOBr+endkSSW+fuGVg594OyEvkoADPJI35g2C5atmXsNcuKLH 6x4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rtnXCy2z; spf=pass (google.com: domain of gcc-patches-return-468855-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468855-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id h5si7712366pgv.9.2017.12.09.15.17.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:17:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468855-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=rtnXCy2z; spf=pass (google.com: domain of gcc-patches-return-468855-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468855-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=j8SdqPxl5LkpahAKlZJKpctf+a1LI thUoe3htApftUBCaDPW4u2rQV1BMCyiJP8l+LMccXdkdfwNqqmVoLN8nD5MNEfEd QybUVstqoPuz5724AGlmgW00ryP9oM+AcBhAhyUm2DHpy5Fg7Kd2OzzV3z/yQikU bXmiVVA6w+wQDU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=rsNheuA8Bw8UYRVf3Tthzfxhq48=; b=rtn XCy2zfL8Oq0mQBdsXzbWuPvZSL/UyrxcgpaeRid/VIFIvbbwgAcnjjBLZjSL9egf HXQTa5KxFaNv56WWngHEaV3b989f8oisVkpAAXpIXge31KRHsdOm1qTVhhu6R95D e/KU8wYVl//jN60cIIk1lVqg3xadVMD/t89ZlxQg= Received: (qmail 93997 invoked by alias); 9 Dec 2017 23:17:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 93963 invoked by uid 89); 9 Dec 2017 23:17:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-14.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS, URIBL_BLACK autolearn=ham version=3.3.2 spammy=wind X-HELO: mail-wr0-f173.google.com Received: from mail-wr0-f173.google.com (HELO mail-wr0-f173.google.com) (209.85.128.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:16:59 +0000 Received: by mail-wr0-f173.google.com with SMTP id z18so14027359wrb.8 for ; Sat, 09 Dec 2017 15:16:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=8AiVb01/m/d4lhmueJDqK8zXM2w/hazr8YbOj5I4Plk=; b=Ai0RiZC3ips0FjUTm1+Q5ZqCXsnDHKGOcr25SLskbv1AUokjY0jk5oMH3B+p7bDSyD 8hSJZXpgIQ6CaKoEeUIiq1c7pUz9qcJXjzZhOBYphy9HST6BXFiEiydjpzEnZdzdwQgq 4knsPaQoezA22hDYXi4ktzMfo/IAFJXBUR14WI4Ansk4oGdhzgZ/39mnMgFwbkD6ZRIN fGkHpLalduLIZcar9l6BwCpj8VR9Yt45b5cXzh/urg49Z3t+oX9Wrdg4vrqER+6JwVmR 430AfAjGtNrnoJy34Sazs7OOPyKbQGt7SwuRWAsLwcDBH91cAhtHBXVwX0DzgpIhucER Zs6g== X-Gm-Message-State: AJaThX4kXheo5RBub7xIrC5A7TmcfHh9jiUb1E7jT8iRVphiDtRupWrt 6tiWhylKim4FDNr0t7puVM0cj3x4YHA= X-Received: by 10.223.201.139 with SMTP id f11mr32333425wrh.283.1512861413985; Sat, 09 Dec 2017 15:16:53 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id c2sm13093644wrg.57.2017.12.09.15.16.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:16:53 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [05/13] Remove vec_perm_const optab References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:16:50 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87vahflcf1.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 One of the changes needed for variable-length VEC_PERM_EXPRs -- and for long fixed-length VEC_PERM_EXPRs -- is the ability to use constant selectors that wouldn't fit in the vectors being permuted. E.g. a permute on two V256QIs can't be done using a V256QI selector. At the moment constant permutes use two interfaces: targetm.vectorizer.vec_perm_const_ok for testing whether a permute is valid and the vec_perm_const optab for actually emitting the permute. The former gets passed a vec<> selector and the latter an rtx selector. Most ports share a lot of code between the hook and the optab, with a wrapper function for each interface. We could try to keep that interface and require ports to define wider vector modes that could be attached to the CONST_VECTOR (e.g. V256HI or V256SI in the example above). But building a CONST_VECTOR rtx seems a bit pointless here, since the expand code only creates the CONST_VECTOR in order to call the optab, and the first thing the target does is take the CONST_VECTOR apart again. The easiest approach therefore seemed to be to remove the optab and reuse the target hook to emit the code. One potential drawback is that it's no longer possible to use match_operand predicates to force operands into the required form, but in practice all targets want register operands anyway. The patch also changes vec_perm_indices into a class that provides some simple routines for handling permutations. A later patch will flesh this out and get rid of auto_vec_perm_indices, but I didn't want to do all that in this patch and make it more complicated than it already is. 2017-12-09 Richard Sandiford gcc/ * Makefile.in (OBJS): Add vec-perm-indices.o. * vec-perm-indices.h: New file. * vec-perm-indices.c: Likewise. * target.h (vec_perm_indices): Replace with a forward class declaration. (auto_vec_perm_indices): Move to vec-perm-indices.h. * optabs.h: Include vec-perm-indices.h. (expand_vec_perm): Delete. (selector_fits_mode_p, expand_vec_perm_var): Declare. (expand_vec_perm_const): Declare. * target.def (vec_perm_const_ok): Replace with... (vec_perm_const): ...this new hook. * doc/tm.texi.in (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Replace with... (TARGET_VECTORIZE_VEC_PERM_CONST): ...this new hook. * doc/tm.texi: Regenerate. * optabs.def (vec_perm_const): Delete. * doc/md.texi (vec_perm_const): Likewise. (vec_perm): Refer to TARGET_VECTORIZE_VEC_PERM_CONST. * expr.c (expand_expr_real_2): Use expand_vec_perm_const rather than expand_vec_perm for constant permutation vectors. Assert that the mode of variable permutation vectors is the integer equivalent of the mode that is being permuted. * optabs-query.h (selector_fits_mode_p): Declare. * optabs-query.c: Include vec-perm-indices.h. (can_vec_perm_const_p): Check whether targetm.vectorize.vec_perm_const is defined, instead of checking whether the vec_perm_const_optab exists. Use targetm.vectorize.vec_perm_const instead of targetm.vectorize.vec_perm_const_ok. Check whether the indices fit in the vector mode before using a variable permute. * optabs.c (shift_amt_for_vec_perm_mask): Take a mode and a vec_perm_indices instead of an rtx. (expand_vec_perm): Replace with... (expand_vec_perm_const): ...this new function. Take the selector as a vec_perm_indices rather than an rtx. Also take the mode of the selector. Update call to shift_amt_for_vec_perm_mask. Use targetm.vectorize.vec_perm_const instead of vec_perm_const_optab. Use vec_perm_indices::new_expanded_vector to expand the original selector into bytes. Check whether the indices fit in the vector mode before using a variable permute. (expand_vec_perm_var): Make global. (expand_mult_highpart): Use expand_vec_perm_const. * fold-const.c: Includes vec-perm-indices.h. * tree-ssa-forwprop.c: Likewise. * tree-vect-data-refs.c: Likewise. * tree-vect-generic.c: Likewise. * tree-vect-loop.c: Likewise. * tree-vect-slp.c: Likewise. * tree-vect-stmts.c: Likewise. * config/aarch64/aarch64-protos.h (aarch64_expand_vec_perm_const): Delete. * config/aarch64/aarch64-simd.md (vec_perm_const): Delete. * config/aarch64/aarch64.c (aarch64_expand_vec_perm_const) (aarch64_vectorize_vec_perm_const_ok): Fuse into... (aarch64_vectorize_vec_perm_const): ...this new function. (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Delete. (TARGET_VECTORIZE_VEC_PERM_CONST): Redefine. * config/arm/arm-protos.h (arm_expand_vec_perm_const): Delete. * config/arm/vec-common.md (vec_perm_const): Delete. * config/arm/arm.c (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Delete. (TARGET_VECTORIZE_VEC_PERM_CONST): Redefine. (arm_expand_vec_perm_const, arm_vectorize_vec_perm_const_ok): Merge into... (arm_vectorize_vec_perm_const): ...this new function. Explicitly check for NEON modes. * config/i386/i386-protos.h (ix86_expand_vec_perm_const): Delete. * config/i386/sse.md (VEC_PERM_CONST, vec_perm_const): Delete. * config/i386/i386.c (ix86_expand_vec_perm_const_1): Update comment. (ix86_expand_vec_perm_const, ix86_vectorize_vec_perm_const_ok): Merge into... (ix86_vectorize_vec_perm_const): ...this new function. Incorporate the old VEC_PERM_CONST conditions. * config/ia64/ia64-protos.h (ia64_expand_vec_perm_const): Delete. * config/ia64/vect.md (vec_perm_const): Delete. * config/ia64/ia64.c (ia64_expand_vec_perm_const) (ia64_vectorize_vec_perm_const_ok): Merge into... (ia64_vectorize_vec_perm_const): ...this new function. * config/mips/loongson.md (vec_perm_const): Delete. * config/mips/mips-msa.md (vec_perm_const): Delete. * config/mips/mips-ps-3d.md (vec_perm_constv2sf): Delete. * config/mips/mips-protos.h (mips_expand_vec_perm_const): Delete. * config/mips/mips.c (mips_expand_vec_perm_const) (mips_vectorize_vec_perm_const_ok): Merge into... (mips_vectorize_vec_perm_const): ...this new function. * config/powerpcspe/altivec.md (vec_perm_constv16qi): Delete. * config/powerpcspe/paired.md (vec_perm_constv2sf): Delete. * config/powerpcspe/spe.md (vec_perm_constv2si): Delete. * config/powerpcspe/vsx.md (vec_perm_const): Delete. * config/powerpcspe/powerpcspe-protos.h (altivec_expand_vec_perm_const) (rs6000_expand_vec_perm_const): Delete. * config/powerpcspe/powerpcspe.c (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Delete. (TARGET_VECTORIZE_VEC_PERM_CONST): Redefine. (altivec_expand_vec_perm_const_le): Take each operand individually. Operate on constant selectors rather than rtxes. (altivec_expand_vec_perm_const): Likewise. Update call to altivec_expand_vec_perm_const_le. (rs6000_expand_vec_perm_const): Delete. (rs6000_vectorize_vec_perm_const_ok): Delete. (rs6000_vectorize_vec_perm_const): New function. (rs6000_do_expand_vec_perm): Take a vec_perm_builder instead of an element count and rtx array. (rs6000_expand_extract_even): Update call accordingly. (rs6000_expand_interleave): Likewise. * config/rs6000/altivec.md (vec_perm_constv16qi): Delete. * config/rs6000/paired.md (vec_perm_constv2sf): Delete. * config/rs6000/vsx.md (vec_perm_const): Delete. * config/rs6000/rs6000-protos.h (altivec_expand_vec_perm_const) (rs6000_expand_vec_perm_const): Delete. * config/rs6000/rs6000.c (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Delete. (TARGET_VECTORIZE_VEC_PERM_CONST): Redefine. (altivec_expand_vec_perm_const_le): Take each operand individually. Operate on constant selectors rather than rtxes. (altivec_expand_vec_perm_const): Likewise. Update call to altivec_expand_vec_perm_const_le. (rs6000_expand_vec_perm_const): Delete. (rs6000_vectorize_vec_perm_const_ok): Delete. (rs6000_vectorize_vec_perm_const): New function. Remove stray reference to the SPE evmerge intructions. (rs6000_do_expand_vec_perm): Take a vec_perm_builder instead of an element count and rtx array. (rs6000_expand_extract_even): Update call accordingly. (rs6000_expand_interleave): Likewise. * config/sparc/sparc.md (vec_perm_constv8qi): Delete in favor of... * config/sparc/sparc.c (sparc_vectorize_vec_perm_const): ...this new function. (TARGET_VECTORIZE_VEC_PERM_CONST): Redefine. Index: gcc/Makefile.in =================================================================== --- gcc/Makefile.in 2017-12-09 22:47:09.549486911 +0000 +++ gcc/Makefile.in 2017-12-09 22:47:27.854318082 +0000 @@ -1584,6 +1584,7 @@ OBJS = \ var-tracking.o \ varasm.o \ varpool.o \ + vec-perm-indices.o \ vmsdbgout.o \ vr-values.o \ vtable-verify.o \ Index: gcc/vec-perm-indices.h =================================================================== --- /dev/null 2017-12-09 13:59:56.352713187 +0000 +++ gcc/vec-perm-indices.h 2017-12-09 22:47:27.885318101 +0000 @@ -0,0 +1,49 @@ +/* A representation of vector permutation indices. + Copyright (C) 2017 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef GCC_VEC_PERN_INDICES_H +#define GCC_VEC_PERN_INDICES_H 1 + +/* This class represents a constant permutation vector, such as that used + as the final operand to a VEC_PERM_EXPR. */ +class vec_perm_indices : public auto_vec +{ + typedef unsigned short element_type; + typedef auto_vec parent_type; + +public: + vec_perm_indices () {} + vec_perm_indices (unsigned int nunits) : parent_type (nunits) {} + + void new_expanded_vector (const vec_perm_indices &, unsigned int); + + bool all_in_range_p (element_type, element_type) const; + +private: + vec_perm_indices (const vec_perm_indices &); +}; + +/* Temporary. */ +typedef vec_perm_indices vec_perm_builder; +typedef vec_perm_indices auto_vec_perm_indices; + +bool tree_to_vec_perm_builder (vec_perm_builder *, tree); +rtx vec_perm_indices_to_rtx (machine_mode, const vec_perm_indices &); + +#endif Index: gcc/vec-perm-indices.c =================================================================== --- /dev/null 2017-12-09 13:59:56.352713187 +0000 +++ gcc/vec-perm-indices.c 2017-12-09 22:47:27.885318101 +0000 @@ -0,0 +1,93 @@ +/* A representation of vector permutation indices. + Copyright (C) 2017 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "vec-perm-indices.h" +#include "tree.h" +#include "backend.h" +#include "rtl.h" +#include "memmodel.h" +#include "emit-rtl.h" + +/* Switch to a new permutation vector that selects the same input elements + as ORIG, but with each element split into FACTOR pieces. For example, + if ORIG is { 1, 2, 0, 3 } and FACTOR is 2, the new permutation is + { 2, 3, 4, 5, 0, 1, 6, 7 }. */ + +void +vec_perm_indices::new_expanded_vector (const vec_perm_indices &orig, + unsigned int factor) +{ + truncate (0); + reserve (orig.length () * factor); + for (unsigned int i = 0; i < orig.length (); ++i) + { + element_type base = orig[i] * factor; + for (unsigned int j = 0; j < factor; ++j) + quick_push (base + j); + } +} + +/* Return true if all elements of the permutation vector are in the range + [START, START + SIZE). */ + +bool +vec_perm_indices::all_in_range_p (element_type start, element_type size) const +{ + for (unsigned int i = 0; i < length (); ++i) + if ((*this)[i] < start || ((*this)[i] - start) >= size) + return false; + return true; +} + +/* Try to read the contents of VECTOR_CST CST as a constant permutation + vector. Return true and add the elements to BUILDER on success, + otherwise return false without modifying BUILDER. */ + +bool +tree_to_vec_perm_builder (vec_perm_builder *builder, tree cst) +{ + unsigned int nelts = TYPE_VECTOR_SUBPARTS (TREE_TYPE (cst)); + for (unsigned int i = 0; i < nelts; ++i) + if (!tree_fits_shwi_p (vector_cst_elt (cst, i))) + return false; + + builder->reserve (nelts); + for (unsigned int i = 0; i < nelts; ++i) + builder->quick_push (tree_to_shwi (vector_cst_elt (cst, i)) + & (2 * nelts - 1)); + return true; +} + +/* Return a CONST_VECTOR of mode MODE that contains the elements of + INDICES. */ + +rtx +vec_perm_indices_to_rtx (machine_mode mode, const vec_perm_indices &indices) +{ + gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT + && GET_MODE_NUNITS (mode) == indices.length ()); + unsigned int nelts = indices.length (); + rtvec v = rtvec_alloc (nelts); + for (unsigned int i = 0; i < nelts; ++i) + RTVEC_ELT (v, i) = gen_int_mode (indices[i], GET_MODE_INNER (mode)); + return gen_rtx_CONST_VECTOR (mode, v); +} Index: gcc/target.h =================================================================== --- gcc/target.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/target.h 2017-12-09 22:47:27.882318099 +0000 @@ -193,13 +193,7 @@ enum vect_cost_model_location { vect_epilogue = 2 }; -/* The type to use for vector permutes with a constant permute vector. - Each entry is an index into the concatenated input vectors. */ -typedef vec vec_perm_indices; - -/* Same, but can be used to construct local permute vectors that are - automatically freed. */ -typedef auto_vec auto_vec_perm_indices; +class vec_perm_indices; /* The target structure. This holds all the backend hooks. */ #define DEFHOOKPOD(NAME, DOC, TYPE, INIT) TYPE NAME; Index: gcc/optabs.h =================================================================== --- gcc/optabs.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/optabs.h 2017-12-09 22:47:27.882318099 +0000 @@ -22,6 +22,7 @@ #define GCC_OPTABS_H #include "optabs-query.h" #include "optabs-libfuncs.h" +#include "vec-perm-indices.h" /* Generate code for a widening multiply. */ extern rtx expand_widening_mult (machine_mode, rtx, rtx, rtx, int, optab); @@ -307,7 +308,9 @@ extern int have_insn_for (enum rtx_code, extern rtx_insn *gen_cond_trap (enum rtx_code, rtx, rtx, rtx); /* Generate code for VEC_PERM_EXPR. */ -extern rtx expand_vec_perm (machine_mode, rtx, rtx, rtx, rtx); +extern rtx expand_vec_perm_var (machine_mode, rtx, rtx, rtx, rtx); +extern rtx expand_vec_perm_const (machine_mode, rtx, rtx, + const vec_perm_builder &, machine_mode, rtx); /* Generate code for vector comparison. */ extern rtx expand_vec_cmp_expr (tree, tree, rtx); Index: gcc/target.def =================================================================== --- gcc/target.def 2017-12-09 22:47:09.549486911 +0000 +++ gcc/target.def 2017-12-09 22:47:27.882318099 +0000 @@ -1841,12 +1841,27 @@ DEFHOOK bool, (const_tree type, bool is_packed), default_builtin_vector_alignment_reachable) -/* Return true if a vector created for vec_perm_const is valid. - A NULL indicates that all constants are valid permutations. */ DEFHOOK -(vec_perm_const_ok, - "Return true if a vector created for @code{vec_perm_const} is valid.", - bool, (machine_mode, vec_perm_indices), +(vec_perm_const, + "This hook is used to test whether the target can permute up to two\n\ +vectors of mode @var{mode} using the permutation vector @code{sel}, and\n\ +also to emit such a permutation. In the former case @var{in0}, @var{in1}\n\ +and @var{out} are all null. In the latter case @var{in0} and @var{in1} are\n\ +the source vectors and @var{out} is the destination vector; all three are\n\ +registers of mode @var{mode}. @var{in1} is the same as @var{in0} if\n\ +@var{sel} describes a permutation on one vector instead of two.\n\ +\n\ +Return true if the operation is possible, emitting instructions for it\n\ +if rtxes are provided.\n\ +\n\ +@cindex @code{vec_perm@var{m}} instruction pattern\n\ +If the hook returns false for a mode with multibyte elements, GCC will\n\ +try the equivalent byte operation. If that also fails, it will try forcing\n\ +the selector into a register and using the @var{vec_perm@var{mode}}\n\ +instruction pattern. There is no need for the hook to handle these two\n\ +implementation approaches itself.", + bool, (machine_mode mode, rtx output, rtx in0, rtx in1, + const vec_perm_indices &sel), NULL) /* Return true if the target supports misaligned store/load of a Index: gcc/doc/tm.texi.in =================================================================== --- gcc/doc/tm.texi.in 2017-12-09 22:47:09.549486911 +0000 +++ gcc/doc/tm.texi.in 2017-12-09 22:47:27.879318098 +0000 @@ -4079,7 +4079,7 @@ address; but often a machine-dependent @hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE -@hook TARGET_VECTORIZE_VEC_PERM_CONST_OK +@hook TARGET_VECTORIZE_VEC_PERM_CONST @hook TARGET_VECTORIZE_BUILTIN_CONVERSION Index: gcc/doc/tm.texi =================================================================== --- gcc/doc/tm.texi 2017-12-09 22:47:09.549486911 +0000 +++ gcc/doc/tm.texi 2017-12-09 22:47:27.878318097 +0000 @@ -5798,8 +5798,24 @@ correct for most targets. Return true if vector alignment is reachable (by peeling N iterations) for the given scalar type @var{type}. @var{is_packed} is false if the scalar access using @var{type} is known to be naturally aligned. @end deftypefn -@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST_OK (machine_mode, @var{vec_perm_indices}) -Return true if a vector created for @code{vec_perm_const} is valid. +@deftypefn {Target Hook} bool TARGET_VECTORIZE_VEC_PERM_CONST (machine_mode @var{mode}, rtx @var{output}, rtx @var{in0}, rtx @var{in1}, const vec_perm_indices @var{&sel}) +This hook is used to test whether the target can permute up to two +vectors of mode @var{mode} using the permutation vector @code{sel}, and +also to emit such a permutation. In the former case @var{in0}, @var{in1} +and @var{out} are all null. In the latter case @var{in0} and @var{in1} are +the source vectors and @var{out} is the destination vector; all three are +registers of mode @var{mode}. @var{in1} is the same as @var{in0} if +@var{sel} describes a permutation on one vector instead of two. + +Return true if the operation is possible, emitting instructions for it +if rtxes are provided. + +@cindex @code{vec_perm@var{m}} instruction pattern +If the hook returns false for a mode with multibyte elements, GCC will +try the equivalent byte operation. If that also fails, it will try forcing +the selector into a register and using the @var{vec_perm@var{mode}} +instruction pattern. There is no need for the hook to handle these two +implementation approaches itself. @end deftypefn @deftypefn {Target Hook} tree TARGET_VECTORIZE_BUILTIN_CONVERSION (unsigned @var{code}, tree @var{dest_type}, tree @var{src_type}) Index: gcc/optabs.def =================================================================== --- gcc/optabs.def 2017-12-09 22:47:09.549486911 +0000 +++ gcc/optabs.def 2017-12-09 22:47:27.882318099 +0000 @@ -302,7 +302,6 @@ OPTAB_D (vec_pack_ssat_optab, "vec_pack_ OPTAB_D (vec_pack_trunc_optab, "vec_pack_trunc_$a") OPTAB_D (vec_pack_ufix_trunc_optab, "vec_pack_ufix_trunc_$a") OPTAB_D (vec_pack_usat_optab, "vec_pack_usat_$a") -OPTAB_D (vec_perm_const_optab, "vec_perm_const$a") OPTAB_D (vec_perm_optab, "vec_perm$a") OPTAB_D (vec_realign_load_optab, "vec_realign_load_$a") OPTAB_D (vec_set_optab, "vec_set$a") Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi 2017-12-09 22:47:09.549486911 +0000 +++ gcc/doc/md.texi 2017-12-09 22:47:27.877318096 +0000 @@ -4972,20 +4972,8 @@ where @var{q} is a vector of @code{QImod the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to mode @var{q}. -@cindex @code{vec_perm_const@var{m}} instruction pattern -@item @samp{vec_perm_const@var{m}} -Like @samp{vec_perm} except that the permutation is a compile-time -constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}. - -Some targets cannot perform a permutation with a variable selector, -but can efficiently perform a constant permutation. Further, the -target hook @code{vec_perm_ok} is queried to determine if the -specific constant permutation is available efficiently; the named -pattern is never expanded without @code{vec_perm_ok} returning true. - -There is no need for a target to supply both @samp{vec_perm@var{m}} -and @samp{vec_perm_const@var{m}} if the former can trivially implement -the operation with, say, the vector constant loaded into a register. +See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs +the analogous operation for constant selectors. @cindex @code{push@var{m}1} instruction pattern @item @samp{push@var{m}1} Index: gcc/expr.c =================================================================== --- gcc/expr.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/expr.c 2017-12-09 22:47:27.880318098 +0000 @@ -9439,28 +9439,24 @@ #define REDUCE_BIT_FIELD(expr) (reduce_b goto binop; case VEC_PERM_EXPR: - expand_operands (treeop0, treeop1, target, &op0, &op1, EXPAND_NORMAL); - op2 = expand_normal (treeop2); - - /* Careful here: if the target doesn't support integral vector modes, - a constant selection vector could wind up smooshed into a normal - integral constant. */ - if (CONSTANT_P (op2) && !VECTOR_MODE_P (GET_MODE (op2))) - { - tree sel_type = TREE_TYPE (treeop2); - machine_mode vmode - = mode_for_vector (SCALAR_TYPE_MODE (TREE_TYPE (sel_type)), - TYPE_VECTOR_SUBPARTS (sel_type)).require (); - gcc_assert (GET_MODE_CLASS (vmode) == MODE_VECTOR_INT); - op2 = simplify_subreg (vmode, op2, TYPE_MODE (sel_type), 0); - gcc_assert (op2 && GET_CODE (op2) == CONST_VECTOR); - } - else - gcc_assert (GET_MODE_CLASS (GET_MODE (op2)) == MODE_VECTOR_INT); - - temp = expand_vec_perm (mode, op0, op1, op2, target); - gcc_assert (temp); - return temp; + { + expand_operands (treeop0, treeop1, target, &op0, &op1, EXPAND_NORMAL); + vec_perm_builder sel; + if (TREE_CODE (treeop2) == VECTOR_CST + && tree_to_vec_perm_builder (&sel, treeop2)) + { + machine_mode sel_mode = TYPE_MODE (TREE_TYPE (treeop2)); + temp = expand_vec_perm_const (mode, op0, op1, sel, + sel_mode, target); + } + else + { + op2 = expand_normal (treeop2); + temp = expand_vec_perm_var (mode, op0, op1, op2, target); + } + gcc_assert (temp); + return temp; + } case DOT_PROD_EXPR: { Index: gcc/optabs-query.h =================================================================== --- gcc/optabs-query.h 2017-12-09 22:47:21.534314227 +0000 +++ gcc/optabs-query.h 2017-12-09 22:47:27.881318099 +0000 @@ -175,6 +175,7 @@ enum insn_code can_float_p (machine_mode enum insn_code can_fix_p (machine_mode, machine_mode, int, bool *); bool can_conditionally_move_p (machine_mode mode); opt_machine_mode qimode_for_vec_perm (machine_mode); +bool selector_fits_mode_p (machine_mode, const vec_perm_indices &); bool can_vec_perm_var_p (machine_mode); bool can_vec_perm_const_p (machine_mode, const vec_perm_indices &, bool = true); Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:47:25.861316866 +0000 +++ gcc/optabs-query.c 2017-12-09 22:47:27.881318099 +0000 @@ -28,6 +28,7 @@ Software Foundation; either version 3, o #include "insn-config.h" #include "rtl.h" #include "recog.h" +#include "vec-perm-indices.h" struct target_optabs default_target_optabs; struct target_optabs *this_fn_optabs = &default_target_optabs; @@ -361,6 +362,17 @@ qimode_for_vec_perm (machine_mode mode) return opt_machine_mode (); } +/* Return true if selector SEL can be represented in the integer + equivalent of vector mode MODE. */ + +bool +selector_fits_mode_p (machine_mode mode, const vec_perm_indices &sel) +{ + unsigned HOST_WIDE_INT mask = GET_MODE_MASK (GET_MODE_INNER (mode)); + return (mask == HOST_WIDE_INT_M1U + || sel.all_in_range_p (0, mask + 1)); +} + /* Return true if VEC_PERM_EXPRs with variable selector operands can be expanded using SIMD extensions of the CPU. MODE is the mode of the vectors being permuted. */ @@ -416,18 +428,22 @@ can_vec_perm_const_p (machine_mode mode, return false; /* It's probably cheaper to test for the variable case first. */ - if (allow_variable_p && can_vec_perm_var_p (mode)) + if (allow_variable_p + && selector_fits_mode_p (mode, sel) + && can_vec_perm_var_p (mode)) return true; - if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing) + if (targetm.vectorize.vec_perm_const != NULL) { - if (targetm.vectorize.vec_perm_const_ok == NULL - || targetm.vectorize.vec_perm_const_ok (mode, sel)) + if (targetm.vectorize.vec_perm_const (mode, NULL_RTX, NULL_RTX, + NULL_RTX, sel)) return true; /* ??? For completeness, we ought to check the QImode version of vec_perm_const_optab. But all users of this implicit lowering - feature implement the variable vec_perm_optab. */ + feature implement the variable vec_perm_optab, and the ia64 + port specifically doesn't want us to lower V2SF operations + into integer operations. */ } return false; Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:47:25.861316866 +0000 +++ gcc/optabs.c 2017-12-09 22:47:27.881318099 +0000 @@ -5367,25 +5367,23 @@ vector_compare_rtx (machine_mode cmp_mod return gen_rtx_fmt_ee (rcode, cmp_mode, ops[0].value, ops[1].value); } -/* Checks if vec_perm mask SEL is a constant equivalent to a shift of the first - vec_perm operand, assuming the second operand is a constant vector of zeroes. - Return the shift distance in bits if so, or NULL_RTX if the vec_perm is not a - shift. */ +/* Check if vec_perm mask SEL is a constant equivalent to a shift of + the first vec_perm operand, assuming the second operand is a constant + vector of zeros. Return the shift distance in bits if so, or NULL_RTX + if the vec_perm is not a shift. MODE is the mode of the value being + shifted. */ static rtx -shift_amt_for_vec_perm_mask (rtx sel) +shift_amt_for_vec_perm_mask (machine_mode mode, const vec_perm_indices &sel) { - unsigned int i, first, nelt = GET_MODE_NUNITS (GET_MODE (sel)); - unsigned int bitsize = GET_MODE_UNIT_BITSIZE (GET_MODE (sel)); + unsigned int i, first, nelt = GET_MODE_NUNITS (mode); + unsigned int bitsize = GET_MODE_UNIT_BITSIZE (mode); - if (GET_CODE (sel) != CONST_VECTOR) - return NULL_RTX; - - first = INTVAL (CONST_VECTOR_ELT (sel, 0)); + first = sel[0]; if (first >= nelt) return NULL_RTX; for (i = 1; i < nelt; i++) { - int idx = INTVAL (CONST_VECTOR_ELT (sel, i)); + int idx = sel[i]; unsigned int expected = i + first; /* Indices into the second vector are all equivalent. */ if (idx < 0 || (MIN (nelt, (unsigned) idx) != MIN (nelt, expected))) @@ -5395,7 +5393,7 @@ shift_amt_for_vec_perm_mask (rtx sel) return GEN_INT (first * bitsize); } -/* A subroutine of expand_vec_perm for expanding one vec_perm insn. */ +/* A subroutine of expand_vec_perm_var for expanding one vec_perm insn. */ static rtx expand_vec_perm_1 (enum insn_code icode, rtx target, @@ -5433,38 +5431,32 @@ expand_vec_perm_1 (enum insn_code icode, return NULL_RTX; } -static rtx expand_vec_perm_var (machine_mode, rtx, rtx, rtx, rtx); - /* Implement a permutation of vectors v0 and v1 using the permutation vector in SEL and return the result. Use TARGET to hold the result if nonnull and convenient. - MODE is the mode of the vectors being permuted (V0 and V1). */ + MODE is the mode of the vectors being permuted (V0 and V1). SEL_MODE + is the TYPE_MODE associated with SEL, or BLKmode if SEL isn't known + to have a particular mode. */ rtx -expand_vec_perm (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) +expand_vec_perm_const (machine_mode mode, rtx v0, rtx v1, + const vec_perm_builder &sel, machine_mode sel_mode, + rtx target) { - enum insn_code icode; - machine_mode qimode; - unsigned int i, w, e, u; - rtx tmp, sel_qi = NULL; - rtvec vec; - - if (GET_CODE (sel) != CONST_VECTOR) - return expand_vec_perm_var (mode, v0, v1, sel, target); - - if (!target || GET_MODE (target) != mode) + if (!target || !register_operand (target, mode)) target = gen_reg_rtx (mode); - w = GET_MODE_SIZE (mode); - e = GET_MODE_NUNITS (mode); - u = GET_MODE_UNIT_SIZE (mode); - /* Set QIMODE to a different vector mode with byte elements. If no such mode, or if MODE already has byte elements, use VOIDmode. */ + machine_mode qimode; if (!qimode_for_vec_perm (mode).exists (&qimode)) qimode = VOIDmode; + rtx_insn *last = get_last_insn (); + + bool single_arg_p = rtx_equal_p (v0, v1); + /* See if this can be handled with a vec_shr. We only do this if the second vector is all zeroes. */ insn_code shift_code = optab_handler (vec_shr_optab, mode); @@ -5476,7 +5468,7 @@ expand_vec_perm (machine_mode mode, rtx && (shift_code != CODE_FOR_nothing || shift_code_qi != CODE_FOR_nothing)) { - rtx shift_amt = shift_amt_for_vec_perm_mask (sel); + rtx shift_amt = shift_amt_for_vec_perm_mask (mode, sel); if (shift_amt) { struct expand_operand ops[3]; @@ -5500,65 +5492,81 @@ expand_vec_perm (machine_mode mode, rtx } } - icode = direct_optab_handler (vec_perm_const_optab, mode); - if (icode != CODE_FOR_nothing) + if (targetm.vectorize.vec_perm_const != NULL) { - tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); - if (tmp) - return tmp; + v0 = force_reg (mode, v0); + if (single_arg_p) + v1 = v0; + else + v1 = force_reg (mode, v1); + + if (targetm.vectorize.vec_perm_const (mode, target, v0, v1, sel)) + return target; } /* Fall back to a constant byte-based permutation. */ + vec_perm_indices qimode_indices; + rtx target_qi = NULL_RTX, v0_qi = NULL_RTX, v1_qi = NULL_RTX; if (qimode != VOIDmode) { - vec = rtvec_alloc (w); - for (i = 0; i < e; ++i) - { - unsigned int j, this_e; + qimode_indices.new_expanded_vector (sel, GET_MODE_UNIT_SIZE (mode)); + target_qi = gen_reg_rtx (qimode); + v0_qi = gen_lowpart (qimode, v0); + v1_qi = gen_lowpart (qimode, v1); + if (targetm.vectorize.vec_perm_const != NULL + && targetm.vectorize.vec_perm_const (qimode, target_qi, v0_qi, + v1_qi, qimode_indices)) + return gen_lowpart (mode, target_qi); + } - this_e = INTVAL (CONST_VECTOR_ELT (sel, i)); - this_e &= 2 * e - 1; - this_e *= u; + /* Otherwise expand as a fully variable permuation. */ - for (j = 0; j < u; ++j) - RTVEC_ELT (vec, i * u + j) = GEN_INT (this_e + j); - } - sel_qi = gen_rtx_CONST_VECTOR (qimode, vec); + /* The optabs are only defined for selectors with the same width + as the values being permuted. */ + machine_mode required_sel_mode; + if (!mode_for_int_vector (mode).exists (&required_sel_mode) + || !VECTOR_MODE_P (required_sel_mode)) + { + delete_insns_since (last); + return NULL_RTX; + } - icode = direct_optab_handler (vec_perm_const_optab, qimode); - if (icode != CODE_FOR_nothing) + /* We know that it is semantically valid to treat SEL as having SEL_MODE. + If that isn't the mode we want then we need to prove that using + REQUIRED_SEL_MODE is OK. */ + if (sel_mode != required_sel_mode) + { + if (!selector_fits_mode_p (required_sel_mode, sel)) { - tmp = gen_reg_rtx (qimode); - tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), - gen_lowpart (qimode, v1), sel_qi); - if (tmp) - return gen_lowpart (mode, tmp); + delete_insns_since (last); + return NULL_RTX; } + sel_mode = required_sel_mode; } - /* Otherwise expand as a fully variable permuation. */ - - icode = direct_optab_handler (vec_perm_optab, mode); + insn_code icode = direct_optab_handler (vec_perm_optab, mode); if (icode != CODE_FOR_nothing) { - rtx tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); + rtx sel_rtx = vec_perm_indices_to_rtx (sel_mode, sel); + rtx tmp = expand_vec_perm_1 (icode, target, v0, v1, sel_rtx); if (tmp) return tmp; } - if (qimode != VOIDmode) + if (qimode != VOIDmode + && selector_fits_mode_p (qimode, qimode_indices)) { icode = direct_optab_handler (vec_perm_optab, qimode); if (icode != CODE_FOR_nothing) { - rtx tmp = gen_reg_rtx (qimode); - tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), - gen_lowpart (qimode, v1), sel_qi); + rtx sel_qi = vec_perm_indices_to_rtx (qimode, qimode_indices); + rtx tmp = expand_vec_perm_1 (icode, target_qi, v0_qi, v1_qi, sel_qi); if (tmp) return gen_lowpart (mode, tmp); } } + delete_insns_since (last); return NULL_RTX; } @@ -5570,7 +5578,7 @@ expand_vec_perm (machine_mode mode, rtx SEL must have the integer equivalent of MODE and is known to be unsuitable for permutes with a constant permutation vector. */ -static rtx +rtx expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) { enum insn_code icode; @@ -5613,17 +5621,16 @@ expand_vec_perm_var (machine_mode mode, gcc_assert (sel != NULL); /* Broadcast the low byte each element into each of its bytes. */ - vec = rtvec_alloc (w); + vec_perm_builder const_sel (w); for (i = 0; i < w; ++i) { int this_e = i / u * u; if (BYTES_BIG_ENDIAN) this_e += u - 1; - RTVEC_ELT (vec, i) = GEN_INT (this_e); + const_sel.quick_push (this_e); } - tmp = gen_rtx_CONST_VECTOR (qimode, vec); sel = gen_lowpart (qimode, sel); - sel = expand_vec_perm (qimode, sel, sel, tmp, NULL); + sel = expand_vec_perm_const (qimode, sel, sel, const_sel, qimode, NULL); gcc_assert (sel != NULL); /* Add the byte offset to each byte element. */ @@ -5797,9 +5804,8 @@ expand_mult_highpart (machine_mode mode, enum insn_code icode; int method, i, nunits; machine_mode wmode; - rtx m1, m2, perm; + rtx m1, m2; optab tab1, tab2; - rtvec v; method = can_mult_highpart_p (mode, uns_p); switch (method) @@ -5842,21 +5848,20 @@ expand_mult_highpart (machine_mode mode, expand_insn (optab_handler (tab2, mode), 3, eops); m2 = gen_lowpart (mode, eops[0].value); - v = rtvec_alloc (nunits); + auto_vec_perm_indices sel (nunits); if (method == 2) { for (i = 0; i < nunits; ++i) - RTVEC_ELT (v, i) = GEN_INT (!BYTES_BIG_ENDIAN + (i & ~1) - + ((i & 1) ? nunits : 0)); - perm = gen_rtx_CONST_VECTOR (mode, v); + sel.quick_push (!BYTES_BIG_ENDIAN + (i & ~1) + + ((i & 1) ? nunits : 0)); } else { - int base = BYTES_BIG_ENDIAN ? 0 : 1; - perm = gen_const_vec_series (mode, GEN_INT (base), GEN_INT (2)); + for (i = 0; i < nunits; ++i) + sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); } - return expand_vec_perm (mode, m1, m2, perm, target); + return expand_vec_perm_const (mode, m1, m2, sel, BLKmode, target); } /* Helper function to find the MODE_CC set in a sync_compare_and_swap Index: gcc/fold-const.c =================================================================== --- gcc/fold-const.c 2017-12-09 22:47:21.534314227 +0000 +++ gcc/fold-const.c 2017-12-09 22:47:27.881318099 +0000 @@ -82,6 +82,7 @@ Software Foundation; either version 3, o #include "stringpool.h" #include "attribs.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" /* Nonzero if we are folding constants inside an initializer; zero otherwise. */ Index: gcc/tree-ssa-forwprop.c =================================================================== --- gcc/tree-ssa-forwprop.c 2017-12-09 22:47:21.534314227 +0000 +++ gcc/tree-ssa-forwprop.c 2017-12-09 22:47:27.883318100 +0000 @@ -47,6 +47,7 @@ the Free Software Foundation; either ver #include "cfganal.h" #include "optabs-tree.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" /* This pass propagates the RHS of assignment statements into use sites of the LHS of the assignment. It's basically a specialized Index: gcc/tree-vect-data-refs.c =================================================================== --- gcc/tree-vect-data-refs.c 2017-12-09 22:47:21.535314227 +0000 +++ gcc/tree-vect-data-refs.c 2017-12-09 22:47:27.883318100 +0000 @@ -52,6 +52,7 @@ Software Foundation; either version 3, o #include "params.h" #include "tree-cfg.h" #include "tree-hash-traits.h" +#include "vec-perm-indices.h" /* Return true if load- or store-lanes optab OPTAB is implemented for COUNT vectors of type VECTYPE. NAME is the name of OPTAB. */ Index: gcc/tree-vect-generic.c =================================================================== --- gcc/tree-vect-generic.c 2017-12-09 22:47:21.535314227 +0000 +++ gcc/tree-vect-generic.c 2017-12-09 22:47:27.883318100 +0000 @@ -38,6 +38,7 @@ Free Software Foundation; either version #include "gimplify.h" #include "tree-cfg.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" static void expand_vector_operations_1 (gimple_stmt_iterator *); Index: gcc/tree-vect-loop.c =================================================================== --- gcc/tree-vect-loop.c 2017-12-09 22:47:21.536314228 +0000 +++ gcc/tree-vect-loop.c 2017-12-09 22:47:27.884318101 +0000 @@ -52,6 +52,7 @@ Software Foundation; either version 3, o #include "tree-if-conv.h" #include "internal-fn.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" /* Loop Vectorization Pass. Index: gcc/tree-vect-slp.c =================================================================== --- gcc/tree-vect-slp.c 2017-12-09 22:47:21.536314228 +0000 +++ gcc/tree-vect-slp.c 2017-12-09 22:47:27.884318101 +0000 @@ -42,6 +42,7 @@ Software Foundation; either version 3, o #include "gimple-walk.h" #include "dbgcnt.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" /* Recursively free the memory allocated for the SLP tree rooted at NODE. */ Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:47:21.537314229 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:47:27.885318101 +0000 @@ -49,6 +49,7 @@ Software Foundation; either version 3, o #include "builtins.h" #include "internal-fn.h" #include "tree-vector-builder.h" +#include "vec-perm-indices.h" /* For lang_hooks.types.type_for_mode. */ #include "langhooks.h" Index: gcc/config/aarch64/aarch64-protos.h =================================================================== --- gcc/config/aarch64/aarch64-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/aarch64/aarch64-protos.h 2017-12-09 22:47:27.854318082 +0000 @@ -474,8 +474,6 @@ extern void aarch64_split_combinev16qi ( extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int); extern bool aarch64_madd_needs_nop (rtx_insn *); extern void aarch64_final_prescan_insn (rtx_insn *); -extern bool -aarch64_expand_vec_perm_const (rtx, rtx, rtx, rtx, unsigned int); void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); int aarch64_ccmp_mode_to_code (machine_mode mode); Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/aarch64/aarch64-simd.md 2017-12-09 22:47:27.854318082 +0000 @@ -5348,20 +5348,6 @@ (define_expand "aarch64_get_qreg" - [(match_operand:VALL_F16 0 "register_operand") - (match_operand:VALL_F16 1 "register_operand") - (match_operand:VALL_F16 2 "register_operand") - (match_operand: 3)] - "TARGET_SIMD" -{ - if (aarch64_expand_vec_perm_const (operands[0], operands[1], - operands[2], operands[3], )) - DONE; - else - FAIL; -}) - (define_expand "vec_perm" [(match_operand:VB 0 "register_operand") (match_operand:VB 1 "register_operand") Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/aarch64/aarch64.c 2017-12-09 22:47:27.856318084 +0000 @@ -141,8 +141,6 @@ static void aarch64_elf_asm_constructor static void aarch64_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED; static void aarch64_override_options_after_change (void); static bool aarch64_vector_mode_supported_p (machine_mode); -static bool aarch64_vectorize_vec_perm_const_ok (machine_mode, - vec_perm_indices); static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool); static bool aarch64_builtin_support_vector_misalignment (machine_mode mode, const_tree type, @@ -13626,29 +13624,27 @@ aarch64_expand_vec_perm_const_1 (struct return false; } -/* Expand a vec_perm_const pattern with the operands given by TARGET, - OP0, OP1 and SEL. NELT is the number of elements in the vector. */ +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ -bool -aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel, - unsigned int nelt) +static bool +aarch64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { struct expand_vec_perm_d d; unsigned int i, which; + d.vmode = vmode; d.target = target; d.op0 = op0; d.op1 = op1; + d.testing_p = !target; - d.vmode = GET_MODE (target); - gcc_assert (VECTOR_MODE_P (d.vmode)); - d.testing_p = false; - + /* Calculate whether all elements are in one vector. */ + unsigned int nelt = sel.length (); d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { - rtx e = XVECEXP (sel, 0, i); - unsigned int ei = INTVAL (e) & (2 * nelt - 1); + unsigned int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); d.perm.quick_push (ei); } @@ -13660,7 +13656,7 @@ aarch64_expand_vec_perm_const (rtx targe case 3: d.one_vector_p = false; - if (!rtx_equal_p (op0, op1)) + if (d.testing_p || !rtx_equal_p (op0, op1)) break; /* The elements of PERM do not suggest that only the first operand @@ -13681,37 +13677,8 @@ aarch64_expand_vec_perm_const (rtx targe break; } - return aarch64_expand_vec_perm_const_1 (&d); -} - -static bool -aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) -{ - struct expand_vec_perm_d d; - unsigned int i, nelt, which; - bool ret; - - d.vmode = vmode; - d.testing_p = true; - d.perm.safe_splice (sel); - - /* Calculate whether all elements are in one vector. */ - nelt = sel.length (); - for (i = which = 0; i < nelt; ++i) - { - unsigned int e = d.perm[i]; - gcc_assert (e < 2 * nelt); - which |= (e < nelt ? 1 : 2); - } - - /* If all elements are from the second vector, reindex as if from the - first vector. */ - if (which == 2) - for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; - - /* Check whether the mask can be applied to a single vector. */ - d.one_vector_p = (which != 3); + if (!d.testing_p) + return aarch64_expand_vec_perm_const_1 (&d); d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); @@ -13719,7 +13686,7 @@ aarch64_vectorize_vec_perm_const_ok (mac d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); start_sequence (); - ret = aarch64_expand_vec_perm_const_1 (&d); + bool ret = aarch64_expand_vec_perm_const_1 (&d); end_sequence (); return ret; @@ -15471,9 +15438,9 @@ #define TARGET_VECTORIZE_VECTOR_ALIGNMEN /* vec_perm support. */ -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ - aarch64_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST \ + aarch64_vectorize_vec_perm_const #undef TARGET_INIT_LIBFUNCS #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs Index: gcc/config/arm/arm-protos.h =================================================================== --- gcc/config/arm/arm-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/arm/arm-protos.h 2017-12-09 22:47:27.856318084 +0000 @@ -357,7 +357,6 @@ extern bool arm_validize_comparison (rtx extern bool arm_gen_setmem (rtx *); extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); -extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); extern bool arm_autoinc_modes_ok_p (machine_mode, enum arm_auto_incmodes); Index: gcc/config/arm/vec-common.md =================================================================== --- gcc/config/arm/vec-common.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/arm/vec-common.md 2017-12-09 22:47:27.858318085 +0000 @@ -109,35 +109,6 @@ (define_expand "umax3" { }) -(define_expand "vec_perm_const" - [(match_operand:VALL 0 "s_register_operand" "") - (match_operand:VALL 1 "s_register_operand" "") - (match_operand:VALL 2 "s_register_operand" "") - (match_operand: 3 "" "")] - "TARGET_NEON - || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))" -{ - if (arm_expand_vec_perm_const (operands[0], operands[1], - operands[2], operands[3])) - DONE; - else - FAIL; -}) - -(define_expand "vec_perm_const" - [(match_operand:VH 0 "s_register_operand") - (match_operand:VH 1 "s_register_operand") - (match_operand:VH 2 "s_register_operand") - (match_operand: 3)] - "TARGET_NEON" -{ - if (arm_expand_vec_perm_const (operands[0], operands[1], - operands[2], operands[3])) - DONE; - else - FAIL; -}) - (define_expand "vec_perm" [(match_operand:VE 0 "s_register_operand" "") (match_operand:VE 1 "s_register_operand" "") Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/arm/arm.c 2017-12-09 22:47:27.858318085 +0000 @@ -288,7 +288,8 @@ static int arm_cortex_a5_branch_cost (bo static int arm_cortex_m_branch_cost (bool, bool); static int arm_cortex_m7_branch_cost (bool, bool); -static bool arm_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices); +static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, + const vec_perm_indices &); static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*); @@ -734,9 +735,8 @@ #define TARGET_VECTORIZE_SUPPORT_VECTOR_ #define TARGET_PREFERRED_RENAME_CLASS \ arm_preferred_rename_class -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ - arm_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST arm_vectorize_vec_perm_const #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \ @@ -29381,28 +29381,31 @@ arm_expand_vec_perm_const_1 (struct expa return false; } -/* Expand a vec_perm_const pattern. */ +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ -bool -arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel) +static bool +arm_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { struct expand_vec_perm_d d; int i, nelt, which; + if (!VALID_NEON_DREG_MODE (vmode) && !VALID_NEON_QREG_MODE (vmode)) + return false; + d.target = target; d.op0 = op0; d.op1 = op1; - d.vmode = GET_MODE (target); + d.vmode = vmode; gcc_assert (VECTOR_MODE_P (d.vmode)); - d.testing_p = false; + d.testing_p = !target; nelt = GET_MODE_NUNITS (d.vmode); d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { - rtx e = XVECEXP (sel, 0, i); - int ei = INTVAL (e) & (2 * nelt - 1); + int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); d.perm.quick_push (ei); } @@ -29414,7 +29417,7 @@ arm_expand_vec_perm_const (rtx target, r case 3: d.one_vector_p = false; - if (!rtx_equal_p (op0, op1)) + if (d.testing_p || !rtx_equal_p (op0, op1)) break; /* The elements of PERM do not suggest that only the first operand @@ -29435,38 +29438,8 @@ arm_expand_vec_perm_const (rtx target, r break; } - return arm_expand_vec_perm_const_1 (&d); -} - -/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ - -static bool -arm_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) -{ - struct expand_vec_perm_d d; - unsigned int i, nelt, which; - bool ret; - - d.vmode = vmode; - d.testing_p = true; - d.perm.safe_splice (sel); - - /* Categorize the set of elements in the selector. */ - nelt = GET_MODE_NUNITS (d.vmode); - for (i = which = 0; i < nelt; ++i) - { - unsigned int e = d.perm[i]; - gcc_assert (e < 2 * nelt); - which |= (e < nelt ? 1 : 2); - } - - /* For all elements from second vector, fold the elements to first. */ - if (which == 2) - for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; - - /* Check whether the mask can be applied to the vector type. */ - d.one_vector_p = (which != 3); + if (d.testing_p) + return arm_expand_vec_perm_const_1 (&d); d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); @@ -29474,7 +29447,7 @@ arm_vectorize_vec_perm_const_ok (machine d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); start_sequence (); - ret = arm_expand_vec_perm_const_1 (&d); + bool ret = arm_expand_vec_perm_const_1 (&d); end_sequence (); return ret; Index: gcc/config/i386/i386-protos.h =================================================================== --- gcc/config/i386/i386-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/i386/i386-protos.h 2017-12-09 22:47:27.859318085 +0000 @@ -133,7 +133,6 @@ extern bool ix86_expand_fp_movcc (rtx[]) extern bool ix86_expand_fp_vcond (rtx[]); extern bool ix86_expand_int_vcond (rtx[]); extern void ix86_expand_vec_perm (rtx[]); -extern bool ix86_expand_vec_perm_const (rtx[]); extern bool ix86_expand_mask_vec_cmp (rtx[]); extern bool ix86_expand_int_vec_cmp (rtx[]); extern bool ix86_expand_fp_vec_cmp (rtx[]); Index: gcc/config/i386/sse.md =================================================================== --- gcc/config/i386/sse.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/i386/sse.md 2017-12-09 22:47:27.863318088 +0000 @@ -11476,30 +11476,6 @@ (define_expand "vec_perm" DONE; }) -(define_mode_iterator VEC_PERM_CONST - [(V4SF "TARGET_SSE") (V4SI "TARGET_SSE") - (V2DF "TARGET_SSE") (V2DI "TARGET_SSE") - (V16QI "TARGET_SSE2") (V8HI "TARGET_SSE2") - (V8SF "TARGET_AVX") (V4DF "TARGET_AVX") - (V8SI "TARGET_AVX") (V4DI "TARGET_AVX") - (V32QI "TARGET_AVX2") (V16HI "TARGET_AVX2") - (V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") - (V16SF "TARGET_AVX512F") (V8DF "TARGET_AVX512F") - (V32HI "TARGET_AVX512BW") (V64QI "TARGET_AVX512BW")]) - -(define_expand "vec_perm_const" - [(match_operand:VEC_PERM_CONST 0 "register_operand") - (match_operand:VEC_PERM_CONST 1 "register_operand") - (match_operand:VEC_PERM_CONST 2 "register_operand") - (match_operand: 3)] - "" -{ - if (ix86_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel bitwise logical operations Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/i386/i386.c 2017-12-09 22:47:27.862318087 +0000 @@ -47588,9 +47588,8 @@ expand_vec_perm_vpshufb4_vpermq2 (struct return true; } -/* The guts of ix86_expand_vec_perm_const, also used by the ok hook. - With all of the interface bits taken care of, perform the expansion - in D and return true on success. */ +/* The guts of ix86_vectorize_vec_perm_const. With all of the interface bits + taken care of, perform the expansion in D and return true on success. */ static bool ix86_expand_vec_perm_const_1 (struct expand_vec_perm_d *d) @@ -47725,69 +47724,29 @@ canonicalize_perm (struct expand_vec_per return (which == 3); } -bool -ix86_expand_vec_perm_const (rtx operands[4]) +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ + +static bool +ix86_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { struct expand_vec_perm_d d; unsigned char perm[MAX_VECT_LEN]; - int i, nelt; + unsigned int i, nelt, which; bool two_args; - rtx sel; - d.target = operands[0]; - d.op0 = operands[1]; - d.op1 = operands[2]; - sel = operands[3]; + d.target = target; + d.op0 = op0; + d.op1 = op1; - d.vmode = GET_MODE (d.target); + d.vmode = vmode; gcc_assert (VECTOR_MODE_P (d.vmode)); d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = false; + d.testing_p = !target; - gcc_assert (GET_CODE (sel) == CONST_VECTOR); - gcc_assert (XVECLEN (sel, 0) == nelt); + gcc_assert (sel.length () == nelt); gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); - for (i = 0; i < nelt; ++i) - { - rtx e = XVECEXP (sel, 0, i); - int ei = INTVAL (e) & (2 * nelt - 1); - d.perm[i] = ei; - perm[i] = ei; - } - - two_args = canonicalize_perm (&d); - - if (ix86_expand_vec_perm_const_1 (&d)) - return true; - - /* If the selector says both arguments are needed, but the operands are the - same, the above tried to expand with one_operand_p and flattened selector. - If that didn't work, retry without one_operand_p; we succeeded with that - during testing. */ - if (two_args && d.one_operand_p) - { - d.one_operand_p = false; - memcpy (d.perm, perm, sizeof (perm)); - return ix86_expand_vec_perm_const_1 (&d); - } - - return false; -} - -/* Implement targetm.vectorize.vec_perm_const_ok. */ - -static bool -ix86_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) -{ - struct expand_vec_perm_d d; - unsigned int i, nelt, which; - bool ret; - - d.vmode = vmode; - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = true; - /* Given sufficient ISA support we can just return true here for selected vector modes. */ switch (d.vmode) @@ -47796,17 +47755,23 @@ ix86_vectorize_vec_perm_const_ok (machin case E_V16SImode: case E_V8DImode: case E_V8DFmode: - if (TARGET_AVX512F) - /* All implementable with a single vperm[it]2 insn. */ + if (!TARGET_AVX512F) + return false; + /* All implementable with a single vperm[it]2 insn. */ + if (d.testing_p) return true; break; case E_V32HImode: - if (TARGET_AVX512BW) + if (!TARGET_AVX512BW) + return false; + if (d.testing_p) /* All implementable with a single vperm[it]2 insn. */ return true; break; case E_V64QImode: - if (TARGET_AVX512BW) + if (!TARGET_AVX512BW) + return false; + if (d.testing_p) /* Implementable with 2 vperm[it]2, 2 vpshufb and 1 or insn. */ return true; break; @@ -47814,73 +47779,108 @@ ix86_vectorize_vec_perm_const_ok (machin case E_V8SFmode: case E_V4DFmode: case E_V4DImode: - if (TARGET_AVX512VL) + if (!TARGET_AVX) + return false; + if (d.testing_p && TARGET_AVX512VL) /* All implementable with a single vperm[it]2 insn. */ return true; break; case E_V16HImode: - if (TARGET_AVX2) + if (!TARGET_SSE2) + return false; + if (d.testing_p && TARGET_AVX2) /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */ return true; break; case E_V32QImode: - if (TARGET_AVX2) + if (!TARGET_SSE2) + return false; + if (d.testing_p && TARGET_AVX2) /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */ return true; break; - case E_V4SImode: - case E_V4SFmode: case E_V8HImode: case E_V16QImode: + if (!TARGET_SSE2) + return false; + /* Fall through. */ + case E_V4SImode: + case E_V4SFmode: + if (!TARGET_SSE) + return false; /* All implementable with a single vpperm insn. */ - if (TARGET_XOP) + if (d.testing_p && TARGET_XOP) return true; /* All implementable with 2 pshufb + 1 ior. */ - if (TARGET_SSSE3) + if (d.testing_p && TARGET_SSSE3) return true; break; case E_V2DImode: case E_V2DFmode: + if (!TARGET_SSE) + return false; /* All implementable with shufpd or unpck[lh]pd. */ - return true; + if (d.testing_p) + return true; + break; default: return false; } - /* Extract the values from the vector CST into the permutation - array in D. */ for (i = which = 0; i < nelt; ++i) { unsigned char e = sel[i]; gcc_assert (e < 2 * nelt); d.perm[i] = e; + perm[i] = e; which |= (e < nelt ? 1 : 2); } - /* For all elements from second vector, fold the elements to first. */ - if (which == 2) - for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; + if (d.testing_p) + { + /* For all elements from second vector, fold the elements to first. */ + if (which == 2) + for (i = 0; i < nelt; ++i) + d.perm[i] -= nelt; + + /* Check whether the mask can be applied to the vector type. */ + d.one_operand_p = (which != 3); + + /* Implementable with shufps or pshufd. */ + if (d.one_operand_p && (d.vmode == V4SFmode || d.vmode == V4SImode)) + return true; + + /* Otherwise we have to go through the motions and see if we can + figure out how to generate the requested permutation. */ + d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); + d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); + if (!d.one_operand_p) + d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); + + start_sequence (); + bool ret = ix86_expand_vec_perm_const_1 (&d); + end_sequence (); - /* Check whether the mask can be applied to the vector type. */ - d.one_operand_p = (which != 3); + return ret; + } - /* Implementable with shufps or pshufd. */ - if (d.one_operand_p && (d.vmode == V4SFmode || d.vmode == V4SImode)) + two_args = canonicalize_perm (&d); + + if (ix86_expand_vec_perm_const_1 (&d)) return true; - /* Otherwise we have to go through the motions and see if we can - figure out how to generate the requested permutation. */ - d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); - d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); - if (!d.one_operand_p) - d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); - - start_sequence (); - ret = ix86_expand_vec_perm_const_1 (&d); - end_sequence (); + /* If the selector says both arguments are needed, but the operands are the + same, the above tried to expand with one_operand_p and flattened selector. + If that didn't work, retry without one_operand_p; we succeeded with that + during testing. */ + if (two_args && d.one_operand_p) + { + d.one_operand_p = false; + memcpy (d.perm, perm, sizeof (perm)); + return ix86_expand_vec_perm_const_1 (&d); + } - return ret; + return false; } void @@ -50532,9 +50532,8 @@ #define TARGET_CLASS_LIKELY_SPILLED_P ix #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \ ix86_builtin_vectorization_cost -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK \ - ix86_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST ix86_vectorize_vec_perm_const #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \ ix86_preferred_simd_mode Index: gcc/config/ia64/ia64-protos.h =================================================================== --- gcc/config/ia64/ia64-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/ia64/ia64-protos.h 2017-12-09 22:47:27.864318089 +0000 @@ -62,7 +62,6 @@ extern const char *get_bundle_name (int) extern const char *output_probe_stack_range (rtx, rtx); extern void ia64_expand_vec_perm_even_odd (rtx, rtx, rtx, int); -extern bool ia64_expand_vec_perm_const (rtx op[4]); extern void ia64_expand_vec_setv2sf (rtx op[3]); #endif /* RTX_CODE */ Index: gcc/config/ia64/vect.md =================================================================== --- gcc/config/ia64/vect.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/ia64/vect.md 2017-12-09 22:47:27.865318089 +0000 @@ -1549,19 +1549,6 @@ (define_expand "vec_pack_trunc_v2si" DONE; }) -(define_expand "vec_perm_const" - [(match_operand:VEC 0 "register_operand" "") - (match_operand:VEC 1 "register_operand" "") - (match_operand:VEC 2 "register_operand" "") - (match_operand: 3 "" "")] - "" -{ - if (ia64_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - ;; Missing operations ;; fprcpa ;; fpsqrta Index: gcc/config/ia64/ia64.c =================================================================== --- gcc/config/ia64/ia64.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/ia64/ia64.c 2017-12-09 22:47:27.864318089 +0000 @@ -333,7 +333,8 @@ static fixed_size_mode ia64_get_reg_raw_ static section * ia64_hpux_function_section (tree, enum node_frequency, bool, bool); -static bool ia64_vectorize_vec_perm_const_ok (machine_mode, vec_perm_indices); +static bool ia64_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, + const vec_perm_indices &); static unsigned int ia64_hard_regno_nregs (unsigned int, machine_mode); static bool ia64_hard_regno_mode_ok (unsigned int, machine_mode); @@ -652,8 +653,8 @@ #define TARGET_DELAY_SCHED2 true #undef TARGET_DELAY_VARTRACK #define TARGET_DELAY_VARTRACK true -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK ia64_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST ia64_vectorize_vec_perm_const #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P ia64_attribute_takes_identifier_p @@ -11741,32 +11742,31 @@ ia64_expand_vec_perm_const_1 (struct exp return false; } -bool -ia64_expand_vec_perm_const (rtx operands[4]) +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ + +static bool +ia64_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { struct expand_vec_perm_d d; unsigned char perm[MAX_VECT_LEN]; - int i, nelt, which; - rtx sel; + unsigned int i, nelt, which; - d.target = operands[0]; - d.op0 = operands[1]; - d.op1 = operands[2]; - sel = operands[3]; + d.target = target; + d.op0 = op0; + d.op1 = op1; - d.vmode = GET_MODE (d.target); + d.vmode = vmode; gcc_assert (VECTOR_MODE_P (d.vmode)); d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = false; + d.testing_p = !target; - gcc_assert (GET_CODE (sel) == CONST_VECTOR); - gcc_assert (XVECLEN (sel, 0) == nelt); + gcc_assert (sel.length () == nelt); gcc_checking_assert (sizeof (d.perm) == sizeof (perm)); for (i = which = 0; i < nelt; ++i) { - rtx e = XVECEXP (sel, 0, i); - int ei = INTVAL (e) & (2 * nelt - 1); + unsigned int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); d.perm[i] = ei; @@ -11779,7 +11779,7 @@ ia64_expand_vec_perm_const (rtx operands gcc_unreachable(); case 3: - if (!rtx_equal_p (d.op0, d.op1)) + if (d.testing_p || !rtx_equal_p (d.op0, d.op1)) { d.one_operand_p = false; break; @@ -11807,6 +11807,22 @@ ia64_expand_vec_perm_const (rtx operands break; } + if (d.testing_p) + { + /* We have to go through the motions and see if we can + figure out how to generate the requested permutation. */ + d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); + d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); + if (!d.one_operand_p) + d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); + + start_sequence (); + bool ret = ia64_expand_vec_perm_const_1 (&d); + end_sequence (); + + return ret; + } + if (ia64_expand_vec_perm_const_1 (&d)) return true; @@ -11823,51 +11839,6 @@ ia64_expand_vec_perm_const (rtx operands return false; } -/* Implement targetm.vectorize.vec_perm_const_ok. */ - -static bool -ia64_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) -{ - struct expand_vec_perm_d d; - unsigned int i, nelt, which; - bool ret; - - d.vmode = vmode; - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = true; - - /* Extract the values from the vector CST into the permutation - array in D. */ - for (i = which = 0; i < nelt; ++i) - { - unsigned char e = sel[i]; - d.perm[i] = e; - gcc_assert (e < 2 * nelt); - which |= (e < nelt ? 1 : 2); - } - - /* For all elements from second vector, fold the elements to first. */ - if (which == 2) - for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; - - /* Check whether the mask can be applied to the vector type. */ - d.one_operand_p = (which != 3); - - /* Otherwise we have to go through the motions and see if we can - figure out how to generate the requested permutation. */ - d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); - d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); - if (!d.one_operand_p) - d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); - - start_sequence (); - ret = ia64_expand_vec_perm_const_1 (&d); - end_sequence (); - - return ret; -} - void ia64_expand_vec_setv2sf (rtx operands[3]) { Index: gcc/config/mips/loongson.md =================================================================== --- gcc/config/mips/loongson.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/mips/loongson.md 2017-12-09 22:47:27.865318089 +0000 @@ -784,19 +784,6 @@ (define_insn "*loongson_punpcklwd_hi" "punpcklwd\t%0,%1,%2" [(set_attr "type" "fcvt")]) -(define_expand "vec_perm_const" - [(match_operand:VWHB 0 "register_operand" "") - (match_operand:VWHB 1 "register_operand" "") - (match_operand:VWHB 2 "register_operand" "") - (match_operand:VWHB 3 "" "")] - "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" -{ - if (mips_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_expand "vec_unpacks_lo_" [(match_operand: 0 "register_operand" "") (match_operand:VHB 1 "register_operand" "")] Index: gcc/config/mips/mips-msa.md =================================================================== --- gcc/config/mips/mips-msa.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/mips/mips-msa.md 2017-12-09 22:47:27.865318089 +0000 @@ -558,19 +558,6 @@ (define_insn_and_split "msa_copy_s_")]) -(define_expand "vec_perm_const" - [(match_operand:MSA 0 "register_operand") - (match_operand:MSA 1 "register_operand") - (match_operand:MSA 2 "register_operand") - (match_operand: 3 "")] - "ISA_HAS_MSA" -{ - if (mips_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_expand "abs2" [(match_operand:IMSA 0 "register_operand" "=f") (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))] Index: gcc/config/mips/mips-ps-3d.md =================================================================== --- gcc/config/mips/mips-ps-3d.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/mips/mips-ps-3d.md 2017-12-09 22:47:27.865318089 +0000 @@ -164,19 +164,6 @@ (define_insn "vec_perm_const_ps" [(set_attr "type" "fmove") (set_attr "mode" "SF")]) -(define_expand "vec_perm_constv2sf" - [(match_operand:V2SF 0 "register_operand" "") - (match_operand:V2SF 1 "register_operand" "") - (match_operand:V2SF 2 "register_operand" "") - (match_operand:V2SI 3 "" "")] - "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" -{ - if (mips_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - ;; Expanders for builtins. The instruction: ;; ;; P[UL][UL].PS , , Index: gcc/config/mips/mips-protos.h =================================================================== --- gcc/config/mips/mips-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/mips/mips-protos.h 2017-12-09 22:47:27.865318089 +0000 @@ -348,7 +348,6 @@ extern void mips_expand_atomic_qihi (uni rtx, rtx, rtx, rtx); extern void mips_expand_vector_init (rtx, rtx); -extern bool mips_expand_vec_perm_const (rtx op[4]); extern void mips_expand_vec_unpack (rtx op[2], bool, bool); extern void mips_expand_vec_reduc (rtx, rtx, rtx (*)(rtx, rtx, rtx)); extern void mips_expand_vec_minmax (rtx, rtx, rtx, Index: gcc/config/mips/mips.c =================================================================== --- gcc/config/mips/mips.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/mips/mips.c 2017-12-09 22:47:27.867318090 +0000 @@ -21377,34 +21377,32 @@ mips_expand_vec_perm_const_1 (struct exp return false; } -/* Expand a vec_perm_const pattern. */ +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ -bool -mips_expand_vec_perm_const (rtx operands[4]) +static bool +mips_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { struct expand_vec_perm_d d; int i, nelt, which; unsigned char orig_perm[MAX_VECT_LEN]; - rtx sel; bool ok; - d.target = operands[0]; - d.op0 = operands[1]; - d.op1 = operands[2]; - sel = operands[3]; - - d.vmode = GET_MODE (d.target); - gcc_assert (VECTOR_MODE_P (d.vmode)); - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = false; + d.target = target; + d.op0 = op0; + d.op1 = op1; + + d.vmode = vmode; + gcc_assert (VECTOR_MODE_P (vmode)); + d.nelt = nelt = GET_MODE_NUNITS (vmode); + d.testing_p = !target; /* This is overly conservative, but ensures we don't get an uninitialized warning on ORIG_PERM. */ memset (orig_perm, 0, MAX_VECT_LEN); for (i = which = 0; i < nelt; ++i) { - rtx e = XVECEXP (sel, 0, i); - int ei = INTVAL (e) & (2 * nelt - 1); + int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); orig_perm[i] = ei; } @@ -21417,7 +21415,7 @@ mips_expand_vec_perm_const (rtx operands case 3: d.one_vector_p = false; - if (!rtx_equal_p (d.op0, d.op1)) + if (d.testing_p || !rtx_equal_p (d.op0, d.op1)) break; /* FALLTHRU */ @@ -21434,6 +21432,19 @@ mips_expand_vec_perm_const (rtx operands break; } + if (d.testing_p) + { + d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); + d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); + if (!d.one_vector_p) + d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); + + start_sequence (); + ok = mips_expand_vec_perm_const_1 (&d); + end_sequence (); + return ok; + } + ok = mips_expand_vec_perm_const_1 (&d); /* If we were given a two-vector permutation which just happened to @@ -21445,8 +21456,8 @@ mips_expand_vec_perm_const (rtx operands the original permutation. */ if (!ok && which == 3) { - d.op0 = operands[1]; - d.op1 = operands[2]; + d.op0 = op0; + d.op1 = op1; d.one_vector_p = false; memcpy (d.perm, orig_perm, MAX_VECT_LEN); ok = mips_expand_vec_perm_const_1 (&d); @@ -21466,48 +21477,6 @@ mips_sched_reassociation_width (unsigned return 1; } -/* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */ - -static bool -mips_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) -{ - struct expand_vec_perm_d d; - unsigned int i, nelt, which; - bool ret; - - d.vmode = vmode; - d.nelt = nelt = GET_MODE_NUNITS (d.vmode); - d.testing_p = true; - - /* Categorize the set of elements in the selector. */ - for (i = which = 0; i < nelt; ++i) - { - unsigned char e = sel[i]; - d.perm[i] = e; - gcc_assert (e < 2 * nelt); - which |= (e < nelt ? 1 : 2); - } - - /* For all elements from second vector, fold the elements to first. */ - if (which == 2) - for (i = 0; i < nelt; ++i) - d.perm[i] -= nelt; - - /* Check whether the mask can be applied to the vector type. */ - d.one_vector_p = (which != 3); - - d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); - d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); - if (!d.one_vector_p) - d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); - - start_sequence (); - ret = mips_expand_vec_perm_const_1 (&d); - end_sequence (); - - return ret; -} - /* Expand an integral vector unpack operation. */ void @@ -22589,8 +22558,8 @@ #define TARGET_SHIFT_TRUNCATION_MASK mip #undef TARGET_PREPARE_PCH_SAVE #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST mips_vectorize_vec_perm_const #undef TARGET_SCHED_REASSOCIATION_WIDTH #define TARGET_SCHED_REASSOCIATION_WIDTH mips_sched_reassociation_width Index: gcc/config/powerpcspe/altivec.md =================================================================== --- gcc/config/powerpcspe/altivec.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/altivec.md 2017-12-09 22:47:27.867318090 +0000 @@ -2080,19 +2080,6 @@ (define_expand "vec_permv16qi" } }) -(define_expand "vec_perm_constv16qi" - [(match_operand:V16QI 0 "register_operand" "") - (match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "") - (match_operand:V16QI 3 "" "")] - "TARGET_ALTIVEC" -{ - if (altivec_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_insn "*altivec_vpermr__internal" [(set (match_operand:VM 0 "register_operand" "=v,?wo") (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") Index: gcc/config/powerpcspe/paired.md =================================================================== --- gcc/config/powerpcspe/paired.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/paired.md 2017-12-09 22:47:27.867318090 +0000 @@ -313,19 +313,6 @@ (define_insn "paired_merge11" "ps_merge11 %0, %1, %2" [(set_attr "type" "fp")]) -(define_expand "vec_perm_constv2sf" - [(match_operand:V2SF 0 "gpc_reg_operand" "") - (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "") - (match_operand:V2SI 3 "" "")] - "TARGET_PAIRED_FLOAT" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_insn "paired_sum0" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (vec_concat:V2SF (plus:SF (vec_select:SF Index: gcc/config/powerpcspe/spe.md =================================================================== --- gcc/config/powerpcspe/spe.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/spe.md 2017-12-09 22:47:27.871318093 +0000 @@ -511,19 +511,6 @@ (define_insn "vec_perm10_v2si" [(set_attr "type" "vecsimple") (set_attr "length" "4")]) -(define_expand "vec_perm_constv2si" - [(match_operand:V2SI 0 "gpc_reg_operand" "") - (match_operand:V2SI 1 "gpc_reg_operand" "") - (match_operand:V2SI 2 "gpc_reg_operand" "") - (match_operand:V2SI 3 "" "")] - "TARGET_SPE" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_expand "spe_evmergehi" [(match_operand:V2SI 0 "register_operand" "") (match_operand:V2SI 1 "register_operand" "") Index: gcc/config/powerpcspe/vsx.md =================================================================== --- gcc/config/powerpcspe/vsx.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/vsx.md 2017-12-09 22:47:27.871318093 +0000 @@ -2543,19 +2543,6 @@ (define_insn "vsx_xxpermdi2__1" } [(set_attr "type" "vecperm")]) -(define_expand "vec_perm_const" - [(match_operand:VSX_D 0 "vsx_register_operand" "") - (match_operand:VSX_D 1 "vsx_register_operand" "") - (match_operand:VSX_D 2 "vsx_register_operand" "") - (match_operand:V2DI 3 "" "")] - "VECTOR_MEM_VSX_P (mode)" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - ;; Extraction of a single element in a small integer vector. Until ISA 3.0, ;; none of the small types were allowed in a vector register, so we had to ;; extract to a DImode and either do a direct move or store. Index: gcc/config/powerpcspe/powerpcspe-protos.h =================================================================== --- gcc/config/powerpcspe/powerpcspe-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/powerpcspe-protos.h 2017-12-09 22:47:27.867318090 +0000 @@ -64,9 +64,7 @@ extern void rs6000_expand_vector_extract extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx); extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode); extern void rs6000_split_v4si_init (rtx []); -extern bool altivec_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_vec_perm_le (rtx op[4]); -extern bool rs6000_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_lvx_be (rtx, rtx, machine_mode, unsigned); extern void altivec_expand_stvx_be (rtx, rtx, machine_mode, unsigned); extern void altivec_expand_stvex_be (rtx, rtx, machine_mode, unsigned); Index: gcc/config/powerpcspe/powerpcspe.c =================================================================== --- gcc/config/powerpcspe/powerpcspe.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/powerpcspe/powerpcspe.c 2017-12-09 22:47:27.871318093 +0000 @@ -1936,8 +1936,8 @@ #define TARGET_SET_CURRENT_FUNCTION rs60 #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const #undef TARGET_CAN_USE_DOLOOP_P #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost @@ -38311,6 +38311,9 @@ rs6000_emit_parity (rtx dst, rtx src) } /* Expand an Altivec constant permutation for little endian mode. + OP0 and OP1 are the input vectors and TARGET is the output vector. + SEL specifies the constant permutation vector. + There are two issues: First, the two input operands must be swapped so that together they form a double-wide array in LE order. Second, the vperm instruction has surprising behavior @@ -38352,22 +38355,18 @@ rs6000_emit_parity (rtx dst, rtx src) vr9 = 00000006 00000004 00000002 00000000. */ -void -altivec_expand_vec_perm_const_le (rtx operands[4]) +static void +altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { unsigned int i; rtx perm[16]; rtx constv, unspec; - rtx target = operands[0]; - rtx op0 = operands[1]; - rtx op1 = operands[2]; - rtx sel = operands[3]; /* Unpack and adjust the constant selector. */ for (i = 0; i < 16; ++i) { - rtx e = XVECEXP (sel, 0, i); - unsigned int elt = 31 - (INTVAL (e) & 31); + unsigned int elt = 31 - (sel[i] & 31); perm[i] = GEN_INT (elt); } @@ -38449,10 +38448,14 @@ altivec_expand_vec_perm_le (rtx operands } /* Expand an Altivec constant permutation. Return true if we match - an efficient implementation; false to fall back to VPERM. */ + an efficient implementation; false to fall back to VPERM. -bool -altivec_expand_vec_perm_const (rtx operands[4]) + OP0 and OP1 are the input vectors and TARGET is the output vector. + SEL specifies the constant permutation vector. */ + +static bool +altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { struct altivec_perm_insn { HOST_WIDE_INT mask; @@ -38496,19 +38499,13 @@ altivec_expand_vec_perm_const (rtx opera unsigned int i, j, elt, which; unsigned char perm[16]; - rtx target, op0, op1, sel, x; + rtx x; bool one_vec; - target = operands[0]; - op0 = operands[1]; - op1 = operands[2]; - sel = operands[3]; - /* Unpack the constant selector. */ for (i = which = 0; i < 16; ++i) { - rtx e = XVECEXP (sel, 0, i); - elt = INTVAL (e) & 31; + elt = sel[i] & 31; which |= (elt < 16 ? 1 : 2); perm[i] = elt; } @@ -38664,7 +38661,7 @@ altivec_expand_vec_perm_const (rtx opera if (!BYTES_BIG_ENDIAN) { - altivec_expand_vec_perm_const_le (operands); + altivec_expand_vec_perm_const_le (target, op0, op1, sel); return true; } @@ -38724,60 +38721,54 @@ rs6000_expand_vec_perm_const_1 (rtx targ return true; } -bool -rs6000_expand_vec_perm_const (rtx operands[4]) -{ - rtx target, op0, op1, sel; - unsigned char perm0, perm1; - - target = operands[0]; - op0 = operands[1]; - op1 = operands[2]; - sel = operands[3]; - - /* Unpack the constant selector. */ - perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3; - perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3; - - return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1); -} - -/* Test whether a constant permutation is supported. */ +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) +rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { + bool testing_p = !target; + /* AltiVec (and thus VSX) can handle arbitrary permutations. */ - if (TARGET_ALTIVEC) + if (TARGET_ALTIVEC && testing_p) return true; - /* Check for ps_merge* or evmerge* insns. */ - if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode) - || (TARGET_SPE && vmode == V2SImode)) - { - rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1); - rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2); - return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]); + /* Check for ps_merge*, evmerge* or xxperm* insns. */ + if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT) + || (vmode == V2SImode && TARGET_SPE) + || ((vmode == V2DFmode || vmode == V2DImode) + && VECTOR_MEM_VSX_P (vmode))) + { + if (testing_p) + { + op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1); + op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2); + } + if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1])) + return true; + } + + if (TARGET_ALTIVEC) + { + /* Force the target-independent code to lower to V16QImode. */ + if (vmode != V16QImode) + return false; + if (altivec_expand_vec_perm_const (target, op0, op1, sel)) + return true; } return false; } -/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */ +/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. + OP0 and OP1 are the input vectors and TARGET is the output vector. + PERM specifies the constant permutation vector. */ static void rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1, - machine_mode vmode, unsigned nelt, rtx perm[]) + machine_mode vmode, const vec_perm_builder &perm) { - machine_mode imode; - rtx x; - - imode = vmode; - if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT) - imode = mode_for_int_vector (vmode).require (); - - x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm)); - x = expand_vec_perm (vmode, op0, op1, x, target); + rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target); if (x != target) emit_move_insn (target, x); } @@ -38789,12 +38780,12 @@ rs6000_expand_extract_even (rtx target, { machine_mode vmode = GET_MODE (target); unsigned i, nelt = GET_MODE_NUNITS (vmode); - rtx perm[16]; + vec_perm_builder perm (nelt); for (i = 0; i < nelt; i++) - perm[i] = GEN_INT (i * 2); + perm.quick_push (i * 2); - rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); + rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm); } /* Expand a vector interleave operation. */ @@ -38804,16 +38795,16 @@ rs6000_expand_interleave (rtx target, rt { machine_mode vmode = GET_MODE (target); unsigned i, high, nelt = GET_MODE_NUNITS (vmode); - rtx perm[16]; + vec_perm_builder perm (nelt); high = (highp ? 0 : nelt / 2); for (i = 0; i < nelt / 2; i++) { - perm[i * 2] = GEN_INT (i + high); - perm[i * 2 + 1] = GEN_INT (i + nelt + high); + perm.quick_push (i + high); + perm.quick_push (i + nelt + high); } - rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); + rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm); } /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */ Index: gcc/config/rs6000/altivec.md =================================================================== --- gcc/config/rs6000/altivec.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/rs6000/altivec.md 2017-12-09 22:47:27.872318093 +0000 @@ -2198,19 +2198,6 @@ (define_expand "vec_permv16qi" } }) -(define_expand "vec_perm_constv16qi" - [(match_operand:V16QI 0 "register_operand" "") - (match_operand:V16QI 1 "register_operand" "") - (match_operand:V16QI 2 "register_operand" "") - (match_operand:V16QI 3 "" "")] - "TARGET_ALTIVEC" -{ - if (altivec_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_insn "*altivec_vpermr__internal" [(set (match_operand:VM 0 "register_operand" "=v,?wo") (unspec:VM [(match_operand:VM 1 "register_operand" "v,wo") Index: gcc/config/rs6000/paired.md =================================================================== --- gcc/config/rs6000/paired.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/rs6000/paired.md 2017-12-09 22:47:27.872318093 +0000 @@ -313,19 +313,6 @@ (define_insn "paired_merge11" "ps_merge11 %0, %1, %2" [(set_attr "type" "fp")]) -(define_expand "vec_perm_constv2sf" - [(match_operand:V2SF 0 "gpc_reg_operand" "") - (match_operand:V2SF 1 "gpc_reg_operand" "") - (match_operand:V2SF 2 "gpc_reg_operand" "") - (match_operand:V2SI 3 "" "")] - "TARGET_PAIRED_FLOAT" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - (define_insn "paired_sum0" [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f") (vec_concat:V2SF (plus:SF (vec_select:SF Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/rs6000/vsx.md 2017-12-09 22:47:27.875318095 +0000 @@ -3189,19 +3189,6 @@ (define_insn "vsx_xxpermdi2__1" } [(set_attr "type" "vecperm")]) -(define_expand "vec_perm_const" - [(match_operand:VSX_D 0 "vsx_register_operand" "") - (match_operand:VSX_D 1 "vsx_register_operand" "") - (match_operand:VSX_D 2 "vsx_register_operand" "") - (match_operand:V2DI 3 "" "")] - "VECTOR_MEM_VSX_P (mode)" -{ - if (rs6000_expand_vec_perm_const (operands)) - DONE; - else - FAIL; -}) - ;; Extraction of a single element in a small integer vector. Until ISA 3.0, ;; none of the small types were allowed in a vector register, so we had to ;; extract to a DImode and either do a direct move or store. Index: gcc/config/rs6000/rs6000-protos.h =================================================================== --- gcc/config/rs6000/rs6000-protos.h 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/rs6000/rs6000-protos.h 2017-12-09 22:47:27.872318093 +0000 @@ -63,9 +63,7 @@ extern void rs6000_expand_vector_extract extern void rs6000_split_vec_extract_var (rtx, rtx, rtx, rtx, rtx); extern rtx rs6000_adjust_vec_address (rtx, rtx, rtx, rtx, machine_mode); extern void rs6000_split_v4si_init (rtx []); -extern bool altivec_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_vec_perm_le (rtx op[4]); -extern bool rs6000_expand_vec_perm_const (rtx op[4]); extern void altivec_expand_lvx_be (rtx, rtx, machine_mode, unsigned); extern void altivec_expand_stvx_be (rtx, rtx, machine_mode, unsigned); extern void altivec_expand_stvex_be (rtx, rtx, machine_mode, unsigned); Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/rs6000/rs6000.c 2017-12-09 22:47:27.874318095 +0000 @@ -1907,8 +1907,8 @@ #define TARGET_SET_CURRENT_FUNCTION rs60 #undef TARGET_LEGITIMATE_CONSTANT_P #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p -#undef TARGET_VECTORIZE_VEC_PERM_CONST_OK -#define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const #undef TARGET_CAN_USE_DOLOOP_P #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost @@ -35545,6 +35545,9 @@ rs6000_emit_parity (rtx dst, rtx src) } /* Expand an Altivec constant permutation for little endian mode. + OP0 and OP1 are the input vectors and TARGET is the output vector. + SEL specifies the constant permutation vector. + There are two issues: First, the two input operands must be swapped so that together they form a double-wide array in LE order. Second, the vperm instruction has surprising behavior @@ -35586,22 +35589,18 @@ rs6000_emit_parity (rtx dst, rtx src) vr9 = 00000006 00000004 00000002 00000000. */ -void -altivec_expand_vec_perm_const_le (rtx operands[4]) +static void +altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { unsigned int i; rtx perm[16]; rtx constv, unspec; - rtx target = operands[0]; - rtx op0 = operands[1]; - rtx op1 = operands[2]; - rtx sel = operands[3]; /* Unpack and adjust the constant selector. */ for (i = 0; i < 16; ++i) { - rtx e = XVECEXP (sel, 0, i); - unsigned int elt = 31 - (INTVAL (e) & 31); + unsigned int elt = 31 - (sel[i] & 31); perm[i] = GEN_INT (elt); } @@ -35683,10 +35682,14 @@ altivec_expand_vec_perm_le (rtx operands } /* Expand an Altivec constant permutation. Return true if we match - an efficient implementation; false to fall back to VPERM. */ + an efficient implementation; false to fall back to VPERM. -bool -altivec_expand_vec_perm_const (rtx operands[4]) + OP0 and OP1 are the input vectors and TARGET is the output vector. + SEL specifies the constant permutation vector. */ + +static bool +altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1, + const vec_perm_indices &sel) { struct altivec_perm_insn { HOST_WIDE_INT mask; @@ -35734,19 +35737,13 @@ altivec_expand_vec_perm_const (rtx opera unsigned int i, j, elt, which; unsigned char perm[16]; - rtx target, op0, op1, sel, x; + rtx x; bool one_vec; - target = operands[0]; - op0 = operands[1]; - op1 = operands[2]; - sel = operands[3]; - /* Unpack the constant selector. */ for (i = which = 0; i < 16; ++i) { - rtx e = XVECEXP (sel, 0, i); - elt = INTVAL (e) & 31; + elt = sel[i] & 31; which |= (elt < 16 ? 1 : 2); perm[i] = elt; } @@ -35902,7 +35899,7 @@ altivec_expand_vec_perm_const (rtx opera if (!BYTES_BIG_ENDIAN) { - altivec_expand_vec_perm_const_le (operands); + altivec_expand_vec_perm_const_le (target, op0, op1, sel); return true; } @@ -35962,59 +35959,53 @@ rs6000_expand_vec_perm_const_1 (rtx targ return true; } -bool -rs6000_expand_vec_perm_const (rtx operands[4]) -{ - rtx target, op0, op1, sel; - unsigned char perm0, perm1; - - target = operands[0]; - op0 = operands[1]; - op1 = operands[2]; - sel = operands[3]; - - /* Unpack the constant selector. */ - perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3; - perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3; - - return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1); -} - -/* Test whether a constant permutation is supported. */ +/* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */ static bool -rs6000_vectorize_vec_perm_const_ok (machine_mode vmode, vec_perm_indices sel) +rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) { + bool testing_p = !target; + /* AltiVec (and thus VSX) can handle arbitrary permutations. */ - if (TARGET_ALTIVEC) + if (TARGET_ALTIVEC && testing_p) return true; - /* Check for ps_merge* or evmerge* insns. */ - if (TARGET_PAIRED_FLOAT && vmode == V2SFmode) + /* Check for ps_merge* or xxpermdi insns. */ + if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT) + || ((vmode == V2DFmode || vmode == V2DImode) + && VECTOR_MEM_VSX_P (vmode))) + { + if (testing_p) + { + op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1); + op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2); + } + if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1])) + return true; + } + + if (TARGET_ALTIVEC) { - rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1); - rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2); - return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]); + /* Force the target-independent code to lower to V16QImode. */ + if (vmode != V16QImode) + return false; + if (altivec_expand_vec_perm_const (target, op0, op1, sel)) + return true; } return false; } -/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */ +/* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. + OP0 and OP1 are the input vectors and TARGET is the output vector. + PERM specifies the constant permutation vector. */ static void rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1, - machine_mode vmode, unsigned nelt, rtx perm[]) + machine_mode vmode, const vec_perm_builder &perm) { - machine_mode imode; - rtx x; - - imode = vmode; - if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT) - imode = mode_for_int_vector (vmode).require (); - - x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm)); - x = expand_vec_perm (vmode, op0, op1, x, target); + rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target); if (x != target) emit_move_insn (target, x); } @@ -36026,12 +36017,12 @@ rs6000_expand_extract_even (rtx target, { machine_mode vmode = GET_MODE (target); unsigned i, nelt = GET_MODE_NUNITS (vmode); - rtx perm[16]; + vec_perm_builder perm (nelt); for (i = 0; i < nelt; i++) - perm[i] = GEN_INT (i * 2); + perm.quick_push (i * 2); - rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); + rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm); } /* Expand a vector interleave operation. */ @@ -36041,16 +36032,16 @@ rs6000_expand_interleave (rtx target, rt { machine_mode vmode = GET_MODE (target); unsigned i, high, nelt = GET_MODE_NUNITS (vmode); - rtx perm[16]; + vec_perm_builder perm (nelt); high = (highp ? 0 : nelt / 2); for (i = 0; i < nelt / 2; i++) { - perm[i * 2] = GEN_INT (i + high); - perm[i * 2 + 1] = GEN_INT (i + nelt + high); + perm.quick_push (i + high); + perm.quick_push (i + nelt + high); } - rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); + rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm); } /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */ Index: gcc/config/sparc/sparc.md =================================================================== --- gcc/config/sparc/sparc.md 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/sparc/sparc.md 2017-12-09 22:47:27.876318096 +0000 @@ -9327,28 +9327,6 @@ (define_insn "bshuffle_vis" (set_attr "subtype" "other") (set_attr "fptype" "double")]) -;; The rtl expanders will happily convert constant permutations on other -;; modes down to V8QI. Rely on this to avoid the complexity of the byte -;; order of the permutation. -(define_expand "vec_perm_constv8qi" - [(match_operand:V8QI 0 "register_operand" "") - (match_operand:V8QI 1 "register_operand" "") - (match_operand:V8QI 2 "register_operand" "") - (match_operand:V8QI 3 "" "")] - "TARGET_VIS2" -{ - unsigned int i, mask; - rtx sel = operands[3]; - - for (i = mask = 0; i < 8; ++i) - mask |= (INTVAL (XVECEXP (sel, 0, i)) & 0xf) << (28 - i*4); - sel = force_reg (SImode, gen_int_mode (mask, SImode)); - - emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx)); - emit_insn (gen_bshufflev8qi_vis (operands[0], operands[1], operands[2])); - DONE; -}) - ;; Unlike constant permutation, we can vastly simplify the compression of ;; the 64-bit selector input to the 32-bit %gsr value by knowing what the ;; width of the input is. Index: gcc/config/sparc/sparc.c =================================================================== --- gcc/config/sparc/sparc.c 2017-12-09 22:47:09.549486911 +0000 +++ gcc/config/sparc/sparc.c 2017-12-09 22:47:27.876318096 +0000 @@ -686,6 +686,8 @@ static bool sparc_modes_tieable_p (machi static bool sparc_can_change_mode_class (machine_mode, machine_mode, reg_class_t); static HOST_WIDE_INT sparc_constant_alignment (const_tree, HOST_WIDE_INT); +static bool sparc_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, + const vec_perm_indices &); #ifdef SUBTARGET_ATTRIBUTE_TABLE /* Table of valid machine attributes. */ @@ -930,6 +932,9 @@ #define TARGET_CAN_CHANGE_MODE_CLASS spa #undef TARGET_CONSTANT_ALIGNMENT #define TARGET_CONSTANT_ALIGNMENT sparc_constant_alignment +#undef TARGET_VECTORIZE_VEC_PERM_CONST +#define TARGET_VECTORIZE_VEC_PERM_CONST sparc_vectorize_vec_perm_const + struct gcc_target targetm = TARGET_INITIALIZER; /* Return the memory reference contained in X if any, zero otherwise. */ @@ -12812,6 +12817,32 @@ sparc_expand_vec_perm_bmask (machine_mod emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1)); } +/* Implement TARGET_VEC_PERM_CONST. */ + +static bool +sparc_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0, + rtx op1, const vec_perm_indices &sel) +{ + /* All permutes are supported. */ + if (!target) + return true; + + /* Force target-independent code to convert constant permutations on other + modes down to V8QI. Rely on this to avoid the complexity of the byte + order of the permutation. */ + if (vmode != V8QImode) + return false; + + unsigned int i, mask; + for (i = mask = 0; i < 8; ++i) + mask |= (sel[i] & 0xf) << (28 - i*4); + rtx mask_rtx = force_reg (SImode, gen_int_mode (mask, SImode)); + + emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), mask_rtx, const0_rtx)); + emit_insn (gen_bshufflev8qi_vis (target, op0, op1)); + return true; +} + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ static bool From patchwork Sat Dec 9 23:18:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121296 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1162913qgn; Sat, 9 Dec 2017 15:18:22 -0800 (PST) X-Google-Smtp-Source: AGs4zMYgwLdZjlhskF8wNJI2qb1TSVnqK8dJUUDr6sxI9Ug/93O3SjcwKgDyMJU3uGx6EnkJ+Cx2 X-Received: by 10.98.182.16 with SMTP id j16mr2861272pff.47.1512861502434; Sat, 09 Dec 2017 15:18:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861502; cv=none; d=google.com; s=arc-20160816; b=Cemhi5I93UoMiJ3Fs8/I0UsgJJY0e+nzQoaItOfcgmFVULlrcxDh29zUMYX2kgo9om j3emDTNdYxAWu6okTpvo5O4adcpe8YNMv6nHIrz6FUxL7kJxzlnVPqztePEZcdhufz7q 3K/PxPFAuz5Z9pFPQ85eON6BHWjNPFMNhOs/OHF3yr/hR8glEHoJvMPm68gR1IhKcbI+ +JqIfBtq3Qd+C5dzzRthJ57oJzN7gyNZCbenA/tlrrW6Ljv/kB/KsEnKGRPGfdpxc1DH IeIXiHIx7+4iBXv+NYI9d/3wHpR8usKKiU7eolC+gccK6oK6v+BQOf7LyZFbt3UCX35u V5DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=6Rl1SrkbrQkzAPjLFH2JUn51EqgBntf7ElE2xWNhYYI=; b=KG8yFnUiQlmOuP+S/54Gx40WTDvpnf+LmMqikLFUqZ7dZ2DOPofH4cLYvceJ9s/qeb dY+aFcVp2ExNj16Dk046gBvsjRoiqjiGYXhj6r185maiL5sKcsbmMkJfc8LBhPziBVK7 j2FC55M+jg5768zkpePq1QG0kjplwQSk38uMAIKbbv5fV2vqrgluUuPRaiQeDwmcbNI9 HEm0b7FKdYuil7A4lipX38263eW1C0mE0ijb+qUituge5Z60TZRamUDiLN+OAfPSsG0p fXJyfF14nWaBCDgIU5jtdd4IS/tucug6TnY5dOVpRTL5JRLaPsFdxIPrzf763jkzBvDo GhAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=DOWjXw3J; spf=pass (google.com: domain of gcc-patches-return-468856-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468856-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. 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This patch adds a corresponding check for whether variable permutes can be lowered to QImode-based permutes. 2017-12-09 Richard Sandiford gcc/ * optabs-query.c (can_vec_perm_var_p): Check whether lowering to qimode could truncate the indices. * optabs.c (expand_vec_perm_var): Likewise. Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:47:21.534314227 +0000 +++ gcc/optabs-query.c 2017-12-09 22:47:25.861316866 +0000 @@ -378,7 +378,8 @@ can_vec_perm_var_p (machine_mode mode) /* We allow fallback to a QI vector mode, and adjust the mask. */ machine_mode qimode; - if (!qimode_for_vec_perm (mode).exists (&qimode)) + if (!qimode_for_vec_perm (mode).exists (&qimode) + || GET_MODE_NUNITS (qimode) > GET_MODE_MASK (QImode) + 1) return false; if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing) Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:47:23.878315657 +0000 +++ gcc/optabs.c 2017-12-09 22:47:25.861316866 +0000 @@ -5595,7 +5595,8 @@ expand_vec_perm_var (machine_mode mode, /* As a special case to aid several targets, lower the element-based permutation to a byte-based permutation and try again. */ machine_mode qimode; - if (!qimode_for_vec_perm (mode).exists (&qimode)) + if (!qimode_for_vec_perm (mode).exists (&qimode) + || GET_MODE_NUNITS (qimode) > GET_MODE_MASK (QImode) + 1) return NULL_RTX; icode = direct_optab_handler (vec_perm_optab, qimode); if (icode == CODE_FOR_nothing) From patchwork Sat Dec 9 23:20:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121297 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1164279qgn; Sat, 9 Dec 2017 15:20:35 -0800 (PST) X-Google-Smtp-Source: AGs4zMbTDc0YJIPjNWwa/8drG2vx7t5slme0BcZM0J3+2CxtwmC9nAtSiVGZT78XJ/jiADRYm8eq X-Received: by 10.98.7.149 with SMTP id 21mr7173807pfh.14.1512861635838; Sat, 09 Dec 2017 15:20:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861635; cv=none; d=google.com; s=arc-20160816; b=XDuOZ9C0O/f3NQlvvy5T6qebxuBHAEi9QfmmqlO5LjxWTHN3e/5QmNl2QbotkOLWja 2OWK+6iVPq9AXL5eTeSZgreYpf2Z7p3wEyxMHSBwp/k22JAJajWXeI9WeRIdCokWkuiD F81tgGSOKcZMgaEBATSDQFaZgNo7aOAeq28vuX6ew/qMcz1tsgkHZcsvmmbfz6wUAen4 hkSG6Klrj1tIfwZMN7yrMQuyJPbcRjfTQ06VGI1OsXieT4Y133N6+U4Ek8PlPjuDlE06 79E5lE6NLZIR4ttSNYJIo8IRVTY8EuBEbLD87KhdTACIDZeLYJAW+uCkP/rcADUxOswB 8CXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=NZw+WHR4wan/YL+5UxEE0PY9fUcCdU/2Btk09/rt34o=; b=CVhnzFcNaYckE0wk/HpRe39ghZk80GiD4wkcVsuGj8v+gu8kKK6bmaBEZIfD/Rphl/ 0dlLuMLXMNXj5CAQEPKsHZue7aRuqr2xZIOdll14GS9PpN2TAUWX51PJ1Xi+u2JVDFLo CMjad8l1uUQvgRuoJCO7y20Knqs2AafqK3vqs//+SwCWkoZGYMkc8+PQH4joiP7kxIUt x+mfxN3cKYbJzYGrat7FtKz1kDrm0+bLbHoohm4Rp5p05RuBS/q3IsZZo64GjWqk8d3r S0BDbmH0CUjgh4Hd8zqxElAYUL6BoH0EFQJnH/zTOD6GB6Pe2Tt9b98aY5k8UYQy6+Jr 0KJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=GczFyBCd; spf=pass (google.com: domain of gcc-patches-return-468857-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468857-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id f1si1061935plb.58.2017.12.09.15.20.35 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:20:35 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468857-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=GczFyBCd; spf=pass (google.com: domain of gcc-patches-return-468857-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468857-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=UXiTrn0KK/3Z9S54lEIfVVwxO7Qfq PZx6r8fZqHxENyCrwDzmCYMBnSmh+UcJcyigvfcX1dg9NxSXR/eu1Nc0SWF5mAnl mWpBWkCauxuExSrpL1K6rhRvFly43iNLPrfts/f1WkkUMMEz59pE8kY2gI/CcKn8 lLwNwuGuxQz3Bk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=Lcvy+FIHjhmhvy5IsGJbx92pYX0=; b=Gcz FyBCdqCfus1sNfa2hohKMK86PDi7kulT7mWTB9k/Nl+0Q1f8gxsTPVMPCgrggITx QNzmhHUMpPljYyPFRFuiY4BH4CiopgPG1k9nkF/QkCy6g2xJmRcaBRnh9eTd1zBq jKGBAZOWk0ETHpD+NiAyn1IJ5ckRSoyJjykFjpsU= Received: (qmail 100445 invoked by alias); 9 Dec 2017 23:20:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 100430 invoked by uid 89); 9 Dec 2017 23:20:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-15.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=stepped X-HELO: mail-wm0-f51.google.com Received: from mail-wm0-f51.google.com (HELO mail-wm0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:20:07 +0000 Received: by mail-wm0-f51.google.com with SMTP id f9so8377438wmh.0 for ; Sat, 09 Dec 2017 15:20:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=NZw+WHR4wan/YL+5UxEE0PY9fUcCdU/2Btk09/rt34o=; b=rY7MkaiXh/rnrwg2XTQDLugdU59OZ6dANoUGsC/cAQls3qiUsQDJaU78RvCifsLJWO rgsAMBLr4DDnpoBfJQwwfGepnJxz7QF8uGDrIoaFAjl5lo2mOlCXdmTsvxR3sT6PnzWD ebGHnopF2jTcFwniXtClPwhM6SxPZAEIBtOfaSYBfIeD6HLNb5x4mDmCJdMedNpSOTNE x/u5aUvghtYbUgC01/YyDVWScSNfIDVZ2GqscoXxrUgU1qZgN97bIDUCMEIAIf2GZ831 yq6ZlUOhUpKV6ebI2iB2rOEoWscLYGl7HNFvm2nMTD+yF1QKhwt9vd4lBMHQmD3HjvuI vbEg== X-Gm-Message-State: AKGB3mLfPwl0xLy5fr1xvtN3gwpVl17g5WozKGy/lFcGea2SERpG/xgB VQt16IktTgz4lBSDe1QisPymVVAMZXI= X-Received: by 10.28.225.197 with SMTP id y188mr6888879wmg.12.1512861603806; Sat, 09 Dec 2017 15:20:03 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id h12sm10586237wre.52.2017.12.09.15.20.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:20:03 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [07/13] Make vec_perm_indices use new vector encoding References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:20:01 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87lgiblc9q.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch changes vec_perm_indices from a plain vec<> to a class that stores a canonicalised permutation, using the same encoding as for VECTOR_CSTs. This means that vec_perm_indices now carries information about the number of vectors being permuted (currently always 1 or 2) and the number of elements in each input vector. A new vec_perm_builder class is used to actually build up the vector, like tree_vector_builder does for trees. vec_perm_indices is the completed representation, a bit like VECTOR_CST is for trees. The patch just does a mechanical conversion of the code to vec_perm_builder: a later patch uses explicit encodings where possible. The point of all this is that it makes the representation suitable for variable-length vectors. It's no longer necessary for the underlying vec<>s to store every element explicitly. In int-vector-builder.h, "using the same encoding as tree and rtx constants" describes the endpoint -- adding the rtx encoding comes later. 2017-12-09 Richard Sandiford gcc/ * int-vector-builder.h: New file. * vec-perm-indices.h: Include int-vector-builder.h. (vec_perm_indices): Redefine as an int_vector_builder. (auto_vec_perm_indices): Delete. (vec_perm_builder): Redefine as a stand-alone class. (vec_perm_indices::vec_perm_indices): New function. (vec_perm_indices::clamp): Likewise. * vec-perm-indices.c: Include fold-const.h and tree-vector-builder.h. (vec_perm_indices::new_vector): New function. (vec_perm_indices::new_expanded_vector): Update for new vec_perm_indices class. (vec_perm_indices::rotate_inputs): New function. (vec_perm_indices::all_in_range_p): Operate directly on the encoded form, without computing elided elements. (tree_to_vec_perm_builder): Operate directly on the VECTOR_CST encoding. Update for new vec_perm_indices class. * optabs.c (expand_vec_perm_const): Create a vec_perm_indices for the given vec_perm_builder. (expand_vec_perm_var): Update vec_perm_builder constructor. (expand_mult_highpart): Use vec_perm_builder instead of auto_vec_perm_indices. * optabs-query.c (can_mult_highpart_p): Use vec_perm_builder and vec_perm_indices instead of auto_vec_perm_indices. Use a single or double series encoding as appropriate. * fold-const.c (fold_ternary_loc): Use vec_perm_builder and vec_perm_indices instead of auto_vec_perm_indices. * tree-ssa-forwprop.c (simplify_vector_constructor): Likewise. * tree-vect-data-refs.c (vect_grouped_store_supported): Likewise. (vect_permute_store_chain): Likewise. (vect_grouped_load_supported): Likewise. (vect_permute_load_chain): Likewise. (vect_shift_permute_load_chain): Likewise. * tree-vect-slp.c (vect_build_slp_tree_1): Likewise. (vect_transform_slp_perm_load): Likewise. (vect_schedule_slp_instance): Likewise. * tree-vect-stmts.c (perm_mask_for_reverse): Likewise. (vectorizable_mask_load_store): Likewise. (vectorizable_bswap): Likewise. (vectorizable_store): Likewise. (vectorizable_load): Likewise. * tree-vect-generic.c (lower_vec_perm): Use vec_perm_builder and vec_perm_indices instead of auto_vec_perm_indices. Use tree_to_vec_perm_builder to read the vector from a tree. * tree-vect-loop.c (calc_vec_perm_mask_for_shift): Take a vec_perm_builder instead of a vec_perm_indices. (have_whole_vector_shift): Use vec_perm_builder and vec_perm_indices instead of auto_vec_perm_indices. Leave the truncation to calc_vec_perm_mask_for_shift. (vect_create_epilog_for_reduction): Likewise. * config/aarch64/aarch64.c (expand_vec_perm_d::perm): Change from auto_vec_perm_indices to vec_perm_indices. (aarch64_expand_vec_perm_const_1): Use rotate_inputs on d.perm instead of changing individual elements. (aarch64_vectorize_vec_perm_const): Use new_vector to install the vector in d.perm. * config/arm/arm.c (expand_vec_perm_d::perm): Change from auto_vec_perm_indices to vec_perm_indices. (arm_expand_vec_perm_const_1): Use rotate_inputs on d.perm instead of changing individual elements. (arm_vectorize_vec_perm_const): Use new_vector to install the vector in d.perm. * config/powerpcspe/powerpcspe.c (rs6000_expand_extract_even): Update vec_perm_builder constructor. (rs6000_expand_interleave): Likewise. * config/rs6000/rs6000.c (rs6000_expand_extract_even): Likewise. (rs6000_expand_interleave): Likewise. Index: gcc/int-vector-builder.h =================================================================== --- /dev/null 2017-12-09 13:59:56.352713187 +0000 +++ gcc/int-vector-builder.h 2017-12-09 22:48:47.545825268 +0000 @@ -0,0 +1,90 @@ +/* A class for building vector integer constants. + Copyright (C) 2017 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef GCC_INT_VECTOR_BUILDER_H +#define GCC_INT_VECTOR_BUILDER_H 1 + +#include "vector-builder.h" + +/* This class is used to build vectors of integer type T using the same + encoding as tree and rtx constants. See vector_builder for more + details. */ +template +class int_vector_builder : public vector_builder > +{ + typedef vector_builder parent; + friend class vector_builder; + +public: + int_vector_builder () {} + int_vector_builder (unsigned int, unsigned int, unsigned int); + + using parent::new_vector; + +private: + bool equal_p (T, T) const; + bool allow_steps_p () const { return true; } + bool integral_p (T) const { return true; } + T step (T, T) const; + T apply_step (T, unsigned int, T) const; + bool can_elide_p (T) const { return true; } + void note_representative (T *, T) {} +}; + +/* Create a new builder for a vector with FULL_NELTS elements. + Initially encode the value as NPATTERNS interleaved patterns with + NELTS_PER_PATTERN elements each. */ + +template +inline +int_vector_builder::int_vector_builder (unsigned int full_nelts, + unsigned int npatterns, + unsigned int nelts_per_pattern) +{ + new_vector (full_nelts, npatterns, nelts_per_pattern); +} + +/* Return true if elements ELT1 and ELT2 are equal. */ + +template +inline bool +int_vector_builder::equal_p (T elt1, T elt2) const +{ + return elt1 == elt2; +} + +/* Return the value of element ELT2 minus the value of element ELT1. */ + +template +inline T +int_vector_builder::step (T elt1, T elt2) const +{ + return elt2 - elt1; +} + +/* Return a vector element with the value BASE + FACTOR * STEP. */ + +template +inline T +int_vector_builder::apply_step (T base, unsigned int factor, T step) const +{ + return base + factor * step; +} + +#endif Index: gcc/vec-perm-indices.h =================================================================== --- gcc/vec-perm-indices.h 2017-12-09 22:47:27.885318101 +0000 +++ gcc/vec-perm-indices.h 2017-12-09 22:48:47.548825399 +0000 @@ -20,30 +20,102 @@ Software Foundation; either version 3, o #ifndef GCC_VEC_PERN_INDICES_H #define GCC_VEC_PERN_INDICES_H 1 +#include "int-vector-builder.h" + +/* A vector_builder for building constant permutation vectors. + The elements do not need to be clamped to a particular range + of input elements. */ +typedef int_vector_builder vec_perm_builder; + /* This class represents a constant permutation vector, such as that used - as the final operand to a VEC_PERM_EXPR. */ -class vec_perm_indices : public auto_vec + as the final operand to a VEC_PERM_EXPR. The vector is canonicalized + for a particular number of input vectors and for a particular number + of elements per input. The class copes with cases in which the + input and output vectors have different numbers of elements. */ +class vec_perm_indices { - typedef unsigned short element_type; - typedef auto_vec parent_type; + typedef HOST_WIDE_INT element_type; public: - vec_perm_indices () {} - vec_perm_indices (unsigned int nunits) : parent_type (nunits) {} + vec_perm_indices (); + vec_perm_indices (const vec_perm_builder &, unsigned int, unsigned int); + void new_vector (const vec_perm_builder &, unsigned int, unsigned int); void new_expanded_vector (const vec_perm_indices &, unsigned int); + void rotate_inputs (int delta); + + /* Return the underlying vector encoding. */ + const vec_perm_builder &encoding () const { return m_encoding; } + + /* Return the number of output elements. This is called length () + so that we present a more vec-like interface. */ + unsigned int length () const { return m_encoding.full_nelts (); } + + /* Return the number of input vectors being permuted. */ + unsigned int ninputs () const { return m_ninputs; } + /* Return the number of elements in each input vector. */ + unsigned int nelts_per_input () const { return m_nelts_per_input; } + + /* Return the total number of input elements. */ + unsigned int input_nelts () const { return m_ninputs * m_nelts_per_input; } + + element_type clamp (element_type) const; + element_type operator[] (unsigned int i) const; bool all_in_range_p (element_type, element_type) const; private: vec_perm_indices (const vec_perm_indices &); -}; -/* Temporary. */ -typedef vec_perm_indices vec_perm_builder; -typedef vec_perm_indices auto_vec_perm_indices; + vec_perm_builder m_encoding; + unsigned int m_ninputs; + unsigned int m_nelts_per_input; +}; bool tree_to_vec_perm_builder (vec_perm_builder *, tree); rtx vec_perm_indices_to_rtx (machine_mode, const vec_perm_indices &); +inline +vec_perm_indices::vec_perm_indices () + : m_ninputs (0), + m_nelts_per_input (0) +{ +} + +/* Construct a permutation vector that selects between NINPUTS vector + inputs that have NELTS_PER_INPUT elements each. Take the elements of + the new vector from ELEMENTS, clamping each one to be in range. */ + +inline +vec_perm_indices::vec_perm_indices (const vec_perm_builder &elements, + unsigned int ninputs, + unsigned int nelts_per_input) +{ + new_vector (elements, ninputs, nelts_per_input); +} + +/* Return the canonical value for permutation vector element ELT, + taking into account the current number of input elements. */ + +inline vec_perm_indices::element_type +vec_perm_indices::clamp (element_type elt) const +{ + element_type limit = input_nelts (); + elt %= limit; + /* Treat negative elements as counting from the end. This only matters + if the vector size is not a power of 2. */ + if (elt < 0) + elt += limit; + return elt; +} + +/* Return the value of vector element I, which might or might not be + explicitly encoded. */ + +inline vec_perm_indices::element_type +vec_perm_indices::operator[] (unsigned int i) const +{ + return clamp (m_encoding.elt (i)); +} + #endif Index: gcc/vec-perm-indices.c =================================================================== --- gcc/vec-perm-indices.c 2017-12-09 22:47:27.885318101 +0000 +++ gcc/vec-perm-indices.c 2017-12-09 22:48:47.548825399 +0000 @@ -22,11 +22,33 @@ Software Foundation; either version 3, o #include "coretypes.h" #include "vec-perm-indices.h" #include "tree.h" +#include "fold-const.h" +#include "tree-vector-builder.h" #include "backend.h" #include "rtl.h" #include "memmodel.h" #include "emit-rtl.h" +/* Switch to a new permutation vector that selects between NINPUTS vector + inputs that have NELTS_PER_INPUT elements each. Take the elements of the + new permutation vector from ELEMENTS, clamping each one to be in range. */ + +void +vec_perm_indices::new_vector (const vec_perm_builder &elements, + unsigned int ninputs, + unsigned int nelts_per_input) +{ + m_ninputs = ninputs; + m_nelts_per_input = nelts_per_input; + /* Expand the encoding and clamp each element. E.g. { 0, 2, 4, ... } + might wrap halfway if there is only one vector input. */ + unsigned int full_nelts = elements.full_nelts (); + m_encoding.new_vector (full_nelts, full_nelts, 1); + for (unsigned int i = 0; i < full_nelts; ++i) + m_encoding.quick_push (clamp (elements.elt (i))); + m_encoding.finalize (); +} + /* Switch to a new permutation vector that selects the same input elements as ORIG, but with each element split into FACTOR pieces. For example, if ORIG is { 1, 2, 0, 3 } and FACTOR is 2, the new permutation is @@ -36,14 +58,31 @@ Software Foundation; either version 3, o vec_perm_indices::new_expanded_vector (const vec_perm_indices &orig, unsigned int factor) { - truncate (0); - reserve (orig.length () * factor); - for (unsigned int i = 0; i < orig.length (); ++i) + m_ninputs = orig.m_ninputs; + m_nelts_per_input = orig.m_nelts_per_input * factor; + m_encoding.new_vector (orig.m_encoding.full_nelts () * factor, + orig.m_encoding.npatterns () * factor, + orig.m_encoding.nelts_per_pattern ()); + unsigned int encoded_nelts = orig.m_encoding.encoded_nelts (); + for (unsigned int i = 0; i < encoded_nelts; ++i) { - element_type base = orig[i] * factor; + element_type base = orig.m_encoding[i] * factor; for (unsigned int j = 0; j < factor; ++j) - quick_push (base + j); + m_encoding.quick_push (base + j); } + m_encoding.finalize (); +} + +/* Rotate the inputs of the permutation right by DELTA inputs. This changes + the values of the permutation vector but it doesn't change the way that + the elements are encoded. */ + +void +vec_perm_indices::rotate_inputs (int delta) +{ + element_type element_delta = delta * m_nelts_per_input; + for (unsigned int i = 0; i < m_encoding.length (); ++i) + m_encoding[i] = clamp (m_encoding[i] + element_delta); } /* Return true if all elements of the permutation vector are in the range @@ -52,9 +91,44 @@ vec_perm_indices::new_expanded_vector (c bool vec_perm_indices::all_in_range_p (element_type start, element_type size) const { - for (unsigned int i = 0; i < length (); ++i) - if ((*this)[i] < start || ((*this)[i] - start) >= size) + /* Check the first two elements of each pattern. */ + unsigned int npatterns = m_encoding.npatterns (); + unsigned int nelts_per_pattern = m_encoding.nelts_per_pattern (); + unsigned int base_nelts = npatterns * MIN (nelts_per_pattern, 2); + for (unsigned int i = 0; i < base_nelts; ++i) + if (m_encoding[i] < start || (m_encoding[i] - start) >= size) return false; + + /* For stepped encodings, check the full range of the series. */ + if (nelts_per_pattern == 3) + { + element_type limit = input_nelts (); + + /* The number of elements in each pattern beyond the first two + that we checked above. */ + unsigned int step_nelts = (m_encoding.full_nelts () / npatterns) - 2; + for (unsigned int i = 0; i < npatterns; ++i) + { + /* BASE1 has been checked but BASE2 hasn't. */ + element_type base1 = m_encoding[i + npatterns]; + element_type base2 = m_encoding[i + base_nelts]; + + /* The step to add to get from BASE1 to each subsequent value. */ + element_type step = clamp (base2 - base1); + + /* STEP has no inherent sign, so a value near LIMIT can + act as a negative step. The series is in range if it + is in range according to one of the two interpretations. + + Since we're dealing with clamped values, ELEMENT_TYPE is + wide enough for overflow not to be a problem. */ + element_type headroom_down = base1 - start; + element_type headroom_up = size - headroom_down - 1; + if (headroom_up < step * step_nelts + && headroom_down < (limit - step) * step_nelts) + return false; + } + } return true; } @@ -65,15 +139,16 @@ vec_perm_indices::all_in_range_p (elemen bool tree_to_vec_perm_builder (vec_perm_builder *builder, tree cst) { - unsigned int nelts = TYPE_VECTOR_SUBPARTS (TREE_TYPE (cst)); - for (unsigned int i = 0; i < nelts; ++i) - if (!tree_fits_shwi_p (vector_cst_elt (cst, i))) + unsigned int encoded_nelts = vector_cst_encoded_nelts (cst); + for (unsigned int i = 0; i < encoded_nelts; ++i) + if (!tree_fits_shwi_p (VECTOR_CST_ENCODED_ELT (cst, i))) return false; - builder->reserve (nelts); - for (unsigned int i = 0; i < nelts; ++i) - builder->quick_push (tree_to_shwi (vector_cst_elt (cst, i)) - & (2 * nelts - 1)); + builder->new_vector (TYPE_VECTOR_SUBPARTS (TREE_TYPE (cst)), + VECTOR_CST_NPATTERNS (cst), + VECTOR_CST_NELTS_PER_PATTERN (cst)); + for (unsigned int i = 0; i < encoded_nelts; ++i) + builder->quick_push (tree_to_shwi (VECTOR_CST_ENCODED_ELT (cst, i))); return true; } Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:47:27.881318099 +0000 +++ gcc/optabs.c 2017-12-09 22:48:47.546825312 +0000 @@ -5456,6 +5456,11 @@ expand_vec_perm_const (machine_mode mode rtx_insn *last = get_last_insn (); bool single_arg_p = rtx_equal_p (v0, v1); + /* Always specify two input vectors here and leave the target to handle + cases in which the inputs are equal. Not all backends can cope with + the single-input representation when testing for a double-input + target instruction. */ + vec_perm_indices indices (sel, 2, GET_MODE_NUNITS (mode)); /* See if this can be handled with a vec_shr. We only do this if the second vector is all zeroes. */ @@ -5468,7 +5473,7 @@ expand_vec_perm_const (machine_mode mode && (shift_code != CODE_FOR_nothing || shift_code_qi != CODE_FOR_nothing)) { - rtx shift_amt = shift_amt_for_vec_perm_mask (mode, sel); + rtx shift_amt = shift_amt_for_vec_perm_mask (mode, indices); if (shift_amt) { struct expand_operand ops[3]; @@ -5500,7 +5505,7 @@ expand_vec_perm_const (machine_mode mode else v1 = force_reg (mode, v1); - if (targetm.vectorize.vec_perm_const (mode, target, v0, v1, sel)) + if (targetm.vectorize.vec_perm_const (mode, target, v0, v1, indices)) return target; } @@ -5509,7 +5514,7 @@ expand_vec_perm_const (machine_mode mode rtx target_qi = NULL_RTX, v0_qi = NULL_RTX, v1_qi = NULL_RTX; if (qimode != VOIDmode) { - qimode_indices.new_expanded_vector (sel, GET_MODE_UNIT_SIZE (mode)); + qimode_indices.new_expanded_vector (indices, GET_MODE_UNIT_SIZE (mode)); target_qi = gen_reg_rtx (qimode); v0_qi = gen_lowpart (qimode, v0); v1_qi = gen_lowpart (qimode, v1); @@ -5536,7 +5541,7 @@ expand_vec_perm_const (machine_mode mode REQUIRED_SEL_MODE is OK. */ if (sel_mode != required_sel_mode) { - if (!selector_fits_mode_p (required_sel_mode, sel)) + if (!selector_fits_mode_p (required_sel_mode, indices)) { delete_insns_since (last); return NULL_RTX; @@ -5547,7 +5552,7 @@ expand_vec_perm_const (machine_mode mode insn_code icode = direct_optab_handler (vec_perm_optab, mode); if (icode != CODE_FOR_nothing) { - rtx sel_rtx = vec_perm_indices_to_rtx (sel_mode, sel); + rtx sel_rtx = vec_perm_indices_to_rtx (sel_mode, indices); rtx tmp = expand_vec_perm_1 (icode, target, v0, v1, sel_rtx); if (tmp) return tmp; @@ -5621,7 +5626,7 @@ expand_vec_perm_var (machine_mode mode, gcc_assert (sel != NULL); /* Broadcast the low byte each element into each of its bytes. */ - vec_perm_builder const_sel (w); + vec_perm_builder const_sel (w, w, 1); for (i = 0; i < w; ++i) { int this_e = i / u * u; @@ -5848,7 +5853,7 @@ expand_mult_highpart (machine_mode mode, expand_insn (optab_handler (tab2, mode), 3, eops); m2 = gen_lowpart (mode, eops[0].value); - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); if (method == 2) { for (i = 0; i < nunits; ++i) Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:47:27.881318099 +0000 +++ gcc/optabs-query.c 2017-12-09 22:48:47.545825268 +0000 @@ -501,12 +501,13 @@ can_mult_highpart_p (machine_mode mode, op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab; if (optab_handler (op, mode) != CODE_FOR_nothing) { - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); for (i = 0; i < nunits; ++i) sel.quick_push (!BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0)); - if (can_vec_perm_const_p (mode, sel)) + vec_perm_indices indices (sel, 2, nunits); + if (can_vec_perm_const_p (mode, indices)) return 2; } } @@ -517,10 +518,11 @@ can_mult_highpart_p (machine_mode mode, op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; if (optab_handler (op, mode) != CODE_FOR_nothing) { - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); for (i = 0; i < nunits; ++i) sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); - if (can_vec_perm_const_p (mode, sel)) + vec_perm_indices indices (sel, 2, nunits); + if (can_vec_perm_const_p (mode, indices)) return 3; } } Index: gcc/fold-const.c =================================================================== --- gcc/fold-const.c 2017-12-09 22:47:27.881318099 +0000 +++ gcc/fold-const.c 2017-12-09 22:48:47.545825268 +0000 @@ -11217,7 +11217,7 @@ fold_ternary_loc (location_t loc, enum t { unsigned int nelts = VECTOR_CST_NELTS (arg0), i; gcc_assert (nelts == TYPE_VECTOR_SUBPARTS (type)); - auto_vec_perm_indices sel (nelts); + vec_perm_builder sel (nelts, nelts, 1); for (i = 0; i < nelts; i++) { tree val = VECTOR_CST_ELT (arg0, i); @@ -11228,7 +11228,8 @@ fold_ternary_loc (location_t loc, enum t else /* Currently unreachable. */ return NULL_TREE; } - tree t = fold_vec_perm (type, arg1, arg2, sel); + tree t = fold_vec_perm (type, arg1, arg2, + vec_perm_indices (sel, 2, nelts)); if (t != NULL_TREE) return t; } @@ -11558,8 +11559,8 @@ fold_ternary_loc (location_t loc, enum t mask2 = 2 * nelts - 1; mask = single_arg ? (nelts - 1) : mask2; gcc_assert (nelts == TYPE_VECTOR_SUBPARTS (type)); - auto_vec_perm_indices sel (nelts); - auto_vec_perm_indices sel2 (nelts); + vec_perm_builder sel (nelts, nelts, 1); + vec_perm_builder sel2 (nelts, nelts, 1); for (i = 0; i < nelts; i++) { tree val = VECTOR_CST_ELT (arg2, i); @@ -11604,12 +11605,13 @@ fold_ternary_loc (location_t loc, enum t need_mask_canon = true; } + vec_perm_indices indices (sel, 2, nelts); if ((TREE_CODE (op0) == VECTOR_CST || TREE_CODE (op0) == CONSTRUCTOR) && (TREE_CODE (op1) == VECTOR_CST || TREE_CODE (op1) == CONSTRUCTOR)) { - tree t = fold_vec_perm (type, op0, op1, sel); + tree t = fold_vec_perm (type, op0, op1, indices); if (t != NULL_TREE) return t; } @@ -11621,11 +11623,14 @@ fold_ternary_loc (location_t loc, enum t argument permutation while still allowing an equivalent 2-argument version. */ if (need_mask_canon && arg2 == op2 - && !can_vec_perm_const_p (TYPE_MODE (type), sel, false) - && can_vec_perm_const_p (TYPE_MODE (type), sel2, false)) + && !can_vec_perm_const_p (TYPE_MODE (type), indices, false) + && can_vec_perm_const_p (TYPE_MODE (type), + vec_perm_indices (sel2, 2, nelts), + false)) { need_mask_canon = need_mask_canon2; - sel = sel2; + sel.truncate (0); + sel.splice (sel2); } if (need_mask_canon && arg2 == op2) Index: gcc/tree-ssa-forwprop.c =================================================================== --- gcc/tree-ssa-forwprop.c 2017-12-09 22:47:27.883318100 +0000 +++ gcc/tree-ssa-forwprop.c 2017-12-09 22:48:47.546825312 +0000 @@ -2019,7 +2019,7 @@ simplify_vector_constructor (gimple_stmt elem_type = TREE_TYPE (type); elem_size = TREE_INT_CST_LOW (TYPE_SIZE (elem_type)); - auto_vec_perm_indices sel (nelts); + vec_perm_builder sel (nelts, nelts, 1); orig = NULL; conv_code = ERROR_MARK; maybe_ident = true; @@ -2109,7 +2109,8 @@ simplify_vector_constructor (gimple_stmt { tree mask_type; - if (!can_vec_perm_const_p (TYPE_MODE (type), sel)) + vec_perm_indices indices (sel, 1, nelts); + if (!can_vec_perm_const_p (TYPE_MODE (type), indices)) return false; mask_type = build_vector_type (build_nonstandard_integer_type (elem_size, 1), Index: gcc/tree-vect-data-refs.c =================================================================== --- gcc/tree-vect-data-refs.c 2017-12-09 22:47:27.883318100 +0000 +++ gcc/tree-vect-data-refs.c 2017-12-09 22:48:47.546825312 +0000 @@ -4566,7 +4566,7 @@ vect_grouped_store_supported (tree vecty if (VECTOR_MODE_P (mode)) { unsigned int i, nelt = GET_MODE_NUNITS (mode); - auto_vec_perm_indices sel (nelt); + vec_perm_builder sel (nelt, nelt, 1); sel.quick_grow (nelt); if (count == 3) @@ -4574,6 +4574,7 @@ vect_grouped_store_supported (tree vecty unsigned int j0 = 0, j1 = 0, j2 = 0; unsigned int i, j; + vec_perm_indices indices; for (j = 0; j < 3; j++) { int nelt0 = ((3 - j) * nelt) % 3; @@ -4588,7 +4589,8 @@ vect_grouped_store_supported (tree vecty if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = 0; } - if (!can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (mode, indices)) { if (dump_enabled_p ()) dump_printf (MSG_MISSED_OPTIMIZATION, @@ -4605,7 +4607,8 @@ vect_grouped_store_supported (tree vecty if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = nelt + j2++; } - if (!can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (mode, indices)) { if (dump_enabled_p ()) dump_printf (MSG_MISSED_OPTIMIZATION, @@ -4625,11 +4628,13 @@ vect_grouped_store_supported (tree vecty sel[i * 2] = i; sel[i * 2 + 1] = i + nelt; } - if (can_vec_perm_const_p (mode, sel)) + vec_perm_indices indices (sel, 2, nelt); + if (can_vec_perm_const_p (mode, indices)) { for (i = 0; i < nelt; i++) sel[i] += nelt / 2; - if (can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (can_vec_perm_const_p (mode, indices)) return true; } } @@ -4731,7 +4736,7 @@ vect_permute_store_chain (vec dr_c unsigned int i, n, log_length = exact_log2 (length); unsigned int j, nelt = TYPE_VECTOR_SUBPARTS (vectype); - auto_vec_perm_indices sel (nelt); + vec_perm_builder sel (nelt, nelt, 1); sel.quick_grow (nelt); result_chain->quick_grow (length); @@ -4742,6 +4747,7 @@ vect_permute_store_chain (vec dr_c { unsigned int j0 = 0, j1 = 0, j2 = 0; + vec_perm_indices indices; for (j = 0; j < 3; j++) { int nelt0 = ((3 - j) * nelt) % 3; @@ -4757,7 +4763,8 @@ vect_permute_store_chain (vec dr_c if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = 0; } - perm3_mask_low = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm3_mask_low = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < nelt; i++) { @@ -4768,7 +4775,8 @@ vect_permute_store_chain (vec dr_c if (3 * i + nelt2 < nelt) sel[3 * i + nelt2] = nelt + j2++; } - perm3_mask_high = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm3_mask_high = vect_gen_perm_mask_checked (vectype, indices); vect1 = dr_chain[0]; vect2 = dr_chain[1]; @@ -4805,11 +4813,13 @@ vect_permute_store_chain (vec dr_c sel[i * 2] = i; sel[i * 2 + 1] = i + nelt; } - perm_mask_high = vect_gen_perm_mask_checked (vectype, sel); + vec_perm_indices indices (sel, 2, nelt); + perm_mask_high = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < nelt; i++) sel[i] += nelt / 2; - perm_mask_low = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm_mask_low = vect_gen_perm_mask_checked (vectype, indices); for (i = 0, n = log_length; i < n; i++) { @@ -5154,11 +5164,12 @@ vect_grouped_load_supported (tree vectyp if (VECTOR_MODE_P (mode)) { unsigned int i, j, nelt = GET_MODE_NUNITS (mode); - auto_vec_perm_indices sel (nelt); + vec_perm_builder sel (nelt, nelt, 1); sel.quick_grow (nelt); if (count == 3) { + vec_perm_indices indices; unsigned int k; for (k = 0; k < 3; k++) { @@ -5167,7 +5178,8 @@ vect_grouped_load_supported (tree vectyp sel[i] = 3 * i + k; else sel[i] = 0; - if (!can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (mode, indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5180,7 +5192,8 @@ vect_grouped_load_supported (tree vectyp sel[i] = i; else sel[i] = nelt + ((nelt + k) % 3) + 3 * (j++); - if (!can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (mode, indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5195,13 +5208,16 @@ vect_grouped_load_supported (tree vectyp { /* If length is not equal to 3 then only power of 2 is supported. */ gcc_assert (pow2p_hwi (count)); + for (i = 0; i < nelt; i++) sel[i] = i * 2; - if (can_vec_perm_const_p (mode, sel)) + vec_perm_indices indices (sel, 2, nelt); + if (can_vec_perm_const_p (mode, indices)) { for (i = 0; i < nelt; i++) sel[i] = i * 2 + 1; - if (can_vec_perm_const_p (mode, sel)) + indices.new_vector (sel, 2, nelt); + if (can_vec_perm_const_p (mode, indices)) return true; } } @@ -5316,7 +5332,7 @@ vect_permute_load_chain (vec dr_ch unsigned int i, j, log_length = exact_log2 (length); unsigned nelt = TYPE_VECTOR_SUBPARTS (vectype); - auto_vec_perm_indices sel (nelt); + vec_perm_builder sel (nelt, nelt, 1); sel.quick_grow (nelt); result_chain->quick_grow (length); @@ -5327,6 +5343,7 @@ vect_permute_load_chain (vec dr_ch { unsigned int k; + vec_perm_indices indices; for (k = 0; k < 3; k++) { for (i = 0; i < nelt; i++) @@ -5334,15 +5351,16 @@ vect_permute_load_chain (vec dr_ch sel[i] = 3 * i + k; else sel[i] = 0; - perm3_mask_low = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm3_mask_low = vect_gen_perm_mask_checked (vectype, indices); for (i = 0, j = 0; i < nelt; i++) if (3 * i + k < 2 * nelt) sel[i] = i; else sel[i] = nelt + ((nelt + k) % 3) + 3 * (j++); - - perm3_mask_high = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm3_mask_high = vect_gen_perm_mask_checked (vectype, indices); first_vect = dr_chain[0]; second_vect = dr_chain[1]; @@ -5374,11 +5392,13 @@ vect_permute_load_chain (vec dr_ch for (i = 0; i < nelt; ++i) sel[i] = i * 2; - perm_mask_even = vect_gen_perm_mask_checked (vectype, sel); + vec_perm_indices indices (sel, 2, nelt); + perm_mask_even = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < nelt; ++i) sel[i] = i * 2 + 1; - perm_mask_odd = vect_gen_perm_mask_checked (vectype, sel); + indices.new_vector (sel, 2, nelt); + perm_mask_odd = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < log_length; i++) { @@ -5514,7 +5534,7 @@ vect_shift_permute_load_chain (vec stmt_vec_info stmt_info = vinfo_for_stmt (stmt); loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_info); - auto_vec_perm_indices sel (nelt); + vec_perm_builder sel (nelt, nelt, 1); sel.quick_grow (nelt); result_chain->quick_grow (length); @@ -5528,7 +5548,8 @@ vect_shift_permute_load_chain (vec sel[i] = i * 2; for (i = 0; i < nelt / 2; ++i) sel[nelt / 2 + i] = i * 2 + 1; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + vec_perm_indices indices (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5536,13 +5557,14 @@ vect_shift_permute_load_chain (vec supported by target\n"); return false; } - perm2_mask1 = vect_gen_perm_mask_checked (vectype, sel); + perm2_mask1 = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < nelt / 2; ++i) sel[i] = i * 2 + 1; for (i = 0; i < nelt / 2; ++i) sel[nelt / 2 + i] = i * 2; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5550,20 +5572,21 @@ vect_shift_permute_load_chain (vec supported by target\n"); return false; } - perm2_mask2 = vect_gen_perm_mask_checked (vectype, sel); + perm2_mask2 = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to shift all elements. For vector length 8 it is {4 5 6 7 8 9 10 11}. */ for (i = 0; i < nelt; i++) sel[i] = nelt / 2 + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "shift permutation is not supported by target\n"); return false; } - shift1_mask = vect_gen_perm_mask_checked (vectype, sel); + shift1_mask = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to select vector from 2. For vector length 8 it is {0 1 2 3 12 13 14 15}. */ @@ -5571,14 +5594,15 @@ vect_shift_permute_load_chain (vec sel[i] = i; for (i = nelt / 2; i < nelt; i++) sel[i] = nelt + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "select is not supported by target\n"); return false; } - select_mask = vect_gen_perm_mask_checked (vectype, sel); + select_mask = vect_gen_perm_mask_checked (vectype, indices); for (i = 0; i < log_length; i++) { @@ -5634,7 +5658,8 @@ vect_shift_permute_load_chain (vec sel[i] = 3 * k + (l % 3); k++; } - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + vec_perm_indices indices (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, @@ -5642,59 +5667,63 @@ vect_shift_permute_load_chain (vec supported by target\n"); return false; } - perm3_mask = vect_gen_perm_mask_checked (vectype, sel); + perm3_mask = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to shift all elements. For vector length 8 it is {6 7 8 9 10 11 12 13}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + (nelt % 3) + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "shift permutation is not supported by target\n"); return false; } - shift1_mask = vect_gen_perm_mask_checked (vectype, sel); + shift1_mask = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to shift all elements. For vector length 8 it is {5 6 7 8 9 10 11 12}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + 1 + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "shift permutation is not supported by target\n"); return false; } - shift2_mask = vect_gen_perm_mask_checked (vectype, sel); + shift2_mask = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to shift all elements. For vector length 8 it is {3 4 5 6 7 8 9 10}. */ for (i = 0; i < nelt; i++) sel[i] = (nelt / 3) + (nelt % 3) / 2 + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "shift permutation is not supported by target\n"); return false; } - shift3_mask = vect_gen_perm_mask_checked (vectype, sel); + shift3_mask = vect_gen_perm_mask_checked (vectype, indices); /* Generating permutation constant to shift all elements. For vector length 8 it is {5 6 7 8 9 10 11 12}. */ for (i = 0; i < nelt; i++) sel[i] = 2 * (nelt / 3) + (nelt % 3) / 2 + i; - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { if (dump_enabled_p ()) dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location, "shift permutation is not supported by target\n"); return false; } - shift4_mask = vect_gen_perm_mask_checked (vectype, sel); + shift4_mask = vect_gen_perm_mask_checked (vectype, indices); for (k = 0; k < 3; k++) { Index: gcc/tree-vect-slp.c =================================================================== --- gcc/tree-vect-slp.c 2017-12-09 22:47:27.884318101 +0000 +++ gcc/tree-vect-slp.c 2017-12-09 22:48:47.547825355 +0000 @@ -894,7 +894,7 @@ vect_build_slp_tree_1 (vec_info *vinfo, && TREE_CODE_CLASS (alt_stmt_code) != tcc_reference) { unsigned int count = TYPE_VECTOR_SUBPARTS (vectype); - auto_vec_perm_indices sel (count); + vec_perm_builder sel (count, count, 1); for (i = 0; i < count; ++i) { unsigned int elt = i; @@ -902,7 +902,8 @@ vect_build_slp_tree_1 (vec_info *vinfo, elt += count; sel.quick_push (elt); } - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + vec_perm_indices indices (sel, 2, count); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) { for (i = 0; i < group_size; ++i) if (gimple_assign_rhs_code (stmts[i]) == alt_stmt_code) @@ -3570,8 +3571,9 @@ vect_transform_slp_perm_load (slp_tree n (int_mode_for_mode (TYPE_MODE (TREE_TYPE (vectype))).require (), 1); mask_type = get_vectype_for_scalar_type (mask_element_type); nunits = TYPE_VECTOR_SUBPARTS (vectype); - auto_vec_perm_indices mask (nunits); + vec_perm_builder mask (nunits, nunits, 1); mask.quick_grow (nunits); + vec_perm_indices indices; /* Initialize the vect stmts of NODE to properly insert the generated stmts later. */ @@ -3644,10 +3646,10 @@ vect_transform_slp_perm_load (slp_tree n noop_p = false; mask[index++] = mask_element; - if (index == nunits) + if (index == nunits && !noop_p) { - if (! noop_p - && ! can_vec_perm_const_p (mode, mask)) + indices.new_vector (mask, 2, nunits); + if (!can_vec_perm_const_p (mode, indices)) { if (dump_enabled_p ()) { @@ -3655,16 +3657,19 @@ vect_transform_slp_perm_load (slp_tree n vect_location, "unsupported vect permute { "); for (i = 0; i < nunits; ++i) - dump_printf (MSG_MISSED_OPTIMIZATION, "%d ", mask[i]); + dump_printf (MSG_MISSED_OPTIMIZATION, + HOST_WIDE_INT_PRINT_DEC " ", mask[i]); dump_printf (MSG_MISSED_OPTIMIZATION, "}\n"); } gcc_assert (analyze_only); return false; } - if (! noop_p) - ++*n_perms; + ++*n_perms; + } + if (index == nunits) + { if (!analyze_only) { tree mask_vec = NULL_TREE; @@ -3797,7 +3802,7 @@ vect_schedule_slp_instance (slp_tree nod enum tree_code code0 = gimple_assign_rhs_code (stmt); enum tree_code ocode = ERROR_MARK; gimple *ostmt; - auto_vec_perm_indices mask (group_size); + vec_perm_builder mask (group_size, group_size, 1); FOR_EACH_VEC_ELT (SLP_TREE_SCALAR_STMTS (node), i, ostmt) if (gimple_assign_rhs_code (ostmt) != code0) { Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:47:27.885318101 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:48:47.548825399 +0000 @@ -1717,13 +1717,14 @@ perm_mask_for_reverse (tree vectype) nunits = TYPE_VECTOR_SUBPARTS (vectype); - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); for (i = 0; i < nunits; ++i) sel.quick_push (nunits - 1 - i); - if (!can_vec_perm_const_p (TYPE_MODE (vectype), sel)) + vec_perm_indices indices (sel, 1, nunits); + if (!can_vec_perm_const_p (TYPE_MODE (vectype), indices)) return NULL_TREE; - return vect_gen_perm_mask_checked (vectype, sel); + return vect_gen_perm_mask_checked (vectype, indices); } /* A subroutine of get_load_store_type, with a subset of the same @@ -2185,27 +2186,32 @@ vectorizable_mask_load_store (gimple *st { modifier = WIDEN; - auto_vec_perm_indices sel (gather_off_nunits); + vec_perm_builder sel (gather_off_nunits, gather_off_nunits, 1); for (i = 0; i < gather_off_nunits; ++i) sel.quick_push (i | nunits); - perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, sel); + vec_perm_indices indices (sel, 1, gather_off_nunits); + perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, + indices); } else if (nunits == gather_off_nunits * 2) { modifier = NARROW; - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); sel.quick_grow (nunits); for (i = 0; i < nunits; ++i) sel[i] = i < gather_off_nunits ? i : i + nunits - gather_off_nunits; + vec_perm_indices indices (sel, 2, nunits); + perm_mask = vect_gen_perm_mask_checked (vectype, indices); - perm_mask = vect_gen_perm_mask_checked (vectype, sel); ncopies *= 2; + for (i = 0; i < nunits; ++i) sel[i] = i | gather_off_nunits; - mask_perm_mask = vect_gen_perm_mask_checked (masktype, sel); + indices.new_vector (sel, 2, gather_off_nunits); + mask_perm_mask = vect_gen_perm_mask_checked (masktype, indices); } else gcc_unreachable (); @@ -2498,12 +2504,13 @@ vectorizable_bswap (gimple *stmt, gimple unsigned int num_bytes = TYPE_VECTOR_SUBPARTS (char_vectype); unsigned word_bytes = num_bytes / nunits; - auto_vec_perm_indices elts (num_bytes); + vec_perm_builder elts (num_bytes, num_bytes, 1); for (unsigned i = 0; i < nunits; ++i) for (unsigned j = 0; j < word_bytes; ++j) elts.quick_push ((i + 1) * word_bytes - j - 1); - if (!can_vec_perm_const_p (TYPE_MODE (char_vectype), elts)) + vec_perm_indices indices (elts, 1, num_bytes); + if (!can_vec_perm_const_p (TYPE_MODE (char_vectype), indices)) return false; if (! vec_stmt) @@ -5809,22 +5816,25 @@ vectorizable_store (gimple *stmt, gimple { modifier = WIDEN; - auto_vec_perm_indices sel (scatter_off_nunits); + vec_perm_builder sel (scatter_off_nunits, scatter_off_nunits, 1); for (i = 0; i < (unsigned int) scatter_off_nunits; ++i) sel.quick_push (i | nunits); - perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, sel); + vec_perm_indices indices (sel, 1, scatter_off_nunits); + perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, + indices); gcc_assert (perm_mask != NULL_TREE); } else if (nunits == (unsigned int) scatter_off_nunits * 2) { modifier = NARROW; - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); for (i = 0; i < (unsigned int) nunits; ++i) sel.quick_push (i | scatter_off_nunits); - perm_mask = vect_gen_perm_mask_checked (vectype, sel); + vec_perm_indices indices (sel, 2, nunits); + perm_mask = vect_gen_perm_mask_checked (vectype, indices); gcc_assert (perm_mask != NULL_TREE); ncopies *= 2; } @@ -6845,22 +6855,25 @@ vectorizable_load (gimple *stmt, gimple_ { modifier = WIDEN; - auto_vec_perm_indices sel (gather_off_nunits); + vec_perm_builder sel (gather_off_nunits, gather_off_nunits, 1); for (i = 0; i < gather_off_nunits; ++i) sel.quick_push (i | nunits); - perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, sel); + vec_perm_indices indices (sel, 1, gather_off_nunits); + perm_mask = vect_gen_perm_mask_checked (gs_info.offset_vectype, + indices); } else if (nunits == gather_off_nunits * 2) { modifier = NARROW; - auto_vec_perm_indices sel (nunits); + vec_perm_builder sel (nunits, nunits, 1); for (i = 0; i < nunits; ++i) sel.quick_push (i < gather_off_nunits ? i : i + nunits - gather_off_nunits); - perm_mask = vect_gen_perm_mask_checked (vectype, sel); + vec_perm_indices indices (sel, 2, nunits); + perm_mask = vect_gen_perm_mask_checked (vectype, indices); ncopies *= 2; } else Index: gcc/tree-vect-generic.c =================================================================== --- gcc/tree-vect-generic.c 2017-12-09 22:47:27.883318100 +0000 +++ gcc/tree-vect-generic.c 2017-12-09 22:48:47.547825355 +0000 @@ -1299,15 +1299,13 @@ lower_vec_perm (gimple_stmt_iterator *gs mask = gimple_assign_rhs1 (def_stmt); } - if (TREE_CODE (mask) == VECTOR_CST) - { - auto_vec_perm_indices sel_int (elements); - - for (i = 0; i < elements; ++i) - sel_int.quick_push (TREE_INT_CST_LOW (VECTOR_CST_ELT (mask, i)) - & (2 * elements - 1)); + vec_perm_builder sel_int; - if (can_vec_perm_const_p (TYPE_MODE (vect_type), sel_int)) + if (TREE_CODE (mask) == VECTOR_CST + && tree_to_vec_perm_builder (&sel_int, mask)) + { + vec_perm_indices indices (sel_int, 2, elements); + if (can_vec_perm_const_p (TYPE_MODE (vect_type), indices)) { gimple_assign_set_rhs3 (stmt, mask); update_stmt (stmt); @@ -1319,14 +1317,14 @@ lower_vec_perm (gimple_stmt_iterator *gs != CODE_FOR_nothing && TREE_CODE (vec1) == VECTOR_CST && initializer_zerop (vec1) - && sel_int[0] - && sel_int[0] < elements) + && indices[0] + && indices[0] < elements) { for (i = 1; i < elements; ++i) { - unsigned int expected = i + sel_int[0]; + unsigned int expected = i + indices[0]; /* Indices into the second vector are all equivalent. */ - if (MIN (elements, (unsigned) sel_int[i]) + if (MIN (elements, (unsigned) indices[i]) != MIN (elements, expected)) break; } Index: gcc/tree-vect-loop.c =================================================================== --- gcc/tree-vect-loop.c 2017-12-09 22:47:27.884318101 +0000 +++ gcc/tree-vect-loop.c 2017-12-09 22:48:47.547825355 +0000 @@ -3714,12 +3714,11 @@ vect_estimate_min_profitable_iters (loop vector elements (not bits) for a vector with NELT elements. */ static void calc_vec_perm_mask_for_shift (unsigned int offset, unsigned int nelt, - vec_perm_indices *sel) + vec_perm_builder *sel) { - unsigned int i; - - for (i = 0; i < nelt; i++) - sel->quick_push ((i + offset) & (2 * nelt - 1)); + sel->new_vector (nelt, nelt, 1); + for (unsigned int i = 0; i < nelt; i++) + sel->quick_push (i + offset); } /* Checks whether the target supports whole-vector shifts for vectors of mode @@ -3732,13 +3731,13 @@ have_whole_vector_shift (machine_mode mo return true; unsigned int i, nelt = GET_MODE_NUNITS (mode); - auto_vec_perm_indices sel (nelt); - + vec_perm_builder sel; + vec_perm_indices indices; for (i = nelt/2; i >= 1; i/=2) { - sel.truncate (0); calc_vec_perm_mask_for_shift (i, nelt, &sel); - if (!can_vec_perm_const_p (mode, sel, false)) + indices.new_vector (sel, 2, nelt); + if (!can_vec_perm_const_p (mode, indices, false)) return false; } return true; @@ -5028,7 +5027,8 @@ vect_create_epilog_for_reduction (vec= 1; elt_offset /= 2) { - sel.truncate (0); calc_vec_perm_mask_for_shift (elt_offset, nelements, &sel); - tree mask = vect_gen_perm_mask_any (vectype, sel); + indices.new_vector (sel, 2, nelements); + tree mask = vect_gen_perm_mask_any (vectype, indices); epilog_stmt = gimple_build_assign (vec_dest, VEC_PERM_EXPR, new_temp, zero_vec, mask); new_name = make_ssa_name (vec_dest, epilog_stmt); Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-12-09 22:47:27.856318084 +0000 +++ gcc/config/aarch64/aarch64.c 2017-12-09 22:48:47.535824832 +0000 @@ -13208,7 +13208,7 @@ #define MAX_VECT_LEN 16 struct expand_vec_perm_d { rtx target, op0, op1; - auto_vec_perm_indices perm; + vec_perm_indices perm; machine_mode vmode; bool one_vector_p; bool testing_p; @@ -13598,10 +13598,7 @@ aarch64_expand_vec_perm_const_1 (struct unsigned int nelt = d->perm.length (); if (d->perm[0] >= nelt) { - gcc_assert (nelt == (nelt & -nelt)); - for (unsigned int i = 0; i < nelt; ++i) - d->perm[i] ^= nelt; /* Keep the same index, but in the other vector. */ - + d->perm.rotate_inputs (1); std::swap (d->op0, d->op1); } @@ -13641,12 +13638,10 @@ aarch64_vectorize_vec_perm_const (machin /* Calculate whether all elements are in one vector. */ unsigned int nelt = sel.length (); - d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { unsigned int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); - d.perm.quick_push (ei); } switch (which) @@ -13665,8 +13660,6 @@ aarch64_vectorize_vec_perm_const (machin input vector. */ /* Fall Through. */ case 2: - for (i = 0; i < nelt; ++i) - d.perm[i] &= nelt - 1; d.op0 = op1; d.one_vector_p = true; break; @@ -13677,6 +13670,8 @@ aarch64_vectorize_vec_perm_const (machin break; } + d.perm.new_vector (sel.encoding (), d.one_vector_p ? 1 : 2, nelt); + if (!d.testing_p) return aarch64_expand_vec_perm_const_1 (&d); Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c 2017-12-09 22:47:27.858318085 +0000 +++ gcc/config/arm/arm.c 2017-12-09 22:48:47.538824963 +0000 @@ -28852,7 +28852,7 @@ #define MAX_VECT_LEN 16 struct expand_vec_perm_d { rtx target, op0, op1; - auto_vec_perm_indices perm; + vec_perm_indices perm; machine_mode vmode; bool one_vector_p; bool testing_p; @@ -29360,9 +29360,7 @@ arm_expand_vec_perm_const_1 (struct expa unsigned int nelt = d->perm.length (); if (d->perm[0] >= nelt) { - for (unsigned int i = 0; i < nelt; ++i) - d->perm[i] = (d->perm[i] + nelt) & (2 * nelt - 1); - + d->perm.rotate_inputs (1); std::swap (d->op0, d->op1); } @@ -29402,12 +29400,10 @@ arm_vectorize_vec_perm_const (machine_mo d.testing_p = !target; nelt = GET_MODE_NUNITS (d.vmode); - d.perm.reserve (nelt); for (i = which = 0; i < nelt; ++i) { int ei = sel[i] & (2 * nelt - 1); which |= (ei < nelt ? 1 : 2); - d.perm.quick_push (ei); } switch (which) @@ -29426,8 +29422,6 @@ arm_vectorize_vec_perm_const (machine_mo input vector. */ /* FALLTHRU */ case 2: - for (i = 0; i < nelt; ++i) - d.perm[i] &= nelt - 1; d.op0 = op1; d.one_vector_p = true; break; @@ -29438,6 +29432,8 @@ arm_vectorize_vec_perm_const (machine_mo break; } + d.perm.new_vector (sel.encoding (), d.one_vector_p ? 1 : 2, nelt); + if (d.testing_p) return arm_expand_vec_perm_const_1 (&d); Index: gcc/config/powerpcspe/powerpcspe.c =================================================================== --- gcc/config/powerpcspe/powerpcspe.c 2017-12-09 22:47:27.871318093 +0000 +++ gcc/config/powerpcspe/powerpcspe.c 2017-12-09 22:48:47.541825094 +0000 @@ -38780,7 +38780,7 @@ rs6000_expand_extract_even (rtx target, { machine_mode vmode = GET_MODE (target); unsigned i, nelt = GET_MODE_NUNITS (vmode); - vec_perm_builder perm (nelt); + vec_perm_builder perm (nelt, nelt, 1); for (i = 0; i < nelt; i++) perm.quick_push (i * 2); @@ -38795,7 +38795,7 @@ rs6000_expand_interleave (rtx target, rt { machine_mode vmode = GET_MODE (target); unsigned i, high, nelt = GET_MODE_NUNITS (vmode); - vec_perm_builder perm (nelt); + vec_perm_builder perm (nelt, nelt, 1); high = (highp ? 0 : nelt / 2); for (i = 0; i < nelt / 2; i++) Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c 2017-12-09 22:47:27.874318095 +0000 +++ gcc/config/rs6000/rs6000.c 2017-12-09 22:48:47.544825224 +0000 @@ -36017,7 +36017,7 @@ rs6000_expand_extract_even (rtx target, { machine_mode vmode = GET_MODE (target); unsigned i, nelt = GET_MODE_NUNITS (vmode); - vec_perm_builder perm (nelt); + vec_perm_builder perm (nelt, nelt, 1); for (i = 0; i < nelt; i++) perm.quick_push (i * 2); @@ -36032,7 +36032,7 @@ rs6000_expand_interleave (rtx target, rt { machine_mode vmode = GET_MODE (target); unsigned i, high, nelt = GET_MODE_NUNITS (vmode); - vec_perm_builder perm (nelt); + vec_perm_builder perm (nelt, nelt, 1); high = (highp ? 0 : nelt / 2); for (i = 0; i < nelt / 2; i++) From patchwork Sat Dec 9 23:20:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121298 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1164766qgn; Sat, 9 Dec 2017 15:21:12 -0800 (PST) X-Google-Smtp-Source: AGs4zMbyyOWzmxe2B9HT86sC0LWVBwunI1mjv92yqIvM3luVUQbnyTVmWxKrCcv6I2sg1MATWzjr X-Received: by 10.99.122.3 with SMTP id v3mr32923067pgc.394.1512861672168; Sat, 09 Dec 2017 15:21:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861672; cv=none; d=google.com; s=arc-20160816; b=Ymdr16QHtRLtvQW+7zHccrA+uiXaa9K83yBUM0QXn3GUI9CqFcgTKPxIlQiAak4MEP FYYGGvAU+4KJB15uwc/yvX8e0oVM1fsCWTTK53NL/j4QLg1qgQtkiOPlqzjwLRp8kjgu ETuMsM3/tvwoZtleyAx2/juioduvxQPma/Gpk4LHKQ+o6c/X5Gt1bBFkSh3aCH/CJIKM c1Qyt4QyAJDPAaMyY+6Z7UFwH0UE1nvj7k+dT8z14OK3SlQMZbsy3yraE5Eyo1EaCI75 3mcKGwpA05TLaNumv/CUPcy+ErXmnQg2z8u1h8Pu1qgvZtHxY5vgk5Qk36Cbmxubx1Sx Uj7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=LDan7GiGx/Ks5YEW/622PosOVVvuOMpGHKyAaX2UZwM=; b=N8hMI/DG6/rP7nTMUK6YYDNoGgltRDeGLlpEIFv4EgbSUf7fcAIoF4DxkGs6gjnQOY OlI7Q1Q3e8+8C0e6UmEKAAFKOcpA5f9H/F3Tye3d9EEw781MUdTAXhAg3DJ4oUeozH7y 73f8b/K64dHgMh3px8ijkId8bSOT8Cqc7JuJGvgxRAww2/dqAzRmx6IoXPqyNI/pi4Do jdqBhtMl/hFsV/BUvnpObdVUPw0Yxs9V42RYjwIDXZuOZZypfGuuuoP3EX45euJQ+wR7 Ub0iu1cuLiJlZkY3/bKs4XbrqUYL/kpR9lXd7t7fBnhKGPEFDFTEWzx1dV2EzQV64kTa +XXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=i8+t6Y3x; spf=pass (google.com: domain of gcc-patches-return-468858-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468858-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. 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(vect_gen_perm_mask_any): Likewise. Index: gcc/vec-perm-indices.h =================================================================== --- gcc/vec-perm-indices.h 2017-12-09 22:48:47.548825399 +0000 +++ gcc/vec-perm-indices.h 2017-12-09 22:48:50.361942571 +0000 @@ -73,6 +73,7 @@ typedef int_vector_builder vec_oprnds = vNULL; @@ -6521,17 +6518,10 @@ vect_gen_perm_mask_any (tree vectype, co { tree mask_elt_type, mask_type; - unsigned int nunits = sel.length (); - gcc_checking_assert (nunits == TYPE_VECTOR_SUBPARTS (vectype)); - mask_elt_type = lang_hooks.types.type_for_mode (int_mode_for_mode (TYPE_MODE (TREE_TYPE (vectype))).require (), 1); mask_type = get_vectype_for_scalar_type (mask_elt_type); - - tree_vector_builder mask_elts (mask_type, nunits, 1); - for (unsigned int i = 0; i < nunits; ++i) - mask_elts.quick_push (build_int_cst (mask_elt_type, sel[i])); - return mask_elts.build (); + return vec_perm_indices_to_tree (mask_type, sel); } /* Checked version of vect_gen_perm_mask_any. Asserts can_vec_perm_const_p, From patchwork Sat Dec 9 23:21:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121299 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1165348qgn; Sat, 9 Dec 2017 15:22:05 -0800 (PST) X-Google-Smtp-Source: AGs4zMYy6s3A00KkeydA2VtZnx23My5qavd5/qtaungf7W8vTSkANY0+eOb5b3t+SERYykv5SuHp X-Received: by 10.84.160.227 with SMTP id v32mr35528968plg.428.1512861724991; Sat, 09 Dec 2017 15:22:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861724; cv=none; d=google.com; s=arc-20160816; b=zDfOCmhMDWIwE78ntRo5rs8HI/aTbIHF9LVizOgaXgpw3tp5rD92Oo5SvjIt+6w5B5 pTSMgZZUA4W+IFd3+I9VsNcEanlz40uFfZWnQHh+3gjCrr94sA+3SZrYQBIda2qiv7se 6DUKG4pGEfXx1OghyivoSSl9jrkHoq69wd65g2HIfxzGiU170sx2RHD3bf60FKpyEWVp YzsSS0mwzarC2/BNUGdooxrALA3Iw5zNlu3ZJQ+KyWGDHFeG1OMoseTkudQ0QlqFPJOR xKRwVHy0FGXt4KsRGutservpt8Rz0/pwZLx1GxRKUi6qSzSjGLSi0JGjKfb/gutmT8y3 cqmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=Aa9aQk3XWGcD8hjxglNyund7ylJYgVmWYBiTffs5nYU=; b=TRM5aWbSSFi94ST/rB8lIlq4XcbRTi555dbuZZhqCsnYEklJLQYoxLK9OUisVt6pjn vauBX2RMI/DOtMZ+HH3L1vh9UOT4YHJZ4Jzg0EiN74Ft9ruWpYWNJlSZ9a3RBwX3laSP UEO4itlrFuykGeCSwsPP/x4WcZFd8upL87whn4O+AfldV6BOW0PENK39phDscYMnhlXH fON07DRGKKjc3VCT9efugoHQbmb1Rn4H8PtTrWIrGMG6FOa+yNlcpZTFsd9pfu10gHOa UtyHJgLu4cIH++ZLX1FIQhjxiLaTSzjpIVzq2itedZZai9yiUKI6GxQXIMjTeqB7c13Y kxTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=YW1ftPg8; spf=pass (google.com: domain of gcc-patches-return-468859-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468859-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id w10si7611467pgr.259.2017.12.09.15.22.04 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:22:04 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468859-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=YW1ftPg8; spf=pass (google.com: domain of gcc-patches-return-468859-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468859-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=jWC4r1A0Clk1DPhtg4V5EN5z9mKjG hO9KOZcFzzIpo77//fls3F1jOZripx0ley3iyz0jKalNd/Jn0QYoHTQFlW0rNZMw k5cJpZ84kY6YgLPk/m/9AZ2xBevxXvLrv/KRPxBqz6+JKtiPCrzu6BbTJK0Ta13E sH39io0dRKfZZk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=Ewv3pTqPQXp0Ow5zYu3SvbqqmXA=; b=YW1 ftPg85Vj0TGz4le+KEFwRbQrMfc8/S46Zle1CGuQjEYr+UFmd8A1Y8xAmy9h91cK nkiKxCeR4ioR0B+hVP6buxXg8ASCDvqPCYdINuz2LkWqXdleDqhMF7UoFpB9vHv+ bFwR2qB6ZHDUFQWkSXoZ0qQ6OseeYe8EZCkyToP0= Received: (qmail 103588 invoked by alias); 9 Dec 2017 23:21:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 103579 invoked by uid 89); 9 Dec 2017 23:21:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f175.google.com Received: from mail-wr0-f175.google.com (HELO mail-wr0-f175.google.com) (209.85.128.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:21:49 +0000 Received: by mail-wr0-f175.google.com with SMTP id l22so14017000wrc.11 for ; Sat, 09 Dec 2017 15:21:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=Aa9aQk3XWGcD8hjxglNyund7ylJYgVmWYBiTffs5nYU=; b=Ffs2loFMbb8X9M2i+ANSPppv6Ftx7HQ97205RGJe9PdRi37BXyZ12EXtGlTMb3Nv4N rXTma85XUpbKWsUvo9bVCVdrfuR7En8WimYaWn76u3ERqY42mIYDw7SbHXDh8oM/7qWK Z6GkwwOFubwSNk+Ni6GPycZ4iQuyWmnt5MsEZj7xxRXlnPJcCN9K2C7oPuc5f3boPTvW pL47HZnlgJri2Kym4/W5VMqByySc2gm5wamttR3oGccLNa6qtm9DMo/ukaVLrV7UbKjd d4DCjf/IxhM8ivMq+P3pvBpemOEqLlV2ovwRxFoCGrbnR5FaRe5PNtH3jjIa3C/P2qDZ fp/Q== X-Gm-Message-State: AJaThX7ompArgtx4xLHzb1wS4melZWaiLKWfMkJPAe65fN9kld3neqz5 ssmDosBjU9cC+7HYCtxJUyY68WeMjuY= X-Received: by 10.223.195.198 with SMTP id d6mr30507148wrg.100.1512861706426; Sat, 09 Dec 2017 15:21:46 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id 187sm5409088wmu.19.2017.12.09.15.21.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:21:45 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [09/13] Use explicit encodings for simple permutes References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:21:44 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87d13nlc6v.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch makes users of vec_perm_builders use the compressed encoding where possible. This means that they work with variable-length vectors. 2017-12-09 Richard Sandiford gcc/ * optabs.c (expand_vec_perm_var): Use an explicit encoding for the broadcast of the low byte. (expand_mult_highpart): Use an explicit encoding for the permutes. * optabs-query.c (can_mult_highpart_p): Likewise. * tree-vect-loop.c (calc_vec_perm_mask_for_shift): Likewise. * tree-vect-stmts.c (perm_mask_for_reverse): Likewise. (vectorizable_bswap): Likewise. * tree-vect-data-refs.c (vect_grouped_store_supported): Use an explicit encoding for the power-of-2 permutes. (vect_permute_store_chain): Likewise. (vect_grouped_load_supported): Likewise. (vect_permute_load_chain): Likewise. Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:48:47.546825312 +0000 +++ gcc/optabs.c 2017-12-09 22:48:52.266015836 +0000 @@ -5625,15 +5625,14 @@ expand_vec_perm_var (machine_mode mode, NULL, 0, OPTAB_DIRECT); gcc_assert (sel != NULL); - /* Broadcast the low byte each element into each of its bytes. */ - vec_perm_builder const_sel (w, w, 1); - for (i = 0; i < w; ++i) - { - int this_e = i / u * u; - if (BYTES_BIG_ENDIAN) - this_e += u - 1; - const_sel.quick_push (this_e); - } + /* Broadcast the low byte each element into each of its bytes. + The encoding has U interleaved stepped patterns, one for each + byte of an element. */ + vec_perm_builder const_sel (w, u, 3); + unsigned int low_byte_in_u = BYTES_BIG_ENDIAN ? u - 1 : 0; + for (i = 0; i < 3; ++i) + for (unsigned int j = 0; j < u; ++j) + const_sel.quick_push (i * u + low_byte_in_u); sel = gen_lowpart (qimode, sel); sel = expand_vec_perm_const (qimode, sel, sel, const_sel, qimode, NULL); gcc_assert (sel != NULL); @@ -5853,16 +5852,20 @@ expand_mult_highpart (machine_mode mode, expand_insn (optab_handler (tab2, mode), 3, eops); m2 = gen_lowpart (mode, eops[0].value); - vec_perm_builder sel (nunits, nunits, 1); + vec_perm_builder sel; if (method == 2) { - for (i = 0; i < nunits; ++i) + /* The encoding has 2 interleaved stepped patterns. */ + sel.new_vector (nunits, 2, 3); + for (i = 0; i < 6; ++i) sel.quick_push (!BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0)); } else { - for (i = 0; i < nunits; ++i) + /* The encoding has a single interleaved stepped pattern. */ + sel.new_vector (nunits, 1, 3); + for (i = 0; i < 3; ++i) sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); } Index: gcc/optabs-query.c =================================================================== --- gcc/optabs-query.c 2017-12-09 22:48:47.545825268 +0000 +++ gcc/optabs-query.c 2017-12-09 22:48:52.265015799 +0000 @@ -501,8 +501,9 @@ can_mult_highpart_p (machine_mode mode, op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab; if (optab_handler (op, mode) != CODE_FOR_nothing) { - vec_perm_builder sel (nunits, nunits, 1); - for (i = 0; i < nunits; ++i) + /* The encoding has 2 interleaved stepped patterns. */ + vec_perm_builder sel (nunits, 2, 3); + for (i = 0; i < 6; ++i) sel.quick_push (!BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0)); @@ -518,8 +519,9 @@ can_mult_highpart_p (machine_mode mode, op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; if (optab_handler (op, mode) != CODE_FOR_nothing) { - vec_perm_builder sel (nunits, nunits, 1); - for (i = 0; i < nunits; ++i) + /* The encoding has a single stepped pattern. */ + vec_perm_builder sel (nunits, 1, 3); + for (int i = 0; i < 3; ++i) sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); vec_perm_indices indices (sel, 2, nunits); if (can_vec_perm_const_p (mode, indices)) Index: gcc/tree-vect-loop.c =================================================================== --- gcc/tree-vect-loop.c 2017-12-09 22:48:47.547825355 +0000 +++ gcc/tree-vect-loop.c 2017-12-09 22:48:52.267015873 +0000 @@ -3716,8 +3716,10 @@ vect_estimate_min_profitable_iters (loop calc_vec_perm_mask_for_shift (unsigned int offset, unsigned int nelt, vec_perm_builder *sel) { - sel->new_vector (nelt, nelt, 1); - for (unsigned int i = 0; i < nelt; i++) + /* The encoding is a single stepped pattern. Any wrap-around is handled + by vec_perm_indices. */ + sel->new_vector (nelt, 1, 3); + for (unsigned int i = 0; i < 3; i++) sel->quick_push (i + offset); } Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:48:50.360942531 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:48:52.268015910 +0000 @@ -1717,8 +1717,9 @@ perm_mask_for_reverse (tree vectype) nunits = TYPE_VECTOR_SUBPARTS (vectype); - vec_perm_builder sel (nunits, nunits, 1); - for (i = 0; i < nunits; ++i) + /* The encoding has a single stepped pattern. */ + vec_perm_builder sel (nunits, 1, 3); + for (i = 0; i < 3; ++i) sel.quick_push (nunits - 1 - i); vec_perm_indices indices (sel, 1, nunits); @@ -2504,8 +2505,9 @@ vectorizable_bswap (gimple *stmt, gimple unsigned int num_bytes = TYPE_VECTOR_SUBPARTS (char_vectype); unsigned word_bytes = num_bytes / nunits; - vec_perm_builder elts (num_bytes, num_bytes, 1); - for (unsigned i = 0; i < nunits; ++i) + /* The encoding uses one stepped pattern for each byte in the word. */ + vec_perm_builder elts (num_bytes, word_bytes, 3); + for (unsigned i = 0; i < 3; ++i) for (unsigned j = 0; j < word_bytes; ++j) elts.quick_push ((i + 1) * word_bytes - j - 1); Index: gcc/tree-vect-data-refs.c =================================================================== --- gcc/tree-vect-data-refs.c 2017-12-09 22:48:47.546825312 +0000 +++ gcc/tree-vect-data-refs.c 2017-12-09 22:48:52.267015873 +0000 @@ -4566,14 +4566,13 @@ vect_grouped_store_supported (tree vecty if (VECTOR_MODE_P (mode)) { unsigned int i, nelt = GET_MODE_NUNITS (mode); - vec_perm_builder sel (nelt, nelt, 1); - sel.quick_grow (nelt); - if (count == 3) { unsigned int j0 = 0, j1 = 0, j2 = 0; unsigned int i, j; + vec_perm_builder sel (nelt, nelt, 1); + sel.quick_grow (nelt); vec_perm_indices indices; for (j = 0; j < 3; j++) { @@ -4623,7 +4622,10 @@ vect_grouped_store_supported (tree vecty /* If length is not equal to 3 then only power of 2 is supported. */ gcc_assert (pow2p_hwi (count)); - for (i = 0; i < nelt / 2; i++) + /* The encoding has 2 interleaved stepped patterns. */ + vec_perm_builder sel (nelt, 2, 3); + sel.quick_grow (6); + for (i = 0; i < 3; i++) { sel[i * 2] = i; sel[i * 2 + 1] = i + nelt; @@ -4631,7 +4633,7 @@ vect_grouped_store_supported (tree vecty vec_perm_indices indices (sel, 2, nelt); if (can_vec_perm_const_p (mode, indices)) { - for (i = 0; i < nelt; i++) + for (i = 0; i < 6; i++) sel[i] += nelt / 2; indices.new_vector (sel, 2, nelt); if (can_vec_perm_const_p (mode, indices)) @@ -4736,9 +4738,6 @@ vect_permute_store_chain (vec dr_c unsigned int i, n, log_length = exact_log2 (length); unsigned int j, nelt = TYPE_VECTOR_SUBPARTS (vectype); - vec_perm_builder sel (nelt, nelt, 1); - sel.quick_grow (nelt); - result_chain->quick_grow (length); memcpy (result_chain->address (), dr_chain.address (), length * sizeof (tree)); @@ -4747,6 +4746,8 @@ vect_permute_store_chain (vec dr_c { unsigned int j0 = 0, j1 = 0, j2 = 0; + vec_perm_builder sel (nelt, nelt, 1); + sel.quick_grow (nelt); vec_perm_indices indices; for (j = 0; j < 3; j++) { @@ -4808,7 +4809,10 @@ vect_permute_store_chain (vec dr_c /* If length is not equal to 3 then only power of 2 is supported. */ gcc_assert (pow2p_hwi (length)); - for (i = 0, n = nelt / 2; i < n; i++) + /* The encoding has 2 interleaved stepped patterns. */ + vec_perm_builder sel (nelt, 2, 3); + sel.quick_grow (6); + for (i = 0; i < 3; i++) { sel[i * 2] = i; sel[i * 2 + 1] = i + nelt; @@ -4816,7 +4820,7 @@ vect_permute_store_chain (vec dr_c vec_perm_indices indices (sel, 2, nelt); perm_mask_high = vect_gen_perm_mask_checked (vectype, indices); - for (i = 0; i < nelt; i++) + for (i = 0; i < 6; i++) sel[i] += nelt / 2; indices.new_vector (sel, 2, nelt); perm_mask_low = vect_gen_perm_mask_checked (vectype, indices); @@ -5164,11 +5168,11 @@ vect_grouped_load_supported (tree vectyp if (VECTOR_MODE_P (mode)) { unsigned int i, j, nelt = GET_MODE_NUNITS (mode); - vec_perm_builder sel (nelt, nelt, 1); - sel.quick_grow (nelt); if (count == 3) { + vec_perm_builder sel (nelt, nelt, 1); + sel.quick_grow (nelt); vec_perm_indices indices; unsigned int k; for (k = 0; k < 3; k++) @@ -5209,12 +5213,15 @@ vect_grouped_load_supported (tree vectyp /* If length is not equal to 3 then only power of 2 is supported. */ gcc_assert (pow2p_hwi (count)); - for (i = 0; i < nelt; i++) + /* The encoding has a single stepped pattern. */ + vec_perm_builder sel (nelt, 1, 3); + sel.quick_grow (3); + for (i = 0; i < 3; i++) sel[i] = i * 2; vec_perm_indices indices (sel, 2, nelt); if (can_vec_perm_const_p (mode, indices)) { - for (i = 0; i < nelt; i++) + for (i = 0; i < 3; i++) sel[i] = i * 2 + 1; indices.new_vector (sel, 2, nelt); if (can_vec_perm_const_p (mode, indices)) @@ -5332,9 +5339,6 @@ vect_permute_load_chain (vec dr_ch unsigned int i, j, log_length = exact_log2 (length); unsigned nelt = TYPE_VECTOR_SUBPARTS (vectype); - vec_perm_builder sel (nelt, nelt, 1); - sel.quick_grow (nelt); - result_chain->quick_grow (length); memcpy (result_chain->address (), dr_chain.address (), length * sizeof (tree)); @@ -5343,6 +5347,8 @@ vect_permute_load_chain (vec dr_ch { unsigned int k; + vec_perm_builder sel (nelt, nelt, 1); + sel.quick_grow (nelt); vec_perm_indices indices; for (k = 0; k < 3; k++) { @@ -5390,12 +5396,15 @@ vect_permute_load_chain (vec dr_ch /* If length is not equal to 3 then only power of 2 is supported. */ gcc_assert (pow2p_hwi (length)); - for (i = 0; i < nelt; ++i) + /* The encoding has a single stepped pattern. */ + vec_perm_builder sel (nelt, 1, 3); + sel.quick_grow (3); + for (i = 0; i < 3; ++i) sel[i] = i * 2; vec_perm_indices indices (sel, 2, nelt); perm_mask_even = vect_gen_perm_mask_checked (vectype, indices); - for (i = 0; i < nelt; ++i) + for (i = 0; i < 3; ++i) sel[i] = i * 2 + 1; indices.new_vector (sel, 2, nelt); perm_mask_odd = vect_gen_perm_mask_checked (vectype, indices); From patchwork Sat Dec 9 23:24:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121300 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1167038qgn; Sat, 9 Dec 2017 15:24:49 -0800 (PST) X-Google-Smtp-Source: AGs4zMZi+HHH35RUutnPwbtYfLZask1y5PEsQJAW75yWQ6wz0BqtPiiXU05mqYjz+s7sS5LQd3IC X-Received: by 10.98.209.8 with SMTP id z8mr2867357pfg.113.1512861889366; Sat, 09 Dec 2017 15:24:49 -0800 (PST) ARC-Seal: i=1; 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[209.132.180.131]) by mx.google.com with ESMTPS id o7si7794817pgn.202.2017.12.09.15.24.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:24:49 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468861-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=sjDzrisk; spf=pass (google.com: domain of gcc-patches-return-468861-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468861-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=lsr/gOBemPy5YtoA3aAsKGzYEh2RZ X7k8QU0FylX5l2WzjMwYuvItDG0YyliJM+LRyZq7fF/gfQspcMaIZ9dKCkn68+Q3 NbEGzK1KA8guD4rcxfyR+Ir1UsvjEOcF/HcX9Glyu+YNSW1+qUh+zsUqe7Z0ui82 IBpSfzPGM7cL3w= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=2e29zrSN7gtWQ6nf/aTb0Y44apg=; b=sjD zriskQzJ68Ca0pmV73OGS2R1bMqgEztJFN3mFT3+gTTNy/kjCFetmJ7S5vn0vi6A +C7lr4doiCfKhqP/+c6Qpb9mVzfkzrrb7bRtvKy+snFVf8GEREeOy0UW1t21DNLc FdY3B/FW4e5bGCz6LCL7sOLM8VvPFxWCsP7ir2o4= Received: (qmail 108425 invoked by alias); 9 Dec 2017 23:24:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 108367 invoked by uid 89); 9 Dec 2017 23:24:25 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wr0-f174.google.com Received: from mail-wr0-f174.google.com (HELO mail-wr0-f174.google.com) (209.85.128.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:24:15 +0000 Received: by mail-wr0-f174.google.com with SMTP id v22so14051198wrb.0 for ; Sat, 09 Dec 2017 15:24:08 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=nM1FbpE5Z6D2JHZKqUBjK/FCHKH98Z63Nyrh+Tl7H/E=; b=oaG51XKYqugu4U9RBRVE0JiIn41AjET1LljYNAA9nG8SwdSjsEJ8jBhdwHpg6Z66k5 B7UdsutEGE/1YdaqMEuiRVe0U2npzbplRAnR2TLKp9uW8Ie6J4BzKFs46DQA6nlPB3pk kpAx77NjP8mq3MRweXJ9NWc3PxbD5nlvHayGq5BqaCb2XWX5UGbohoVzslRrzy45GFmM ikvYBDaWnLDh4PF+7Wz84vB3b4zZPc0FqNlZcf1dBgaJ1+jorgXEcpliKVgPULqP4/xJ spAGkEFKIPj3hDreLoPeqEtVF8WRQidXa0pbM1Bx1v8r5F+3baaemfjxLNyB54kSyujy LT8g== X-Gm-Message-State: AJaThX5UpcHVC91YzP8q9aD8JGtcoCWGCbQ/xm2Tr3/k6uSfIGvsIaYy YvyS3UB2f3pM4UY0pB3TNtyjX8AKWjM= X-Received: by 10.223.151.197 with SMTP id t5mr28550016wrb.263.1512861846330; Sat, 09 Dec 2017 15:24:06 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id n32sm13880726wrb.62.2017.12.09.15.24.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:24:05 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [11/13] Use vec_perm_builder::series_p in shift_amt_for_vec_perm_mask References: <87indfmrgt.fsf@linaro.org> <877etvlc4g.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:24:05 +0000 In-Reply-To: <877etvlc4g.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:23:11 +0000") Message-ID: <871sk3lc2y.fsf_-_@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch makes shift_amt_for_vec_perm_mask use series_p to check for the simple case of a natural linear series before falling back to testing each element individually. The series_p test works with variable-length vectors but testing every individual element doesn't. 2017-12-09 Richard Sandiford gcc/ * optabs.c (shift_amt_for_vec_perm_mask): Try using series_p before testing each element individually. Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 22:48:52.266015836 +0000 +++ gcc/optabs.c 2017-12-09 22:48:56.257154317 +0000 @@ -5375,20 +5375,20 @@ vector_compare_rtx (machine_mode cmp_mod static rtx shift_amt_for_vec_perm_mask (machine_mode mode, const vec_perm_indices &sel) { - unsigned int i, first, nelt = GET_MODE_NUNITS (mode); + unsigned int nelt = GET_MODE_NUNITS (mode); unsigned int bitsize = GET_MODE_UNIT_BITSIZE (mode); - - first = sel[0]; + unsigned int first = sel[0]; if (first >= nelt) return NULL_RTX; - for (i = 1; i < nelt; i++) - { - int idx = sel[i]; - unsigned int expected = i + first; - /* Indices into the second vector are all equivalent. */ - if (idx < 0 || (MIN (nelt, (unsigned) idx) != MIN (nelt, expected))) - return NULL_RTX; - } + + if (!sel.series_p (0, 1, first, 1)) + for (unsigned int i = 1; i < nelt; i++) + { + unsigned int expected = i + first; + /* Indices into the second vector are all equivalent. */ + if (MIN (nelt, sel[i]) != MIN (nelt, expected)) + return NULL_RTX; + } return GEN_INT (first * bitsize); } From patchwork Sat Dec 9 23:25:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121301 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1167372qgn; Sat, 9 Dec 2017 15:25:26 -0800 (PST) X-Google-Smtp-Source: AGs4zMbH3p3HFlvytxkY4SAQOB7xW8Fzlu0S3Z/0pxvX6/4COEpHzgWd2pSHw8iQ6FYw2NdUMuyd X-Received: by 10.84.143.70 with SMTP id 64mr34637709ply.277.1512861926749; Sat, 09 Dec 2017 15:25:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512861926; cv=none; d=google.com; s=arc-20160816; b=cyfrTHuIIU1qR+IdjGJX4Xm62PTG2n9mxSy6b0+BE43WF7AK3842Cv3FPTbKt7yWN6 CIEj6b9w1QnzDVdLLPcQ5LR3/UfXdReewdUt1Jrm30m87hto8C7GnvmMVECFfV5hRtWE VYzdmgqufnGvNqMVo9RHu48Xr9BR3c9zjeK+QxYzYauVsXPTL0Gqab6mjRBAcJPqr9mu 5pMOr4pB0Yp0PTl4xjjge8nEUdIgnP8rmoSqiemFUR+Yol9QvrKEEJ3W0NAI9KyW1Avn Gn2j+FA9mKS7iA/w68BgGA6z7LgjQP7tefSbQjsceC6ut5I/zKFZmdNOnTPruCigG04K LAUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=COYpxelZ5xPd25qvlL1FxMAi9mGRYKURy65PkcONibU=; b=ay2J7b8rKyKHCDSsJmo5q69GCtHf7g7te/tJvuOInwbP5thmLbWb9V040xQEfo5dww nxbnfQGQkzJWSgF5fSLLKK1glr5x2viY2DYPsAXZa7lBWc5zyWZAGtIzzMGRjWA6MNdu CrZHFxevsWNZ/Cu+TEWG+bhj+pF1nWjVgiqFUkSQqcSclsMS0YyuUg6x58Mq+Z+3D5wN 1OVjNt+fzALxYQ2DBYit5M4BGIRYWH2KeLKQb7OsMYly7a2Mq8twIK35sIJjeXeDgN03 72bD05MxdyJf07CXOGeROugj7vcK2JFwdLNpOuLSHxtCjpHyNGv+h8OGVfXc6GD47rfC 4VXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=G9uw2BI+; spf=pass (google.com: domain of gcc-patches-return-468862-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468862-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id s194si7758544pgc.0.2017.12.09.15.25.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:25:26 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468862-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=G9uw2BI+; spf=pass (google.com: domain of gcc-patches-return-468862-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468862-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=jwH+5gsSzp4IVzHYObbNN6AwFGi23 hgdZ6HZrmmXFWbzSYDH/9x8i/Hx0W/OY/PpkLDsdsihk0O8ENYeXqWjbX2q+LLRQ wQ8xjOj+ghoyjUmoeTw+SLAp886rnd6JrQWmisUJ50sZe/RS6uiXwrVFTZ3llBEL sDT69DGxe6+3Sk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=Hc3ekcdscwjww7E+6+s8IX+TOGw=; b=G9u w2BI+DrJl09Yzlb7ZVnQ/hwRc44OjQkGwPedmY3j2qWaHG3shpcNvAUCZGrU08YQ 5d9p1v4gcxEOvdt2ntFCL50UcEpDQCFwP1PHcFLfkhuiCNsbNng0it17eBCUDF1m drIB/PMAQKnLczjaMuDZ7aSDUfD9s1kEkkV1JsMY= Received: (qmail 109950 invoked by alias); 9 Dec 2017 23:25:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 109940 invoked by uid 89); 9 Dec 2017 23:25:14 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f50.google.com Received: from mail-wm0-f50.google.com (HELO mail-wm0-f50.google.com) (74.125.82.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:25:13 +0000 Received: by mail-wm0-f50.google.com with SMTP id b76so8380326wmg.1 for ; Sat, 09 Dec 2017 15:25:12 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=COYpxelZ5xPd25qvlL1FxMAi9mGRYKURy65PkcONibU=; b=f3RoPfrFGrIb8vCZ7OqugmZPgBlUxuD9jKaKKX3pqnL7ZRWtJDSCAwJLRtFNVKonpa UUZNwGApsPtKTBTg3BQTY3WBqQri0hiiw9GO63U2vltple1+o9ysfDXehU+gbciTBai6 ub/dC69gcAW0Y0rhOEHPdMeGTl3Ft9Rc3+PnGEf3ZjHDpjEUhEdfSNiRQSooxSz8shON 9F8SUdbYYSStBjyY42PgFQkGtBdf1g06NunIHrgRC8pAoi43ZjEQzy5xZokJ3HJw+NCi t3hFMed+N4Y/1Hf54RFqAtcKWud/t1R2FwpBOOvevrYxLfVgRxvcr2BNJMWumRoTtlJU NWqw== X-Gm-Message-State: AKGB3mKybtuzzMapZPC28xJZO7uLlV6bmkooUTgwR9VTBGIAlXAnPKbS Rdt6IHQn7rPmJJ3e8AOnh5e0/Q25VsI= X-Received: by 10.28.55.82 with SMTP id e79mr6768652wma.60.1512861910706; Sat, 09 Dec 2017 15:25:10 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id k19sm12830591wrk.88.2017.12.09.15.25.09 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:25:09 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [12/13] Use ssizetype selectors for autovectorised VEC_PERM_EXPRs References: <87indfmrgt.fsf@linaro.org> <877etvlc4g.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:25:09 +0000 In-Reply-To: <877etvlc4g.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:23:11 +0000") Message-ID: <87wp1vjxgq.fsf_-_@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 The previous patches mean that there's no reason that constant VEC_PERM_EXPRs need to have the same shape as the data inputs. This patch makes the autovectoriser use ssizetype elements instead, so that indices don't get truncated for large or variable-length vectors. 2017-12-09 Richard Sandiford gcc/ * tree-cfg.c (verify_gimple_assign_ternary): Allow the size of the selector elements to be different from the data elements if the selector is a VECTOR_CST. * tree-vect-stmts.c (vect_gen_perm_mask_any): Use a vector of ssizetype for the selector. Index: gcc/tree-cfg.c =================================================================== --- gcc/tree-cfg.c 2017-12-09 22:47:07.103588314 +0000 +++ gcc/tree-cfg.c 2017-12-09 22:48:58.259216407 +0000 @@ -4300,8 +4300,11 @@ verify_gimple_assign_ternary (gassign *s } if (TREE_CODE (TREE_TYPE (rhs3_type)) != INTEGER_TYPE - || GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE (TREE_TYPE (rhs3_type))) - != GET_MODE_BITSIZE (SCALAR_TYPE_MODE (TREE_TYPE (rhs1_type)))) + || (TREE_CODE (rhs3) != VECTOR_CST + && (GET_MODE_BITSIZE (SCALAR_INT_TYPE_MODE + (TREE_TYPE (rhs3_type))) + != GET_MODE_BITSIZE (SCALAR_TYPE_MODE + (TREE_TYPE (rhs1_type)))))) { error ("invalid mask type in vector permute expression"); debug_generic_expr (lhs_type); Index: gcc/tree-vect-stmts.c =================================================================== --- gcc/tree-vect-stmts.c 2017-12-09 22:48:52.268015910 +0000 +++ gcc/tree-vect-stmts.c 2017-12-09 22:48:58.259216407 +0000 @@ -6518,11 +6518,12 @@ vectorizable_store (gimple *stmt, gimple tree vect_gen_perm_mask_any (tree vectype, const vec_perm_indices &sel) { - tree mask_elt_type, mask_type; + tree mask_type; - mask_elt_type = lang_hooks.types.type_for_mode - (int_mode_for_mode (TYPE_MODE (TREE_TYPE (vectype))).require (), 1); - mask_type = get_vectype_for_scalar_type (mask_elt_type); + unsigned int nunits = sel.length (); + gcc_assert (nunits == TYPE_VECTOR_SUBPARTS (vectype)); + + mask_type = build_vector_type (ssizetype, nunits); return vec_perm_indices_to_tree (mask_type, sel); } From patchwork Sat Dec 9 23:27:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 121305 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp1168953qgn; Sat, 9 Dec 2017 15:28:06 -0800 (PST) X-Google-Smtp-Source: AGs4zMZkpXfwQzhVdATuREdxS0c6HNosf7sARDmnuVBkcD1MlnIl1QWcTtraLTXkcbVPTu125G2o X-Received: by 10.159.194.138 with SMTP id y10mr34510556pln.85.1512862086675; Sat, 09 Dec 2017 15:28:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512862086; cv=none; d=google.com; s=arc-20160816; b=OZuL8pUvfB56A0s5JpeB3NlYB/Trx2AIFho2rHvw4s+roryL0XKbW1FixMxKDu8Yhp WaDW1OOF3ZL7tgcwJBjc2DX/8q8XMUZ+mpQghtLDUbIsLyRTmIH0MD48t+3n0p76joz2 n4mbRVGXRUnXDsIG0qK+yasge03wa95wnNDFyobh0MYy7JaS0cMu5a7Lo/GH9wsPAp5v EW6vIE/S5niV8K5xO+rrGrsT/YyVd2niuUdPU2us49MSaQpDtEqF6wajHW9KIxthkGWQ +bgxn4hagnPDcHBC5ILYvVqMuDW63ac62uuRruJ655rU/sX6MrLW7h+IDGKIjTA6nG7f Yqeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:message-id:in-reply-to:date:references :subject:cc:mail-followup-to:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=KIXL1kW9NDen3xwvQQirLGdpe+IFK1DodLkapB7Fsbg=; b=kD6bUggII/yIuAOHHbxa9o76vlwnwrRSmoRXFdkJk4bHATl2mPRMBIqsSHqdAZRqbV pBthDh7G11YISwVRqXydjN9wGyHvGRZY92CCbmxLrxdVoI80lsQg3qE8ViHTVk/jA7TA Z6WrD86pIdpoS1FCm2G9nAg7whSZApzrD/wo2a+/drODNOKd914Iy7JErZGdxSne3P6z ryS9OIcIp+1CR/4rlOd6InRCHhE8VcBpAtB+Ka23os/12QxDMffpSUCA53Z+NK27zo9d Hhu3Yg9bAOsk9wwby+RILC3KthD0b0s4PBq3GCANSrAlO3/mJ/V1acjwl1rT0h16H4HS 7sLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=qPa0Bfks; spf=pass (google.com: domain of gcc-patches-return-468863-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468863-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. 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This means that they extend naturally to variable-length vectors. Also, aarch64_evpc_dup was the only function that generated rtl when testing_p is true, and that looked accidental. The patch adds the missing check and then replaces the gen_rtx_REG/start_sequence/ end_sequence stuff with an assert that no rtl is generated. Tested on aarch64-linux-gnu. Also tested by making sure that there were no assembly output differences for aarch64_be-linux-gnu or aarch64_be-linux-gnu. OK to install? Richard 2017-12-09 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_evpc_trn): Use d.perm.series_p instead of checking each element individually. (aarch64_evpc_uzp): Likewise. (aarch64_evpc_zip): Likewise. (aarch64_evpc_ext): Likewise. (aarch64_evpc_rev): Likewise. (aarch64_evpc_dup): Test the encoding for a single duplicated element, instead of checking each element individually. Return true without generating rtl if (aarch64_vectorize_vec_perm_const): Use all_from_input_p to test whether all selected elements come from the same input, instead of checking each element individually. Remove calls to gen_rtx_REG, start_sequence and end_sequence and instead assert that no rtl is generated. Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-12-09 22:48:47.535824832 +0000 +++ gcc/config/aarch64/aarch64.c 2017-12-09 22:49:00.139270410 +0000 @@ -13295,7 +13295,7 @@ aarch64_expand_vec_perm (rtx target, rtx static bool aarch64_evpc_trn (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->perm.length (); + unsigned int odd, nelt = d->perm.length (); rtx out, in0, in1, x; machine_mode vmode = d->vmode; @@ -13304,21 +13304,11 @@ aarch64_evpc_trn (struct expand_vec_perm /* Note that these are little-endian tests. We correct for big-endian later. */ - if (d->perm[0] == 0) - odd = 0; - else if (d->perm[0] == 1) - odd = 1; - else + odd = d->perm[0]; + if ((odd != 0 && odd != 1) + || !d->perm.series_p (0, 2, odd, 2) + || !d->perm.series_p (1, 2, nelt + odd, 2)) return false; - mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); - - for (i = 0; i < nelt; i += 2) - { - if (d->perm[i] != i + odd) - return false; - if (d->perm[i + 1] != ((i + nelt + odd) & mask)) - return false; - } /* Success! */ if (d->testing_p) @@ -13342,7 +13332,7 @@ aarch64_evpc_trn (struct expand_vec_perm static bool aarch64_evpc_uzp (struct expand_vec_perm_d *d) { - unsigned int i, odd, mask, nelt = d->perm.length (); + unsigned int odd; rtx out, in0, in1, x; machine_mode vmode = d->vmode; @@ -13351,20 +13341,10 @@ aarch64_evpc_uzp (struct expand_vec_perm /* Note that these are little-endian tests. We correct for big-endian later. */ - if (d->perm[0] == 0) - odd = 0; - else if (d->perm[0] == 1) - odd = 1; - else + odd = d->perm[0]; + if ((odd != 0 && odd != 1) + || !d->perm.series_p (0, 1, odd, 2)) return false; - mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); - - for (i = 0; i < nelt; i++) - { - unsigned elt = (i * 2 + odd) & mask; - if (d->perm[i] != elt) - return false; - } /* Success! */ if (d->testing_p) @@ -13388,7 +13368,7 @@ aarch64_evpc_uzp (struct expand_vec_perm static bool aarch64_evpc_zip (struct expand_vec_perm_d *d) { - unsigned int i, high, mask, nelt = d->perm.length (); + unsigned int high, nelt = d->perm.length (); rtx out, in0, in1, x; machine_mode vmode = d->vmode; @@ -13397,25 +13377,11 @@ aarch64_evpc_zip (struct expand_vec_perm /* Note that these are little-endian tests. We correct for big-endian later. */ - high = nelt / 2; - if (d->perm[0] == high) - /* Do Nothing. */ - ; - else if (d->perm[0] == 0) - high = 0; - else + high = d->perm[0]; + if ((high != 0 && high * 2 != nelt) + || !d->perm.series_p (0, 2, high, 1) + || !d->perm.series_p (1, 2, high + nelt, 1)) return false; - mask = (d->one_vector_p ? nelt - 1 : 2 * nelt - 1); - - for (i = 0; i < nelt / 2; i++) - { - unsigned elt = (i + high) & mask; - if (d->perm[i * 2] != elt) - return false; - elt = (elt + nelt) & mask; - if (d->perm[i * 2 + 1] != elt) - return false; - } /* Success! */ if (d->testing_p) @@ -13440,23 +13406,14 @@ aarch64_evpc_zip (struct expand_vec_perm static bool aarch64_evpc_ext (struct expand_vec_perm_d *d) { - unsigned int i, nelt = d->perm.length (); + unsigned int nelt = d->perm.length (); rtx offset; unsigned int location = d->perm[0]; /* Always < nelt. */ /* Check if the extracted indices are increasing by one. */ - for (i = 1; i < nelt; i++) - { - unsigned int required = location + i; - if (d->one_vector_p) - { - /* We'll pass the same vector in twice, so allow indices to wrap. */ - required &= (nelt - 1); - } - if (d->perm[i] != required) - return false; - } + if (!d->perm.series_p (0, 1, location, 1)) + return false; /* Success! */ if (d->testing_p) @@ -13488,7 +13445,7 @@ aarch64_evpc_ext (struct expand_vec_perm static bool aarch64_evpc_rev (struct expand_vec_perm_d *d) { - unsigned int i, j, diff, size, unspec, nelt = d->perm.length (); + unsigned int i, diff, size, unspec; if (!d->one_vector_p) return false; @@ -13504,18 +13461,10 @@ aarch64_evpc_rev (struct expand_vec_perm else return false; - for (i = 0; i < nelt ; i += diff + 1) - for (j = 0; j <= diff; j += 1) - { - /* This is guaranteed to be true as the value of diff - is 7, 3, 1 and we should have enough elements in the - queue to generate this. Getting a vector mask with a - value of diff other than these values implies that - something is wrong by the time we get here. */ - gcc_assert (i + j < nelt); - if (d->perm[i + j] != i + diff - j) - return false; - } + unsigned int step = diff + 1; + for (i = 0; i < step; ++i) + if (!d->perm.series_p (i, step, diff - i, step)) + return false; /* Success! */ if (d->testing_p) @@ -13532,15 +13481,17 @@ aarch64_evpc_dup (struct expand_vec_perm rtx out = d->target; rtx in0; machine_mode vmode = d->vmode; - unsigned int i, elt, nelt = d->perm.length (); + unsigned int elt; rtx lane; + if (d->perm.encoding ().encoded_nelts () != 1) + return false; + + /* Success! */ + if (d->testing_p) + return true; + elt = d->perm[0]; - for (i = 1; i < nelt; i++) - { - if (elt != d->perm[i]) - return false; - } /* The generic preparation in aarch64_expand_vec_perm_const_1 swaps the operand order and the permute indices if it finds @@ -13628,61 +13579,37 @@ aarch64_vectorize_vec_perm_const (machin rtx op1, const vec_perm_indices &sel) { struct expand_vec_perm_d d; - unsigned int i, which; - d.vmode = vmode; - d.target = target; - d.op0 = op0; - d.op1 = op1; - d.testing_p = !target; - - /* Calculate whether all elements are in one vector. */ - unsigned int nelt = sel.length (); - for (i = which = 0; i < nelt; ++i) + /* Check whether the mask can be applied to a single vector. */ + if (op0 && rtx_equal_p (op0, op1)) + d.one_vector_p = true; + else if (sel.all_from_input_p (0)) { - unsigned int ei = sel[i] & (2 * nelt - 1); - which |= (ei < nelt ? 1 : 2); + d.one_vector_p = true; + op1 = op0; } - - switch (which) + else if (sel.all_from_input_p (1)) { - default: - gcc_unreachable (); - - case 3: - d.one_vector_p = false; - if (d.testing_p || !rtx_equal_p (op0, op1)) - break; - - /* The elements of PERM do not suggest that only the first operand - is used, but both operands are identical. Allow easier matching - of the permutation by folding the permutation into the single - input vector. */ - /* Fall Through. */ - case 2: - d.op0 = op1; - d.one_vector_p = true; - break; - - case 1: - d.op1 = op0; d.one_vector_p = true; - break; + op0 = op1; } + else + d.one_vector_p = false; - d.perm.new_vector (sel.encoding (), d.one_vector_p ? 1 : 2, nelt); + d.perm.new_vector (sel.encoding (), d.one_vector_p ? 1 : 2, + sel.nelts_per_input ()); + d.vmode = vmode; + d.target = target; + d.op0 = op0; + d.op1 = op1; + d.testing_p = !target; if (!d.testing_p) return aarch64_expand_vec_perm_const_1 (&d); - d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1); - d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2); - if (!d.one_vector_p) - d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3); - - start_sequence (); + rtx_insn *last = get_last_insn (); bool ret = aarch64_expand_vec_perm_const_1 (&d); - end_sequence (); + gcc_assert (last == get_last_insn ()); return ret; }