From patchwork Tue Dec 12 14:52:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121522 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4221261qgn; Tue, 12 Dec 2017 06:53:39 -0800 (PST) X-Google-Smtp-Source: ACJfBottA+clRn2tozyk6NUX360GJtTLpmMvHejwIjqvHRem37XmVmmisVkIJLnPSuhCvPidHy6z X-Received: by 10.84.244.9 with SMTP id g9mr2580557pll.192.1513090418905; Tue, 12 Dec 2017 06:53:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090418; cv=none; d=google.com; s=arc-20160816; b=vnV81F3qNWFk9alMikPyUJcK9OUII+mEKgLHN7MYOXbhhlTu+tP72aHobw1pbulMoD U2js4aGWok/EEP4u8XWqcjRvwSwyzZvmOb44ZSlKAf9TqZLJYqD5cfkLa6tgUwPDvcd9 jGr86lQOP4aT2J0mhFbR4q9sdmjB5csQpFwnVpHkUht/Cegd+zO1TGt+l1sHCW+sZME7 yZAib0f72kDWQk4NYE9cD1IfctqSVAFdOJdHjRyWVNtinEc0iRyWoYOwTRXcEUfNAR/V QLuSQoDdgFNAVvVlrnOT2cwC9WpTdyuB+cZMg9TbYYgwYO0xSNC2mg5jhwNvHe4ZHVOa AzxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=8qLTD7nR9jOG0wDCMILBzzQz60CGcaKzy2C14Xb6/n4=; b=wD/2ONeUgKWZFbsmS9oAJ3qIGZq8VwFWbSUPFQzxM8B9dVKQIWH8WN1ST5lxEZxgSE D8wX/4TvaMdrJxk+N3H0AfntRWGWJz49OBZFwsgdZVzLIZOtwQL59muC83AnUltCTI+B IUVanzwpTqYxa+3fyzD2IvZNx3KrI1m/VVNXy0qo6qDfoVp7/j8tSwcKjOB43kmRAtcT Wu+K2sOJUEomsg2YfXpMXnW99bkVw0hS2vvrNH99WpHT6Yl/TnSkizfUoV/QQEwhgxv6 ENbr1rqSaUXO98r1VgTAAQi+/7/6D0+V3zFHJdJTT4Laibw/XPiq+QSdhvn+ShRehpYJ lw+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s10si12953698pfg.229.2017.12.12.06.53.38; Tue, 12 Dec 2017 06:53:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752471AbdLLOxf (ORCPT + 11 others); Tue, 12 Dec 2017 09:53:35 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44986 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751728AbdLLOxc (ORCPT ); Tue, 12 Dec 2017 09:53:32 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A11AE1529; Tue, 12 Dec 2017 06:53:32 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8940F3F577; Tue, 12 Dec 2017 06:53:29 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/24] staging: ccree: remove ahash wrappers Date: Tue, 12 Dec 2017 14:52:47 +0000 Message-Id: <1513090395-7938-2-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove a no longer needed abstraction around ccree hash crypto API internals that used to allow same ops to be used in synchronous and asynchronous fashion. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_hash.c | 260 ++++++++++++--------------------------- 1 file changed, 76 insertions(+), 184 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 0c4f3db..a762eef 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -426,13 +426,15 @@ static void ssi_hash_complete(struct device *dev, void *ssi_req) req->base.complete(&req->base, 0); } -static int ssi_hash_digest(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, u8 *result, - void *async_req) +static int ssi_ahash_digest(struct ahash_request *req) { + struct ahash_req_ctx *state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + u32 digestsize = crypto_ahash_digestsize(tfm); + struct scatterlist *src = req->src; + unsigned int nbytes = req->nbytes; + u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; @@ -460,11 +462,9 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, return -ENOMEM; } - if (async_req) { - /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_digest_complete; - ssi_req.user_arg = (void *)async_req; - } + /* Setup DX request structure */ + ssi_req.user_cb = ssi_hash_digest_complete; + ssi_req.user_arg = req; /* If HMAC then load hash IPAD xor key, if HASH then load initial * digest @@ -563,44 +563,32 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_cipher_mode(&desc[idx], ctx->hw_mode); /* TODO */ set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, - NS_BIT, (async_req ? 1 : 0)); - if (async_req) - set_queue_last_ind(&desc[idx]); + NS_BIT, 1); + set_queue_last_ind(&desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); idx++; - if (async_req) { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); - if (rc != -EINPROGRESS) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - ssi_hash_unmap_request(dev, state, ctx); - } - } else { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); - if (rc) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - } else { - cc_unmap_hash_request(dev, state, src, false); - } + rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + if (rc != -EINPROGRESS) { + dev_err(dev, "send_request() failed (rc=%d)\n", rc); + cc_unmap_hash_request(dev, state, src, true); ssi_hash_unmap_result(dev, state, digestsize, result); ssi_hash_unmap_request(dev, state, ctx); } return rc; } -static int ssi_hash_update(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int block_size, - struct scatterlist *src, - unsigned int nbytes, - void *async_req) +static int ssi_ahash_update(struct ahash_request *req) { + struct ahash_req_ctx *state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); + struct scatterlist *src = req->src; + unsigned int nbytes = req->nbytes; struct device *dev = drvdata_to_dev(ctx->drvdata); struct ssi_crypto_req ssi_req = {}; struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; @@ -628,11 +616,9 @@ static int ssi_hash_update(struct ahash_req_ctx *state, return -ENOMEM; } - if (async_req) { - /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_update_complete; - ssi_req.user_arg = async_req; - } + /* Setup DX request structure */ + ssi_req.user_cb = ssi_hash_update_complete; + ssi_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -666,39 +652,29 @@ static int ssi_hash_update(struct ahash_req_ctx *state, hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, - HASH_LEN_SIZE, NS_BIT, (async_req ? 1 : 0)); - if (async_req) - set_queue_last_ind(&desc[idx]); + HASH_LEN_SIZE, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); idx++; - if (async_req) { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); - if (rc != -EINPROGRESS) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - } - } else { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); - if (rc) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - } else { - cc_unmap_hash_request(dev, state, src, false); - } + rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + if (rc != -EINPROGRESS) { + dev_err(dev, "send_request() failed (rc=%d)\n", rc); + cc_unmap_hash_request(dev, state, src, true); } return rc; } -static int ssi_hash_finup(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, - u8 *result, - void *async_req) +static int ssi_ahash_finup(struct ahash_request *req) { + struct ahash_req_ctx *state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + u32 digestsize = crypto_ahash_digestsize(tfm); + struct scatterlist *src = req->src; + unsigned int nbytes = req->nbytes; + u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; @@ -718,11 +694,9 @@ static int ssi_hash_finup(struct ahash_req_ctx *state, return -ENOMEM; } - if (async_req) { - /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_complete; - ssi_req.user_arg = async_req; - } + /* Setup DX request structure */ + ssi_req.user_cb = ssi_hash_complete; + ssi_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -794,9 +768,8 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); hw_desc_init(&desc[idx]); /* TODO */ set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, - NS_BIT, (async_req ? 1 : 0)); - if (async_req) - set_queue_last_ind(&desc[idx]); + NS_BIT, 1); + set_queue_last_ind(&desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); @@ -804,36 +777,24 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - if (async_req) { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); - if (rc != -EINPROGRESS) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - } - } else { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); - if (rc) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - } else { - cc_unmap_hash_request(dev, state, src, false); - ssi_hash_unmap_result(dev, state, digestsize, result); - ssi_hash_unmap_request(dev, state, ctx); - } + rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + if (rc != -EINPROGRESS) { + dev_err(dev, "send_request() failed (rc=%d)\n", rc); + cc_unmap_hash_request(dev, state, src, true); + ssi_hash_unmap_result(dev, state, digestsize, result); } return rc; } -static int ssi_hash_final(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, - u8 *result, - void *async_req) +static int ssi_ahash_final(struct ahash_request *req) { + struct ahash_req_ctx *state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + u32 digestsize = crypto_ahash_digestsize(tfm); + struct scatterlist *src = req->src; + unsigned int nbytes = req->nbytes; + u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; @@ -854,11 +815,9 @@ static int ssi_hash_final(struct ahash_req_ctx *state, return -ENOMEM; } - if (async_req) { - /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_complete; - ssi_req.user_arg = async_req; - } + /* Setup DX request structure */ + ssi_req.user_cb = ssi_hash_complete; + ssi_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -939,9 +898,8 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); /* Get final MAC result */ hw_desc_init(&desc[idx]); set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, - NS_BIT, (async_req ? 1 : 0)); - if (async_req) - set_queue_last_ind(&desc[idx]); + NS_BIT, 1); + set_queue_last_ind(&desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); @@ -949,34 +907,25 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - if (async_req) { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); - if (rc != -EINPROGRESS) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - } - } else { - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); - if (rc) { - dev_err(dev, "send_request() failed (rc=%d)\n", rc); - cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - } else { - cc_unmap_hash_request(dev, state, src, false); - ssi_hash_unmap_result(dev, state, digestsize, result); - ssi_hash_unmap_request(dev, state, ctx); - } + rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + if (rc != -EINPROGRESS) { + dev_err(dev, "send_request() failed (rc=%d)\n", rc); + cc_unmap_hash_request(dev, state, src, true); + ssi_hash_unmap_result(dev, state, digestsize, result); } return rc; } -static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) +static int ssi_ahash_init(struct ahash_request *req) { + struct ahash_req_ctx *state = ahash_request_ctx(req); + struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); - state->xcbc_count = 0; + dev_dbg(dev, "===== init (%d) ====\n", req->nbytes); + state->xcbc_count = 0; ssi_hash_map_request(dev, state, ctx); return 0; @@ -1713,63 +1662,6 @@ static int ssi_mac_digest(struct ahash_request *req) return rc; } -//ahash wrap functions -static int ssi_ahash_digest(struct ahash_request *req) -{ - struct ahash_req_ctx *state = ahash_request_ctx(req); - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - u32 digestsize = crypto_ahash_digestsize(tfm); - - return ssi_hash_digest(state, ctx, digestsize, req->src, req->nbytes, - req->result, (void *)req); -} - -static int ssi_ahash_update(struct ahash_request *req) -{ - struct ahash_req_ctx *state = ahash_request_ctx(req); - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); - - return ssi_hash_update(state, ctx, block_size, req->src, req->nbytes, - (void *)req); -} - -static int ssi_ahash_finup(struct ahash_request *req) -{ - struct ahash_req_ctx *state = ahash_request_ctx(req); - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - u32 digestsize = crypto_ahash_digestsize(tfm); - - return ssi_hash_finup(state, ctx, digestsize, req->src, req->nbytes, - req->result, (void *)req); -} - -static int ssi_ahash_final(struct ahash_request *req) -{ - struct ahash_req_ctx *state = ahash_request_ctx(req); - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - u32 digestsize = crypto_ahash_digestsize(tfm); - - return ssi_hash_final(state, ctx, digestsize, req->src, req->nbytes, - req->result, (void *)req); -} - -static int ssi_ahash_init(struct ahash_request *req) -{ - struct ahash_req_ctx *state = ahash_request_ctx(req); - struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - struct device *dev = drvdata_to_dev(ctx->drvdata); - - dev_dbg(dev, "===== init (%d) ====\n", req->nbytes); - - return ssi_hash_init(state, ctx); -} - static int ssi_ahash_export(struct ahash_request *req, void *out) { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); @@ -1829,7 +1721,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) /* call init() to allocate bufs if the user hasn't */ if (!state->digest_buff) { - rc = ssi_hash_init(state, ctx); + rc = ssi_ahash_init(req); if (rc) goto out; } From patchwork Tue Dec 12 14:52:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121524 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4221705qgn; Tue, 12 Dec 2017 06:53:59 -0800 (PST) X-Google-Smtp-Source: ACJfBovDLcX0R1/I6bdUO7cpJFamV7S1vNFqYrzbBZbRbNQ/gdI/MH1J6QNv3dLoVZA2JP6+1IcK X-Received: by 10.84.133.162 with SMTP id f31mr2575039plf.304.1513090439675; Tue, 12 Dec 2017 06:53:59 -0800 (PST) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id f84si11276354pfd.161.2017.12.12.06.53.59; Tue, 12 Dec 2017 06:53:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752585AbdLLOxx (ORCPT + 11 others); Tue, 12 Dec 2017 09:53:53 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44994 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752373AbdLLOxp (ORCPT ); Tue, 12 Dec 2017 09:53:45 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2E891529; Tue, 12 Dec 2017 06:53:44 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB8CE3F577; Tue, 12 Dec 2017 06:53:37 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/24] staging: ccree: fix hash naming convention Date: Tue, 12 Dec 2017 14:52:48 +0000 Message-Id: <1513090395-7938-3-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The hash files were using a naming convention which was inconsistent (ssi vs. cc), included a useless prefix (ssi_hash) and often used too long function names producing monster such as ssi_ahash_get_initial_digest_len_sram_addr() that made the call site hard to read. Make the code more readable by switching to a simpler, consistent naming convention for the file. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 10 +- drivers/staging/ccree/ssi_driver.c | 8 +- drivers/staging/ccree/ssi_hash.c | 494 ++++++++++++++++++------------------- drivers/staging/ccree/ssi_hash.h | 16 +- drivers/staging/ccree/ssi_pm.c | 2 +- 5 files changed, 257 insertions(+), 273 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 5548c7b..408ea24 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -1023,10 +1023,8 @@ static void cc_set_hmac_desc(struct aead_request *req, struct cc_hw_desc desc[], /* Load init. digest len (64 bytes) */ hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], hash_mode); - set_din_sram(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, - hash_mode), - HASH_LEN_SIZE); + set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode), + HASH_LEN_SIZE); set_flow_mode(&desc[idx], S_DIN_to_HASH); set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; @@ -1152,9 +1150,7 @@ static void cc_proc_scheme_desc(struct aead_request *req, /* Load init. digest len (64 bytes) */ hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], hash_mode); - set_din_sram(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, - hash_mode), + set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode), HASH_LEN_SIZE); set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); set_flow_mode(&desc[idx], S_DIN_to_HASH); diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index a0d8eb8..513c5e4 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -358,9 +358,9 @@ static int init_cc_resources(struct platform_device *plat_dev) } /* hash must be allocated before aead since hash exports APIs */ - rc = ssi_hash_alloc(new_drvdata); + rc = cc_hash_alloc(new_drvdata); if (rc) { - dev_err(dev, "ssi_hash_alloc failed\n"); + dev_err(dev, "cc_hash_alloc failed\n"); goto post_cipher_err; } @@ -379,7 +379,7 @@ static int init_cc_resources(struct platform_device *plat_dev) return 0; post_hash_err: - ssi_hash_free(new_drvdata); + cc_hash_free(new_drvdata); post_cipher_err: ssi_ablkcipher_free(new_drvdata); post_ivgen_err: @@ -417,7 +417,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) (struct ssi_drvdata *)platform_get_drvdata(plat_dev); cc_aead_free(drvdata); - ssi_hash_free(drvdata); + cc_hash_free(drvdata); ssi_ablkcipher_free(drvdata); ssi_ivgen_fini(drvdata); cc_pm_fini(drvdata); diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index a762eef..6bc42e4 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -31,10 +31,10 @@ #include "ssi_hash.h" #include "ssi_sram_mgr.h" -#define SSI_MAX_AHASH_SEQ_LEN 12 -#define SSI_MAX_OPAD_KEYS_SIZE SSI_MAX_HASH_BLCK_SIZE +#define CC_MAX_HASH_SEQ_LEN 12 +#define CC_MAX_OPAD_KEYS_SIZE CC_MAX_HASH_BLCK_SIZE -struct ssi_hash_handle { +struct cc_hash_handle { ssi_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/ ssi_sram_addr_t larval_digest_sram_addr; /* const value in SRAM */ struct list_head hash_list; @@ -64,16 +64,15 @@ static const u64 sha512_init[] = { SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 }; #endif -static void ssi_hash_create_xcbc_setup( +static void cc_setup_xcbc( struct ahash_request *areq, struct cc_hw_desc desc[], unsigned int *seq_size); -static void ssi_hash_create_cmac_setup(struct ahash_request *areq, - struct cc_hw_desc desc[], - unsigned int *seq_size); +static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[], + unsigned int *seq_size); -struct ssi_hash_alg { +struct cc_hash_alg { struct list_head entry; int hash_mode; int hw_mode; @@ -88,13 +87,13 @@ struct hash_key_req_ctx { }; /* hash per-session context */ -struct ssi_hash_ctx { +struct cc_hash_ctx { struct ssi_drvdata *drvdata; /* holds the origin digest; the digest after "setkey" if HMAC,* * the initial digest if HASH. */ - u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; - u8 opad_tmp_keys_buff[SSI_MAX_OPAD_KEYS_SIZE] ____cacheline_aligned; + u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; + u8 opad_tmp_keys_buff[CC_MAX_OPAD_KEYS_SIZE] ____cacheline_aligned; dma_addr_t opad_tmp_keys_dma_addr ____cacheline_aligned; dma_addr_t digest_buff_dma_addr; @@ -107,14 +106,14 @@ struct ssi_hash_ctx { bool is_hmac; }; -static void ssi_hash_create_data_desc( +static void cc_set_desc( struct ahash_req_ctx *areq_ctx, - struct ssi_hash_ctx *ctx, + struct cc_hash_ctx *ctx, unsigned int flow_mode, struct cc_hw_desc desc[], bool is_not_last_data, unsigned int *seq_size); -static void ssi_set_hash_endianity(u32 mode, struct cc_hw_desc *desc) +static void cc_set_endianity(u32 mode, struct cc_hw_desc *desc) { if (mode == DRV_HASH_MD5 || mode == DRV_HASH_SHA384 || mode == DRV_HASH_SHA512) { @@ -124,9 +123,8 @@ static void ssi_set_hash_endianity(u32 mode, struct cc_hw_desc *desc) } } -static int ssi_hash_map_result(struct device *dev, - struct ahash_req_ctx *state, - unsigned int digestsize) +static int cc_map_result(struct device *dev, struct ahash_req_ctx *state, + unsigned int digestsize) { state->digest_result_dma_addr = dma_map_single(dev, (void *)state->digest_result_buff, @@ -144,9 +142,8 @@ static int ssi_hash_map_result(struct device *dev, return 0; } -static int ssi_hash_map_request(struct device *dev, - struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx) +static int cc_map_req(struct device *dev, struct ahash_req_ctx *state, + struct cc_hash_ctx *ctx) { bool is_hmac = ctx->is_hmac; ssi_sram_addr_t larval_digest_addr = @@ -155,15 +152,15 @@ static int ssi_hash_map_request(struct device *dev, struct cc_hw_desc desc; int rc = -ENOMEM; - state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); + state->buff0 = kzalloc(CC_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); if (!state->buff0) goto fail0; - state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); + state->buff1 = kzalloc(CC_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); if (!state->buff1) goto fail_buff0; - state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, + state->digest_result_buff = kzalloc(CC_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA); if (!state->digest_result_buff) goto fail_buff1; @@ -330,9 +327,8 @@ static int ssi_hash_map_request(struct device *dev, return rc; } -static void ssi_hash_unmap_request(struct device *dev, - struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx) +static void cc_unmap_req(struct device *dev, struct ahash_req_ctx *state, + struct cc_hash_ctx *ctx) { if (state->digest_buff_dma_addr) { dma_unmap_single(dev, state->digest_buff_dma_addr, @@ -364,9 +360,8 @@ static void ssi_hash_unmap_request(struct device *dev, kfree(state->buff0); } -static void ssi_hash_unmap_result(struct device *dev, - struct ahash_req_ctx *state, - unsigned int digestsize, u8 *result) +static void cc_unmap_result(struct device *dev, struct ahash_req_ctx *state, + unsigned int digestsize, u8 *result) { if (state->digest_result_dma_addr) { dma_unmap_single(dev, @@ -383,7 +378,7 @@ static void ssi_hash_unmap_result(struct device *dev, state->digest_result_dma_addr = 0; } -static void ssi_hash_update_complete(struct device *dev, void *ssi_req) +static void cc_update_complete(struct device *dev, void *ssi_req) { struct ahash_request *req = (struct ahash_request *)ssi_req; struct ahash_req_ctx *state = ahash_request_ctx(req); @@ -394,43 +389,43 @@ static void ssi_hash_update_complete(struct device *dev, void *ssi_req) req->base.complete(&req->base, 0); } -static void ssi_hash_digest_complete(struct device *dev, void *ssi_req) +static void cc_digest_complete(struct device *dev, void *ssi_req) { struct ahash_request *req = (struct ahash_request *)ssi_req; struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); u32 digestsize = crypto_ahash_digestsize(tfm); dev_dbg(dev, "req=%pK\n", req); cc_unmap_hash_request(dev, state, req->src, false); - ssi_hash_unmap_result(dev, state, digestsize, req->result); - ssi_hash_unmap_request(dev, state, ctx); + cc_unmap_result(dev, state, digestsize, req->result); + cc_unmap_req(dev, state, ctx); req->base.complete(&req->base, 0); } -static void ssi_hash_complete(struct device *dev, void *ssi_req) +static void cc_hash_complete(struct device *dev, void *ssi_req) { struct ahash_request *req = (struct ahash_request *)ssi_req; struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); u32 digestsize = crypto_ahash_digestsize(tfm); dev_dbg(dev, "req=%pK\n", req); cc_unmap_hash_request(dev, state, req->src, false); - ssi_hash_unmap_result(dev, state, digestsize, req->result); - ssi_hash_unmap_request(dev, state, ctx); + cc_unmap_result(dev, state, digestsize, req->result); + cc_unmap_req(dev, state, ctx); req->base.complete(&req->base, 0); } -static int ssi_ahash_digest(struct ahash_request *req) +static int cc_hash_digest(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); u32 digestsize = crypto_ahash_digestsize(tfm); struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; @@ -438,7 +433,7 @@ static int ssi_ahash_digest(struct ahash_request *req) struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; ssi_sram_addr_t larval_digest_addr = cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode); int idx = 0; @@ -447,12 +442,12 @@ static int ssi_ahash_digest(struct ahash_request *req) dev_dbg(dev, "===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); - if (ssi_hash_map_request(dev, state, ctx)) { + if (cc_map_req(dev, state, ctx)) { dev_err(dev, "map_ahash_source() failed\n"); return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } @@ -463,7 +458,7 @@ static int ssi_ahash_digest(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = ssi_hash_digest_complete; + ssi_req.user_cb = cc_digest_complete; ssi_req.user_arg = req; /* If HMAC then load hash IPAD xor key, if HASH then load initial @@ -501,7 +496,7 @@ static int ssi_ahash_digest(struct ahash_request *req) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); + cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); if (is_hmac) { /* HW last hash block padding (aka. "DO_PAD") */ @@ -520,7 +515,7 @@ static int ssi_ahash_digest(struct ahash_request *req) set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); set_flow_mode(&desc[idx], S_HASH_to_DOUT); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; @@ -537,8 +532,8 @@ static int ssi_ahash_digest(struct ahash_request *req) hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); set_din_sram(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr( -ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + cc_digest_len_addr(ctx->drvdata, ctx->hash_mode), + HASH_LEN_SIZE); set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); set_flow_mode(&desc[idx], S_DIN_to_HASH); set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); @@ -568,30 +563,30 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); idx++; rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); - ssi_hash_unmap_request(dev, state, ctx); + cc_unmap_result(dev, state, digestsize, result); + cc_unmap_req(dev, state, ctx); } return rc; } -static int ssi_ahash_update(struct ahash_request *req) +static int cc_hash_update(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; struct device *dev = drvdata_to_dev(ctx->drvdata); struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; u32 idx = 0; int rc; @@ -617,7 +612,7 @@ static int ssi_ahash_update(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = ssi_hash_update_complete; + ssi_req.user_cb = cc_update_complete; ssi_req.user_arg = req; /* Restore hash digest */ @@ -637,7 +632,7 @@ static int ssi_ahash_update(struct ahash_request *req) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); + cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); /* store the hash digest result in context */ hw_desc_init(&desc[idx]); @@ -666,11 +661,11 @@ static int ssi_ahash_update(struct ahash_request *req) return rc; } -static int ssi_ahash_finup(struct ahash_request *req) +static int cc_hash_finup(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); u32 digestsize = crypto_ahash_digestsize(tfm); struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; @@ -678,7 +673,7 @@ static int ssi_ahash_finup(struct ahash_request *req) struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc; @@ -689,13 +684,13 @@ static int ssi_ahash_finup(struct ahash_request *req) dev_err(dev, "map_ahash_request_final() failed\n"); return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } /* Setup DX request structure */ - ssi_req.user_cb = ssi_hash_complete; + ssi_req.user_cb = cc_hash_complete; ssi_req.user_arg = req; /* Restore hash digest */ @@ -717,7 +712,7 @@ static int ssi_ahash_finup(struct ahash_request *req) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); + cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); if (is_hmac) { /* Store the hash digest result in the context */ @@ -725,7 +720,7 @@ static int ssi_ahash_finup(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; @@ -743,8 +738,8 @@ static int ssi_ahash_finup(struct ahash_request *req) hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); set_din_sram(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr( -ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + cc_digest_len_addr(ctx->drvdata, ctx->hash_mode), + HASH_LEN_SIZE); set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); set_flow_mode(&desc[idx], S_DIN_to_HASH); set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); @@ -773,7 +768,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; @@ -781,16 +776,16 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); + cc_unmap_result(dev, state, digestsize, result); } return rc; } -static int ssi_ahash_final(struct ahash_request *req) +static int cc_hash_final(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); u32 digestsize = crypto_ahash_digestsize(tfm); struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; @@ -798,7 +793,7 @@ static int ssi_ahash_final(struct ahash_request *req) struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc; @@ -810,13 +805,13 @@ static int ssi_ahash_final(struct ahash_request *req) return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } /* Setup DX request structure */ - ssi_req.user_cb = ssi_hash_complete; + ssi_req.user_cb = cc_hash_complete; ssi_req.user_arg = req; /* Restore hash digest */ @@ -838,7 +833,7 @@ static int ssi_ahash_final(struct ahash_request *req) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); + cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx); /* "DO-PAD" must be enabled only when writing current length to HW */ hw_desc_init(&desc[idx]); @@ -856,7 +851,7 @@ static int ssi_ahash_final(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; @@ -874,8 +869,8 @@ static int ssi_ahash_final(struct ahash_request *req) hw_desc_init(&desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); set_din_sram(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr( -ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + cc_digest_len_addr(ctx->drvdata, ctx->hash_mode), + HASH_LEN_SIZE); set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); set_flow_mode(&desc[idx], S_DIN_to_HASH); set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); @@ -903,7 +898,7 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; @@ -911,36 +906,36 @@ ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); - ssi_hash_unmap_result(dev, state, digestsize, result); + cc_unmap_result(dev, state, digestsize, result); } return rc; } -static int ssi_ahash_init(struct ahash_request *req) +static int cc_hash_init(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); dev_dbg(dev, "===== init (%d) ====\n", req->nbytes); state->xcbc_count = 0; - ssi_hash_map_request(dev, state, ctx); + cc_map_req(dev, state, ctx); return 0; } -static int ssi_ahash_setkey(struct crypto_ahash *ahash, const u8 *key, - unsigned int keylen) +static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, + unsigned int keylen) { unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST }; struct ssi_crypto_req ssi_req = {}; - struct ssi_hash_ctx *ctx = NULL; + struct cc_hash_ctx *ctx = NULL; int blocksize = 0; int digestsize = 0; int i, idx = 0, rc = 0; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; ssi_sram_addr_t larval_addr; struct device *dev; @@ -1006,7 +1001,7 @@ static int ssi_ahash_setkey(struct crypto_ahash *ahash, const u8 *key, set_flow_mode(&desc[idx], S_HASH_to_DOUT); set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); - ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + cc_set_endianity(ctx->hash_mode, &desc[idx]); idx++; hw_desc_init(&desc[idx]); @@ -1120,14 +1115,14 @@ static int ssi_ahash_setkey(struct crypto_ahash *ahash, const u8 *key, return rc; } -static int ssi_xcbc_setkey(struct crypto_ahash *ahash, - const u8 *key, unsigned int keylen) +static int cc_xcbc_setkey(struct crypto_ahash *ahash, + const u8 *key, unsigned int keylen) { struct ssi_crypto_req ssi_req = {}; - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct device *dev = drvdata_to_dev(ctx->drvdata); int idx = 0, rc = 0; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; dev_dbg(dev, "===== setkey (%d) ====\n", keylen); @@ -1203,10 +1198,10 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, } #if SSI_CC_HAS_CMAC -static int ssi_cmac_setkey(struct crypto_ahash *ahash, - const u8 *key, unsigned int keylen) +static int cc_cmac_setkey(struct crypto_ahash *ahash, + const u8 *key, unsigned int keylen) { - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct device *dev = drvdata_to_dev(ctx->drvdata); dev_dbg(dev, "===== setkey (%d) ====\n", keylen); @@ -1244,7 +1239,7 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash, } #endif -static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) +static void cc_free_ctx(struct cc_hash_ctx *ctx) { struct device *dev = drvdata_to_dev(ctx->drvdata); @@ -1267,7 +1262,7 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) ctx->key_params.keylen = 0; } -static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) +static int cc_alloc_ctx(struct cc_hash_ctx *ctx) { struct device *dev = drvdata_to_dev(ctx->drvdata); @@ -1303,19 +1298,19 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) return 0; fail: - ssi_hash_free_ctx(ctx); + cc_free_ctx(ctx); return -ENOMEM; } -static int ssi_ahash_cra_init(struct crypto_tfm *tfm) +static int cc_cra_init(struct crypto_tfm *tfm) { - struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_tfm_ctx(tfm); struct hash_alg_common *hash_alg_common = container_of(tfm->__crt_alg, struct hash_alg_common, base); struct ahash_alg *ahash_alg = container_of(hash_alg_common, struct ahash_alg, halg); - struct ssi_hash_alg *ssi_alg = - container_of(ahash_alg, struct ssi_hash_alg, + struct cc_hash_alg *ssi_alg = + container_of(ahash_alg, struct cc_hash_alg, ahash_alg); crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), @@ -1326,27 +1321,27 @@ static int ssi_ahash_cra_init(struct crypto_tfm *tfm) ctx->inter_digestsize = ssi_alg->inter_digestsize; ctx->drvdata = ssi_alg->drvdata; - return ssi_hash_alloc_ctx(ctx); + return cc_alloc_ctx(ctx); } -static void ssi_hash_cra_exit(struct crypto_tfm *tfm) +static void cc_cra_exit(struct crypto_tfm *tfm) { - struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); - dev_dbg(dev, "ssi_hash_cra_exit"); - ssi_hash_free_ctx(ctx); + dev_dbg(dev, "cc_cra_exit"); + cc_free_ctx(ctx); } -static int ssi_mac_update(struct ahash_request *req) +static int cc_mac_update(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int rc; u32 idx = 0; @@ -1371,11 +1366,11 @@ static int ssi_mac_update(struct ahash_request *req) } if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) - ssi_hash_create_xcbc_setup(req, desc, &idx); + cc_setup_xcbc(req, desc, &idx); else - ssi_hash_create_cmac_setup(req, desc, &idx); + cc_setup_cmac(req, desc, &idx); - ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx); + cc_set_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx); /* store the hash digest result in context */ hw_desc_init(&desc[idx]); @@ -1388,7 +1383,7 @@ static int ssi_mac_update(struct ahash_request *req) idx++; /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_update_complete; + ssi_req.user_cb = (void *)cc_update_complete; ssi_req.user_arg = (void *)req; rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); @@ -1399,14 +1394,14 @@ static int ssi_mac_update(struct ahash_request *req) return rc; } -static int ssi_mac_final(struct ahash_request *req) +static int cc_mac_final(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc = 0; u32 key_size, key_len; @@ -1432,13 +1427,13 @@ static int ssi_mac_final(struct ahash_request *req) return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_complete; + ssi_req.user_cb = (void *)cc_hash_complete; ssi_req.user_arg = (void *)req; if (state->xcbc_count && rem_cnt == 0) { @@ -1473,9 +1468,9 @@ static int ssi_mac_final(struct ahash_request *req) } if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) - ssi_hash_create_xcbc_setup(req, desc, &idx); + cc_setup_xcbc(req, desc, &idx); else - ssi_hash_create_cmac_setup(req, desc, &idx); + cc_setup_cmac(req, desc, &idx); if (state->xcbc_count == 0) { hw_desc_init(&desc[idx]); @@ -1485,8 +1480,7 @@ static int ssi_mac_final(struct ahash_request *req) set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else if (rem_cnt > 0) { - ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, - false, &idx); + cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } else { hw_desc_init(&desc[idx]); set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE); @@ -1509,19 +1503,19 @@ static int ssi_mac_final(struct ahash_request *req) if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); - ssi_hash_unmap_result(dev, state, digestsize, req->result); + cc_unmap_result(dev, state, digestsize, req->result); } return rc; } -static int ssi_mac_finup(struct ahash_request *req) +static int cc_mac_finup(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc = 0; u32 key_len = 0; @@ -1530,7 +1524,7 @@ static int ssi_mac_finup(struct ahash_request *req) dev_dbg(dev, "===== finup xcbc(%d) ====\n", req->nbytes); if (state->xcbc_count > 0 && req->nbytes == 0) { dev_dbg(dev, "No data to update. Call to fdx_mac_final\n"); - return ssi_mac_final(req); + return cc_mac_final(req); } if (cc_map_hash_request_final(ctx->drvdata, state, req->src, @@ -1538,21 +1532,21 @@ static int ssi_mac_finup(struct ahash_request *req) dev_err(dev, "map_ahash_request_final() failed\n"); return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_complete; + ssi_req.user_cb = (void *)cc_hash_complete; ssi_req.user_arg = (void *)req; if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { key_len = CC_AES_128_BIT_KEY_SIZE; - ssi_hash_create_xcbc_setup(req, desc, &idx); + cc_setup_xcbc(req, desc, &idx); } else { key_len = ctx->key_params.keylen; - ssi_hash_create_cmac_setup(req, desc, &idx); + cc_setup_cmac(req, desc, &idx); } if (req->nbytes == 0) { @@ -1563,8 +1557,7 @@ static int ssi_mac_finup(struct ahash_request *req) set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else { - ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, - false, &idx); + cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } /* Get final MAC result */ @@ -1582,31 +1575,31 @@ static int ssi_mac_finup(struct ahash_request *req) if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); - ssi_hash_unmap_result(dev, state, digestsize, req->result); + cc_unmap_result(dev, state, digestsize, req->result); } return rc; } -static int ssi_mac_digest(struct ahash_request *req) +static int cc_mac_digest(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); u32 digestsize = crypto_ahash_digestsize(tfm); struct ssi_crypto_req ssi_req = {}; - struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; u32 key_len; int idx = 0; int rc; dev_dbg(dev, "===== -digest mac (%d) ====\n", req->nbytes); - if (ssi_hash_map_request(dev, state, ctx)) { + if (cc_map_req(dev, state, ctx)) { dev_err(dev, "map_ahash_source() failed\n"); return -ENOMEM; } - if (ssi_hash_map_result(dev, state, digestsize)) { + if (cc_map_result(dev, state, digestsize)) { dev_err(dev, "map_ahash_digest() failed\n"); return -ENOMEM; } @@ -1618,15 +1611,15 @@ static int ssi_mac_digest(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_hash_digest_complete; + ssi_req.user_cb = (void *)cc_digest_complete; ssi_req.user_arg = (void *)req; if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { key_len = CC_AES_128_BIT_KEY_SIZE; - ssi_hash_create_xcbc_setup(req, desc, &idx); + cc_setup_xcbc(req, desc, &idx); } else { key_len = ctx->key_params.keylen; - ssi_hash_create_cmac_setup(req, desc, &idx); + cc_setup_cmac(req, desc, &idx); } if (req->nbytes == 0) { @@ -1637,8 +1630,7 @@ static int ssi_mac_digest(struct ahash_request *req) set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else { - ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, - false, &idx); + cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } /* Get final MAC result */ @@ -1656,16 +1648,16 @@ static int ssi_mac_digest(struct ahash_request *req) if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); - ssi_hash_unmap_result(dev, state, digestsize, req->result); - ssi_hash_unmap_request(dev, state, ctx); + cc_unmap_result(dev, state, digestsize, req->result); + cc_unmap_req(dev, state, ctx); } return rc; } -static int ssi_ahash_export(struct ahash_request *req, void *out) +static int cc_hash_export(struct ahash_request *req, void *out) { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct device *dev = drvdata_to_dev(ctx->drvdata); struct ahash_req_ctx *state = ahash_request_ctx(req); u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0; @@ -1703,10 +1695,10 @@ static int ssi_ahash_export(struct ahash_request *req, void *out) return 0; } -static int ssi_ahash_import(struct ahash_request *req, const void *in) +static int cc_hash_import(struct ahash_request *req, const void *in) { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct device *dev = drvdata_to_dev(ctx->drvdata); struct ahash_req_ctx *state = ahash_request_ctx(req); u32 tmp; @@ -1721,7 +1713,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) /* call init() to allocate bufs if the user hasn't */ if (!state->digest_buff) { - rc = ssi_ahash_init(req); + rc = cc_hash_init(req); if (rc) goto out; } @@ -1750,7 +1742,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) /* Sanity check the data as much as possible */ memcpy(&tmp, in, sizeof(u32)); - if (tmp > SSI_MAX_HASH_BLCK_SIZE) { + if (tmp > CC_MAX_HASH_BLCK_SIZE) { rc = -EINVAL; goto out; } @@ -1763,7 +1755,7 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in) return rc; } -struct ssi_hash_template { +struct cc_hash_template { char name[CRYPTO_MAX_ALG_NAME]; char driver_name[CRYPTO_MAX_ALG_NAME]; char mac_name[CRYPTO_MAX_ALG_NAME]; @@ -1778,10 +1770,10 @@ struct ssi_hash_template { }; #define CC_STATE_SIZE(_x) \ - ((_x) + HASH_LEN_SIZE + SSI_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32))) + ((_x) + HASH_LEN_SIZE + CC_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32))) /* hash descriptors */ -static struct ssi_hash_template driver_hash[] = { +static struct cc_hash_template driver_hash[] = { //Asynchronize hash template { .name = "sha1", @@ -1791,14 +1783,14 @@ static struct ssi_hash_template driver_hash[] = { .blocksize = SHA1_BLOCK_SIZE, .synchronize = false, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = SHA1_DIGEST_SIZE, .statesize = CC_STATE_SIZE(SHA1_DIGEST_SIZE), @@ -1815,14 +1807,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "hmac-sha256-dx", .blocksize = SHA256_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = SHA256_DIGEST_SIZE, .statesize = CC_STATE_SIZE(SHA256_DIGEST_SIZE) @@ -1839,14 +1831,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "hmac-sha224-dx", .blocksize = SHA224_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = SHA224_DIGEST_SIZE, .statesize = CC_STATE_SIZE(SHA224_DIGEST_SIZE), @@ -1864,14 +1856,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "hmac-sha384-dx", .blocksize = SHA384_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = SHA384_DIGEST_SIZE, .statesize = CC_STATE_SIZE(SHA384_DIGEST_SIZE), @@ -1888,14 +1880,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "hmac-sha512-dx", .blocksize = SHA512_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = SHA512_DIGEST_SIZE, .statesize = CC_STATE_SIZE(SHA512_DIGEST_SIZE), @@ -1913,14 +1905,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "hmac-md5-dx", .blocksize = MD5_HMAC_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, - .export = ssi_ahash_export, - .import = ssi_ahash_import, - .setkey = ssi_ahash_setkey, + .init = cc_hash_init, + .update = cc_hash_update, + .final = cc_hash_final, + .finup = cc_hash_finup, + .digest = cc_hash_digest, + .export = cc_hash_export, + .import = cc_hash_import, + .setkey = cc_hash_setkey, .halg = { .digestsize = MD5_DIGEST_SIZE, .statesize = CC_STATE_SIZE(MD5_DIGEST_SIZE), @@ -1935,14 +1927,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "xcbc-aes-dx", .blocksize = AES_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_mac_update, - .final = ssi_mac_final, - .finup = ssi_mac_finup, - .digest = ssi_mac_digest, - .setkey = ssi_xcbc_setkey, - .export = ssi_ahash_export, - .import = ssi_ahash_import, + .init = cc_hash_init, + .update = cc_mac_update, + .final = cc_mac_final, + .finup = cc_mac_finup, + .digest = cc_mac_digest, + .setkey = cc_xcbc_setkey, + .export = cc_hash_export, + .import = cc_hash_import, .halg = { .digestsize = AES_BLOCK_SIZE, .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), @@ -1958,14 +1950,14 @@ static struct ssi_hash_template driver_hash[] = { .mac_driver_name = "cmac-aes-dx", .blocksize = AES_BLOCK_SIZE, .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_mac_update, - .final = ssi_mac_final, - .finup = ssi_mac_finup, - .digest = ssi_mac_digest, - .setkey = ssi_cmac_setkey, - .export = ssi_ahash_export, - .import = ssi_ahash_import, + .init = cc_hash_init, + .update = cc_mac_update, + .final = cc_mac_final, + .finup = cc_mac_finup, + .digest = cc_mac_digest, + .setkey = cc_cmac_setkey, + .export = cc_hash_export, + .import = cc_hash_import, .halg = { .digestsize = AES_BLOCK_SIZE, .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), @@ -1979,11 +1971,11 @@ static struct ssi_hash_template driver_hash[] = { }; -static struct ssi_hash_alg * -ssi_hash_create_alg(struct ssi_hash_template *template, struct device *dev, - bool keyed) +static struct cc_hash_alg * +cc_alloc_hash_alg(struct cc_hash_template *template, struct device *dev, + bool keyed) { - struct ssi_hash_alg *t_crypto_alg; + struct cc_hash_alg *t_crypto_alg; struct crypto_alg *alg; struct ahash_alg *halg; @@ -2008,13 +2000,13 @@ ssi_hash_create_alg(struct ssi_hash_template *template, struct device *dev, template->driver_name); } alg->cra_module = THIS_MODULE; - alg->cra_ctxsize = sizeof(struct ssi_hash_ctx); + alg->cra_ctxsize = sizeof(struct cc_hash_ctx); alg->cra_priority = SSI_CRA_PRIO; alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; - alg->cra_exit = ssi_hash_cra_exit; + alg->cra_exit = cc_cra_exit; - alg->cra_init = ssi_ahash_cra_init; + alg->cra_init = cc_cra_init; alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_KERN_DRIVER_ONLY; alg->cra_type = &crypto_ahash_type; @@ -2026,9 +2018,9 @@ ssi_hash_create_alg(struct ssi_hash_template *template, struct device *dev, return t_crypto_alg; } -int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) +int cc_init_hash_sram(struct ssi_drvdata *drvdata) { - struct ssi_hash_handle *hash_handle = drvdata->hash_handle; + struct cc_hash_handle *hash_handle = drvdata->hash_handle; ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; unsigned int larval_seq_len = 0; struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; @@ -2146,9 +2138,9 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) return rc; } -int ssi_hash_alloc(struct ssi_drvdata *drvdata) +int cc_hash_alloc(struct ssi_drvdata *drvdata) { - struct ssi_hash_handle *hash_handle; + struct cc_hash_handle *hash_handle; ssi_sram_addr_t sram_buff; u32 sram_size_to_alloc; struct device *dev = drvdata_to_dev(drvdata); @@ -2184,7 +2176,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) hash_handle->digest_len_sram_addr = sram_buff; /*must be set before the alg registration as it is being used there*/ - rc = ssi_hash_init_sram_digest_consts(drvdata); + rc = cc_init_hash_sram(drvdata); if (rc) { dev_err(dev, "Init digest CONST failed (rc=%d)\n", rc); goto fail; @@ -2192,11 +2184,11 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) /* ahash registration */ for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { - struct ssi_hash_alg *t_alg; + struct cc_hash_alg *t_alg; int hw_mode = driver_hash[alg].hw_mode; /* register hmac version */ - t_alg = ssi_hash_create_alg(&driver_hash[alg], dev, true); + t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, true); if (IS_ERR(t_alg)) { rc = PTR_ERR(t_alg); dev_err(dev, "%s alg allocation failed\n", @@ -2221,7 +2213,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) continue; /* register hash version */ - t_alg = ssi_hash_create_alg(&driver_hash[alg], dev, false); + t_alg = cc_alloc_hash_alg(&driver_hash[alg], dev, false); if (IS_ERR(t_alg)) { rc = PTR_ERR(t_alg); dev_err(dev, "%s alg allocation failed\n", @@ -2249,10 +2241,10 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) return rc; } -int ssi_hash_free(struct ssi_drvdata *drvdata) +int cc_hash_free(struct ssi_drvdata *drvdata) { - struct ssi_hash_alg *t_hash_alg, *hash_n; - struct ssi_hash_handle *hash_handle = drvdata->hash_handle; + struct cc_hash_alg *t_hash_alg, *hash_n; + struct cc_hash_handle *hash_handle = drvdata->hash_handle; if (hash_handle) { list_for_each_entry_safe(t_hash_alg, hash_n, @@ -2268,14 +2260,13 @@ int ssi_hash_free(struct ssi_drvdata *drvdata) return 0; } -static void ssi_hash_create_xcbc_setup(struct ahash_request *areq, - struct cc_hw_desc desc[], - unsigned int *seq_size) +static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[], + unsigned int *seq_size) { unsigned int idx = *seq_size; struct ahash_req_ctx *state = ahash_request_ctx(areq); struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); /* Setup XCBC MAC K1 */ hw_desc_init(&desc[idx]); @@ -2326,14 +2317,13 @@ static void ssi_hash_create_xcbc_setup(struct ahash_request *areq, *seq_size = idx; } -static void ssi_hash_create_cmac_setup(struct ahash_request *areq, - struct cc_hw_desc desc[], - unsigned int *seq_size) +static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[], + unsigned int *seq_size) { unsigned int idx = *seq_size; struct ahash_req_ctx *state = ahash_request_ctx(areq); struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); /* Setup CMAC Key */ hw_desc_init(&desc[idx]); @@ -2360,12 +2350,10 @@ static void ssi_hash_create_cmac_setup(struct ahash_request *areq, *seq_size = idx; } -static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, - struct ssi_hash_ctx *ctx, - unsigned int flow_mode, - struct cc_hw_desc desc[], - bool is_not_last_data, - unsigned int *seq_size) +static void cc_set_desc(struct ahash_req_ctx *areq_ctx, + struct cc_hash_ctx *ctx, unsigned int flow_mode, + struct cc_hw_desc desc[], bool is_not_last_data, + unsigned int *seq_size) { unsigned int idx = *seq_size; struct device *dev = drvdata_to_dev(ctx->drvdata); @@ -2418,7 +2406,7 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) { struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; - struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; + struct cc_hash_handle *hash_handle = _drvdata->hash_handle; struct device *dev = drvdata_to_dev(_drvdata); switch (mode) { @@ -2462,10 +2450,10 @@ ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) } ssi_sram_addr_t -ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode) +cc_digest_len_addr(void *drvdata, u32 mode) { struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; - struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; + struct cc_hash_handle *hash_handle = _drvdata->hash_handle; ssi_sram_addr_t digest_len_addr = hash_handle->digest_len_sram_addr; switch (mode) { diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index 32eb473..ade4119 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -27,12 +27,12 @@ #define HMAC_OPAD_CONST 0x5C5C5C5C #if (DX_DEV_SHA_MAX > 256) #define HASH_LEN_SIZE 16 -#define SSI_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE -#define SSI_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE +#define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE +#define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE #else #define HASH_LEN_SIZE 8 -#define SSI_MAX_HASH_DIGEST_SIZE SHA256_DIGEST_SIZE -#define SSI_MAX_HASH_BLCK_SIZE SHA256_BLOCK_SIZE +#define CC_MAX_HASH_DIGEST_SIZE SHA256_DIGEST_SIZE +#define CC_MAX_HASH_BLCK_SIZE SHA256_BLOCK_SIZE #endif #define XCBC_MAC_K1_OFFSET 0 @@ -75,9 +75,9 @@ struct ahash_req_ctx { struct mlli_params mlli_params; }; -int ssi_hash_alloc(struct ssi_drvdata *drvdata); -int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata); -int ssi_hash_free(struct ssi_drvdata *drvdata); +int cc_hash_alloc(struct ssi_drvdata *drvdata); +int cc_init_hash_sram(struct ssi_drvdata *drvdata); +int cc_hash_free(struct ssi_drvdata *drvdata); /*! * Gets the initial digest length @@ -89,7 +89,7 @@ int ssi_hash_free(struct ssi_drvdata *drvdata); * \return u32 returns the address of the initial digest length in SRAM */ ssi_sram_addr_t -ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode); +cc_digest_len_addr(void *drvdata, u32 mode); /*! * Gets the address of the initial digest in SRAM diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c index 5e2ef5e..d1a6318 100644 --- a/drivers/staging/ccree/ssi_pm.c +++ b/drivers/staging/ccree/ssi_pm.c @@ -79,7 +79,7 @@ int cc_pm_resume(struct device *dev) } /* must be after the queue resuming as it uses the HW queue*/ - ssi_hash_init_sram_digest_consts(drvdata); + cc_init_hash_sram(drvdata); ssi_ivgen_init_sram_pool(drvdata); return 0; From patchwork Tue Dec 12 14:52:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121523 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4221718qgn; Tue, 12 Dec 2017 06:54:00 -0800 (PST) X-Google-Smtp-Source: ACJfBosM/rB6AKc/u61x+mu7NTaaqTs97Eawd0w5kqjmiDdJcp6TjGZZk53JN8nvlkCO9JJ3Zi4Q X-Received: by 10.98.92.194 with SMTP id q185mr2574214pfb.115.1513090440424; Tue, 12 Dec 2017 06:54:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090440; cv=none; d=google.com; s=arc-20160816; b=Os8PwfrAJKx33idOxRhJFPdDLCdEZr2zDWZnxh6I2+59aoy8txcQ7RrYUHF+E6qn2h rVJ5v0gxizyNXjaL/MucU2EwZZBl/oyd31ZtBkZehu7ykkzW4cEzqhWAIUIRcl8gZ6QV J2XTE1Sek9wwnfuA2EjiwPhXLMPOkYD7H6H1gto4G/nshZ+dLXOeFGxUDxK0OlSvZWgR Y4QgTA86Qyz7NhZnKVUlBf2dZQr3ZLIPrAkPCUd6611WcwCkU3XFE7LBTobtp9T808IM r9Em61wpH4Q6fKtAZZ9Qjd7MpyXO8fUNo3h1IC+Pztgv7osPFcrZlT19x74hez6xb+dg enWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dl3R+jWc9qB1hQn7fTHhPXMAOBE7rrgFwEXKKzIj/Kk=; b=FKF52v3OkTcsob9pjbHk39Cz+mz5IIB+/lbrk1HDgXTVLKE3TVuA38POCYz7Q2jOuZ xpP1kXrkdo0kyxjZq/NXl36Sj6sChX3MKGDaGrUF4HOXL1OBpmZWAVuFYoyTbGi6x5k3 yQEOmQoDAvGAn6KtaWXV2xgtlCwfDS1svgbGA22HNwehOfviJvlUTOU6fuO0cBKTT1Z/ /wcUdWntZwmB7juzUUZC1ZiJL3sEoFMsGLrBmULHJ+eXZ/dHL6M4hPBtzXTNyo56rbo+ W+CDW4YYmpCk8TE4Hiio0C24r8DXFmCt60s6/sf4fJKunAgOsx0G+PLspg42vAJZpsE7 OpIw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f84si11276354pfd.161.2017.12.12.06.54.00; Tue, 12 Dec 2017 06:54:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752604AbdLLOx5 (ORCPT + 11 others); Tue, 12 Dec 2017 09:53:57 -0500 Received: from foss.arm.com ([217.140.101.70]:45022 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752582AbdLLOxx (ORCPT ); Tue, 12 Dec 2017 09:53:53 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CBABE15AD; Tue, 12 Dec 2017 06:53:52 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 203333F577; Tue, 12 Dec 2017 06:53:50 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/24] staging: ccree: amend hash func def for readability Date: Tue, 12 Dec 2017 14:52:49 +0000 Message-Id: <1513090395-7938-4-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Func definitions in the hash implementation were did not adhere to coding style. Fix them for better readability. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_hash.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 6bc42e4..a80279e 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -64,10 +64,8 @@ static const u64 sha512_init[] = { SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 }; #endif -static void cc_setup_xcbc( - struct ahash_request *areq, - struct cc_hw_desc desc[], - unsigned int *seq_size); +static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[], + unsigned int *seq_size); static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[], unsigned int *seq_size); @@ -106,12 +104,9 @@ struct cc_hash_ctx { bool is_hmac; }; -static void cc_set_desc( - struct ahash_req_ctx *areq_ctx, - struct cc_hash_ctx *ctx, - unsigned int flow_mode, struct cc_hw_desc desc[], - bool is_not_last_data, - unsigned int *seq_size); +static void cc_set_desc(struct ahash_req_ctx *areq_ctx, struct cc_hash_ctx *ctx, + unsigned int flow_mode, struct cc_hw_desc desc[], + bool is_not_last_data, unsigned int *seq_size); static void cc_set_endianity(u32 mode, struct cc_hw_desc *desc) { @@ -1971,9 +1966,8 @@ static struct cc_hash_template driver_hash[] = { }; -static struct cc_hash_alg * -cc_alloc_hash_alg(struct cc_hash_template *template, struct device *dev, - bool keyed) +static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template, + struct device *dev, bool keyed) { struct cc_hash_alg *t_crypto_alg; struct crypto_alg *alg; From patchwork Tue Dec 12 14:52:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121527 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222292qgn; Tue, 12 Dec 2017 06:54:25 -0800 (PST) X-Google-Smtp-Source: ACJfBou+IZfh467i4dD7AWFdrI7U7k1EjnQrGWexgr3ZzZI3TZc9TF2vbbBvl2kfHXx1QCua+EkS X-Received: by 10.99.120.131 with SMTP id t125mr2224172pgc.83.1513090465742; Tue, 12 Dec 2017 06:54:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090465; cv=none; d=google.com; s=arc-20160816; b=Q3Q8H4OuHG55pi/lpQSTngPrQFWxuDuJw+xUATWgkkVMU/Lz804fZMmStvTpsV7Vo1 nSEoKMMx/0X2sYpDGrF3/A7vLOKxL52C58/T0X8I/lZXc5DmB0/HhDCeRo2ibefqK29C qijXfbQ/h5BznsFhjOWwi40ISkx4TpmlkaPFH8fR6TPLXOTJnSbuJ9ny2YlLTF/cVyTB Nonpwb/KzZfICWgVR5exPztb1g2T//umZZOnpCvLYIsilGu7J4SeIPxp94sgj1Nn23xw qmcMOasilQd+Z1yAl/je7PRzXxfVFhV6+Rzy8nDsxZKK9JsE47DWQ+/bdXKqY/P1Ojv9 xV5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=6m7CxIZVkRZwpQLoAtGQQ/iMP8MXlUo+4Ch4v0YpniA=; b=blDvF5o8P3M08XPMBxT5t/T13s50c8PpzIyK6O5mwg1z1LzAtk7SD5HbqKzdmO1yhy Vm+eziOHJCJOznUQnQJ1Ul+DbGyHjHWb17XsEdU7iCBh/ONkEgDbPKVNvPKJegN70TJn I1yhfZ7EYG+hULKe6N3sqBJS0FJ2sooEV8U3i4Mvahu1XcNKqB+pfuQzDt+TVrVSsMxF zc+/vt9cqqjFBKbyT3KJeN7h4dPT/zvhzZrHfkHPGmGjJnxKvZQpL4G9WZ4D85uEBn+h z2QjI8aQd9oWB7FHf1LhPrIlxjhRZp5UO+YEhZvg0MNYw37dr/jhpnvNho6r19NX1deb FfXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j69si11578375pgd.355.2017.12.12.06.54.25; Tue, 12 Dec 2017 06:54:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752679AbdLLOyW (ORCPT + 11 others); Tue, 12 Dec 2017 09:54:22 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45056 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751499AbdLLOyS (ORCPT ); Tue, 12 Dec 2017 09:54:18 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A1E351529; Tue, 12 Dec 2017 06:54:17 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 033F23F577; Tue, 12 Dec 2017 06:54:13 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/24] staging: ccree: fix func def and decl coding style Date: Tue, 12 Dec 2017 14:52:52 +0000 Message-Id: <1513090395-7938-7-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix functions definition and declaration indentation according to coding style guide lines for better code readability Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 5 +- drivers/staging/ccree/ssi_buffer_mgr.c | 144 +++++++++++++-------------------- drivers/staging/ccree/ssi_sram_mgr.h | 7 +- 3 files changed, 63 insertions(+), 93 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 62d45e9..112fba3 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -2686,9 +2686,8 @@ static struct ssi_alg_template aead_algs[] = { #endif /*SSI_CC_HAS_AES_GCM*/ }; -static struct ssi_crypto_alg *cc_create_aead_alg( - struct ssi_alg_template *tmpl, - struct device *dev) +static struct ssi_crypto_alg *cc_create_aead_alg(struct ssi_alg_template *tmpl, + struct device *dev) { struct ssi_crypto_alg *t_alg; struct aead_alg *alg; diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index c5bc027..099d83d 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -100,9 +100,10 @@ static void cc_copy_mac(struct device *dev, struct aead_request *req, * @nbytes: [IN] Total SGL data bytes. * @lbytes: [OUT] Returns the amount of bytes at the last entry */ -static unsigned int cc_get_sgl_nents( - struct device *dev, struct scatterlist *sg_list, - unsigned int nbytes, u32 *lbytes, bool *is_chained) +static unsigned int cc_get_sgl_nents(struct device *dev, + struct scatterlist *sg_list, + unsigned int nbytes, u32 *lbytes, + bool *is_chained) { unsigned int nents = 0; @@ -155,10 +156,8 @@ void cc_zero_sgl(struct scatterlist *sgl, u32 data_len) * @end: * @direct: */ -void cc_copy_sg_portion( - struct device *dev, u8 *dest, - struct scatterlist *sg, u32 to_skip, - u32 end, enum ssi_sg_cpy_direct direct) +void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg, + u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct) { u32 nents, lbytes; @@ -167,9 +166,9 @@ void cc_copy_sg_portion( (direct == SSI_SG_TO_BUF)); } -static int cc_render_buff_to_mlli( - struct device *dev, dma_addr_t buff_dma, u32 buff_size, - u32 *curr_nents, u32 **mlli_entry_pp) +static int cc_render_buff_to_mlli(struct device *dev, dma_addr_t buff_dma, + u32 buff_size, u32 *curr_nents, + u32 **mlli_entry_pp) { u32 *mlli_entry_p = *mlli_entry_pp; u32 new_nents; @@ -203,10 +202,9 @@ static int cc_render_buff_to_mlli( return 0; } -static int cc_render_sg_to_mlli( - struct device *dev, struct scatterlist *sgl, - u32 sgl_data_len, u32 sgl_offset, u32 *curr_nents, - u32 **mlli_entry_pp) +static int cc_render_sg_to_mlli(struct device *dev, struct scatterlist *sgl, + u32 sgl_data_len, u32 sgl_offset, + u32 *curr_nents, u32 **mlli_entry_pp) { struct scatterlist *curr_sgl = sgl; u32 *mlli_entry_p = *mlli_entry_pp; @@ -231,10 +229,8 @@ static int cc_render_sg_to_mlli( return 0; } -static int cc_generate_mlli( - struct device *dev, - struct buffer_array *sg_data, - struct mlli_params *mlli_params) +static int cc_generate_mlli(struct device *dev, struct buffer_array *sg_data, + struct mlli_params *mlli_params) { u32 *mlli_p; u32 total_nents = 0, prev_total_nents = 0; @@ -292,10 +288,10 @@ static int cc_generate_mlli( return rc; } -static void cc_add_buffer_entry( - struct device *dev, struct buffer_array *sgl_data, - dma_addr_t buffer_dma, unsigned int buffer_len, - bool is_last_entry, u32 *mlli_nents) +static void cc_add_buffer_entry(struct device *dev, + struct buffer_array *sgl_data, + dma_addr_t buffer_dma, unsigned int buffer_len, + bool is_last_entry, u32 *mlli_nents) { unsigned int index = sgl_data->num_of_buffers; @@ -313,15 +309,10 @@ static void cc_add_buffer_entry( sgl_data->num_of_buffers++; } -static void cc_add_sg_entry( - struct device *dev, - struct buffer_array *sgl_data, - unsigned int nents, - struct scatterlist *sgl, - unsigned int data_len, - unsigned int data_offset, - bool is_last_table, - u32 *mlli_nents) +static void cc_add_sg_entry(struct device *dev, struct buffer_array *sgl_data, + unsigned int nents, struct scatterlist *sgl, + unsigned int data_len, unsigned int data_offset, + bool is_last_table, u32 *mlli_nents) { unsigned int index = sgl_data->num_of_buffers; @@ -339,9 +330,8 @@ static void cc_add_sg_entry( sgl_data->num_of_buffers++; } -static int -cc_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents, - enum dma_data_direction direction) +static int cc_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents, + enum dma_data_direction direction) { u32 i, j; struct scatterlist *l_sg = sg; @@ -368,11 +358,9 @@ cc_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents, return 0; } -static int cc_map_sg( - struct device *dev, struct scatterlist *sg, - unsigned int nbytes, int direction, - u32 *nents, u32 max_sg_nents, - u32 *lbytes, u32 *mapped_nents) +static int cc_map_sg(struct device *dev, struct scatterlist *sg, + unsigned int nbytes, int direction, u32 *nents, + u32 max_sg_nents, u32 *lbytes, u32 *mapped_nents) { bool is_chained = false; @@ -478,12 +466,9 @@ static int ssi_ahash_handle_curr_buf(struct device *dev, return 0; } -void cc_unmap_blkcipher_request( - struct device *dev, - void *ctx, - unsigned int ivsize, - struct scatterlist *src, - struct scatterlist *dst) +void cc_unmap_blkcipher_request(struct device *dev, void *ctx, + unsigned int ivsize, struct scatterlist *src, + struct scatterlist *dst) { struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; @@ -511,14 +496,10 @@ void cc_unmap_blkcipher_request( } } -int cc_map_blkcipher_request( - struct ssi_drvdata *drvdata, - void *ctx, - unsigned int ivsize, - unsigned int nbytes, - void *info, - struct scatterlist *src, - struct scatterlist *dst) +int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, + unsigned int ivsize, unsigned int nbytes, + void *info, struct scatterlist *src, + struct scatterlist *dst) { struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; struct mlli_params *mlli_params = &req_ctx->mlli_params; @@ -704,13 +685,10 @@ void cc_unmap_aead_request(struct device *dev, struct aead_request *req) } } -static int cc_get_aead_icv_nents( - struct device *dev, - struct scatterlist *sgl, - unsigned int sgl_nents, - unsigned int authsize, - u32 last_entry_data_size, - bool *is_icv_fragmented) +static int cc_get_aead_icv_nents(struct device *dev, struct scatterlist *sgl, + unsigned int sgl_nents, unsigned int authsize, + u32 last_entry_data_size, + bool *is_icv_fragmented) { unsigned int icv_max_size = 0; unsigned int icv_required_size = authsize > last_entry_data_size ? @@ -758,11 +736,10 @@ static int cc_get_aead_icv_nents( return nents; } -static int cc_aead_chain_iv( - struct ssi_drvdata *drvdata, - struct aead_request *req, - struct buffer_array *sg_data, - bool is_last, bool do_chain) +static int cc_aead_chain_iv(struct ssi_drvdata *drvdata, + struct aead_request *req, + struct buffer_array *sg_data, + bool is_last, bool do_chain) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); unsigned int hw_iv_size = areq_ctx->hw_iv_size; @@ -803,11 +780,10 @@ static int cc_aead_chain_iv( return rc; } -static int cc_aead_chain_assoc( - struct ssi_drvdata *drvdata, - struct aead_request *req, - struct buffer_array *sg_data, - bool is_last, bool do_chain) +static int cc_aead_chain_assoc(struct ssi_drvdata *drvdata, + struct aead_request *req, + struct buffer_array *sg_data, + bool is_last, bool do_chain) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc = 0; @@ -895,9 +871,8 @@ static int cc_aead_chain_assoc( return rc; } -static void cc_prepare_aead_data_dlli( - struct aead_request *req, - u32 *src_last_bytes, u32 *dst_last_bytes) +static void cc_prepare_aead_data_dlli(struct aead_request *req, + u32 *src_last_bytes, u32 *dst_last_bytes) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; @@ -931,12 +906,11 @@ static void cc_prepare_aead_data_dlli( } } -static int cc_prepare_aead_data_mlli( - struct ssi_drvdata *drvdata, - struct aead_request *req, - struct buffer_array *sg_data, - u32 *src_last_bytes, u32 *dst_last_bytes, - bool is_last_table) +static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, + struct aead_request *req, + struct buffer_array *sg_data, + u32 *src_last_bytes, u32 *dst_last_bytes, + bool is_last_table) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; @@ -1066,11 +1040,10 @@ static int cc_prepare_aead_data_mlli( return rc; } -static int cc_aead_chain_data( - struct ssi_drvdata *drvdata, - struct aead_request *req, - struct buffer_array *sg_data, - bool is_last_table, bool do_chain) +static int cc_aead_chain_data(struct ssi_drvdata *drvdata, + struct aead_request *req, + struct buffer_array *sg_data, + bool is_last_table, bool do_chain) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct device *dev = drvdata_to_dev(drvdata); @@ -1238,8 +1211,7 @@ static void cc_update_aead_mlli_nents(struct ssi_drvdata *drvdata, } } -int cc_map_aead_request( - struct ssi_drvdata *drvdata, struct aead_request *req) +int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct mlli_params *mlli_params = &areq_ctx->mlli_params; diff --git a/drivers/staging/ccree/ssi_sram_mgr.h b/drivers/staging/ccree/ssi_sram_mgr.h index 9e39262..76719ec 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.h +++ b/drivers/staging/ccree/ssi_sram_mgr.h @@ -71,9 +71,8 @@ ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size); * @seq: A pointer to the given IN/OUT descriptor sequence * @seq_len: A pointer to the given IN/OUT sequence length */ -void cc_set_sram_desc( - const u32 *src, ssi_sram_addr_t dst, - unsigned int nelement, - struct cc_hw_desc *seq, unsigned int *seq_len); +void cc_set_sram_desc(const u32 *src, ssi_sram_addr_t dst, + unsigned int nelement, struct cc_hw_desc *seq, + unsigned int *seq_len); #endif /*__SSI_SRAM_MGR_H__*/ From patchwork Tue Dec 12 14:52:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121528 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222436qgn; Tue, 12 Dec 2017 06:54:34 -0800 (PST) X-Google-Smtp-Source: ACJfBov9e15hr4qHc7sNx7z1pCFxzqhMLVGQIaK1kJbyTbWChBkJBnVzSm5nLEioYnPBU2hJc+47 X-Received: by 10.98.14.144 with SMTP id 16mr2577486pfo.195.1513090474708; Tue, 12 Dec 2017 06:54:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090474; cv=none; d=google.com; s=arc-20160816; b=vHP6Z/6wbsB0NjyJ5SsTbcsh/4UcTRa+c/uv7jqwrx4Qm8NM0qTJq6RTqbzIpr7lCB 21+d3xEvqBm100S9FmgudJ5aVWbTVaNBdf7L6wuO1gqqQg8le5p+h2jJEwRXIjUGB9Ew +ncJSj7DMrxLHiCPsWNipdFyfws7epPLC6/PrW1ErsffOBNN/SyBW9J6e3jQQHgL6qDZ TPGVEvHTaGo+NTNA+1dL7CxcGLULrJxZpubM4fmrw3zft4rlXm2dGzYC8xrO1MS1+Zeu HmFtPdCl1uWQMXqnq4b7fW0MxR7kg5aoe9WIWBcAeGD36RJTjQ6wQngYqQnwOSInQgdp oE+g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id v9si10144691plo.199.2017.12.12.06.54.34; Tue, 12 Dec 2017 06:54:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752707AbdLLOyb (ORCPT + 11 others); Tue, 12 Dec 2017 09:54:31 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45080 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752467AbdLLOy0 (ORCPT ); Tue, 12 Dec 2017 09:54:26 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF4BA1529; Tue, 12 Dec 2017 06:54:25 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0627D3F577; Tue, 12 Dec 2017 06:54:23 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/24] staging: ccree: simplify expression with local var Date: Tue, 12 Dec 2017 14:52:53 +0000 Message-Id: <1513090395-7938-8-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Simplify expression by using a local variable for better code readability. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_buffer_mgr.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 099d83d..490dd5a 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -917,6 +917,7 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, unsigned int authsize = areq_ctx->req_authsize; int rc = 0, icv_nents; struct device *dev = drvdata_to_dev(drvdata); + struct scatterlist *sg; if (req->src == req->dst) { /*INPLACE*/ @@ -955,12 +956,11 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, areq_ctx->mac_buf_dma_addr; } } else { /* Contig. ICV */ + sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1]; /*Should hanlde if the sg is not contig.*/ - areq_ctx->icv_dma_addr = sg_dma_address( - &areq_ctx->src_sgl[areq_ctx->src.nents - 1]) + + areq_ctx->icv_dma_addr = sg_dma_address(sg) + (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - &areq_ctx->src_sgl[areq_ctx->src.nents - 1]) + + areq_ctx->icv_virt_addr = sg_virt(sg) + (*src_last_bytes - authsize); } @@ -993,12 +993,11 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { /* Contig. ICV */ + sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1]; /*Should hanlde if the sg is not contig.*/ - areq_ctx->icv_dma_addr = sg_dma_address( - &areq_ctx->src_sgl[areq_ctx->src.nents - 1]) + + areq_ctx->icv_dma_addr = sg_dma_address(sg) + (*src_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - &areq_ctx->src_sgl[areq_ctx->src.nents - 1]) + + areq_ctx->icv_virt_addr = sg_virt(sg) + (*src_last_bytes - authsize); } @@ -1023,12 +1022,11 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, } if (!areq_ctx->is_icv_fragmented) { + sg = &areq_ctx->dst_sgl[areq_ctx->dst.nents - 1]; /* Contig. ICV */ - areq_ctx->icv_dma_addr = sg_dma_address( - &areq_ctx->dst_sgl[areq_ctx->dst.nents - 1]) + + areq_ctx->icv_dma_addr = sg_dma_address(sg) + (*dst_last_bytes - authsize); - areq_ctx->icv_virt_addr = sg_virt( - &areq_ctx->dst_sgl[areq_ctx->dst.nents - 1]) + + areq_ctx->icv_virt_addr = sg_virt(sg) + (*dst_last_bytes - authsize); } else { areq_ctx->icv_dma_addr = areq_ctx->mac_buf_dma_addr; From patchwork Tue Dec 12 14:52:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121531 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4222935qgn; Tue, 12 Dec 2017 06:55:00 -0800 (PST) X-Google-Smtp-Source: ACJfBot24q2wAW4RokXxxvFEC+IzzXLP2/q6wSmUvB3MNox51cF0lbmXcwpe+/g8WN2BSybtqJhl X-Received: by 10.99.49.81 with SMTP id x78mr1961440pgx.35.1513090500455; Tue, 12 Dec 2017 06:55:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090500; cv=none; d=google.com; s=arc-20160816; b=St4uJVZi42YNIILICKwMIu7uYB/zZQoecJBpgY666pJrVlKRRrUwFZb7Jfnms86mG1 9p6AFHaFWlaBJX6ZHH/Idpoxp1MUA2uHVjqz0BbcjzD4R/pQnJKK7i4TFem7NzIGWLU8 2pFbM0/L7DaVePhL1WsMzFSDzSLlXZPlgop9wko0cXPOkpioHrVmJHhhkjcwwuyxvrLI sby7mop6SWQw/wrjpEaYF30PBvUM3Un5ddR0wF3GGUuRO8md/IPdiOUd++JjTwZRL9dD pV61EY1Vkp7YeBUsWSblFdZhtCV1gqYJRUCiN15tvVYTsHp3o0LEcZWbfRZH47DH9Fkl Rxnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=7X8z7jF8nFxLKhBaKXRECeDMZE/onvtUIFVOqeTXNh8=; b=BCpfJsfvDlWY99Uoe4VeBaz061MVsKdMdGDeVdXE35+wq3R/sccKiTf7bYz6tqIhUi /o40nC8TWfrIALh54z/uRYt/3M629hjldQ7ZTilJ2UWbjz3fmiklyPJCsXs76bhZIpFa Pq/CKLGeDaJLZOHGqA/zcywhi91J8ZIX0sWY3a98XDo8mCMunBpoOr8oIdEEnx40Hwiz dVtRbspj+0irmzu4sSuW1z+LwyOKOkAeYxBH9ktEjge8kjzkzCAvj1TTAQsUjU+RiJ/j en1l07ZQrt13JBbA4r+0f68qhr6BbKFiCvbH7GRzOCU1z4kOPajXsZsuEU8CyzYmXkVo 2v3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 12 Dec 2017 06:54:46 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/24] staging: ccree: fix req mgr func def coding style Date: Tue, 12 Dec 2017 14:52:56 +0000 Message-Id: <1513090395-7938-11-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix request manager functions definition indentation according to coding style guide lines for better code readability Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_request_mgr.c | 21 +++++++++------------ drivers/staging/ccree/ssi_request_mgr.h | 9 ++++----- 2 files changed, 13 insertions(+), 17 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index dbdfd0c..91f5e2d 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -165,9 +165,8 @@ int cc_req_mgr_init(struct ssi_drvdata *drvdata) return rc; } -static void enqueue_seq( - void __iomem *cc_base, - struct cc_hw_desc seq[], unsigned int seq_len) +static void enqueue_seq(void __iomem *cc_base, struct cc_hw_desc seq[], + unsigned int seq_len) { int i, w; void * __iomem reg = cc_base + CC_REG(DSCRPTR_QUEUE_WORD0); @@ -202,10 +201,9 @@ static void request_mgr_complete(struct device *dev, void *dx_compl_h) complete(this_compl); } -static int cc_queues_status( - struct ssi_drvdata *drvdata, - struct cc_req_mgr_handle *req_mgr_h, - unsigned int total_seq_len) +static int cc_queues_status(struct ssi_drvdata *drvdata, + struct cc_req_mgr_handle *req_mgr_h, + unsigned int total_seq_len) { unsigned long poll_queue; struct device *dev = drvdata_to_dev(drvdata); @@ -259,9 +257,8 @@ static int cc_queues_status( * * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false" */ -int send_request( - struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, - struct cc_hw_desc *desc, unsigned int len, bool is_dout) +int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, + struct cc_hw_desc *desc, unsigned int len, bool is_dout) { void __iomem *cc_base = drvdata->cc_base; struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; @@ -413,8 +410,8 @@ int send_request( * * \return int Returns "0" upon success */ -int send_request_init( - struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len) +int send_request_init(struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, + unsigned int len) { void __iomem *cc_base = drvdata->cc_base; struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index d018f51..91e0d47 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -38,12 +38,11 @@ int cc_req_mgr_init(struct ssi_drvdata *drvdata); * * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false" */ -int send_request( - struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, - struct cc_hw_desc *desc, unsigned int len, bool is_dout); +int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, + struct cc_hw_desc *desc, unsigned int len, bool is_dout); -int send_request_init( - struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len); +int send_request_init(struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, + unsigned int len); void complete_request(struct ssi_drvdata *drvdata); From patchwork Tue Dec 12 14:52:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121533 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223266qgn; Tue, 12 Dec 2017 06:55:17 -0800 (PST) X-Google-Smtp-Source: ACJfBourbSlcCWyPIDZHZx5ex1BjtKRSoNleo7a9UsdUkwdcEerXJzxTETUvie2hL4ktpyBv/7+z X-Received: by 10.99.96.87 with SMTP id u84mr2327286pgb.424.1513090517124; Tue, 12 Dec 2017 06:55:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090517; cv=none; d=google.com; s=arc-20160816; b=hSOgg+3nRaSh78OWw1PmKDtneG7UMr8kJ2N04+u8rti15nQ1kyhE4pBRwll7Fys9t5 6tUFUUTt5YQ25Z4t5fdt5y0YSTm2D86besV06HmX+3oUKy5mOL9Z5XKBq/SYrmOsOaDz 8gLVrHrM4UwLAWWpqeqZqYLhae5oMLQOMVeTZoyzpF4HIDuPD5b6nkj2P90J2SBhp5EX AE+F9TLZY0Oug9qMVO8zBODqupRr7TQqLZ0PQjdlmZ7yaabiInl0dM+C1GGPg0WlfcbL 57mHYjFp4flArSEaowumWNnCTDpG/ORpJ1mYi6ziMsfoPY1mb6CLhVmI6qRYaD6aVv3R 1oxw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id r82si6861696pfi.277.2017.12.12.06.55.16; Tue, 12 Dec 2017 06:55:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752815AbdLLOzM (ORCPT + 11 others); Tue, 12 Dec 2017 09:55:12 -0500 Received: from foss.arm.com ([217.140.101.70]:45130 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752435AbdLLOzI (ORCPT ); Tue, 12 Dec 2017 09:55:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 030B71529; Tue, 12 Dec 2017 06:55:08 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45D013F318; Tue, 12 Dec 2017 06:55:04 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/24] staging: ccree: fix cipher naming convention Date: Tue, 12 Dec 2017 14:52:58 +0000 Message-Id: <1513090395-7938-13-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The blkcipher files were using a func naming convention which was inconsistent (ssi vs. cc), included a long prefix (ssi_ablkcipher) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_cipher.c | 221 ++++++++++++++++++------------------- drivers/staging/ccree/ssi_cipher.h | 8 +- drivers/staging/ccree/ssi_driver.c | 8 +- 3 files changed, 118 insertions(+), 119 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index 0dc63f1..d7687a4 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -38,9 +38,9 @@ #define template_ablkcipher template_u.ablkcipher -#define SSI_MIN_AES_XTS_SIZE 0x10 -#define SSI_MAX_AES_XTS_SIZE 0x2000 -struct ssi_blkcipher_handle { +#define CC_MIN_AES_XTS_SIZE 0x10 +#define CC_MAX_AES_XTS_SIZE 0x2000 +struct cc_cipher_handle { struct list_head blkcipher_alg_list; }; @@ -54,7 +54,7 @@ struct cc_hw_key_info { enum cc_hw_crypto_key key2_slot; }; -struct ssi_ablkcipher_ctx { +struct cc_cipher_ctx { struct ssi_drvdata *drvdata; int keylen; int key_round_number; @@ -67,9 +67,9 @@ struct ssi_ablkcipher_ctx { struct crypto_shash *shash_tfm; }; -static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req); +static void cc_cipher_complete(struct device *dev, void *ssi_req); -static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) +static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) { switch (ctx_p->flow_mode) { case S_DIN_to_AES: @@ -109,15 +109,15 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) return -EINVAL; } -static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, +static int validate_data_size(struct cc_cipher_ctx *ctx_p, unsigned int size) { switch (ctx_p->flow_mode) { case S_DIN_to_AES: switch (ctx_p->cipher_mode) { case DRV_CIPHER_XTS: - if (size >= SSI_MIN_AES_XTS_SIZE && - size <= SSI_MAX_AES_XTS_SIZE && + if (size >= CC_MIN_AES_XTS_SIZE && + size <= CC_MAX_AES_XTS_SIZE && IS_ALIGNED(size, AES_BLOCK_SIZE)) return 0; break; @@ -180,9 +180,9 @@ static unsigned int get_max_keysize(struct crypto_tfm *tfm) return 0; } -static int ssi_ablkcipher_init(struct crypto_tfm *tfm) +static int cc_cipher_init(struct crypto_tfm *tfm) { - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct crypto_alg *alg = tfm->__crt_alg; struct ssi_crypto_alg *ssi_alg = container_of(alg, struct ssi_crypto_alg, crypto_alg); @@ -232,9 +232,9 @@ static int ssi_ablkcipher_init(struct crypto_tfm *tfm) return rc; } -static void ssi_blkcipher_exit(struct crypto_tfm *tfm) +static void cc_cipher_exit(struct crypto_tfm *tfm) { - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); unsigned int max_key_buf_size = get_max_keysize(tfm); @@ -270,7 +270,7 @@ static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; /* The function verifies that tdes keys are not weak.*/ -static int ssi_verify_3des_keys(const u8 *key, unsigned int keylen) +static int cc_verify_3des_keys(const u8 *key, unsigned int keylen) { struct tdes_keys *tdes_key = (struct tdes_keys *)key; @@ -300,11 +300,11 @@ static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num) return END_OF_KEYS; } -static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, - unsigned int keylen) +static int cc_cipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, + unsigned int keylen) { struct crypto_tfm *tfm = crypto_ablkcipher_tfm(atfm); - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); u32 tmp[DES_EXPKEY_WORDS]; unsigned int max_key_buf_size = get_max_keysize(tfm); @@ -329,7 +329,7 @@ static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, return -EINVAL; } - if (ssi_is_hw_key(tfm)) { + if (cc_is_hw_key(tfm)) { /* setting HW key slots */ struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key; @@ -363,7 +363,7 @@ static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, } ctx_p->keylen = keylen; - dev_dbg(dev, "ssi_is_hw_key ret 0"); + dev_dbg(dev, "cc_is_hw_key ret 0"); return 0; } @@ -384,7 +384,7 @@ static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, } if (ctx_p->flow_mode == S_DIN_to_DES && keylen == DES3_EDE_KEY_SIZE && - ssi_verify_3des_keys(key, keylen)) { + cc_verify_3des_keys(key, keylen)) { dev_dbg(dev, "weak 3DES key"); return -EINVAL; } @@ -436,7 +436,7 @@ static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, } static void -ssi_blkcipher_create_setup_desc( +cc_setup_cipher_desc( struct crypto_tfm *tfm, struct blkcipher_req_ctx *req_ctx, unsigned int ivsize, @@ -444,7 +444,7 @@ ssi_blkcipher_create_setup_desc( struct cc_hw_desc desc[], unsigned int *seq_size) { - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); int cipher_mode = ctx_p->cipher_mode; int flow_mode = ctx_p->flow_mode; @@ -491,7 +491,7 @@ ssi_blkcipher_create_setup_desc( set_cipher_mode(&desc[*seq_size], cipher_mode); set_cipher_config0(&desc[*seq_size], direction); if (flow_mode == S_DIN_to_AES) { - if (ssi_is_hw_key(tfm)) { + if (cc_is_hw_key(tfm)) { set_hw_crypto_key(&desc[*seq_size], ctx_p->hw.key1_slot); } else { @@ -518,7 +518,7 @@ ssi_blkcipher_create_setup_desc( hw_desc_init(&desc[*seq_size]); set_cipher_mode(&desc[*seq_size], cipher_mode); set_cipher_config0(&desc[*seq_size], direction); - if (ssi_is_hw_key(tfm)) { + if (cc_is_hw_key(tfm)) { set_hw_crypto_key(&desc[*seq_size], ctx_p->hw.key1_slot); } else { @@ -534,7 +534,7 @@ ssi_blkcipher_create_setup_desc( hw_desc_init(&desc[*seq_size]); set_cipher_mode(&desc[*seq_size], cipher_mode); set_cipher_config0(&desc[*seq_size], direction); - if (ssi_is_hw_key(tfm)) { + if (cc_is_hw_key(tfm)) { set_hw_crypto_key(&desc[*seq_size], ctx_p->hw.key2_slot); } else { @@ -565,14 +565,14 @@ ssi_blkcipher_create_setup_desc( } #if SSI_CC_HAS_MULTI2 -static void ssi_blkcipher_create_multi2_setup_desc( +static void cc_setup_multi2_desc( struct crypto_tfm *tfm, struct blkcipher_req_ctx *req_ctx, unsigned int ivsize, struct cc_hw_desc desc[], unsigned int *seq_size) { - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); int direction = req_ctx->gen_ctx.op_type; /* Load system key */ @@ -610,7 +610,7 @@ static void ssi_blkcipher_create_multi2_setup_desc( #endif /*SSI_CC_HAS_MULTI2*/ static void -ssi_blkcipher_create_data_desc( +cc_setup_cipher_data( struct crypto_tfm *tfm, struct blkcipher_req_ctx *req_ctx, struct scatterlist *dst, struct scatterlist *src, @@ -619,7 +619,7 @@ ssi_blkcipher_create_data_desc( struct cc_hw_desc desc[], unsigned int *seq_size) { - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); unsigned int flow_mode = ctx_p->flow_mode; @@ -703,7 +703,7 @@ ssi_blkcipher_create_data_desc( } } -static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req) +static void cc_cipher_complete(struct device *dev, void *ssi_req) { struct ablkcipher_request *areq = (struct ablkcipher_request *)ssi_req; struct scatterlist *dst = areq->dst; @@ -747,7 +747,7 @@ static int cc_cipher_process(struct ablkcipher_request *req, struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; void *info = req->info; - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); + struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; struct ssi_crypto_req ssi_req = {}; @@ -790,7 +790,7 @@ static int cc_cipher_process(struct ablkcipher_request *req, } /* Setup DX request structure */ - ssi_req.user_cb = (void *)ssi_ablkcipher_complete; + ssi_req.user_cb = (void *)cc_cipher_complete; ssi_req.user_arg = (void *)req; #ifdef ENABLE_CYCLE_COUNT @@ -816,15 +816,14 @@ static int cc_cipher_process(struct ablkcipher_request *req, /* Setup processing */ #if SSI_CC_HAS_MULTI2 if (ctx_p->flow_mode == S_DIN_to_MULTI2) - ssi_blkcipher_create_multi2_setup_desc(tfm, req_ctx, ivsize, - desc, &seq_len); + cc_setup_multi2_desc(tfm, req_ctx, ivsize, desc, &seq_len); else #endif /*SSI_CC_HAS_MULTI2*/ - ssi_blkcipher_create_setup_desc(tfm, req_ctx, ivsize, nbytes, - desc, &seq_len); + cc_setup_cipher_desc(tfm, req_ctx, ivsize, nbytes, desc, + &seq_len); /* Data processing */ - ssi_blkcipher_create_data_desc(tfm, req_ctx, dst, src, nbytes, req, - desc, &seq_len); + cc_setup_cipher_data(tfm, req_ctx, dst, src, nbytes, req, desc, + &seq_len); /* do we need to generate IV? */ if (req_ctx->is_giv) { @@ -856,7 +855,7 @@ static int cc_cipher_process(struct ablkcipher_request *req, return rc; } -static int ssi_ablkcipher_encrypt(struct ablkcipher_request *req) +static int cc_cipher_encrypt(struct ablkcipher_request *req) { struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req); @@ -866,7 +865,7 @@ static int ssi_ablkcipher_encrypt(struct ablkcipher_request *req) return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT); } -static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req) +static int cc_cipher_decrypt(struct ablkcipher_request *req) { struct crypto_ablkcipher *ablk_tfm = crypto_ablkcipher_reqtfm(req); struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(req); @@ -896,9 +895,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -913,9 +912,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -929,9 +928,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -947,9 +946,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -963,9 +962,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -979,9 +978,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -997,9 +996,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -1013,9 +1012,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_512, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -1029,9 +1028,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_BULK_DU_4096, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE * 2, .max_keysize = AES_MAX_KEY_SIZE * 2, .ivsize = AES_BLOCK_SIZE, @@ -1046,9 +1045,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = 0, @@ -1062,9 +1061,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, @@ -1078,9 +1077,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, @@ -1095,9 +1094,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = AES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, @@ -1112,9 +1111,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = 1, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, @@ -1128,9 +1127,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = DES3_EDE_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = DES3_EDE_KEY_SIZE, .max_keysize = DES3_EDE_KEY_SIZE, .ivsize = DES3_EDE_BLOCK_SIZE, @@ -1144,9 +1143,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = DES3_EDE_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = DES3_EDE_KEY_SIZE, .max_keysize = DES3_EDE_KEY_SIZE, .ivsize = 0, @@ -1160,9 +1159,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = DES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = DES_KEY_SIZE, .max_keysize = DES_KEY_SIZE, .ivsize = DES_BLOCK_SIZE, @@ -1176,9 +1175,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = DES_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = DES_KEY_SIZE, .max_keysize = DES_KEY_SIZE, .ivsize = 0, @@ -1193,9 +1192,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = CC_MULTI2_BLOCK_SIZE, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_decrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_decrypt, .min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, .max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, .ivsize = CC_MULTI2_IV_SIZE, @@ -1209,9 +1208,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .blocksize = 1, .type = CRYPTO_ALG_TYPE_ABLKCIPHER, .template_ablkcipher = { - .setkey = ssi_ablkcipher_setkey, - .encrypt = ssi_ablkcipher_encrypt, - .decrypt = ssi_ablkcipher_encrypt, + .setkey = cc_cipher_setkey, + .encrypt = cc_cipher_encrypt, + .decrypt = cc_cipher_encrypt, .min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, .max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, .ivsize = CC_MULTI2_IV_SIZE, @@ -1223,8 +1222,8 @@ static struct ssi_alg_template blkcipher_algs[] = { }; static -struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template - *template, struct device *dev) +struct ssi_crypto_alg *cc_cipher_create_alg(struct ssi_alg_template *template, + struct device *dev) { struct ssi_crypto_alg *t_alg; struct crypto_alg *alg; @@ -1242,10 +1241,10 @@ struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template alg->cra_priority = SSI_CRA_PRIO; alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; - alg->cra_ctxsize = sizeof(struct ssi_ablkcipher_ctx); + alg->cra_ctxsize = sizeof(struct cc_cipher_ctx); - alg->cra_init = ssi_ablkcipher_init; - alg->cra_exit = ssi_blkcipher_exit; + alg->cra_init = cc_cipher_init; + alg->cra_exit = cc_cipher_exit; alg->cra_type = &crypto_ablkcipher_type; alg->cra_ablkcipher = template->template_ablkcipher; alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | @@ -1257,10 +1256,10 @@ struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template return t_alg; } -int ssi_ablkcipher_free(struct ssi_drvdata *drvdata) +int cc_cipher_free(struct ssi_drvdata *drvdata) { struct ssi_crypto_alg *t_alg, *n; - struct ssi_blkcipher_handle *blkcipher_handle = + struct cc_cipher_handle *blkcipher_handle = drvdata->blkcipher_handle; if (blkcipher_handle) { /* Remove registered algs */ @@ -1277,9 +1276,9 @@ int ssi_ablkcipher_free(struct ssi_drvdata *drvdata) return 0; } -int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) +int cc_cipher_alloc(struct ssi_drvdata *drvdata) { - struct ssi_blkcipher_handle *ablkcipher_handle; + struct cc_cipher_handle *ablkcipher_handle; struct ssi_crypto_alg *t_alg; struct device *dev = drvdata_to_dev(drvdata); int rc = -ENOMEM; @@ -1297,7 +1296,7 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) ARRAY_SIZE(blkcipher_algs)); for (alg = 0; alg < ARRAY_SIZE(blkcipher_algs); alg++) { dev_dbg(dev, "creating %s\n", blkcipher_algs[alg].driver_name); - t_alg = ssi_ablkcipher_create_alg(&blkcipher_algs[alg], dev); + t_alg = cc_cipher_create_alg(&blkcipher_algs[alg], dev); if (IS_ERR(t_alg)) { rc = PTR_ERR(t_alg); dev_err(dev, "%s alg allocation failed\n", @@ -1326,6 +1325,6 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) return 0; fail0: - ssi_ablkcipher_free(drvdata); + cc_cipher_free(drvdata); return rc; } diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index 14c0ad9..ef6d6e9 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -51,9 +51,9 @@ struct blkcipher_req_ctx { struct mlli_params mlli_params; }; -int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata); +int cc_cipher_alloc(struct ssi_drvdata *drvdata); -int ssi_ablkcipher_free(struct ssi_drvdata *drvdata); +int cc_cipher_free(struct ssi_drvdata *drvdata); #ifndef CRYPTO_ALG_BULK_MASK @@ -65,7 +65,7 @@ int ssi_ablkcipher_free(struct ssi_drvdata *drvdata); #ifdef CRYPTO_TFM_REQ_HW_KEY -static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) +static inline bool cc_is_hw_key(struct crypto_tfm *tfm) { return (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_HW_KEY); } @@ -77,7 +77,7 @@ struct arm_hw_key_info { int hw_key2; }; -static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) +static inline bool cc_is_hw_key(struct crypto_tfm *tfm) { return false; } diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 491e2b9..2a0dd85 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -351,9 +351,9 @@ static int init_cc_resources(struct platform_device *plat_dev) } /* Allocate crypto algs */ - rc = ssi_ablkcipher_alloc(new_drvdata); + rc = cc_cipher_alloc(new_drvdata); if (rc) { - dev_err(dev, "ssi_ablkcipher_alloc failed\n"); + dev_err(dev, "cc_cipher_alloc failed\n"); goto post_ivgen_err; } @@ -381,7 +381,7 @@ static int init_cc_resources(struct platform_device *plat_dev) post_hash_err: cc_hash_free(new_drvdata); post_cipher_err: - ssi_ablkcipher_free(new_drvdata); + cc_cipher_free(new_drvdata); post_ivgen_err: ssi_ivgen_fini(new_drvdata); post_power_mgr_err: @@ -418,7 +418,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) cc_aead_free(drvdata); cc_hash_free(drvdata); - ssi_ablkcipher_free(drvdata); + cc_cipher_free(drvdata); ssi_ivgen_fini(drvdata); cc_pm_fini(drvdata); cc_buffer_mgr_fini(drvdata); From patchwork Tue Dec 12 14:53:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121535 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223610qgn; Tue, 12 Dec 2017 06:55:32 -0800 (PST) X-Google-Smtp-Source: ACJfBouoxEkivveUDb8ev2lMUVMAhBz6XhbAX1ystSGwTckXt6Z8Af2ltZzxR8nL57bCs98QmM/9 X-Received: by 10.84.244.9 with SMTP id g9mr2585814pll.192.1513090532466; Tue, 12 Dec 2017 06:55:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090532; cv=none; d=google.com; s=arc-20160816; b=l1SoxyydR9H96SVuN4tcMdB6p6GtTlyHhcKbr0mlHaOTzpjIGiv8PN2KbS0fT9lG7s NfuFny4Hnhy7Zgz9p9TtL6k0BuGMfwXkBHI+iKrL+2ukJEAVKVI7Upq8lAuSgxVwo7Zq 7MoUUIR1hpsztR0WBcB3EomtqRI7tFXhsFo30pD1seus5uRqKSnDWH2s7d8D5tJBI9Eo cdt6qVZzt5rO6Pkdo7DFfOBhWsmRjTIgeFP6Or8/P1dE6adkmdol5dccvYk65eMFUTo/ HtA0TU/4m4TgMX4kpGe50SpUnAyorbQ+EY2En4Qsi3+XSLcIBdsVR4CZvrgXEANEg7X4 xLmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=XbaXsAAKXYiC636rLSNZu2jfWxsQUl0l+fEc5h26Kzk=; b=iMVTvuDft2sXMOzlZblyOj4HYoqRBcLcDh+XEpNCQiQsH6NjykuYKD5SdeeByaMgEt qF2uNByql3YPel1S+oiVNJ1EmXTpnkZcC2IrATKLm1bgpKGcHSzNKu4R3rR6nNUJK6II gzgsMSeXjh0QzIDcw/zIwKmSVFXGJtgIEntIgbucycaQ8umlv4YVmuuQsdcoXpIZPAZX dNCetKLxZv19FOkptQ1HOl7WwMmxpBVr3HRq0vJdbuy+1Nbl9Q4hqnz5I2mN1Ckedszg /Ys6bWj2AphvZMoErqNONswOS3vDreUqddvcprtLgiT5jwatDsPCJzFL3IQIVk9nNkB5 EZ8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3si9308189plm.630.2017.12.12.06.55.32; Tue, 12 Dec 2017 06:55:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752857AbdLLOz3 (ORCPT + 11 others); Tue, 12 Dec 2017 09:55:29 -0500 Received: from foss.arm.com ([217.140.101.70]:45152 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752830AbdLLOzY (ORCPT ); Tue, 12 Dec 2017 09:55:24 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8AE3F1529; Tue, 12 Dec 2017 06:55:24 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 020853F318; Tue, 12 Dec 2017 06:55:20 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/24] staging: ccree: fix ivgen naming convention Date: Tue, 12 Dec 2017 14:53:00 +0000 Message-Id: <1513090395-7938-15-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ivgen files were using a func naming convention which was inconsistent (ssi vs. cc), included a long prefix (ssi_ivgen) and often too long. Make the code more readable by switching to a simpler, consistent naming convention. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_driver.c | 8 ++-- drivers/staging/ccree/ssi_ivgen.c | 66 ++++++++++++++++----------------- drivers/staging/ccree/ssi_ivgen.h | 8 ++-- drivers/staging/ccree/ssi_pm.c | 2 +- drivers/staging/ccree/ssi_request_mgr.c | 7 ++-- 5 files changed, 46 insertions(+), 45 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 2a0dd85..f4164eb 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -344,9 +344,9 @@ static int init_cc_resources(struct platform_device *plat_dev) goto post_buf_mgr_err; } - rc = ssi_ivgen_init(new_drvdata); + rc = cc_ivgen_init(new_drvdata); if (rc) { - dev_err(dev, "ssi_ivgen_init failed\n"); + dev_err(dev, "cc_ivgen_init failed\n"); goto post_power_mgr_err; } @@ -383,7 +383,7 @@ static int init_cc_resources(struct platform_device *plat_dev) post_cipher_err: cc_cipher_free(new_drvdata); post_ivgen_err: - ssi_ivgen_fini(new_drvdata); + cc_ivgen_fini(new_drvdata); post_power_mgr_err: cc_pm_fini(new_drvdata); post_buf_mgr_err: @@ -419,7 +419,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) cc_aead_free(drvdata); cc_hash_free(drvdata); cc_cipher_free(drvdata); - ssi_ivgen_fini(drvdata); + cc_ivgen_fini(drvdata); cc_pm_fini(drvdata); cc_buffer_mgr_fini(drvdata); cc_req_mgr_fini(drvdata); diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index febee22..ad6cd97 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -24,15 +24,15 @@ #include "ssi_buffer_mgr.h" /* The max. size of pool *MUST* be <= SRAM total size */ -#define SSI_IVPOOL_SIZE 1024 +#define CC_IVPOOL_SIZE 1024 /* The first 32B fraction of pool are dedicated to the * next encryption "key" & "IV" for pool regeneration */ -#define SSI_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128) -#define SSI_IVPOOL_GEN_SEQ_LEN 4 +#define CC_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128) +#define CC_IVPOOL_GEN_SEQ_LEN 4 /** - * struct ssi_ivgen_ctx -IV pool generation context + * struct cc_ivgen_ctx -IV pool generation context * @pool: the start address of the iv-pool resides in internal RAM * @ctr_key_dma: address of pool's encryption key material in internal RAM * @ctr_iv_dma: address of pool's counter iv in internal RAM @@ -40,7 +40,7 @@ * @pool_meta: virt. address of the initial enc. key/IV * @pool_meta_dma: phys. address of the initial enc. key/IV */ -struct ssi_ivgen_ctx { +struct cc_ivgen_ctx { ssi_sram_addr_t pool; ssi_sram_addr_t ctr_key; ssi_sram_addr_t ctr_iv; @@ -50,21 +50,21 @@ struct ssi_ivgen_ctx { }; /*! - * Generates SSI_IVPOOL_SIZE of random bytes by + * Generates CC_IVPOOL_SIZE of random bytes by * encrypting 0's using AES128-CTR. * * \param ivgen iv-pool context * \param iv_seq IN/OUT array to the descriptors sequence * \param iv_seq_len IN/OUT pointer to the sequence length */ -static int ssi_ivgen_generate_pool( - struct ssi_ivgen_ctx *ivgen_ctx, +static int cc_gen_iv_pool( + struct cc_ivgen_ctx *ivgen_ctx, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { unsigned int idx = *iv_seq_len; - if ((*iv_seq_len + SSI_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) { + if ((*iv_seq_len + CC_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } @@ -97,15 +97,15 @@ static int ssi_ivgen_generate_pool( /* Generate IV pool */ hw_desc_init(&iv_seq[idx]); - set_din_const(&iv_seq[idx], 0, SSI_IVPOOL_SIZE); - set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, SSI_IVPOOL_SIZE); + set_din_const(&iv_seq[idx], 0, CC_IVPOOL_SIZE); + set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_IVPOOL_SIZE); set_flow_mode(&iv_seq[idx], DIN_AES_DOUT); idx++; *iv_seq_len = idx; /* Update sequence length */ /* queue ordering assures pool readiness */ - ivgen_ctx->next_iv_ofs = SSI_IVPOOL_META_SIZE; + ivgen_ctx->next_iv_ofs = CC_IVPOOL_META_SIZE; return 0; } @@ -118,15 +118,15 @@ static int ssi_ivgen_generate_pool( * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata) +int cc_init_iv_sram(struct ssi_drvdata *drvdata) { - struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; + struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; unsigned int iv_seq_len = 0; int rc; /* Generate initial enc. key/iv */ - get_random_bytes(ivgen_ctx->pool_meta, SSI_IVPOOL_META_SIZE); + get_random_bytes(ivgen_ctx->pool_meta, CC_IVPOOL_META_SIZE); /* The first 32B reserved for the enc. Key/IV */ ivgen_ctx->ctr_key = ivgen_ctx->pool; @@ -135,14 +135,14 @@ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata) /* Copy initial enc. key and IV to SRAM at a single descriptor */ hw_desc_init(&iv_seq[iv_seq_len]); set_din_type(&iv_seq[iv_seq_len], DMA_DLLI, ivgen_ctx->pool_meta_dma, - SSI_IVPOOL_META_SIZE, NS_BIT); + CC_IVPOOL_META_SIZE, NS_BIT); set_dout_sram(&iv_seq[iv_seq_len], ivgen_ctx->pool, - SSI_IVPOOL_META_SIZE); + CC_IVPOOL_META_SIZE); set_flow_mode(&iv_seq[iv_seq_len], BYPASS); iv_seq_len++; /* Generate initial pool */ - rc = ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, &iv_seq_len); + rc = cc_gen_iv_pool(ivgen_ctx, iv_seq, &iv_seq_len); if (rc) return rc; @@ -155,17 +155,17 @@ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata) * * \param drvdata */ -void ssi_ivgen_fini(struct ssi_drvdata *drvdata) +void cc_ivgen_fini(struct ssi_drvdata *drvdata) { - struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; + struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct device *device = &drvdata->plat_dev->dev; if (!ivgen_ctx) return; if (ivgen_ctx->pool_meta) { - memset(ivgen_ctx->pool_meta, 0, SSI_IVPOOL_META_SIZE); - dma_free_coherent(device, SSI_IVPOOL_META_SIZE, + memset(ivgen_ctx->pool_meta, 0, CC_IVPOOL_META_SIZE); + dma_free_coherent(device, CC_IVPOOL_META_SIZE, ivgen_ctx->pool_meta, ivgen_ctx->pool_meta_dma); } @@ -184,9 +184,9 @@ void ssi_ivgen_fini(struct ssi_drvdata *drvdata) * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_init(struct ssi_drvdata *drvdata) +int cc_ivgen_init(struct ssi_drvdata *drvdata) { - struct ssi_ivgen_ctx *ivgen_ctx; + struct cc_ivgen_ctx *ivgen_ctx; struct device *device = &drvdata->plat_dev->dev; int rc; @@ -199,27 +199,27 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) ivgen_ctx = drvdata->ivgen_handle; /* Allocate pool's header for initial enc. key/IV */ - ivgen_ctx->pool_meta = dma_alloc_coherent(device, SSI_IVPOOL_META_SIZE, + ivgen_ctx->pool_meta = dma_alloc_coherent(device, CC_IVPOOL_META_SIZE, &ivgen_ctx->pool_meta_dma, GFP_KERNEL); if (!ivgen_ctx->pool_meta) { dev_err(device, "Not enough memory to allocate DMA of pool_meta (%u B)\n", - SSI_IVPOOL_META_SIZE); + CC_IVPOOL_META_SIZE); rc = -ENOMEM; goto out; } /* Allocate IV pool in SRAM */ - ivgen_ctx->pool = cc_sram_alloc(drvdata, SSI_IVPOOL_SIZE); + ivgen_ctx->pool = cc_sram_alloc(drvdata, CC_IVPOOL_SIZE); if (ivgen_ctx->pool == NULL_SRAM_ADDR) { dev_err(device, "SRAM pool exhausted\n"); rc = -ENOMEM; goto out; } - return ssi_ivgen_init_sram_pool(drvdata); + return cc_init_iv_sram(drvdata); out: - ssi_ivgen_fini(drvdata); + cc_ivgen_fini(drvdata); return rc; } @@ -236,7 +236,7 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_getiv( +int cc_get_iv( struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, @@ -244,7 +244,7 @@ int ssi_ivgen_getiv( struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { - struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; + struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; unsigned int idx = *iv_seq_len; struct device *dev = drvdata_to_dev(drvdata); unsigned int t; @@ -291,10 +291,10 @@ int ssi_ivgen_getiv( /* Update iv index */ ivgen_ctx->next_iv_ofs += iv_out_size; - if ((SSI_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) { + if ((CC_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) { dev_dbg(dev, "Pool exhausted, regenerating iv-pool\n"); /* pool is drained -regenerate it! */ - return ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, iv_seq_len); + return cc_gen_iv_pool(ivgen_ctx, iv_seq, iv_seq_len); } return 0; diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h index fd28309..fe3d919 100644 --- a/drivers/staging/ccree/ssi_ivgen.h +++ b/drivers/staging/ccree/ssi_ivgen.h @@ -29,14 +29,14 @@ * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_init(struct ssi_drvdata *drvdata); +int cc_ivgen_init(struct ssi_drvdata *drvdata); /*! * Free iv-pool and ivgen context. * * \param drvdata */ -void ssi_ivgen_fini(struct ssi_drvdata *drvdata); +void cc_ivgen_fini(struct ssi_drvdata *drvdata); /*! * Generates the initial pool in SRAM. @@ -46,7 +46,7 @@ void ssi_ivgen_fini(struct ssi_drvdata *drvdata); * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata); +int cc_init_iv_sram(struct ssi_drvdata *drvdata); /*! * Acquires 16 Bytes IV from the iv-pool @@ -61,7 +61,7 @@ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata); * * \return int Zero for success, negative value otherwise. */ -int ssi_ivgen_getiv( +int cc_get_iv( struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c index d1a6318..f0e3baf 100644 --- a/drivers/staging/ccree/ssi_pm.c +++ b/drivers/staging/ccree/ssi_pm.c @@ -81,7 +81,7 @@ int cc_pm_resume(struct device *dev) /* must be after the queue resuming as it uses the HW queue*/ cc_init_hash_sram(drvdata); - ssi_ivgen_init_sram_pool(drvdata); + cc_init_iv_sram(drvdata); return 0; } diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 91f5e2d..3d25b72 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -329,9 +329,10 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, ssi_req->ivgen_size); /* Acquire IV from pool */ - rc = ssi_ivgen_getiv(drvdata, ssi_req->ivgen_dma_addr, - ssi_req->ivgen_dma_addr_len, - ssi_req->ivgen_size, iv_seq, &iv_seq_len); + rc = cc_get_iv(drvdata, ssi_req->ivgen_dma_addr, + ssi_req->ivgen_dma_addr_len, + ssi_req->ivgen_size, + iv_seq, &iv_seq_len); if (rc) { dev_err(dev, "Failed to generate IV (rc=%d)\n", rc); From patchwork Tue Dec 12 14:53:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121536 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223830qgn; Tue, 12 Dec 2017 06:55:42 -0800 (PST) X-Google-Smtp-Source: ACJfBou9JE2TzX2grZ2+DURPn2YuVxCi8NKfZsuDvLZx/WmgdTR/IKB31150vTsPXMI5NDHl8Lcy X-Received: by 10.99.95.22 with SMTP id t22mr2235084pgb.195.1513090542062; Tue, 12 Dec 2017 06:55:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090542; cv=none; d=google.com; s=arc-20160816; b=PQnzJ5/rbnT0g/fveDtLjn08rcjyrom2OjJpkz3MG/K6SUmO/NDhXRlP2xojQ9zD4b cG3j0YpEuDlbMQs7LXbb+fhiUhD+V3XXmeBtUmGMjAIDIO1fVUy+8g1L6PPjeS/deARo W9X1jQ5sy/EJs6y3lMvB2QEypU2cst2KQGO/juahDs8sGZkeuatzYTrjPhDmS8rTQ17i ieW5ZVh2qUeB6kQ4HR6n+qFRmrR42lvLrWTimeOllk4qzs3hMDLXB873UEYD6tbZhrpS KwJnRwlBw3s2DeJM9OiGMyGond0wExYn2xfDcuuxuCAOx3aAhTj+jw8byBuBspAnVY6e 8utw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=QrSoR1DPguuFPFsHcr4Iwbm81CGLVMS4KS0TQGURofM=; b=R0nZ4HXUd5ACHnZ9rolYBcnDEnhWpsUHHftGfUhvY6RXQKGO2/OBgKyWgi7DHxLz3m wHI6Tl0BOs+w/euxYFNbFaJ4cpSqQ9sAwf8GS4r9meYMK5wEFTFSLmQh8kvfGp88Rm0h 4h6a8fqjWG4GJdYUMPC5wbBVXMASyops97WKsX6ZFr8ggFhVtQJP2Z9OmB+DnpQIm5o5 OTXzc7pgOD5LlTYdV2nTi+2luL1j2p+bh4G/QGO/Pz92F3A1dCOyy0m+Gv2cF4E1rGEN MrDw0OWD39HW7oTKCM2h73J6N9OfR+4ZhVdIE3GPYPZKLIsYpzJYCHYKt2+IhHu2YBaB IScg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Tue, 12 Dec 2017 06:55:29 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 15/24] staging: ccree: fix ivgen func def coding style Date: Tue, 12 Dec 2017 14:53:01 +0000 Message-Id: <1513090395-7938-16-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix ivgen functions definition indentation according to coding style guide lines for better code readability Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_ivgen.c | 16 +++++----------- drivers/staging/ccree/ssi_ivgen.h | 10 +++------- 2 files changed, 8 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index ad6cd97..c499361 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -57,10 +57,8 @@ struct cc_ivgen_ctx { * \param iv_seq IN/OUT array to the descriptors sequence * \param iv_seq_len IN/OUT pointer to the sequence length */ -static int cc_gen_iv_pool( - struct cc_ivgen_ctx *ivgen_ctx, - struct cc_hw_desc iv_seq[], - unsigned int *iv_seq_len) +static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx, + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { unsigned int idx = *iv_seq_len; @@ -236,13 +234,9 @@ int cc_ivgen_init(struct ssi_drvdata *drvdata) * * \return int Zero for success, negative value otherwise. */ -int cc_get_iv( - struct ssi_drvdata *drvdata, - dma_addr_t iv_out_dma[], - unsigned int iv_out_dma_len, - unsigned int iv_out_size, - struct cc_hw_desc iv_seq[], - unsigned int *iv_seq_len) +int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], + unsigned int iv_out_dma_len, unsigned int iv_out_size, + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; unsigned int idx = *iv_seq_len; diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h index fe3d919..bbd0245 100644 --- a/drivers/staging/ccree/ssi_ivgen.h +++ b/drivers/staging/ccree/ssi_ivgen.h @@ -61,12 +61,8 @@ int cc_init_iv_sram(struct ssi_drvdata *drvdata); * * \return int Zero for success, negative value otherwise. */ -int cc_get_iv( - struct ssi_drvdata *drvdata, - dma_addr_t iv_out_dma[], - unsigned int iv_out_dma_len, - unsigned int iv_out_size, - struct cc_hw_desc iv_seq[], - unsigned int *iv_seq_len); +int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], + unsigned int iv_out_dma_len, unsigned int iv_out_size, + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len); #endif /*__SSI_IVGEN_H__*/ From patchwork Tue Dec 12 14:53:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121537 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4223963qgn; Tue, 12 Dec 2017 06:55:49 -0800 (PST) X-Google-Smtp-Source: ACJfBovT7nV2JpudzH4PTIo2LBj/P56AiEQOoQzuIXKhyfdG41DwXgM83doWneVJDyv4eLVVyogq X-Received: by 10.84.173.1 with SMTP id o1mr2575295plb.135.1513090549866; Tue, 12 Dec 2017 06:55:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090549; cv=none; d=google.com; s=arc-20160816; b=0/hXdL4rTAL1RWNzrLoGoKHyQmmpr6pQon8cUSFu4x7v5ZoJhjXaP8gFAMn/s1T8gq lYhNXQqiDuYZ8FxJQ+4FgMuER7n36wCziLNEzhf6F0MnZaysceisBWap8ZeaE5iiPaq7 Trkpp7ZKN+s5mIHF/Wf/VZAb9D4iQLa50xPVthEft6UfKELJf8XyR9P6WViY+vDAzBm9 q99DGtMaHLXNFNYacV+ODGECJg6YLW21x2h22x9wxHQHSY/sTXYCrbc9C2xcD99itpzO w+sIHoRkErJGvBb2o+NqpCZXL+qLl8bHtinNSN/epOAPX3QoDhDcRaMQYyl0Ql/QTIBD DhZg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id a13si11713975pgd.155.2017.12.12.06.55.49; Tue, 12 Dec 2017 06:55:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752902AbdLLOzq (ORCPT + 11 others); Tue, 12 Dec 2017 09:55:46 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45174 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752883AbdLLOzl (ORCPT ); Tue, 12 Dec 2017 09:55:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E0BA61529; Tue, 12 Dec 2017 06:55:40 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 10C1A3F318; Tue, 12 Dec 2017 06:55:36 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 16/24] staging: ccree: drop unsupported MULTI2 mode code Date: Tue, 12 Dec 2017 14:53:02 +0000 Message-Id: <1513090395-7938-17-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove the code support for MULTI2 mode which is not supported by the current hardware. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_crypto_ctx.h | 17 ---- drivers/staging/ccree/cc_hw_queue_defs.h | 2 - drivers/staging/ccree/ssi_cipher.c | 167 ++++--------------------------- drivers/staging/ccree/ssi_driver.h | 1 - 4 files changed, 18 insertions(+), 169 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/cc_crypto_ctx.h b/drivers/staging/ccree/cc_crypto_ctx.h index 591f6fd..0e34d9a 100644 --- a/drivers/staging/ccree/cc_crypto_ctx.h +++ b/drivers/staging/ccree/cc_crypto_ctx.h @@ -82,15 +82,6 @@ #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX -#define CC_MULTI2_SYSTEM_KEY_SIZE 32 -#define CC_MULTI2_DATA_KEY_SIZE 8 -#define CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE \ - (CC_MULTI2_SYSTEM_KEY_SIZE + CC_MULTI2_DATA_KEY_SIZE) -#define CC_MULTI2_BLOCK_SIZE 8 -#define CC_MULTI2_IV_SIZE 8 -#define CC_MULTI2_MIN_NUM_ROUNDS 8 -#define CC_MULTI2_MAX_NUM_ROUNDS 128 - #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX enum drv_engine_type { @@ -168,14 +159,6 @@ enum drv_hash_hw_mode { DRV_HASH_HW_RESERVE32B = S32_MAX }; -enum drv_multi2_mode { - DRV_MULTI2_NULL = -1, - DRV_MULTI2_ECB = 0, - DRV_MULTI2_CBC = 1, - DRV_MULTI2_OFB = 2, - DRV_MULTI2_RESERVE32B = S32_MAX -}; - /* drv_crypto_key_type[1:0] is mapped to cipher_do[1:0] */ /* drv_crypto_key_type[2] is mapped to cipher_config2 */ enum drv_crypto_key_type { diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index c5aaa79..3ca548d 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -120,7 +120,6 @@ enum cc_flow_mode { AES_to_AES_to_HASH_and_DOUT = 13, AES_to_AES_to_HASH = 14, AES_to_HASH_and_AES = 15, - DIN_MULTI2_DOUT = 16, DIN_AES_AESMAC = 17, HASH_to_DOUT = 18, /* setup flows */ @@ -128,7 +127,6 @@ enum cc_flow_mode { S_DIN_to_AES2 = 33, S_DIN_to_DES = 34, S_DIN_to_RC4 = 35, - S_DIN_to_MULTI2 = 36, S_DIN_to_HASH = 37, S_AES_to_DOUT = 38, S_AES2_to_DOUT = 39, diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index 0b464d8..a158213 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -97,12 +97,6 @@ static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) if (size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE) return 0; break; -#if SSI_CC_HAS_MULTI2 - case S_DIN_to_MULTI2: - if (size == CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE) - return 0; - break; -#endif default: break; } @@ -143,20 +137,6 @@ static int validate_data_size(struct cc_cipher_ctx *ctx_p, if (IS_ALIGNED(size, DES_BLOCK_SIZE)) return 0; break; -#if SSI_CC_HAS_MULTI2 - case S_DIN_to_MULTI2: - switch (ctx_p->cipher_mode) { - case DRV_MULTI2_CBC: - if (IS_ALIGNED(size, CC_MULTI2_BLOCK_SIZE)) - return 0; - break; - case DRV_MULTI2_OFB: - return 0; - default: - break; - } - break; -#endif /*SSI_CC_HAS_MULTI2*/ default: break; } @@ -315,14 +295,6 @@ static int cc_cipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, /* STAT_PHASE_0: Init and sanity checks */ -#if SSI_CC_HAS_MULTI2 - /* last byte of key buffer is round number and should not be a part - * of key size - */ - if (ctx_p->flow_mode == S_DIN_to_MULTI2) - keylen -= 1; -#endif /*SSI_CC_HAS_MULTI2*/ - if (validate_keys_sizes(ctx_p, keylen)) { dev_err(dev, "Unsupported key size %d.\n", keylen); crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); @@ -393,38 +365,23 @@ static int cc_cipher_setkey(struct crypto_ablkcipher *atfm, const u8 *key, dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr, max_key_buf_size, DMA_TO_DEVICE); - if (ctx_p->flow_mode == S_DIN_to_MULTI2) { -#if SSI_CC_HAS_MULTI2 - memcpy(ctx_p->user.key, key, CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE); - ctx_p->key_round_number = - key[CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE]; - if (ctx_p->key_round_number < CC_MULTI2_MIN_NUM_ROUNDS || - ctx_p->key_round_number > CC_MULTI2_MAX_NUM_ROUNDS) { - crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); - dev_dbg(dev, "SSI_CC_HAS_MULTI2 einval"); - return -EINVAL; -#endif /*SSI_CC_HAS_MULTI2*/ - } else { - memcpy(ctx_p->user.key, key, keylen); - if (keylen == 24) - memset(ctx_p->user.key + 24, 0, - CC_AES_KEY_SIZE_MAX - 24); - - if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { - /* sha256 for key2 - use sw implementation */ - int key_len = keylen >> 1; - int err; - SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm); - - desc->tfm = ctx_p->shash_tfm; - - err = crypto_shash_digest(desc, ctx_p->user.key, - key_len, - ctx_p->user.key + key_len); - if (err) { - dev_err(dev, "Failed to hash ESSIV key.\n"); - return err; - } + memcpy(ctx_p->user.key, key, keylen); + if (keylen == 24) + memset(ctx_p->user.key + 24, 0, CC_AES_KEY_SIZE_MAX - 24); + + if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) { + /* sha256 for key2 - use sw implementation */ + int key_len = keylen >> 1; + int err; + SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm); + + desc->tfm = ctx_p->shash_tfm; + + err = crypto_shash_digest(desc, ctx_p->user.key, key_len, + ctx_p->user.key + key_len); + if (err) { + dev_err(dev, "Failed to hash ESSIV key.\n"); + return err; } } dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr, @@ -561,49 +518,6 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm, } } -#if SSI_CC_HAS_MULTI2 -static void cc_setup_multi2_desc(struct crypto_tfm *tfm, - struct blkcipher_req_ctx *req_ctx, - unsigned int ivsize, struct cc_hw_desc desc[], - unsigned int *seq_size) -{ - struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - - int direction = req_ctx->gen_ctx.op_type; - /* Load system key */ - hw_desc_init(&desc[*seq_size]); - set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); - set_cipher_config0(&desc[*seq_size], direction); - set_din_type(&desc[*seq_size], DMA_DLLI, ctx_p->user.key_dma_addr, - CC_MULTI2_SYSTEM_KEY_SIZE, NS_BIT); - set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); - (*seq_size)++; - - /* load data key */ - hw_desc_init(&desc[*seq_size]); - set_din_type(&desc[*seq_size], DMA_DLLI, - (ctx_p->user.key_dma_addr + CC_MULTI2_SYSTEM_KEY_SIZE), - CC_MULTI2_DATA_KEY_SIZE, NS_BIT); - set_multi2_num_rounds(&desc[*seq_size], ctx_p->key_round_number); - set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); - set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); - set_cipher_config0(&desc[*seq_size], direction); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0); - (*seq_size)++; - - /* Set state */ - hw_desc_init(&desc[*seq_size]); - set_din_type(&desc[*seq_size], DMA_DLLI, req_ctx->gen_ctx.iv_dma_addr, - ivsize, NS_BIT); - set_cipher_config0(&desc[*seq_size], direction); - set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); - set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); - set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); - (*seq_size)++; -} -#endif /*SSI_CC_HAS_MULTI2*/ - static void cc_setup_cipher_data(struct crypto_tfm *tfm, struct blkcipher_req_ctx *req_ctx, struct scatterlist *dst, @@ -622,11 +536,6 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, case S_DIN_to_DES: flow_mode = DIN_DES_DOUT; break; -#if SSI_CC_HAS_MULTI2 - case S_DIN_to_MULTI2: - flow_mode = DIN_MULTI2_DOUT; - break; -#endif /*SSI_CC_HAS_MULTI2*/ default: dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode); return; @@ -806,13 +715,7 @@ static int cc_cipher_process(struct ablkcipher_request *req, /* STAT_PHASE_2: Create sequence */ /* Setup processing */ -#if SSI_CC_HAS_MULTI2 - if (ctx_p->flow_mode == S_DIN_to_MULTI2) - cc_setup_multi2_desc(tfm, req_ctx, ivsize, desc, &seq_len); - else -#endif /*SSI_CC_HAS_MULTI2*/ - cc_setup_cipher_desc(tfm, req_ctx, ivsize, nbytes, desc, - &seq_len); + cc_setup_cipher_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len); /* Data processing */ cc_setup_cipher_data(tfm, req_ctx, dst, src, nbytes, req, desc, &seq_len); @@ -1177,40 +1080,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_ECB, .flow_mode = S_DIN_to_DES, }, -#if SSI_CC_HAS_MULTI2 - { - .name = "cbc(multi2)", - .driver_name = "cbc-multi2-dx", - .blocksize = CC_MULTI2_BLOCK_SIZE, - .type = CRYPTO_ALG_TYPE_ABLKCIPHER, - .template_ablkcipher = { - .setkey = cc_cipher_setkey, - .encrypt = cc_cipher_encrypt, - .decrypt = cc_cipher_decrypt, - .min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, - .max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, - .ivsize = CC_MULTI2_IV_SIZE, - }, - .cipher_mode = DRV_MULTI2_CBC, - .flow_mode = S_DIN_to_MULTI2, - }, - { - .name = "ofb(multi2)", - .driver_name = "ofb-multi2-dx", - .blocksize = 1, - .type = CRYPTO_ALG_TYPE_ABLKCIPHER, - .template_ablkcipher = { - .setkey = cc_cipher_setkey, - .encrypt = cc_cipher_encrypt, - .decrypt = cc_cipher_encrypt, - .min_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, - .max_keysize = CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE + 1, - .ivsize = CC_MULTI2_IV_SIZE, - }, - .cipher_mode = DRV_MULTI2_OFB, - .flow_mode = S_DIN_to_MULTI2, - }, -#endif /*SSI_CC_HAS_MULTI2*/ }; static diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index f92867b..a2de584 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -60,7 +60,6 @@ #define SSI_CC_HAS_AES_ESSIV 1 #define SSI_CC_HAS_AES_BITLOCKER 1 #define SSI_CC_HAS_AES_CTS 1 -#define SSI_CC_HAS_MULTI2 0 #define SSI_CC_HAS_CMAC 1 #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ From patchwork Tue Dec 12 14:53:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121538 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4224108qgn; Tue, 12 Dec 2017 06:55:56 -0800 (PST) X-Google-Smtp-Source: ACJfBot7zhD7YSyhG4pKa8GEPSDRDeaySRxydhrsXAbJ1ZtDySyjEcmarSxEEVUCO8NSIn0b3HSh X-Received: by 10.99.97.76 with SMTP id v73mr2228283pgb.378.1513090556453; Tue, 12 Dec 2017 06:55:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[209.132.180.67]) by mx.google.com with ESMTP id a13si11713975pgd.155.2017.12.12.06.55.56; Tue, 12 Dec 2017 06:55:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752598AbdLLOzx (ORCPT + 11 others); Tue, 12 Dec 2017 09:55:53 -0500 Received: from foss.arm.com ([217.140.101.70]:45188 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752883AbdLLOzt (ORCPT ); Tue, 12 Dec 2017 09:55:49 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 690751529; Tue, 12 Dec 2017 06:55:49 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D19803F318; Tue, 12 Dec 2017 06:55:45 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 17/24] staging: ccree: remove SSI_CC_HAS_ macros Date: Tue, 12 Dec 2017 14:53:03 +0000 Message-Id: <1513090395-7938-18-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove macro controlling build of various features. This needs to happen dynamically in registration time. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 33 --------------------------------- drivers/staging/ccree/ssi_buffer_mgr.c | 4 ---- drivers/staging/ccree/ssi_cipher.c | 8 -------- drivers/staging/ccree/ssi_driver.h | 8 -------- drivers/staging/ccree/ssi_hash.c | 5 ----- 5 files changed, 58 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 112fba3..ac9961c 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -662,7 +662,6 @@ cc_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) return rc; } -#if SSI_CC_HAS_AES_CCM static int cc_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) { @@ -676,7 +675,6 @@ static int cc_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, return cc_aead_setkey(tfm, key, keylen); } -#endif /*SSI_CC_HAS_AES_CCM*/ static int cc_aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize) @@ -696,7 +694,6 @@ static int cc_aead_setauthsize(struct crypto_aead *authenc, return 0; } -#if SSI_CC_HAS_AES_CCM static int cc_rfc4309_ccm_setauthsize(struct crypto_aead *authenc, unsigned int authsize) { @@ -730,7 +727,6 @@ static int cc_ccm_setauthsize(struct crypto_aead *authenc, return cc_aead_setauthsize(authenc, authsize); } -#endif /*SSI_CC_HAS_AES_CCM*/ static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode, struct cc_hw_desc desc[], unsigned int *seq_size) @@ -1374,7 +1370,6 @@ static int validate_data_size(struct cc_aead_ctx *ctx, return -EINVAL; } -#if SSI_CC_HAS_AES_CCM static unsigned int format_ccm_a0(u8 *pa0_buff, u32 header_size) { unsigned int len = 0; @@ -1623,9 +1618,6 @@ static void cc_proc_rfc4309_ccm(struct aead_request *req) req->iv = areq_ctx->ctr_iv; req->assoclen -= CCM_BLOCK_IV_SIZE; } -#endif /*SSI_CC_HAS_AES_CCM*/ - -#if SSI_CC_HAS_AES_GCM static void cc_set_ghash_desc(struct aead_request *req, struct cc_hw_desc desc[], unsigned int *seq_size) @@ -1952,8 +1944,6 @@ static void cc_proc_rfc4_gcm(struct aead_request *req) req->assoclen -= GCM_BLOCK_RFC4_IV_SIZE; } -#endif /*SSI_CC_HAS_AES_GCM*/ - static int cc_proc_aead(struct aead_request *req, enum drv_crypto_direction direct) { @@ -2020,7 +2010,6 @@ static int cc_proc_aead(struct aead_request *req, areq_ctx->hw_iv_size = crypto_aead_ivsize(tfm); } -#if SSI_CC_HAS_AES_CCM if (ctx->cipher_mode == DRV_CIPHER_CCM) { rc = config_ccm_adata(req); if (rc) { @@ -2031,11 +2020,7 @@ static int cc_proc_aead(struct aead_request *req, } else { areq_ctx->ccm_hdr_size = ccm_header_size_null; } -#else - areq_ctx->ccm_hdr_size = ccm_header_size_null; -#endif /*SSI_CC_HAS_AES_CCM*/ -#if SSI_CC_HAS_AES_GCM if (ctx->cipher_mode == DRV_CIPHER_GCTR) { rc = config_gcm_context(req); if (rc) { @@ -2044,7 +2029,6 @@ static int cc_proc_aead(struct aead_request *req, goto exit; } } -#endif /*SSI_CC_HAS_AES_GCM*/ rc = cc_map_aead_request(ctx->drvdata, req); if (rc) { @@ -2100,18 +2084,12 @@ static int cc_proc_aead(struct aead_request *req, case DRV_HASH_XCBC_MAC: cc_xcbc_authenc(req, desc, &seq_len); break; -#if (SSI_CC_HAS_AES_CCM || SSI_CC_HAS_AES_GCM) case DRV_HASH_NULL: -#if SSI_CC_HAS_AES_CCM if (ctx->cipher_mode == DRV_CIPHER_CCM) cc_ccm(req, desc, &seq_len); -#endif /*SSI_CC_HAS_AES_CCM*/ -#if SSI_CC_HAS_AES_GCM if (ctx->cipher_mode == DRV_CIPHER_GCTR) cc_gcm(req, desc, &seq_len); -#endif /*SSI_CC_HAS_AES_GCM*/ break; -#endif default: dev_err(dev, "Unsupported authenc (%d)\n", ctx->auth_mode); cc_unmap_aead_request(dev, req); @@ -2151,7 +2129,6 @@ static int cc_aead_encrypt(struct aead_request *req) return rc; } -#if SSI_CC_HAS_AES_CCM static int cc_rfc4309_ccm_encrypt(struct aead_request *req) { /* Very similar to cc_aead_encrypt() above. */ @@ -2180,7 +2157,6 @@ static int cc_rfc4309_ccm_encrypt(struct aead_request *req) out: return rc; } -#endif /* SSI_CC_HAS_AES_CCM */ static int cc_aead_decrypt(struct aead_request *req) { @@ -2201,7 +2177,6 @@ static int cc_aead_decrypt(struct aead_request *req) return rc; } -#if SSI_CC_HAS_AES_CCM static int cc_rfc4309_ccm_decrypt(struct aead_request *req) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -2229,9 +2204,6 @@ static int cc_rfc4309_ccm_decrypt(struct aead_request *req) out: return rc; } -#endif /* SSI_CC_HAS_AES_CCM */ - -#if SSI_CC_HAS_AES_GCM static int cc_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) @@ -2429,7 +2401,6 @@ static int cc_rfc4543_gcm_decrypt(struct aead_request *req) return rc; } -#endif /* SSI_CC_HAS_AES_GCM */ /* DX Block aead alg */ static struct ssi_alg_template aead_algs[] = { @@ -2585,7 +2556,6 @@ static struct ssi_alg_template aead_algs[] = { .flow_mode = S_DIN_to_AES, .auth_mode = DRV_HASH_XCBC_MAC, }, -#if SSI_CC_HAS_AES_CCM { .name = "ccm(aes)", .driver_name = "ccm-aes-dx", @@ -2624,8 +2594,6 @@ static struct ssi_alg_template aead_algs[] = { .flow_mode = S_DIN_to_AES, .auth_mode = DRV_HASH_NULL, }, -#endif /*SSI_CC_HAS_AES_CCM*/ -#if SSI_CC_HAS_AES_GCM { .name = "gcm(aes)", .driver_name = "gcm-aes-dx", @@ -2683,7 +2651,6 @@ static struct ssi_alg_template aead_algs[] = { .flow_mode = S_DIN_to_AES, .auth_mode = DRV_HASH_NULL, }, -#endif /*SSI_CC_HAS_AES_GCM*/ }; static struct ssi_crypto_alg *cc_create_aead_alg(struct ssi_alg_template *tmpl, diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 4ab76dc..c28ce7c 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -604,7 +604,6 @@ void cc_unmap_aead_request(struct device *dev, struct aead_request *req) MAX_MAC_SIZE, DMA_BIDIRECTIONAL); } -#if SSI_CC_HAS_AES_GCM if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) { if (areq_ctx->hkey_dma_addr) { dma_unmap_single(dev, areq_ctx->hkey_dma_addr, @@ -626,7 +625,6 @@ void cc_unmap_aead_request(struct device *dev, struct aead_request *req) AES_BLOCK_SIZE, DMA_TO_DEVICE); } } -#endif if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { if (areq_ctx->ccm_iv0_dma_addr) { @@ -1269,7 +1267,6 @@ int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) } } -#if SSI_CC_HAS_AES_GCM if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) { dma_addr = dma_map_single(dev, areq_ctx->hkey, AES_BLOCK_SIZE, DMA_BIDIRECTIONAL); @@ -1315,7 +1312,6 @@ int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) } areq_ctx->gcm_iv_inc2_dma_addr = dma_addr; } -#endif /*SSI_CC_HAS_AES_GCM*/ size_to_map = req->cryptlen + req->assoclen; if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index a158213..299e73a 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -783,7 +783,6 @@ static int cc_cipher_decrypt(struct ablkcipher_request *req) /* DX Block cipher alg */ static struct ssi_alg_template blkcipher_algs[] = { -#if SSI_CC_HAS_AES_XTS { .name = "xts(aes)", .driver_name = "xts-aes-dx", @@ -833,8 +832,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_XTS, .flow_mode = S_DIN_to_AES, }, -#endif /*SSI_CC_HAS_AES_XTS*/ -#if SSI_CC_HAS_AES_ESSIV { .name = "essiv(aes)", .driver_name = "essiv-aes-dx", @@ -883,8 +880,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_ESSIV, .flow_mode = S_DIN_to_AES, }, -#endif /*SSI_CC_HAS_AES_ESSIV*/ -#if SSI_CC_HAS_AES_BITLOCKER { .name = "bitlocker(aes)", .driver_name = "bitlocker-aes-dx", @@ -933,7 +928,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_BITLOCKER, .flow_mode = S_DIN_to_AES, }, -#endif /*SSI_CC_HAS_AES_BITLOCKER*/ { .name = "ecb(aes)", .driver_name = "ecb-aes-dx", @@ -982,7 +976,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_OFB, .flow_mode = S_DIN_to_AES, }, -#if SSI_CC_HAS_AES_CTS { .name = "cts1(cbc(aes))", .driver_name = "cts1-cbc-aes-dx", @@ -999,7 +992,6 @@ static struct ssi_alg_template blkcipher_algs[] = { .cipher_mode = DRV_CIPHER_CBC_CTS, .flow_mode = S_DIN_to_AES, }, -#endif { .name = "ctr(aes)", .driver_name = "ctr-aes-dx", diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index a2de584..c9fdb89 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -54,14 +54,6 @@ #define SSI_DEV_NAME_STR "cc715ree" #define CC_COHERENT_CACHE_PARAMS 0xEEE -#define SSI_CC_HAS_AES_CCM 1 -#define SSI_CC_HAS_AES_GCM 1 -#define SSI_CC_HAS_AES_XTS 1 -#define SSI_CC_HAS_AES_ESSIV 1 -#define SSI_CC_HAS_AES_BITLOCKER 1 -#define SSI_CC_HAS_AES_CTS 1 -#define SSI_CC_HAS_CMAC 1 - #define SSI_AXI_IRQ_MASK ((1 << DX_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ (1 << DX_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ (1 << DX_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \ diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 29c17f3..10c73ef 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -1190,7 +1190,6 @@ static int cc_xcbc_setkey(struct crypto_ahash *ahash, return rc; } -#if SSI_CC_HAS_CMAC static int cc_cmac_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { @@ -1230,7 +1229,6 @@ static int cc_cmac_setkey(struct crypto_ahash *ahash, return 0; } -#endif static void cc_free_ctx(struct cc_hash_ctx *ctx) { @@ -1937,7 +1935,6 @@ static struct cc_hash_template driver_hash[] = { .hw_mode = DRV_CIPHER_XCBC_MAC, .inter_digestsize = AES_BLOCK_SIZE, }, -#if SSI_CC_HAS_CMAC { .mac_name = "cmac(aes)", .mac_driver_name = "cmac-aes-dx", @@ -1960,8 +1957,6 @@ static struct cc_hash_template driver_hash[] = { .hw_mode = DRV_CIPHER_CMAC, .inter_digestsize = AES_BLOCK_SIZE, }, -#endif - }; static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template, From patchwork Tue Dec 12 14:53:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121545 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4226456qgn; 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Tue, 12 Dec 2017 06:56:16 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A6E5A3F318; Tue, 12 Dec 2017 06:56:11 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 20/24] staging: ccree: rename vars/structs/enums from ssi_ to cc_ Date: Tue, 12 Dec 2017 14:53:06 +0000 Message-Id: <1513090395-7938-21-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Unify naming convention by renaming all ssi_ vars/structs/enums and variables to cc_* Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_aead.c | 82 +++++++++---------- drivers/staging/ccree/ssi_aead.h | 14 ++-- drivers/staging/ccree/ssi_buffer_mgr.c | 30 +++---- drivers/staging/ccree/ssi_buffer_mgr.h | 22 +++--- drivers/staging/ccree/ssi_cipher.c | 72 ++++++++--------- drivers/staging/ccree/ssi_cipher.h | 6 +- drivers/staging/ccree/ssi_driver.c | 16 ++-- drivers/staging/ccree/ssi_driver.h | 30 +++---- drivers/staging/ccree/ssi_fips.c | 20 ++--- drivers/staging/ccree/ssi_fips.h | 16 ++-- drivers/staging/ccree/ssi_hash.c | 136 ++++++++++++++++---------------- drivers/staging/ccree/ssi_hash.h | 12 +-- drivers/staging/ccree/ssi_ivgen.c | 14 ++-- drivers/staging/ccree/ssi_ivgen.h | 8 +- drivers/staging/ccree/ssi_pm.c | 12 +-- drivers/staging/ccree/ssi_pm.h | 4 +- drivers/staging/ccree/ssi_request_mgr.c | 70 ++++++++-------- drivers/staging/ccree/ssi_request_mgr.h | 18 ++--- drivers/staging/ccree/ssi_sram_mgr.c | 12 +-- drivers/staging/ccree/ssi_sram_mgr.h | 14 ++-- drivers/staging/ccree/ssi_sysfs.c | 12 +-- drivers/staging/ccree/ssi_sysfs.h | 4 +- 22 files changed, 312 insertions(+), 312 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index d07b38d..73ae970 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -52,7 +52,7 @@ #define ICV_VERIF_OK 0x01 struct cc_aead_handle { - ssi_sram_addr_t sram_workspace_addr; + cc_sram_addr_t sram_workspace_addr; struct list_head aead_list; }; @@ -69,7 +69,7 @@ struct cc_xcbc_s { }; struct cc_aead_ctx { - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; u8 ctr_nonce[MAX_NONCE_SIZE]; /* used for ctr3686 iv and aes ccm */ u8 *enckey; dma_addr_t enckey_dma_addr; @@ -148,18 +148,18 @@ static int cc_aead_init(struct crypto_aead *tfm) { struct aead_alg *alg = crypto_aead_alg(tfm); struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); - struct ssi_crypto_alg *ssi_alg = - container_of(alg, struct ssi_crypto_alg, aead_alg); - struct device *dev = drvdata_to_dev(ssi_alg->drvdata); + struct cc_crypto_alg *cc_alg = + container_of(alg, struct cc_crypto_alg, aead_alg); + struct device *dev = drvdata_to_dev(cc_alg->drvdata); dev_dbg(dev, "Initializing context @%p for %s\n", ctx, crypto_tfm_alg_name(&tfm->base)); /* Initialize modes in instance */ - ctx->cipher_mode = ssi_alg->cipher_mode; - ctx->flow_mode = ssi_alg->flow_mode; - ctx->auth_mode = ssi_alg->auth_mode; - ctx->drvdata = ssi_alg->drvdata; + ctx->cipher_mode = cc_alg->cipher_mode; + ctx->flow_mode = cc_alg->flow_mode; + ctx->auth_mode = cc_alg->auth_mode; + ctx->drvdata = cc_alg->drvdata; crypto_aead_set_reqsize(tfm, sizeof(struct aead_req_ctx)); /* Allocate key buffer, cache line aligned */ @@ -226,11 +226,11 @@ static int cc_aead_init(struct crypto_aead *tfm) return -ENOMEM; } -static void cc_aead_complete(struct device *dev, void *ssi_req) +static void cc_aead_complete(struct device *dev, void *cc_req) { - struct aead_request *areq = (struct aead_request *)ssi_req; + struct aead_request *areq = (struct aead_request *)cc_req; struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); - struct crypto_aead *tfm = crypto_aead_reqtfm(ssi_req); + struct crypto_aead *tfm = crypto_aead_reqtfm(cc_req); struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); int err = 0; @@ -442,7 +442,7 @@ cc_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); u32 larval_addr = cc_larval_digest_addr(ctx->drvdata, ctx->auth_mode); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; unsigned int blocksize; unsigned int digestsize; unsigned int hashmode; @@ -546,7 +546,7 @@ cc_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, idx++; } - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 0); if (rc) dev_err(dev, "send_request() failed (rc=%d)\n", rc); @@ -561,7 +561,7 @@ cc_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) { struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct rtattr *rta = (struct rtattr *)key; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct crypto_authenc_key_param *param; struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ]; int seq_len = 0, rc = -EINVAL; @@ -645,7 +645,7 @@ cc_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) /* STAT_PHASE_3: Submit sequence to HW */ if (seq_len > 0) { /* For CCM there is no sequence to setup the key */ - rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 0); + rc = send_request(ctx->drvdata, &cc_req, desc, seq_len, 0); if (rc) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); goto setkey_error; @@ -734,7 +734,7 @@ static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode, struct crypto_aead *tfm = crypto_aead_reqtfm(areq); struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); - enum ssi_req_dma_buf_type assoc_dma_type = areq_ctx->assoc_buff_type; + enum cc_req_dma_buf_type assoc_dma_type = areq_ctx->assoc_buff_type; unsigned int idx = *seq_size; struct device *dev = drvdata_to_dev(ctx->drvdata); @@ -773,7 +773,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, unsigned int *seq_size, int direct) { struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); - enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; + enum cc_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; unsigned int idx = *seq_size; struct crypto_aead *tfm = crypto_aead_reqtfm(areq); struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); @@ -803,7 +803,7 @@ static void cc_proc_authen_desc(struct aead_request *areq, * assoc. + iv + data -compact in one table * if assoclen is ZERO only IV perform */ - ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr; + cc_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr; u32 mlli_nents = areq_ctx->assoc.mlli_nents; if (areq_ctx->is_single_pass) { @@ -838,7 +838,7 @@ static void cc_proc_cipher_desc(struct aead_request *areq, { unsigned int idx = *seq_size; struct aead_req_ctx *areq_ctx = aead_request_ctx(areq); - enum ssi_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; + enum cc_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type; struct crypto_aead *tfm = crypto_aead_reqtfm(areq); struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); @@ -1954,7 +1954,7 @@ static int cc_proc_aead(struct aead_request *req, struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct device *dev = drvdata_to_dev(ctx->drvdata); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; dev_dbg(dev, "%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n", ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Enc" : "Dec"), @@ -1972,8 +1972,8 @@ static int cc_proc_aead(struct aead_request *req, } /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_aead_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_aead_complete; + cc_req.user_arg = (void *)req; /* Setup request context */ areq_ctx->gen_ctx.op_type = direct; @@ -2040,34 +2040,34 @@ static int cc_proc_aead(struct aead_request *req, if (areq_ctx->backup_giv) { /* set the DMA mapped IV address*/ if (ctx->cipher_mode == DRV_CIPHER_CTR) { - ssi_req.ivgen_dma_addr[0] = + cc_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CTR_RFC3686_NONCE_SIZE; - ssi_req.ivgen_dma_addr_len = 1; + cc_req.ivgen_dma_addr_len = 1; } else if (ctx->cipher_mode == DRV_CIPHER_CCM) { /* In ccm, the IV needs to exist both inside B0 and * inside the counter.It is also copied to iv_dma_addr * for other reasons (like returning it to the user). * So, using 3 (identical) IV outputs. */ - ssi_req.ivgen_dma_addr[0] = + cc_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CCM_BLOCK_IV_OFFSET; - ssi_req.ivgen_dma_addr[1] = + cc_req.ivgen_dma_addr[1] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_B0_OFFSET + CCM_BLOCK_IV_OFFSET; - ssi_req.ivgen_dma_addr[2] = + cc_req.ivgen_dma_addr[2] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_CTR_COUNT_0_OFFSET + CCM_BLOCK_IV_OFFSET; - ssi_req.ivgen_dma_addr_len = 3; + cc_req.ivgen_dma_addr_len = 3; } else { - ssi_req.ivgen_dma_addr[0] = + cc_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr; - ssi_req.ivgen_dma_addr_len = 1; + cc_req.ivgen_dma_addr_len = 1; } /* set the IV size (8/16 B long)*/ - ssi_req.ivgen_size = crypto_aead_ivsize(tfm); + cc_req.ivgen_size = crypto_aead_ivsize(tfm); } /* STAT_PHASE_2: Create sequence */ @@ -2099,7 +2099,7 @@ static int cc_proc_aead(struct aead_request *req, /* STAT_PHASE_3: Lock HW and push sequence */ - rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, seq_len, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); @@ -2403,7 +2403,7 @@ static int cc_rfc4543_gcm_decrypt(struct aead_request *req) } /* DX Block aead alg */ -static struct ssi_alg_template aead_algs[] = { +static struct cc_alg_template aead_algs[] = { { .name = "authenc(hmac(sha1),cbc(aes))", .driver_name = "authenc-hmac-sha1-cbc-aes-dx", @@ -2653,10 +2653,10 @@ static struct ssi_alg_template aead_algs[] = { }, }; -static struct ssi_crypto_alg *cc_create_aead_alg(struct ssi_alg_template *tmpl, - struct device *dev) +static struct cc_crypto_alg *cc_create_aead_alg(struct cc_alg_template *tmpl, + struct device *dev) { - struct ssi_crypto_alg *t_alg; + struct cc_crypto_alg *t_alg; struct aead_alg *alg; t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); @@ -2687,9 +2687,9 @@ static struct ssi_crypto_alg *cc_create_aead_alg(struct ssi_alg_template *tmpl, return t_alg; } -int cc_aead_free(struct ssi_drvdata *drvdata) +int cc_aead_free(struct cc_drvdata *drvdata) { - struct ssi_crypto_alg *t_alg, *n; + struct cc_crypto_alg *t_alg, *n; struct cc_aead_handle *aead_handle = (struct cc_aead_handle *)drvdata->aead_handle; @@ -2708,10 +2708,10 @@ int cc_aead_free(struct ssi_drvdata *drvdata) return 0; } -int cc_aead_alloc(struct ssi_drvdata *drvdata) +int cc_aead_alloc(struct cc_drvdata *drvdata) { struct cc_aead_handle *aead_handle; - struct ssi_crypto_alg *t_alg; + struct cc_crypto_alg *t_alg; int rc = -ENOMEM; int alg; struct device *dev = drvdata_to_dev(drvdata); diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h index e41040e..2507be1 100644 --- a/drivers/staging/ccree/ssi_aead.h +++ b/drivers/staging/ccree/ssi_aead.h @@ -96,15 +96,15 @@ struct aead_req_ctx { u8 *icv_virt_addr; /* Virt. address of ICV */ struct async_gen_req_ctx gen_ctx; - struct ssi_mlli assoc; - struct ssi_mlli src; - struct ssi_mlli dst; + struct cc_mlli assoc; + struct cc_mlli src; + struct cc_mlli dst; struct scatterlist *src_sgl; struct scatterlist *dst_sgl; unsigned int src_offset; unsigned int dst_offset; - enum ssi_req_dma_buf_type assoc_buff_type; - enum ssi_req_dma_buf_type data_buff_type; + enum cc_req_dma_buf_type assoc_buff_type; + enum cc_req_dma_buf_type data_buff_type; struct mlli_params mlli_params; unsigned int cryptlen; struct scatterlist ccm_adata_sg; @@ -116,7 +116,7 @@ struct aead_req_ctx { bool plaintext_authenticate_only; //for gcm_rfc4543 }; -int cc_aead_alloc(struct ssi_drvdata *drvdata); -int cc_aead_free(struct ssi_drvdata *drvdata); +int cc_aead_alloc(struct cc_drvdata *drvdata); +int cc_aead_free(struct cc_drvdata *drvdata); #endif /*__CC_AEAD_H__*/ diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index ee5c086..8649bcb 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -58,7 +58,7 @@ struct buffer_array { u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI]; }; -static inline char *cc_dma_buf_type(enum ssi_req_dma_buf_type type) +static inline char *cc_dma_buf_type(enum cc_req_dma_buf_type type) { switch (type) { case CC_DMA_BUF_NULL: @@ -80,7 +80,7 @@ static inline char *cc_dma_buf_type(enum ssi_req_dma_buf_type type) * @dir: [IN] copy from/to sgl */ static void cc_copy_mac(struct device *dev, struct aead_request *req, - enum ssi_sg_cpy_direct dir) + enum cc_sg_cpy_direct dir) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -157,7 +157,7 @@ void cc_zero_sgl(struct scatterlist *sgl, u32 data_len) * @direct: */ void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg, - u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct) + u32 to_skip, u32 end, enum cc_sg_cpy_direct direct) { u32 nents, lbytes; @@ -496,7 +496,7 @@ void cc_unmap_blkcipher_request(struct device *dev, void *ctx, } } -int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_blkcipher_request(struct cc_drvdata *drvdata, void *ctx, unsigned int ivsize, unsigned int nbytes, void *info, struct scatterlist *src, struct scatterlist *dst) @@ -594,7 +594,7 @@ void cc_unmap_aead_request(struct device *dev, struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); unsigned int hw_iv_size = areq_ctx->hw_iv_size; struct crypto_aead *tfm = crypto_aead_reqtfm(req); - struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + struct cc_drvdata *drvdata = dev_get_drvdata(dev); u32 dummy; bool chained; u32 size_to_unmap = 0; @@ -734,7 +734,7 @@ static int cc_get_aead_icv_nents(struct device *dev, struct scatterlist *sgl, return nents; } -static int cc_aead_chain_iv(struct ssi_drvdata *drvdata, +static int cc_aead_chain_iv(struct cc_drvdata *drvdata, struct aead_request *req, struct buffer_array *sg_data, bool is_last, bool do_chain) @@ -778,7 +778,7 @@ static int cc_aead_chain_iv(struct ssi_drvdata *drvdata, return rc; } -static int cc_aead_chain_assoc(struct ssi_drvdata *drvdata, +static int cc_aead_chain_assoc(struct cc_drvdata *drvdata, struct aead_request *req, struct buffer_array *sg_data, bool is_last, bool do_chain) @@ -898,7 +898,7 @@ static void cc_prepare_aead_data_dlli(struct aead_request *req, } } -static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, +static int cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata, struct aead_request *req, struct buffer_array *sg_data, u32 *src_last_bytes, u32 *dst_last_bytes, @@ -1030,7 +1030,7 @@ static int cc_prepare_aead_data_mlli(struct ssi_drvdata *drvdata, return rc; } -static int cc_aead_chain_data(struct ssi_drvdata *drvdata, +static int cc_aead_chain_data(struct cc_drvdata *drvdata, struct aead_request *req, struct buffer_array *sg_data, bool is_last_table, bool do_chain) @@ -1150,7 +1150,7 @@ static int cc_aead_chain_data(struct ssi_drvdata *drvdata, return rc; } -static void cc_update_aead_mlli_nents(struct ssi_drvdata *drvdata, +static void cc_update_aead_mlli_nents(struct cc_drvdata *drvdata, struct aead_request *req) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); @@ -1201,7 +1201,7 @@ static void cc_update_aead_mlli_nents(struct ssi_drvdata *drvdata, } } -int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) +int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct mlli_params *mlli_params = &areq_ctx->mlli_params; @@ -1400,7 +1400,7 @@ int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req) return rc; } -int cc_map_hash_request_final(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, bool do_update) { @@ -1481,7 +1481,7 @@ int cc_map_hash_request_final(struct ssi_drvdata *drvdata, void *ctx, return -ENOMEM; } -int cc_map_hash_request_update(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, unsigned int block_size) { @@ -1639,7 +1639,7 @@ void cc_unmap_hash_request(struct device *dev, void *ctx, } } -int cc_buffer_mgr_init(struct ssi_drvdata *drvdata) +int cc_buffer_mgr_init(struct cc_drvdata *drvdata) { struct buff_mgr_handle *buff_mgr_handle; struct device *dev = drvdata_to_dev(drvdata); @@ -1666,7 +1666,7 @@ int cc_buffer_mgr_init(struct ssi_drvdata *drvdata) return -ENOMEM; } -int cc_buffer_mgr_fini(struct ssi_drvdata *drvdata) +int cc_buffer_mgr_fini(struct cc_drvdata *drvdata) { struct buff_mgr_handle *buff_mgr_handle = drvdata->buff_mgr_handle; diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h index 77744a6..da43354 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.h +++ b/drivers/staging/ccree/ssi_buffer_mgr.h @@ -26,19 +26,19 @@ #include "ssi_config.h" #include "ssi_driver.h" -enum ssi_req_dma_buf_type { +enum cc_req_dma_buf_type { CC_DMA_BUF_NULL = 0, CC_DMA_BUF_DLLI, CC_DMA_BUF_MLLI }; -enum ssi_sg_cpy_direct { +enum cc_sg_cpy_direct { CC_SG_TO_BUF = 0, CC_SG_FROM_BUF = 1 }; -struct ssi_mlli { - ssi_sram_addr_t sram_addr; +struct cc_mlli { + cc_sram_addr_t sram_addr; unsigned int nents; //sg nents unsigned int mlli_nents; //mlli nents might be different than the above }; @@ -50,11 +50,11 @@ struct mlli_params { u32 mlli_len; }; -int cc_buffer_mgr_init(struct ssi_drvdata *drvdata); +int cc_buffer_mgr_init(struct cc_drvdata *drvdata); -int cc_buffer_mgr_fini(struct ssi_drvdata *drvdata); +int cc_buffer_mgr_fini(struct cc_drvdata *drvdata); -int cc_map_blkcipher_request(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_blkcipher_request(struct cc_drvdata *drvdata, void *ctx, unsigned int ivsize, unsigned int nbytes, void *info, struct scatterlist *src, struct scatterlist *dst); @@ -64,15 +64,15 @@ void cc_unmap_blkcipher_request(struct device *dev, void *ctx, struct scatterlist *src, struct scatterlist *dst); -int cc_map_aead_request(struct ssi_drvdata *drvdata, struct aead_request *req); +int cc_map_aead_request(struct cc_drvdata *drvdata, struct aead_request *req); void cc_unmap_aead_request(struct device *dev, struct aead_request *req); -int cc_map_hash_request_final(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, bool do_update); -int cc_map_hash_request_update(struct ssi_drvdata *drvdata, void *ctx, +int cc_map_hash_request_update(struct cc_drvdata *drvdata, void *ctx, struct scatterlist *src, unsigned int nbytes, unsigned int block_size); @@ -80,7 +80,7 @@ void cc_unmap_hash_request(struct device *dev, void *ctx, struct scatterlist *src, bool do_revert); void cc_copy_sg_portion(struct device *dev, u8 *dest, struct scatterlist *sg, - u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct); + u32 to_skip, u32 end, enum cc_sg_cpy_direct direct); void cc_zero_sgl(struct scatterlist *sgl, u32 data_len); diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index c437a79..791fe75 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -55,7 +55,7 @@ struct cc_hw_key_info { }; struct cc_cipher_ctx { - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; int keylen; int key_round_number; int cipher_mode; @@ -67,7 +67,7 @@ struct cc_cipher_ctx { struct crypto_shash *shash_tfm; }; -static void cc_cipher_complete(struct device *dev, void *ssi_req); +static void cc_cipher_complete(struct device *dev, void *cc_req); static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size) { @@ -145,17 +145,17 @@ static int validate_data_size(struct cc_cipher_ctx *ctx_p, static unsigned int get_max_keysize(struct crypto_tfm *tfm) { - struct ssi_crypto_alg *ssi_alg = - container_of(tfm->__crt_alg, struct ssi_crypto_alg, + struct cc_crypto_alg *cc_alg = + container_of(tfm->__crt_alg, struct cc_crypto_alg, crypto_alg); - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == + if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_ABLKCIPHER) - return ssi_alg->crypto_alg.cra_ablkcipher.max_keysize; + return cc_alg->crypto_alg.cra_ablkcipher.max_keysize; - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == + if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER) - return ssi_alg->crypto_alg.cra_blkcipher.max_keysize; + return cc_alg->crypto_alg.cra_blkcipher.max_keysize; return 0; } @@ -164,9 +164,9 @@ static int cc_cipher_init(struct crypto_tfm *tfm) { struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct crypto_alg *alg = tfm->__crt_alg; - struct ssi_crypto_alg *ssi_alg = - container_of(alg, struct ssi_crypto_alg, crypto_alg); - struct device *dev = drvdata_to_dev(ssi_alg->drvdata); + struct cc_crypto_alg *cc_alg = + container_of(alg, struct cc_crypto_alg, crypto_alg); + struct device *dev = drvdata_to_dev(cc_alg->drvdata); int rc = 0; unsigned int max_key_buf_size = get_max_keysize(tfm); struct ablkcipher_tfm *ablktfm = &tfm->crt_ablkcipher; @@ -176,9 +176,9 @@ static int cc_cipher_init(struct crypto_tfm *tfm) ablktfm->reqsize = sizeof(struct blkcipher_req_ctx); - ctx_p->cipher_mode = ssi_alg->cipher_mode; - ctx_p->flow_mode = ssi_alg->flow_mode; - ctx_p->drvdata = ssi_alg->drvdata; + ctx_p->cipher_mode = cc_alg->cipher_mode; + ctx_p->flow_mode = cc_alg->flow_mode; + ctx_p->drvdata = cc_alg->drvdata; /* Allocate key buffer, cache line aligned */ ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA); @@ -408,14 +408,14 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm, dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr; unsigned int du_size = nbytes; - struct ssi_crypto_alg *ssi_alg = - container_of(tfm->__crt_alg, struct ssi_crypto_alg, + struct cc_crypto_alg *cc_alg = + container_of(tfm->__crt_alg, struct cc_crypto_alg, crypto_alg); - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == + if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == CRYPTO_ALG_BULK_DU_512) du_size = 512; - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == + if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) == CRYPTO_ALG_BULK_DU_4096) du_size = 4096; @@ -604,9 +604,9 @@ static void cc_setup_cipher_data(struct crypto_tfm *tfm, } } -static void cc_cipher_complete(struct device *dev, void *ssi_req) +static void cc_cipher_complete(struct device *dev, void *cc_req) { - struct ablkcipher_request *areq = (struct ablkcipher_request *)ssi_req; + struct ablkcipher_request *areq = (struct ablkcipher_request *)cc_req; struct scatterlist *dst = areq->dst; struct scatterlist *src = areq->src; struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(areq); @@ -651,7 +651,7 @@ static int cc_cipher_process(struct ablkcipher_request *req, struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = drvdata_to_dev(ctx_p->drvdata); struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; int rc, seq_len = 0, cts_restore_flag = 0; dev_dbg(dev, "%s req=%p info=%p nbytes=%d\n", @@ -691,11 +691,11 @@ static int cc_cipher_process(struct ablkcipher_request *req, } /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_cipher_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_cipher_complete; + cc_req.user_arg = (void *)req; #ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = (direction == DRV_CRYPTO_DIRECTION_DECRYPT) ? + cc_req.op_type = (direction == DRV_CRYPTO_DIRECTION_DECRYPT) ? STAT_OP_TYPE_DECODE : STAT_OP_TYPE_ENCODE; #endif @@ -722,15 +722,15 @@ static int cc_cipher_process(struct ablkcipher_request *req, /* do we need to generate IV? */ if (req_ctx->is_giv) { - ssi_req.ivgen_dma_addr[0] = req_ctx->gen_ctx.iv_dma_addr; - ssi_req.ivgen_dma_addr_len = 1; + cc_req.ivgen_dma_addr[0] = req_ctx->gen_ctx.iv_dma_addr; + cc_req.ivgen_dma_addr_len = 1; /* set the IV size (8/16 B long)*/ - ssi_req.ivgen_size = ivsize; + cc_req.ivgen_size = ivsize; } /* STAT_PHASE_3: Lock HW and push sequence */ - rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, 1); + rc = send_request(ctx_p->drvdata, &cc_req, desc, seq_len, 1); if (rc != -EINPROGRESS) { /* Failed to send the request or request completed * synchronously @@ -782,7 +782,7 @@ static int cc_cipher_decrypt(struct ablkcipher_request *req) } /* DX Block cipher alg */ -static struct ssi_alg_template blkcipher_algs[] = { +static struct cc_alg_template blkcipher_algs[] = { { .name = "xts(aes)", .driver_name = "xts-aes-dx", @@ -1075,10 +1075,10 @@ static struct ssi_alg_template blkcipher_algs[] = { }; static -struct ssi_crypto_alg *cc_cipher_create_alg(struct ssi_alg_template *template, - struct device *dev) +struct cc_crypto_alg *cc_cipher_create_alg(struct cc_alg_template *template, + struct device *dev) { - struct ssi_crypto_alg *t_alg; + struct cc_crypto_alg *t_alg; struct crypto_alg *alg; t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL); @@ -1109,9 +1109,9 @@ struct ssi_crypto_alg *cc_cipher_create_alg(struct ssi_alg_template *template, return t_alg; } -int cc_cipher_free(struct ssi_drvdata *drvdata) +int cc_cipher_free(struct cc_drvdata *drvdata) { - struct ssi_crypto_alg *t_alg, *n; + struct cc_crypto_alg *t_alg, *n; struct cc_cipher_handle *blkcipher_handle = drvdata->blkcipher_handle; if (blkcipher_handle) { @@ -1129,10 +1129,10 @@ int cc_cipher_free(struct ssi_drvdata *drvdata) return 0; } -int cc_cipher_alloc(struct ssi_drvdata *drvdata) +int cc_cipher_alloc(struct cc_drvdata *drvdata) { struct cc_cipher_handle *ablkcipher_handle; - struct ssi_crypto_alg *t_alg; + struct cc_crypto_alg *t_alg; struct device *dev = drvdata_to_dev(drvdata); int rc = -ENOMEM; int alg; diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index 977b543..5d94cd3 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -40,7 +40,7 @@ struct blkcipher_req_ctx { struct async_gen_req_ctx gen_ctx; - enum ssi_req_dma_buf_type dma_buf_type; + enum cc_req_dma_buf_type dma_buf_type; u32 in_nents; u32 in_mlli_nents; u32 out_nents; @@ -51,9 +51,9 @@ struct blkcipher_req_ctx { struct mlli_params mlli_params; }; -int cc_cipher_alloc(struct ssi_drvdata *drvdata); +int cc_cipher_alloc(struct cc_drvdata *drvdata); -int cc_cipher_free(struct ssi_drvdata *drvdata); +int cc_cipher_free(struct cc_drvdata *drvdata); #ifndef CRYPTO_ALG_BULK_MASK diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index 078d146..3f02ceb 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -89,7 +89,7 @@ void dump_byte_array(const char *name, const u8 *buf, size_t len) static irqreturn_t cc_isr(int irq, void *dev_id) { - struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_id; + struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id; struct device *dev = drvdata_to_dev(drvdata); u32 irr; u32 imr; @@ -150,7 +150,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id) return IRQ_HANDLED; } -int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) +int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe) { unsigned int val, cache_params; struct device *dev = drvdata_to_dev(drvdata); @@ -202,7 +202,7 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) static int init_cc_resources(struct platform_device *plat_dev) { struct resource *req_mem_cc_regs = NULL; - struct ssi_drvdata *new_drvdata; + struct cc_drvdata *new_drvdata; struct device *dev = &plat_dev->dev; struct device_node *np = dev->of_node; u32 signature_val; @@ -405,7 +405,7 @@ static int init_cc_resources(struct platform_device *plat_dev) return rc; } -void fini_cc_regs(struct ssi_drvdata *drvdata) +void fini_cc_regs(struct cc_drvdata *drvdata) { /* Mask all interrupts */ cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF); @@ -413,8 +413,8 @@ void fini_cc_regs(struct ssi_drvdata *drvdata) static void cleanup_cc_resources(struct platform_device *plat_dev) { - struct ssi_drvdata *drvdata = - (struct ssi_drvdata *)platform_get_drvdata(plat_dev); + struct cc_drvdata *drvdata = + (struct cc_drvdata *)platform_get_drvdata(plat_dev); cc_aead_free(drvdata); cc_hash_free(drvdata); @@ -432,7 +432,7 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) cc_clk_off(drvdata); } -int cc_clk_on(struct ssi_drvdata *drvdata) +int cc_clk_on(struct cc_drvdata *drvdata) { struct clk *clk = drvdata->clk; int rc; @@ -448,7 +448,7 @@ int cc_clk_on(struct ssi_drvdata *drvdata) return 0; } -void cc_clk_off(struct ssi_drvdata *drvdata) +void cc_clk_off(struct cc_drvdata *drvdata) { struct clk *clk = drvdata->clk; diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index 4d94a06..35e1b72 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -89,7 +89,7 @@ */ #define CC_MAX_IVGEN_DMA_ADDRESSES 3 -struct ssi_crypto_req { +struct cc_crypto_req { void (*user_cb)(struct device *dev, void *req); void *user_arg; dma_addr_t ivgen_dma_addr[CC_MAX_IVGEN_DMA_ADDRESSES]; @@ -105,20 +105,20 @@ struct ssi_crypto_req { }; /** - * struct ssi_drvdata - driver private data context + * struct cc_drvdata - driver private data context * @cc_base: virt address of the CC registers * @irq: device IRQ number * @irq_mask: Interrupt mask shadow (1 for masked interrupts) * @fw_ver: SeP loaded firmware version */ -struct ssi_drvdata { +struct cc_drvdata { void __iomem *cc_base; int irq; u32 irq_mask; u32 fw_ver; struct completion hw_queue_avail; /* wait for HW queue availability */ struct platform_device *plat_dev; - ssi_sram_addr_t mlli_sram_addr; + cc_sram_addr_t mlli_sram_addr; void *buff_mgr_handle; void *hash_handle; void *aead_handle; @@ -131,17 +131,17 @@ struct ssi_drvdata { bool coherent; }; -struct ssi_crypto_alg { +struct cc_crypto_alg { struct list_head entry; int cipher_mode; int flow_mode; /* Note: currently, refers to the cipher mode only. */ int auth_mode; - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; struct crypto_alg crypto_alg; struct aead_alg aead_alg; }; -struct ssi_alg_template { +struct cc_alg_template { char name[CRYPTO_MAX_ALG_NAME]; char driver_name[CRYPTO_MAX_ALG_NAME]; unsigned int blocksize; @@ -156,7 +156,7 @@ struct ssi_alg_template { int cipher_mode; int flow_mode; /* Note: currently, refers to the cipher mode only. */ int auth_mode; - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; }; struct async_gen_req_ctx { @@ -164,7 +164,7 @@ struct async_gen_req_ctx { enum drv_crypto_direction op_type; }; -static inline struct device *drvdata_to_dev(struct ssi_drvdata *drvdata) +static inline struct device *drvdata_to_dev(struct cc_drvdata *drvdata) { return &drvdata->plat_dev->dev; } @@ -177,17 +177,17 @@ static inline void dump_byte_array(const char *name, const u8 *the_array, unsigned long size) {}; #endif -int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); -void fini_cc_regs(struct ssi_drvdata *drvdata); -int cc_clk_on(struct ssi_drvdata *drvdata); -void cc_clk_off(struct ssi_drvdata *drvdata); +int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe); +void fini_cc_regs(struct cc_drvdata *drvdata); +int cc_clk_on(struct cc_drvdata *drvdata); +void cc_clk_off(struct cc_drvdata *drvdata); -static inline void cc_iowrite(struct ssi_drvdata *drvdata, u32 reg, u32 val) +static inline void cc_iowrite(struct cc_drvdata *drvdata, u32 reg, u32 val) { iowrite32(val, (drvdata->cc_base + reg)); } -static inline u32 cc_ioread(struct ssi_drvdata *drvdata, u32 reg) +static inline u32 cc_ioread(struct cc_drvdata *drvdata, u32 reg) { return ioread32(drvdata->cc_base + reg); } diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c index 273b414..036215f 100644 --- a/drivers/staging/ccree/ssi_fips.c +++ b/drivers/staging/ccree/ssi_fips.c @@ -23,14 +23,14 @@ static void fips_dsr(unsigned long devarg); -struct ssi_fips_handle { +struct cc_fips_handle { struct tasklet_struct tasklet; }; /* The function called once at driver entry point to check * whether TEE FIPS error occurred. */ -static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata) +static bool cc_get_tee_fips_status(struct cc_drvdata *drvdata) { u32 reg; @@ -42,7 +42,7 @@ static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata) * This function should push the FIPS REE library status towards the TEE library * by writing the error state to HOST_GPR0 register. */ -void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status) +void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool status) { int val = CC_FIPS_SYNC_REE_STATUS; @@ -51,9 +51,9 @@ void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status) cc_iowrite(drvdata, CC_REG(HOST_GPR0), val); } -void ssi_fips_fini(struct ssi_drvdata *drvdata) +void ssi_fips_fini(struct cc_drvdata *drvdata) { - struct ssi_fips_handle *fips_h = drvdata->fips_handle; + struct cc_fips_handle *fips_h = drvdata->fips_handle; if (!fips_h) return; /* Not allocated */ @@ -65,9 +65,9 @@ void ssi_fips_fini(struct ssi_drvdata *drvdata) drvdata->fips_handle = NULL; } -void fips_handler(struct ssi_drvdata *drvdata) +void fips_handler(struct cc_drvdata *drvdata) { - struct ssi_fips_handle *fips_handle_ptr = + struct cc_fips_handle *fips_handle_ptr = drvdata->fips_handle; tasklet_schedule(&fips_handle_ptr->tasklet); @@ -84,7 +84,7 @@ static inline void tee_fips_error(struct device *dev) /* Deferred service handler, run as interrupt-fired tasklet */ static void fips_dsr(unsigned long devarg) { - struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; + struct cc_drvdata *drvdata = (struct cc_drvdata *)devarg; struct device *dev = drvdata_to_dev(drvdata); u32 irq, state, val; @@ -105,9 +105,9 @@ static void fips_dsr(unsigned long devarg) } /* The function called once at driver entry point .*/ -int ssi_fips_init(struct ssi_drvdata *p_drvdata) +int ssi_fips_init(struct cc_drvdata *p_drvdata) { - struct ssi_fips_handle *fips_h; + struct cc_fips_handle *fips_h; struct device *dev = drvdata_to_dev(p_drvdata); fips_h = kzalloc(sizeof(*fips_h), GFP_KERNEL); diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h index 1889c74..5eed9f6 100644 --- a/drivers/staging/ccree/ssi_fips.h +++ b/drivers/staging/ccree/ssi_fips.h @@ -27,22 +27,22 @@ enum cc_fips_status { CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX }; -int ssi_fips_init(struct ssi_drvdata *p_drvdata); -void ssi_fips_fini(struct ssi_drvdata *drvdata); -void fips_handler(struct ssi_drvdata *drvdata); -void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool ok); +int ssi_fips_init(struct cc_drvdata *p_drvdata); +void ssi_fips_fini(struct cc_drvdata *drvdata); +void fips_handler(struct cc_drvdata *drvdata); +void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool ok); #else /* CONFIG_CRYPTO_FIPS */ -static inline int ssi_fips_init(struct ssi_drvdata *p_drvdata) +static inline int ssi_fips_init(struct cc_drvdata *p_drvdata) { return 0; } -static inline void ssi_fips_fini(struct ssi_drvdata *drvdata) {} -static inline void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, +static inline void ssi_fips_fini(struct cc_drvdata *drvdata) {} +static inline void cc_set_ree_fips_status(struct cc_drvdata *drvdata, bool ok) {} -static inline void fips_handler(struct ssi_drvdata *drvdata) {} +static inline void fips_handler(struct cc_drvdata *drvdata) {} #endif /* CONFIG_CRYPTO_FIPS */ diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index 5a041bb..e5e71c2 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -35,8 +35,8 @@ #define CC_MAX_OPAD_KEYS_SIZE CC_MAX_HASH_BLCK_SIZE struct cc_hash_handle { - ssi_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/ - ssi_sram_addr_t larval_digest_sram_addr; /* const value in SRAM */ + cc_sram_addr_t digest_len_sram_addr; /* const value in SRAM*/ + cc_sram_addr_t larval_digest_sram_addr; /* const value in SRAM */ struct list_head hash_list; struct completion init_comp; }; @@ -75,7 +75,7 @@ struct cc_hash_alg { int hash_mode; int hw_mode; int inter_digestsize; - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; struct ahash_alg ahash_alg; }; @@ -86,7 +86,7 @@ struct hash_key_req_ctx { /* hash per-session context */ struct cc_hash_ctx { - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; /* holds the origin digest; the digest after "setkey" if HMAC,* * the initial digest if HASH. */ @@ -141,9 +141,9 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state, struct cc_hash_ctx *ctx) { bool is_hmac = ctx->is_hmac; - ssi_sram_addr_t larval_digest_addr = + cc_sram_addr_t larval_digest_addr = cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc; int rc = -ENOMEM; @@ -244,7 +244,7 @@ static int cc_map_req(struct device *dev, struct ahash_req_ctx *state, ctx->inter_digestsize, NS_BIT, 0); set_flow_mode(&desc, BYPASS); - rc = send_request(ctx->drvdata, &ssi_req, &desc, 1, 0); + rc = send_request(ctx->drvdata, &cc_req, &desc, 1, 0); if (rc) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); goto fail4; @@ -373,9 +373,9 @@ static void cc_unmap_result(struct device *dev, struct ahash_req_ctx *state, state->digest_result_dma_addr = 0; } -static void cc_update_complete(struct device *dev, void *ssi_req) +static void cc_update_complete(struct device *dev, void *cc_req) { - struct ahash_request *req = (struct ahash_request *)ssi_req; + struct ahash_request *req = (struct ahash_request *)cc_req; struct ahash_req_ctx *state = ahash_request_ctx(req); dev_dbg(dev, "req=%pK\n", req); @@ -384,9 +384,9 @@ static void cc_update_complete(struct device *dev, void *ssi_req) req->base.complete(&req->base, 0); } -static void cc_digest_complete(struct device *dev, void *ssi_req) +static void cc_digest_complete(struct device *dev, void *cc_req) { - struct ahash_request *req = (struct ahash_request *)ssi_req; + struct ahash_request *req = (struct ahash_request *)cc_req; struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); @@ -400,9 +400,9 @@ static void cc_digest_complete(struct device *dev, void *ssi_req) req->base.complete(&req->base, 0); } -static void cc_hash_complete(struct device *dev, void *ssi_req) +static void cc_hash_complete(struct device *dev, void *cc_req) { - struct ahash_request *req = (struct ahash_request *)ssi_req; + struct ahash_request *req = (struct ahash_request *)cc_req; struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); @@ -427,9 +427,9 @@ static int cc_hash_digest(struct ahash_request *req) u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; - ssi_sram_addr_t larval_digest_addr = + cc_sram_addr_t larval_digest_addr = cc_larval_digest_addr(ctx->drvdata, ctx->hash_mode); int idx = 0; int rc = 0; @@ -453,8 +453,8 @@ static int cc_hash_digest(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = cc_digest_complete; - ssi_req.user_arg = req; + cc_req.user_cb = cc_digest_complete; + cc_req.user_arg = req; /* If HMAC then load hash IPAD xor key, if HASH then load initial * digest @@ -561,7 +561,7 @@ static int cc_hash_digest(struct ahash_request *req) cc_set_endianity(ctx->hash_mode, &desc[idx]); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); @@ -580,7 +580,7 @@ static int cc_hash_update(struct ahash_request *req) struct scatterlist *src = req->src; unsigned int nbytes = req->nbytes; struct device *dev = drvdata_to_dev(ctx->drvdata); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; u32 idx = 0; int rc; @@ -607,8 +607,8 @@ static int cc_hash_update(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = cc_update_complete; - ssi_req.user_arg = req; + cc_req.user_cb = cc_update_complete; + cc_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -648,7 +648,7 @@ static int cc_hash_update(struct ahash_request *req) set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); @@ -667,7 +667,7 @@ static int cc_hash_finup(struct ahash_request *req) u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc; @@ -685,8 +685,8 @@ static int cc_hash_finup(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = cc_hash_complete; - ssi_req.user_arg = req; + cc_req.user_cb = cc_hash_complete; + cc_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -767,7 +767,7 @@ static int cc_hash_finup(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); @@ -787,7 +787,7 @@ static int cc_hash_final(struct ahash_request *req) u8 *result = req->result; struct device *dev = drvdata_to_dev(ctx->drvdata); bool is_hmac = ctx->is_hmac; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc; @@ -806,8 +806,8 @@ static int cc_hash_final(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = cc_hash_complete; - ssi_req.user_arg = req; + cc_req.user_cb = cc_hash_complete; + cc_req.user_arg = req; /* Restore hash digest */ hw_desc_init(&desc[idx]); @@ -897,7 +897,7 @@ static int cc_hash_final(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, src, true); @@ -925,13 +925,13 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST }; - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hash_ctx *ctx = NULL; int blocksize = 0; int digestsize = 0; int i, idx = 0, rc = 0; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; - ssi_sram_addr_t larval_addr; + cc_sram_addr_t larval_addr; struct device *dev; ctx = crypto_ahash_ctx(ahash); @@ -1037,7 +1037,7 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, idx++; } - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 0); if (rc) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); goto out; @@ -1094,7 +1094,7 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, idx++; } - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 0); out: if (rc) @@ -1112,7 +1112,7 @@ static int cc_hash_setkey(struct crypto_ahash *ahash, const u8 *key, static int cc_xcbc_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hash_ctx *ctx = crypto_ahash_ctx(ahash); struct device *dev = drvdata_to_dev(ctx->drvdata); int idx = 0, rc = 0; @@ -1177,7 +1177,7 @@ static int cc_xcbc_setkey(struct crypto_ahash *ahash, CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 0); if (rc) crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); @@ -1300,17 +1300,17 @@ static int cc_cra_init(struct crypto_tfm *tfm) container_of(tfm->__crt_alg, struct hash_alg_common, base); struct ahash_alg *ahash_alg = container_of(hash_alg_common, struct ahash_alg, halg); - struct cc_hash_alg *ssi_alg = + struct cc_hash_alg *cc_alg = container_of(ahash_alg, struct cc_hash_alg, ahash_alg); crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct ahash_req_ctx)); - ctx->hash_mode = ssi_alg->hash_mode; - ctx->hw_mode = ssi_alg->hw_mode; - ctx->inter_digestsize = ssi_alg->inter_digestsize; - ctx->drvdata = ssi_alg->drvdata; + ctx->hash_mode = cc_alg->hash_mode; + ctx->hw_mode = cc_alg->hw_mode; + ctx->inter_digestsize = cc_alg->inter_digestsize; + ctx->drvdata = cc_alg->drvdata; return cc_alloc_ctx(ctx); } @@ -1331,7 +1331,7 @@ static int cc_mac_update(struct ahash_request *req) struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int rc; u32 idx = 0; @@ -1374,10 +1374,10 @@ static int cc_mac_update(struct ahash_request *req) idx++; /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_update_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_update_complete; + cc_req.user_arg = (void *)req; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); @@ -1391,7 +1391,7 @@ static int cc_mac_final(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc = 0; @@ -1424,8 +1424,8 @@ static int cc_mac_final(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_hash_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_hash_complete; + cc_req.user_arg = (void *)req; if (state->xcbc_count && rem_cnt == 0) { /* Load key for ECB decryption */ @@ -1490,7 +1490,7 @@ static int cc_mac_final(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); @@ -1505,7 +1505,7 @@ static int cc_mac_finup(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; int idx = 0; int rc = 0; @@ -1529,8 +1529,8 @@ static int cc_mac_finup(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_hash_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_hash_complete; + cc_req.user_arg = (void *)req; if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { key_len = CC_AES_128_BIT_KEY_SIZE; @@ -1562,7 +1562,7 @@ static int cc_mac_finup(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); @@ -1578,7 +1578,7 @@ static int cc_mac_digest(struct ahash_request *req) struct cc_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = drvdata_to_dev(ctx->drvdata); u32 digestsize = crypto_ahash_digestsize(tfm); - struct ssi_crypto_req ssi_req = {}; + struct cc_crypto_req cc_req = {}; struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN]; u32 key_len; int idx = 0; @@ -1602,8 +1602,8 @@ static int cc_mac_digest(struct ahash_request *req) } /* Setup DX request structure */ - ssi_req.user_cb = (void *)cc_digest_complete; - ssi_req.user_arg = (void *)req; + cc_req.user_cb = (void *)cc_digest_complete; + cc_req.user_arg = (void *)req; if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { key_len = CC_AES_128_BIT_KEY_SIZE; @@ -1635,7 +1635,7 @@ static int cc_mac_digest(struct ahash_request *req) set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); + rc = send_request(ctx->drvdata, &cc_req, desc, idx, 1); if (rc != -EINPROGRESS) { dev_err(dev, "send_request() failed (rc=%d)\n", rc); cc_unmap_hash_request(dev, state, req->src, true); @@ -1757,7 +1757,7 @@ struct cc_hash_template { int hash_mode; int hw_mode; int inter_digestsize; - struct ssi_drvdata *drvdata; + struct cc_drvdata *drvdata; }; #define CC_STATE_SIZE(_x) \ @@ -2005,10 +2005,10 @@ static struct cc_hash_alg *cc_alloc_hash_alg(struct cc_hash_template *template, return t_crypto_alg; } -int cc_init_hash_sram(struct ssi_drvdata *drvdata) +int cc_init_hash_sram(struct cc_drvdata *drvdata) { struct cc_hash_handle *hash_handle = drvdata->hash_handle; - ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; + cc_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; unsigned int larval_seq_len = 0; struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; struct device *dev = drvdata_to_dev(drvdata); @@ -2125,10 +2125,10 @@ int cc_init_hash_sram(struct ssi_drvdata *drvdata) return rc; } -int cc_hash_alloc(struct ssi_drvdata *drvdata) +int cc_hash_alloc(struct cc_drvdata *drvdata) { struct cc_hash_handle *hash_handle; - ssi_sram_addr_t sram_buff; + cc_sram_addr_t sram_buff; u32 sram_size_to_alloc; struct device *dev = drvdata_to_dev(drvdata); int rc = 0; @@ -2228,7 +2228,7 @@ int cc_hash_alloc(struct ssi_drvdata *drvdata) return rc; } -int cc_hash_free(struct ssi_drvdata *drvdata) +int cc_hash_free(struct cc_drvdata *drvdata) { struct cc_hash_alg *t_hash_alg, *hash_n; struct cc_hash_handle *hash_handle = drvdata->hash_handle; @@ -2390,9 +2390,9 @@ static void cc_set_desc(struct ahash_req_ctx *areq_ctx, * * \return u32 The address of the initial digest in SRAM */ -ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) +cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) { - struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; + struct cc_drvdata *_drvdata = (struct cc_drvdata *)drvdata; struct cc_hash_handle *hash_handle = _drvdata->hash_handle; struct device *dev = drvdata_to_dev(_drvdata); @@ -2436,12 +2436,12 @@ ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode) return hash_handle->larval_digest_sram_addr; } -ssi_sram_addr_t +cc_sram_addr_t cc_digest_len_addr(void *drvdata, u32 mode) { - struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; + struct cc_drvdata *_drvdata = (struct cc_drvdata *)drvdata; struct cc_hash_handle *hash_handle = _drvdata->hash_handle; - ssi_sram_addr_t digest_len_addr = hash_handle->digest_len_sram_addr; + cc_sram_addr_t digest_len_addr = hash_handle->digest_len_sram_addr; switch (mode) { case DRV_HASH_SHA1: diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index 9d1af96..81f57fc 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -56,7 +56,7 @@ struct ahash_req_ctx { u8 *buff1; u8 *digest_result_buff; struct async_gen_req_ctx gen_ctx; - enum ssi_req_dma_buf_type data_dma_buf_type; + enum cc_req_dma_buf_type data_dma_buf_type; u8 *digest_buff; u8 *opad_digest_buff; u8 *digest_bytes_len; @@ -75,9 +75,9 @@ struct ahash_req_ctx { struct mlli_params mlli_params; }; -int cc_hash_alloc(struct ssi_drvdata *drvdata); -int cc_init_hash_sram(struct ssi_drvdata *drvdata); -int cc_hash_free(struct ssi_drvdata *drvdata); +int cc_hash_alloc(struct cc_drvdata *drvdata); +int cc_init_hash_sram(struct cc_drvdata *drvdata); +int cc_hash_free(struct cc_drvdata *drvdata); /*! * Gets the initial digest length @@ -88,7 +88,7 @@ int cc_hash_free(struct ssi_drvdata *drvdata); * * \return u32 returns the address of the initial digest length in SRAM */ -ssi_sram_addr_t +cc_sram_addr_t cc_digest_len_addr(void *drvdata, u32 mode); /*! @@ -101,7 +101,7 @@ cc_digest_len_addr(void *drvdata, u32 mode); * * \return u32 The address of the initial digest in SRAM */ -ssi_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode); +cc_sram_addr_t cc_larval_digest_addr(void *drvdata, u32 mode); #endif /*__CC_HASH_H__*/ diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index d362bf6..0303c85 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -41,9 +41,9 @@ * @pool_meta_dma: phys. address of the initial enc. key/IV */ struct cc_ivgen_ctx { - ssi_sram_addr_t pool; - ssi_sram_addr_t ctr_key; - ssi_sram_addr_t ctr_iv; + cc_sram_addr_t pool; + cc_sram_addr_t ctr_key; + cc_sram_addr_t ctr_iv; u32 next_iv_ofs; u8 *pool_meta; dma_addr_t pool_meta_dma; @@ -116,7 +116,7 @@ static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx, * * \return int Zero for success, negative value otherwise. */ -int cc_init_iv_sram(struct ssi_drvdata *drvdata) +int cc_init_iv_sram(struct cc_drvdata *drvdata) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN]; @@ -153,7 +153,7 @@ int cc_init_iv_sram(struct ssi_drvdata *drvdata) * * \param drvdata */ -void cc_ivgen_fini(struct ssi_drvdata *drvdata) +void cc_ivgen_fini(struct cc_drvdata *drvdata) { struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct device *device = &drvdata->plat_dev->dev; @@ -182,7 +182,7 @@ void cc_ivgen_fini(struct ssi_drvdata *drvdata) * * \return int Zero for success, negative value otherwise. */ -int cc_ivgen_init(struct ssi_drvdata *drvdata) +int cc_ivgen_init(struct cc_drvdata *drvdata) { struct cc_ivgen_ctx *ivgen_ctx; struct device *device = &drvdata->plat_dev->dev; @@ -234,7 +234,7 @@ int cc_ivgen_init(struct ssi_drvdata *drvdata) * * \return int Zero for success, negative value otherwise. */ -int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], +int cc_get_iv(struct cc_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h index 9890f62..eeca45e3 100644 --- a/drivers/staging/ccree/ssi_ivgen.h +++ b/drivers/staging/ccree/ssi_ivgen.h @@ -29,14 +29,14 @@ * * \return int Zero for success, negative value otherwise. */ -int cc_ivgen_init(struct ssi_drvdata *drvdata); +int cc_ivgen_init(struct cc_drvdata *drvdata); /*! * Free iv-pool and ivgen context. * * \param drvdata */ -void cc_ivgen_fini(struct ssi_drvdata *drvdata); +void cc_ivgen_fini(struct cc_drvdata *drvdata); /*! * Generates the initial pool in SRAM. @@ -46,7 +46,7 @@ void cc_ivgen_fini(struct ssi_drvdata *drvdata); * * \return int Zero for success, negative value otherwise. */ -int cc_init_iv_sram(struct ssi_drvdata *drvdata); +int cc_init_iv_sram(struct cc_drvdata *drvdata); /*! * Acquires 16 Bytes IV from the iv-pool @@ -61,7 +61,7 @@ int cc_init_iv_sram(struct ssi_drvdata *drvdata); * * \return int Zero for success, negative value otherwise. */ -int cc_get_iv(struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], +int cc_get_iv(struct cc_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len); diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c index e387d46..3c4892b 100644 --- a/drivers/staging/ccree/ssi_pm.c +++ b/drivers/staging/ccree/ssi_pm.c @@ -36,7 +36,7 @@ int cc_pm_suspend(struct device *dev) { - struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + struct cc_drvdata *drvdata = dev_get_drvdata(dev); int rc; dev_dbg(dev, "set HOST_POWER_DOWN_EN\n"); @@ -55,7 +55,7 @@ int cc_pm_suspend(struct device *dev) int cc_pm_resume(struct device *dev) { int rc; - struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + struct cc_drvdata *drvdata = dev_get_drvdata(dev); dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n"); cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE); @@ -88,7 +88,7 @@ int cc_pm_resume(struct device *dev) int cc_pm_get(struct device *dev) { int rc = 0; - struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + struct cc_drvdata *drvdata = dev_get_drvdata(dev); if (cc_req_queue_suspended(drvdata)) rc = pm_runtime_get_sync(dev); @@ -101,7 +101,7 @@ int cc_pm_get(struct device *dev) int cc_pm_put_suspend(struct device *dev) { int rc = 0; - struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + struct cc_drvdata *drvdata = dev_get_drvdata(dev); if (!cc_req_queue_suspended(drvdata)) { pm_runtime_mark_last_busy(dev); @@ -116,7 +116,7 @@ int cc_pm_put_suspend(struct device *dev) #endif -int cc_pm_init(struct ssi_drvdata *drvdata) +int cc_pm_init(struct cc_drvdata *drvdata) { int rc = 0; #if defined(CONFIG_PM) @@ -135,7 +135,7 @@ int cc_pm_init(struct ssi_drvdata *drvdata) return rc; } -void cc_pm_fini(struct ssi_drvdata *drvdata) +void cc_pm_fini(struct cc_drvdata *drvdata) { #if defined(CONFIG_PM) pm_runtime_disable(drvdata_to_dev(drvdata)); diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h index 940ef2d..a5f2b1b 100644 --- a/drivers/staging/ccree/ssi_pm.h +++ b/drivers/staging/ccree/ssi_pm.h @@ -25,9 +25,9 @@ #define CC_SUSPEND_TIMEOUT 3000 -int cc_pm_init(struct ssi_drvdata *drvdata); +int cc_pm_init(struct cc_drvdata *drvdata); -void cc_pm_fini(struct ssi_drvdata *drvdata); +void cc_pm_fini(struct cc_drvdata *drvdata); #if defined(CONFIG_PM) int cc_pm_suspend(struct device *dev); diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index f1356d1..480e6d3 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -38,7 +38,7 @@ struct cc_req_mgr_handle { unsigned int hw_queue_size; /* HW capability */ unsigned int min_free_hw_slots; unsigned int max_used_sw_slots; - struct ssi_crypto_req req_queue[MAX_REQUEST_QUEUE_SIZE]; + struct cc_crypto_req req_queue[MAX_REQUEST_QUEUE_SIZE]; u32 req_queue_head; u32 req_queue_tail; u32 axi_completed; @@ -68,7 +68,7 @@ static void comp_handler(unsigned long devarg); static void comp_work_handler(struct work_struct *work); #endif -void cc_req_mgr_fini(struct ssi_drvdata *drvdata) +void cc_req_mgr_fini(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; struct device *dev = drvdata_to_dev(drvdata); @@ -97,7 +97,7 @@ void cc_req_mgr_fini(struct ssi_drvdata *drvdata) drvdata->request_mgr_handle = NULL; } -int cc_req_mgr_init(struct ssi_drvdata *drvdata) +int cc_req_mgr_init(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *req_mgr_h; struct device *dev = drvdata_to_dev(drvdata); @@ -201,7 +201,7 @@ static void request_mgr_complete(struct device *dev, void *dx_compl_h) complete(this_compl); } -static int cc_queues_status(struct ssi_drvdata *drvdata, +static int cc_queues_status(struct cc_drvdata *drvdata, struct cc_req_mgr_handle *req_mgr_h, unsigned int total_seq_len) { @@ -248,7 +248,7 @@ static int cc_queues_status(struct ssi_drvdata *drvdata, * Enqueue caller request to crypto hardware. * * \param drvdata - * \param ssi_req The request to enqueue + * \param cc_req The request to enqueue * \param desc The crypto sequence * \param len The crypto sequence length * \param is_dout If "true": completion is handled by the caller @@ -257,7 +257,7 @@ static int cc_queues_status(struct ssi_drvdata *drvdata, * * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false" */ -int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, +int send_request(struct cc_drvdata *drvdata, struct cc_crypto_req *cc_req, struct cc_hw_desc *desc, unsigned int len, bool is_dout) { void __iomem *cc_base = drvdata->cc_base; @@ -270,7 +270,7 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, int rc; unsigned int max_required_seq_len = (total_seq_len + - ((ssi_req->ivgen_dma_addr_len == 0) ? 0 : + ((cc_req->ivgen_dma_addr_len == 0) ? 0 : CC_IVPOOL_SEQ_LEN) + (!is_dout ? 1 : 0)); #if defined(CONFIG_PM) @@ -314,24 +314,24 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, * enabled any DLLI/MLLI DOUT bit in the given sequence */ if (!is_dout) { - init_completion(&ssi_req->seq_compl); - ssi_req->user_cb = request_mgr_complete; - ssi_req->user_arg = &ssi_req->seq_compl; + init_completion(&cc_req->seq_compl); + cc_req->user_cb = request_mgr_complete; + cc_req->user_arg = &cc_req->seq_compl; total_seq_len++; } - if (ssi_req->ivgen_dma_addr_len > 0) { + if (cc_req->ivgen_dma_addr_len > 0) { dev_dbg(dev, "Acquire IV from pool into %d DMA addresses %pad, %pad, %pad, IV-size=%u\n", - ssi_req->ivgen_dma_addr_len, - &ssi_req->ivgen_dma_addr[0], - &ssi_req->ivgen_dma_addr[1], - &ssi_req->ivgen_dma_addr[2], - ssi_req->ivgen_size); + cc_req->ivgen_dma_addr_len, + &cc_req->ivgen_dma_addr[0], + &cc_req->ivgen_dma_addr[1], + &cc_req->ivgen_dma_addr[2], + cc_req->ivgen_size); /* Acquire IV from pool */ - rc = cc_get_iv(drvdata, ssi_req->ivgen_dma_addr, - ssi_req->ivgen_dma_addr_len, - ssi_req->ivgen_size, + rc = cc_get_iv(drvdata, cc_req->ivgen_dma_addr, + cc_req->ivgen_dma_addr_len, + cc_req->ivgen_size, iv_seq, &iv_seq_len); if (rc) { @@ -353,7 +353,7 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, req_mgr_h->max_used_sw_slots = used_sw_slots; /* Enqueue request - must be locked with HW lock*/ - req_mgr_h->req_queue[req_mgr_h->req_queue_head] = *ssi_req; + req_mgr_h->req_queue[req_mgr_h->req_queue_head] = *cc_req; req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); /* TODO: Use circ_buf.h ? */ @@ -393,7 +393,7 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, /* Wait upon sequence completion. * Return "0" -Operation done successfully. */ - wait_for_completion(&ssi_req->seq_compl); + wait_for_completion(&cc_req->seq_compl); return 0; } /* Operation still in process */ @@ -411,7 +411,7 @@ int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, * * \return int Returns "0" upon success */ -int send_request_init(struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, +int send_request_init(struct cc_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len) { void __iomem *cc_base = drvdata->cc_base; @@ -442,7 +442,7 @@ int send_request_init(struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, return 0; } -void complete_request(struct ssi_drvdata *drvdata) +void complete_request(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; @@ -459,16 +459,16 @@ void complete_request(struct ssi_drvdata *drvdata) #ifdef COMP_IN_WQ static void comp_work_handler(struct work_struct *work) { - struct ssi_drvdata *drvdata = - container_of(work, struct ssi_drvdata, compwork.work); + struct cc_drvdata *drvdata = + container_of(work, struct cc_drvdata, compwork.work); comp_handler((unsigned long)drvdata); } #endif -static void proc_completions(struct ssi_drvdata *drvdata) +static void proc_completions(struct cc_drvdata *drvdata) { - struct ssi_crypto_req *ssi_req; + struct cc_crypto_req *cc_req; struct device *dev = drvdata_to_dev(drvdata); struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; @@ -492,7 +492,7 @@ static void proc_completions(struct ssi_drvdata *drvdata) break; } - ssi_req = &request_mgr_handle->req_queue[*tail]; + cc_req = &request_mgr_handle->req_queue[*tail]; #ifdef FLUSH_CACHE_ALL flush_cache_all(); @@ -511,8 +511,8 @@ static void proc_completions(struct ssi_drvdata *drvdata) } #endif /* COMPLETION_DELAY */ - if (ssi_req->user_cb) - ssi_req->user_cb(dev, ssi_req->user_arg); + if (cc_req->user_cb) + cc_req->user_cb(dev, cc_req->user_arg); *tail = (*tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); dev_dbg(dev, "Dequeue request tail=%u\n", *tail); dev_dbg(dev, "Request completed. axi_completed=%d\n", @@ -526,7 +526,7 @@ static void proc_completions(struct ssi_drvdata *drvdata) } } -static inline u32 cc_axi_comp_count(struct ssi_drvdata *drvdata) +static inline u32 cc_axi_comp_count(struct cc_drvdata *drvdata) { return FIELD_GET(AXIM_MON_COMP_VALUE, cc_ioread(drvdata, CC_REG(AXIM_MON_COMP))); @@ -535,7 +535,7 @@ static inline u32 cc_axi_comp_count(struct ssi_drvdata *drvdata) /* Deferred service handler, run as interrupt-fired tasklet */ static void comp_handler(unsigned long devarg) { - struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; + struct cc_drvdata *drvdata = (struct cc_drvdata *)devarg; struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; @@ -584,7 +584,7 @@ static void comp_handler(unsigned long devarg) * inside the spin lock protection */ #if defined(CONFIG_PM) -int cc_resume_req_queue(struct ssi_drvdata *drvdata) +int cc_resume_req_queue(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; @@ -600,7 +600,7 @@ int cc_resume_req_queue(struct ssi_drvdata *drvdata) * suspend the queue configuration. Since it is used for the runtime suspend * only verify that the queue can be suspended. */ -int cc_suspend_req_queue(struct ssi_drvdata *drvdata) +int cc_suspend_req_queue(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; @@ -618,7 +618,7 @@ int cc_suspend_req_queue(struct ssi_drvdata *drvdata) return 0; } -bool cc_req_queue_suspended(struct ssi_drvdata *drvdata) +bool cc_req_queue_suspended(struct cc_drvdata *drvdata) { struct cc_req_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index 91e0d47..eb068bf 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -23,13 +23,13 @@ #include "cc_hw_queue_defs.h" -int cc_req_mgr_init(struct ssi_drvdata *drvdata); +int cc_req_mgr_init(struct cc_drvdata *drvdata); /*! * Enqueue caller request to crypto hardware. * * \param drvdata - * \param ssi_req The request to enqueue + * \param cc_req The request to enqueue * \param desc The crypto sequence * \param len The crypto sequence length * \param is_dout If "true": completion is handled by the caller @@ -38,22 +38,22 @@ int cc_req_mgr_init(struct ssi_drvdata *drvdata); * * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false" */ -int send_request(struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, +int send_request(struct cc_drvdata *drvdata, struct cc_crypto_req *cc_req, struct cc_hw_desc *desc, unsigned int len, bool is_dout); -int send_request_init(struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, +int send_request_init(struct cc_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len); -void complete_request(struct ssi_drvdata *drvdata); +void complete_request(struct cc_drvdata *drvdata); -void cc_req_mgr_fini(struct ssi_drvdata *drvdata); +void cc_req_mgr_fini(struct cc_drvdata *drvdata); #if defined(CONFIG_PM) -int cc_resume_req_queue(struct ssi_drvdata *drvdata); +int cc_resume_req_queue(struct cc_drvdata *drvdata); -int cc_suspend_req_queue(struct ssi_drvdata *drvdata); +int cc_suspend_req_queue(struct cc_drvdata *drvdata); -bool cc_req_queue_suspended(struct ssi_drvdata *drvdata); +bool cc_req_queue_suspended(struct cc_drvdata *drvdata); #endif #endif /*__REQUEST_MGR_H__*/ diff --git a/drivers/staging/ccree/ssi_sram_mgr.c b/drivers/staging/ccree/ssi_sram_mgr.c index cbe5e3b..5d83af5 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.c +++ b/drivers/staging/ccree/ssi_sram_mgr.c @@ -22,7 +22,7 @@ * @sram_free_offset: the offset to the non-allocated area */ struct ssi_sram_mgr_ctx { - ssi_sram_addr_t sram_free_offset; + cc_sram_addr_t sram_free_offset; }; /** @@ -30,7 +30,7 @@ struct ssi_sram_mgr_ctx { * * @drvdata: Associated device driver context */ -void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata) +void ssi_sram_mgr_fini(struct cc_drvdata *drvdata) { struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; @@ -48,7 +48,7 @@ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata) * * @drvdata: Associated device driver context */ -int ssi_sram_mgr_init(struct ssi_drvdata *drvdata) +int ssi_sram_mgr_init(struct cc_drvdata *drvdata) { /* Allocate "this" context */ drvdata->sram_mgr_handle = kzalloc(sizeof(*drvdata->sram_mgr_handle), @@ -69,11 +69,11 @@ int ssi_sram_mgr_init(struct ssi_drvdata *drvdata) * \param drvdata * \param size The requested bytes to allocate */ -ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size) +cc_sram_addr_t cc_sram_alloc(struct cc_drvdata *drvdata, u32 size) { struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; struct device *dev = drvdata_to_dev(drvdata); - ssi_sram_addr_t p; + cc_sram_addr_t p; if ((size & 0x3)) { dev_err(dev, "Requested buffer size (%u) is not multiple of 4", @@ -103,7 +103,7 @@ ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size) * @seq: A pointer to the given IN/OUT descriptor sequence * @seq_len: A pointer to the given IN/OUT sequence length */ -void cc_set_sram_desc(const u32 *src, ssi_sram_addr_t dst, +void cc_set_sram_desc(const u32 *src, cc_sram_addr_t dst, unsigned int nelement, struct cc_hw_desc *seq, unsigned int *seq_len) { diff --git a/drivers/staging/ccree/ssi_sram_mgr.h b/drivers/staging/ccree/ssi_sram_mgr.h index fdd325b..52f5288 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.h +++ b/drivers/staging/ccree/ssi_sram_mgr.h @@ -21,15 +21,15 @@ #define CC_CC_SRAM_SIZE 4096 #endif -struct ssi_drvdata; +struct cc_drvdata; /** * Address (offset) within CC internal SRAM */ -typedef u64 ssi_sram_addr_t; +typedef u64 cc_sram_addr_t; -#define NULL_SRAM_ADDR ((ssi_sram_addr_t)-1) +#define NULL_SRAM_ADDR ((cc_sram_addr_t)-1) /*! * Initializes SRAM pool. @@ -40,14 +40,14 @@ typedef u64 ssi_sram_addr_t; * * \return int Zero for success, negative value otherwise. */ -int ssi_sram_mgr_init(struct ssi_drvdata *drvdata); +int ssi_sram_mgr_init(struct cc_drvdata *drvdata); /*! * Uninits SRAM pool. * * \param drvdata */ -void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata); +void ssi_sram_mgr_fini(struct cc_drvdata *drvdata); /*! * Allocated buffer from SRAM pool. @@ -58,7 +58,7 @@ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata); * \param drvdata * \param size The requested bytes to allocate */ -ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size); +cc_sram_addr_t cc_sram_alloc(struct cc_drvdata *drvdata, u32 size); /** * cc_set_sram_desc() - Create const descriptors sequence to @@ -71,7 +71,7 @@ ssi_sram_addr_t cc_sram_alloc(struct ssi_drvdata *drvdata, u32 size); * @seq: A pointer to the given IN/OUT descriptor sequence * @seq_len: A pointer to the given IN/OUT sequence length */ -void cc_set_sram_desc(const u32 *src, ssi_sram_addr_t dst, +void cc_set_sram_desc(const u32 *src, cc_sram_addr_t dst, unsigned int nelement, struct cc_hw_desc *seq, unsigned int *seq_len); diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c index 6b11a72..b2e58f5 100644 --- a/drivers/staging/ccree/ssi_sysfs.c +++ b/drivers/staging/ccree/ssi_sysfs.c @@ -22,12 +22,12 @@ #ifdef ENABLE_CC_SYSFS -static struct ssi_drvdata *sys_get_drvdata(void); +static struct cc_drvdata *sys_get_drvdata(void); static ssize_t ssi_sys_regdump_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { - struct ssi_drvdata *drvdata = sys_get_drvdata(); + struct cc_drvdata *drvdata = sys_get_drvdata(); u32 register_value; int offset = 0; @@ -86,7 +86,7 @@ struct sys_dir { struct attribute_group sys_dir_attr_group; struct attribute **sys_dir_attr_list; u32 num_of_attrs; - struct ssi_drvdata *drvdata; /* Associated driver context */ + struct cc_drvdata *drvdata; /* Associated driver context */ }; /* top level directory structures */ @@ -105,7 +105,7 @@ static struct kobj_attribute ssi_sys_top_level_attrs[] = { }; -static struct ssi_drvdata *sys_get_drvdata(void) +static struct cc_drvdata *sys_get_drvdata(void) { /* TODO: supporting multiple SeP devices would require avoiding * global "top_dir" and finding associated "top_dir" by traversing @@ -114,7 +114,7 @@ static struct ssi_drvdata *sys_get_drvdata(void) return sys_top_dir.drvdata; } -static int sys_init_dir(struct sys_dir *sys_dir, struct ssi_drvdata *drvdata, +static int sys_init_dir(struct sys_dir *sys_dir, struct cc_drvdata *drvdata, struct kobject *parent_dir_kobj, const char *dir_name, struct kobj_attribute *attrs, u32 num_of_attrs) { @@ -169,7 +169,7 @@ static void sys_free_dir(struct sys_dir *sys_dir) } } -int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata) +int ssi_sysfs_init(struct kobject *sys_dev_obj, struct cc_drvdata *drvdata) { int retval; struct device *dev = drvdata_to_dev(drvdata); diff --git a/drivers/staging/ccree/ssi_sysfs.h b/drivers/staging/ccree/ssi_sysfs.h index de68bc6..9833d18 100644 --- a/drivers/staging/ccree/ssi_sysfs.h +++ b/drivers/staging/ccree/ssi_sysfs.h @@ -24,9 +24,9 @@ #include /* forward declaration */ -struct ssi_drvdata; +struct cc_drvdata; -int ssi_sysfs_init(struct kobject *sys_dev_obj, struct ssi_drvdata *drvdata); +int ssi_sysfs_init(struct kobject *sys_dev_obj, struct cc_drvdata *drvdata); void ssi_sysfs_fini(void); #endif /*__CC_SYSFS_H__*/ From patchwork Tue Dec 12 14:53:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 121542 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4225148qgn; Tue, 12 Dec 2017 06:56:48 -0800 (PST) X-Google-Smtp-Source: ACJfBouiv6aZrNrWuy46rwh4+Hl9S8UUNhVLLSahqUTTHxmxoQZ7K7ytrOsMUjeg1eCBrQpG0mDf X-Received: by 10.98.80.208 with SMTP id g77mr2566701pfj.201.1513090608166; Tue, 12 Dec 2017 06:56:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513090608; cv=none; d=google.com; s=arc-20160816; b=foHeoqzUtqa1Pr9RhZHpXdAY6vZC2WjMIF3Z1nvqmzTbcCfEZZqvoDqMSQmR7ZnT9n 5sLHW3gHWlwGnR5jcPSMJyUrbID7SmFbpx3V4k2pIt8iCzoGbYrUjQ0G+3KgdkR7AGBS GGUzdQPSY6EtZRYlVZ1vxkm3Bl39Sokx/tJB3GXXrXEDq5jF5C3G8QzJu7NREx4MtNLa 56dvC1Sv9cgVIUUxoCt+GgCPsXzOmKtCRrcR/RVYc8MkXPmakqQtDDhSTmSh/wgLy37E kP2uMHskQYOq7QQhKDG+waSxx7dv738I5i55PKgBo2546YyKuwFc/GgvSDEBz+xVf2mG I2Xw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id d3si11534267pgq.709.2017.12.12.06.56.47; Tue, 12 Dec 2017 06:56:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753128AbdLLO4o (ORCPT + 11 others); Tue, 12 Dec 2017 09:56:44 -0500 Received: from foss.arm.com ([217.140.101.70]:45258 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752306AbdLLO4l (ORCPT ); Tue, 12 Dec 2017 09:56:41 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C40E01529; Tue, 12 Dec 2017 06:56:40 -0800 (PST) Received: from sugar.kfn.arm.com (unknown [10.45.48.196]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1FA4A3F318; Tue, 12 Dec 2017 06:56:37 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org Subject: [PATCH 23/24] staging: ccree: simplify freeing SRAM memory address Date: Tue, 12 Dec 2017 14:53:09 +0000 Message-Id: <1513090395-7938-24-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513090395-7938-1-git-send-email-gilad@benyossef.com> References: <1513090395-7938-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The code freeing the SRAM memory address was zeroing the address on release although there is nothing secret about it. Simplify the code by simply calling kfree directly. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/ssi_sram_mgr.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/staging/ccree/ssi_sram_mgr.c b/drivers/staging/ccree/ssi_sram_mgr.c index b664e9b..f72d64a 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.c +++ b/drivers/staging/ccree/ssi_sram_mgr.c @@ -32,13 +32,8 @@ struct cc_sram_ctx { */ void cc_sram_mgr_fini(struct cc_drvdata *drvdata) { - struct cc_sram_ctx *smgr_ctx = drvdata->sram_mgr_handle; - /* Free "this" context */ - if (smgr_ctx) { - memset(smgr_ctx, 0, sizeof(struct cc_sram_ctx)); - kfree(smgr_ctx); - } + kfree(drvdata->sram_mgr_handle); } /**