From patchwork Wed Dec 13 16:52:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121796 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5709787qgn; Wed, 13 Dec 2017 08:52:24 -0800 (PST) X-Google-Smtp-Source: ACJfBou34LdYx0lhLOI23GfHP1Ok3mvFHYQVzUVa+vCVP7kqoQ2ZQvVlukpYwjXVhdiAT9uuKlAt X-Received: by 10.223.197.131 with SMTP id m3mr3191300wrg.203.1513183944307; Wed, 13 Dec 2017 08:52:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513183944; cv=none; d=google.com; s=arc-20160816; b=Wlq8+HW+XPLv+nUW1SsDdrE1uLN1h6ryiOplIdmjV63ljATmQ2+W5ijSaq9rLgLS8e 2krWcM6aip7A+svtboOLnXMwT9nMul/965mw2Tt0XVKRotUiEQslABxnrSTgf5xi0EAj UWG3VERf1AIAs3akl82cTQ7l5fhR6kFzwibtW6VfePNj+fIWwjITm9oO5Oq3zvaHBl3z 3b9SL6YOz7eCpYyLnpC3MY6Z2GqdbXKk2/zzbSm4ptVJW+a3F/EmurNncdYKAVI7SOUw cALwrcoyegXRG5ETn8x8APABzPpJ+QoKsRAJP9tmZYSGekz5jzSv5NfeSFQOZDzwsl71 pnzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=u38s6KJ1/xZSIqRdoq9FFsnR/cXGlKL7BFSl8xycdlQ=; b=lo6KB7I3IPCF7s0Jln3eG/kUIYvXPK554qCydfSn/xepevRtloc+mfTi/ELkJcJ9qK 5SyPOCRgk4tJAUNJumMc2AucRj4vLfaJBzSPiXOrEn71CD+f4L/ReycQntXqBlofoHFN UXIW3wVb2a9b6FLhCJRuZHyjxQbJzTSTmkA/X1O/my/nwlv+LTfD1D4Iedn/kdw3/MVL Cf6TSKY7pqq9aYi8zxh3PuKiSe7pwl3C7v5e1sOMOERb9iJZlO71nIHiV6aYooZsjtl6 0N4OAoifzNxc2XX6d7DpcgKDtOZ3Sw1Psc/NGjGwAjJcgwqY43gYylbnAkwuGKQ4gi8r gfEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id e12si1797882wre.304.2017.12.13.08.52.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Dec 2017 08:52:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePAGd-0007OQ-Ga; Wed, 13 Dec 2017 16:52:23 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Laszlo Ersek , Ard Biesheuvel Subject: [PATCH 1/2] hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI Date: Wed, 13 Dec 2017 16:52:20 +0000 Message-Id: <1513183941-24300-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> References: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> The GICv3 specification says that reserved register addresses should RAZ/WI. This means we need to return MEMTX_OK, not MEMTX_ERROR, because now that we support generating external aborts the latter will cause an abort on new board models. Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_dist.c | 13 +++++++++++++ hw/intc/arm_gicv3_its_common.c | 8 +++----- hw/intc/arm_gicv3_redist.c | 13 +++++++++++++ 3 files changed, 29 insertions(+), 5 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index 3ea3dd0..93fe936 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -817,6 +817,13 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, "%s: invalid guest read at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; + *data = 0; } else { trace_gicv3_dist_read(offset, *data, size, attrs.secure); } @@ -852,6 +859,12 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, "%s: invalid guest write at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; } else { trace_gicv3_dist_write(offset, data, size, attrs.secure); } diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index 2bd2f0f..284c0a7 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -67,7 +67,8 @@ static MemTxResult gicv3_its_trans_read(void *opaque, hwaddr offset, MemTxAttrs attrs) { qemu_log_mask(LOG_GUEST_ERROR, "ITS read at offset 0x%"PRIx64"\n", offset); - return MEMTX_ERROR; + *data = 0; + return MEMTX_OK; } static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, @@ -82,15 +83,12 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hwaddr offset, if (ret <= 0) { qemu_log_mask(LOG_GUEST_ERROR, "ITS: Error sending MSI: %s\n", strerror(-ret)); - return MEMTX_DECODE_ERROR; } - - return MEMTX_OK; } else { qemu_log_mask(LOG_GUEST_ERROR, "ITS write at bad offset 0x%"PRIx64"\n", offset); - return MEMTX_DECODE_ERROR; } + return MEMTX_OK; } static const MemoryRegionOps gicv3_its_trans_ops = { diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 77e5cfa..8a8684d 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -455,6 +455,13 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, "size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; + *data = 0; } else { trace_gicv3_redist_read(gicv3_redist_affid(cs), offset, *data, size, attrs.secure); @@ -505,6 +512,12 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, "size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); + /* The spec requires that reserved registers are RAZ/WI; + * so use MEMTX_ERROR returns from leaf functions as a way to + * trigger the guest-error logging but don't return it to + * the caller, or we'll cause a spurious guest data abort. + */ + r = MEMTX_OK; } else { trace_gicv3_redist_write(gicv3_redist_affid(cs), offset, data, size, attrs.secure); From patchwork Wed Dec 13 16:52:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 121797 Delivered-To: patches@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5709799qgn; Wed, 13 Dec 2017 08:52:25 -0800 (PST) X-Google-Smtp-Source: ACJfBosHIfeqpQyjLW2AxvFdRga2z2ytk9cOrWEtdig5Guimd/YACOOOZ7mbBbLQJMJc2afJCcJN X-Received: by 10.28.137.5 with SMTP id l5mr2691746wmd.123.1513183945223; Wed, 13 Dec 2017 08:52:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n68si1688240wmg.151.2017.12.13.08.52.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Dec 2017 08:52:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ePAGe-0007Oi-Ec; Wed, 13 Dec 2017 16:52:24 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Laszlo Ersek , Ard Biesheuvel Subject: [PATCH 2/2] hw/intc/arm_gic: reserved register addresses are RAZ/WI Date: Wed, 13 Dec 2017 16:52:21 +0000 Message-Id: <1513183941-24300-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> References: <1513183941-24300-1-git-send-email-peter.maydell@linaro.org> The GICv2 specification says that reserved register addresses must RAZ/WI; now that we implement external abort handling for Arm CPUs this means we must return MEMTX_OK rather than MEMTX_ERROR, to avoid generating a spurious guest data abort. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.7.4 Reviewed-by: Alistair Francis diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 5a0e2a3..d701e49 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + *data = 0; + break; } return MEMTX_OK; } @@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); - return MEMTX_ERROR; + return MEMTX_OK; } gic_update(s); return MEMTX_OK;