From patchwork Fri Dec 15 08:52:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 122068 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp193232qgn; Fri, 15 Dec 2017 00:54:05 -0800 (PST) X-Google-Smtp-Source: ACJfBosSOGrnjkJ1/p8ykfuxnuT8kLq6UkS2qeDVKq6bwTjsRvqUxOaU4sKUvm+JCCUJlkBxhK0L X-Received: by 10.84.128.197 with SMTP id a63mr12454955pla.212.1513328045260; Fri, 15 Dec 2017 00:54:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513328045; cv=none; d=google.com; s=arc-20160816; b=N0CawHOGmV28fdjW6yjYLu7WBp0dWKrL4fGSimHwJrKh32rgykYHl+RYPZDNjc6ors 0kiXKgF3Tm4LTV3yc32lCuFgdrMUqynuj4GRxqG8GrYhLtRVupSkftdpo/jHuvlF8iQA dto73969X3lPzArJQ69DL0ijH1NOr7NVnApBjL0rRsHV1BEj+pAwbc0AqoRG4Ju/LCCu +p07pC0DivK0pNOvy9+9f5OgB2b6fedFpTtbT5vHMdcI9CU9qSZs4gN4DswXngrlZZtk OTHd3gvSA0Pgfvantl/WjgfOSNyQ2noDXDMv4ZUz6iPHetD9O9L97B8OJDYPhqJIKWm6 3rbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=9Xjv8RL1vzZBmwiNxumm5rwhFwm+3E6M/B3+hUCOdno=; b=Wka0zT6JNnpVDvITfV9oIajbpN/51nnziHn/SfGDN/TXmvOj0JbPb7shTPsAApb6qs bKdVTJfFqGMXxBREkkODrQPoMy967PGuFON+4gA0n+CrwdYaia6wf+l3zx5Hokj/wswC Z0C9Lqwa/wZ+lAsre74eeABEc/tf9XdgEfsS7/Hg09BZxprhXoSfXPnEp5XO+wBwdEBu cg6WCVR5QJbOXVQBp/c4RAcwJBBNaPCrD9wWpztXEJHAFUzzVdGMgpZ6iVjfZBMPq/iH sZVng8P4Sg2wrLlP6OImLTYe08h9oKN7jv4gKGRd+kkWomZBbR5RCZaUf4gJKqPqKEFV DpHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dp+Zip29; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p5si4260270pgr.52.2017.12.15.00.54.04; Fri, 15 Dec 2017 00:54:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dp+Zip29; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755106AbdLOIyB (ORCPT + 20 others); Fri, 15 Dec 2017 03:54:01 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:37453 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753714AbdLOIxI (ORCPT ); Fri, 15 Dec 2017 03:53:08 -0500 Received: by mail-wm0-f65.google.com with SMTP id f140so16022751wmd.2 for ; Fri, 15 Dec 2017 00:53:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9Xjv8RL1vzZBmwiNxumm5rwhFwm+3E6M/B3+hUCOdno=; b=dp+Zip292cASPJpCJ/nHJ3CWxVc0pVmu5Lf6fAzJJ73cC54LtZzMFHcZZear6UFD5x +6AO6FpnU7GwCTO4zp/5EtA5+GcHThkeZn8Fngol6dt1wwobiGKEFPK6e/nar7ZUDM6N SxCk0u9/TvmLaRaAP7b8HCfWnIS3EuflRdoWw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9Xjv8RL1vzZBmwiNxumm5rwhFwm+3E6M/B3+hUCOdno=; b=UaT3A1TWjmYMC0DeY3qvpsmlZ2BDmJkwcm1wgGM1kUoTxvk82gkEBvz4i2JfWSRWen hi4E/LM5nCxrOnJ0XL+DsLWx7cBlnamMYJJAqYZxNskajjXbBpKTgTgHYEcPFuYS526I n1aX33p71Dy7EUEPs2iRSfgqDThwR7C3VMLOlPEiMt3cZpR+pXaBUfQwZGVP2aqyyMEN k22NhSPXQlfGMqub3Q4LJzpKRSdxdjw1b7T1owBUDV99fIVx08ShTHPN+cgbJyFpyA39 m0tNl+yxtFjPCYl2F3HdI8iH1AFlkHIRBePLz7Ok+vskDcRrl8Kf6rLwNr/ICTOQ9gnF OoYw== X-Gm-Message-State: AKGB3mIaDav2NBPraJ+M5w17pEo/PD9TyW80SEkg0pxDxJGvfgy6knmO Hfjo0d4byQ8H02TK+G2iGNKnLQ== X-Received: by 10.28.51.133 with SMTP id z127mr4919779wmz.84.1513327986796; Fri, 15 Dec 2017 00:53:06 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.40.214]) by smtp.gmail.com with ESMTPSA id r14sm3211803wra.71.2017.12.15.00.53.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Dec 2017 00:53:06 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 1/4] clocksource: stm32: convert driver to timer_of Date: Fri, 15 Dec 2017 09:52:44 +0100 Message-Id: <20171215085247.14946-2-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171215085247.14946-1-benjamin.gaignard@st.com> References: <20171215085247.14946-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert driver to use timer_of helpers. This allow to remove custom proprietary structure. Given counter number of bits (16 or 32) set a different prescaler value and adjust timer_of rate, period and rating. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 179 +++++++++++++++----------------------- 2 files changed, 72 insertions(+), 108 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c729a88007d0..28bc55951512 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -269,6 +269,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f2423789ba9..23a321cca45b 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,9 @@ #include #include #include +#include + +#include "timer-of.h" #define TIM_CR1 0x00 #define TIM_DIER 0x0c @@ -34,157 +37,117 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(0, timer_of_base(to) + TIM_CR1); - writel_relaxed(0, base + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(evt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + evt->event_handler(evt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static void __init stm32_clockevent_init(struct timer_of *to) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; - struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } + unsigned long max_delta; + int prescaler; - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); - if (!IS_ERR(rstc)) { - reset_control_assert(rstc); - reset_control_deassert(rstc); - } - - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } - - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } + to->clkevt.name = "stm32_clockevent"; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; - bits = 32; + to->clkevt.rating = 250; } else { prescaler = 1024; - bits = 16; + to->clkevt.rating = 50; } - writel_relaxed(0, data->base + TIM_ARR); - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + + /* adjust rate and period given the prescaler value */ + to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x1, max_delta); +} + +static int __init stm32_timer_init(struct device_node *node) +{ + struct reset_control *rstc; + struct timer_of *to; + int ret; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->of_irq.handler = stm32_clock_event_handler; - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); + ret = timer_of_init(node, to); + if (ret) + goto err; - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; + rstc = of_reset_control_get(node, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); } - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + stm32_clockevent_init(to); - return ret; + return 0; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: +err: + kfree(to); return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Fri Dec 15 08:52:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 122065 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp192652qgn; Fri, 15 Dec 2017 00:53:17 -0800 (PST) X-Google-Smtp-Source: ACJfBoupvtFEX9UqBfwbkmTh8t7b4FOQwsvfEb/n6C7o4SX9qun9l771aMsJHpfdQx316dK1Y/fw X-Received: by 10.84.208.227 with SMTP id c32mr12477269plj.290.1513327997160; Fri, 15 Dec 2017 00:53:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513327997; cv=none; d=google.com; s=arc-20160816; b=zdFcKa/DHeKsEd9uDhKhNICOqDtP1vMK5Vp0ls9K16qw/U8ZqQHu9itq42M3W3hTe7 91ZjW+xUMw/ggP+ja+gS/MVpuiSyztdJf3Rauam382yCeT72xiT/4esHufpvWHLN2By5 uCv9H7uuTUZkjOd8nPSaLaUScnbT0bjMtB57FXS6kyjmO3+2aj9sCpwK4eCH+9t/cApR 4D+8pmL0LZdDMrbQaBaToYLdTOPUdEOQAhBWiMlRQMe63Uq6i4oFu0cIQLnrDzcxP8mL ubxuDJSPe4lXvdbyo79xSCxqe9MpI4fFQRaSUF6KJV9HGb6dyB2N5tCVMd4toXtq23KT fuhQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id f11si4822525plm.77.2017.12.15.00.53.16; Fri, 15 Dec 2017 00:53:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H8MfPQhI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754887AbdLOIxP (ORCPT + 20 others); Fri, 15 Dec 2017 03:53:15 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:45521 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753622AbdLOIxL (ORCPT ); Fri, 15 Dec 2017 03:53:11 -0500 Received: by mail-wm0-f66.google.com with SMTP id 9so15922105wme.4 for ; Fri, 15 Dec 2017 00:53:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7UYSmJ//9Mfom7wNt9+xW9mt5SqRdz1LBQvLuanRgz0=; b=H8MfPQhIj0f7Q3kSiaGLwur9RaQ+bVA/5/8ZCOUzf5mDnEyyZekYhB349AEeug9yHB 88f9t3RlYt3ohcrQ1EvKPWCmGNqhXw2UzTJ7d3+gAvm42tIbnpOKYlRt24CZRV2jBUUZ sh/qK5UHdWkas4vY99GdLKjr0sIdigoZjHuZI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7UYSmJ//9Mfom7wNt9+xW9mt5SqRdz1LBQvLuanRgz0=; b=Ak29pQqQVkepbcKcCh3CMMJ/fX2ZAcRtGyMahW20eBOkaAwpELvAZUnU7kAVEQy/gQ SIjFVOMqq+eK6s3fGYSIE2d9XuXOd2Rwa13hC7KtuhlFAyMEYPEvktmwoHqCXnt/FzDE TmRJ8IQJfvA6Wqxco29Q3upbDK1W7C9mBx9LwFF8N+bfFjjI6LcB+HpNhXD9mXamvQ1T EvtiGSLadzPACNEKgyjculFKnKgTNdb7aem1lBQF7pi8PTXq1nc5Jg2VBKdOLWF469sc wqwf5xhfrVmjrEjrgIGnwbxoZmfk+M0HbceRfVY7qF9BiAUrpFA068Fg8FwZ2oNev+en xeVQ== X-Gm-Message-State: AKGB3mKEGw6EXm6RUEQqgDIZAN6d7BHRWSW25goouMVKwBooZoIme4W+ xaZn0GdZqIje5nAHpMJNLKYOfQ== X-Received: by 10.28.106.16 with SMTP id f16mr4892031wmc.58.1513327989970; Fri, 15 Dec 2017 00:53:09 -0800 (PST) Received: from lmecxl0911.lme.st.com ([80.215.40.214]) by smtp.gmail.com with ESMTPSA id r14sm3211803wra.71.2017.12.15.00.53.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Dec 2017 00:53:09 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 2/4] clocksource: stm32: use prescaler to adjust the resolution Date: Fri, 15 Dec 2017 09:52:45 +0100 Message-Id: <20171215085247.14946-3-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171215085247.14946-1-benjamin.gaignard@st.com> References: <20171215085247.14946-1-benjamin.gaignard@st.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rather than use fixed prescaler values compute it to get a clock as close as possible of 10KHz and a resolution of 0.1ms. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 23a321cca45b..de721d318065 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -37,6 +37,11 @@ #define TIM_EGR_UG BIT(0) +#define MAX_TIM_PSC 0xFFFF + +/* Target a 10KHz clock to get a resolution of 0.1 ms */ +#define TARGETED_CLK_RATE 10000 + static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); @@ -83,7 +88,7 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static void __init stm32_clockevent_init(struct timer_of *to) { unsigned long max_delta; - int prescaler; + unsigned long prescaler; to->clkevt.name = "stm32_clockevent"; to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; @@ -96,13 +101,17 @@ static void __init stm32_clockevent_init(struct timer_of *to) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; + to->clkevt.rating = 50; + if (max_delta == ~0U) to->clkevt.rating = 250; - } else { - prescaler = 1024; - to->clkevt.rating = 50; - } + + /* + * Get the highest possible prescaler value to be as close + * as possible of TARGETED_CLK_RATE + */ + prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to), TARGETED_CLK_RATE); + if (prescaler > MAX_TIM_PSC) + prescaler = MAX_TIM_PSC; writel_relaxed(0, timer_of_base(to) + TIM_ARR); writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); From patchwork Fri Dec 15 08:52:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 122067 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp192767qgn; Fri, 15 Dec 2017 00:53:27 -0800 (PST) X-Google-Smtp-Source: ACJfBovnAbvND2lO9/KkofH2wXZSfzx5CCrTUfSjRrIbz9hU63UY8afuhiJbiNhS8OmzUpvzsmTL X-Received: by 10.98.7.149 with SMTP id 21mr12663165pfh.14.1513328007851; Fri, 15 Dec 2017 00:53:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513328007; cv=none; d=google.com; s=arc-20160816; b=Seanedybu6XcxUTyDMeRjwwBCIgRTPj3jPxKQZtQQN6kuGHH+qCcTiaZlOF8pXkWFs ygkao3Wje6uF9LP2ppDlANEIQjHMJbRPaE6befX9CzRyDgYYm/43d9At8kziRtl/G7A3 r/C4ieDIXqYSAaB06t45n0J2BY2H1jtqjvSS0fkKatFxSW6ugA5LbD/EXFbwUEp+/sn7 A5wWXDzpgbujyvsPNstyvlqDZfpujvOLNGKohuX8Ykjsfm4JYa3p1rSdjgx4qX9lClaN pv0XXsvISgxwO9RilmBPRj7oreRKntJG/yNqtdTVRqxkAyRxqQZhzyTS0sHmb9a/5rvk DBcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=x3KScFFwwOM34xGrbmU5fD1gHbJT73ffPl7KKkyHzWs=; b=sKl+xI2qUnhbDg26Q/CZSB0owAiSrb0a1hUxqOFo7g2xY6HeDdujU4qXXk2SCt2oAe kZfWrlLvctVzydF0kbvZF6H2ke7QsnMNq4HuK2kp0Fzknt+UAhXHuZB+b3iba8drmz07 XdMSIkbxV4/2h38NNPzhB9xbOPL8uD/pZjk5kUdI7g/xDg/OvkKNfRgrO9q19srilDe/ 3V0qj8yRYJ1p5DBZuAlsfQCipfmncpSbFWGg/p1IrfMEry6e1vvTBpfmKrbfQkMPuoaN Cv0qBQaKFYgpeUs1AgmIRdGXkW5BlzhQX/oL2D29B/g6/LfYf8c5HOctpFFGdmZQ/wK+ ZmKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H6dkACLg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Implement this by enabling the free running counter in the hardware block and converting the clock event part from a count down event timer to a comparator based timer. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 114 ++++++++++++++++++++++++++++---------- 1 file changed, 86 insertions(+), 28 deletions(-) -- 2.15.0 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index de721d318065..38eb59bb7f8a 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -24,17 +25,15 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) -#define TIM_CR1_OPM BIT(3) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_ARPE BIT(7) - -#define TIM_DIER_UIE BIT(0) - -#define TIM_SR_UIF BIT(0) - +#define TIM_DIER_CC1IE BIT(1) #define TIM_EGR_UG BIT(0) #define MAX_TIM_PSC 0xFFFF @@ -46,29 +45,44 @@ static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { - struct timer_of *to = to_timer_of(evt); + struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; + + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *evt) { - struct timer_of *to = to_timer_of(clkevt); + struct timer_of *to = to_timer_of(evt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + return stm32_clock_event_set_next_event(timer_of_period(to), evt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *evt) +{ + struct timer_of *to = to_timer_of(evt); + unsigned long val; + + val = readl_relaxed(timer_of_base(to) + TIM_CNT); + writel_relaxed(val, timer_of_base(to) + TIM_CCR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } @@ -80,6 +94,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(evt)) + stm32_clock_event_set_periodic(evt); + else + stm32_clock_event_shutdown(evt); + evt->event_handler(evt); return IRQ_HANDLED; @@ -88,22 +107,46 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static void __init stm32_clockevent_init(struct timer_of *to) { unsigned long max_delta; - unsigned long prescaler; to->clkevt.name = "stm32_clockevent"; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; /* Detect whether the timer is 16 or 32 bits */ + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); + + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x1, max_delta); +} + +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + +static int __init stm32_clocksource_init(struct timer_of *to) +{ + unsigned long max_delta, prescaler; + int bits = 16; + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_DIER); + + /* Detect whether the timer is 16 or 32 bits */ max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); + to->clkevt.rating = 50; - if (max_delta == ~0U) + if (max_delta == ~0U) { + bits = 32; to->clkevt.rating = 250; + } /* * Get the highest possible prescaler value to be as close @@ -113,18 +156,27 @@ static void __init stm32_clockevent_init(struct timer_of *to) if (prescaler > MAX_TIM_PSC) prescaler = MAX_TIM_PSC; - writel_relaxed(0, timer_of_base(to) + TIM_ARR); writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); - writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - writel_relaxed(0, timer_of_base(to) + TIM_SR); - /* adjust rate and period given the prescaler value */ + /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); - clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + /* Make sure that registers are updated */ + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + + /* Enable controller */ + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_UDIS | TIM_CR1_CEN, + timer_of_base(to) + TIM_CR1); + + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + + return clocksource_mmio_init(stm32_timer_cnt, "stm32_timer", + timer_of_rate(to), + to->clkevt.rating, + bits, + clocksource_mmio_readl_up); } static int __init stm32_timer_init(struct device_node *node) @@ -150,10 +202,16 @@ static int __init stm32_timer_init(struct device_node *node) reset_control_deassert(rstc); } + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0; +deinit: + timer_of_cleanup(to); err: kfree(to); return ret; From patchwork Fri Dec 15 08:52:47 2017 Content-Type: text/plain; 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