From patchwork Wed Dec 20 03:23:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122425 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5023172qgn; Tue, 19 Dec 2017 19:23:59 -0800 (PST) X-Google-Smtp-Source: ACJfBouuUlynfllJDxlNlgyd5joKwDA7ZhfONQvig61bkkZWcsiNrkLvFxUGIKNfbo2j8tZiI7ui X-Received: by 10.99.124.16 with SMTP id x16mr5038539pgc.124.1513740239156; Tue, 19 Dec 2017 19:23:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513740239; cv=none; d=google.com; s=arc-20160816; b=Akz3xbGYxt9WD/AiyIOpCGiPecHNtJXBvbCPJ2VAjWULE4wiZmmfGYkyrDxhWbVEot e4KpNfIfJDn9wTJwxxu7pmmWFuPxz+WNzCD8GiWNaRWA/qMQ6bMyqxudNPL2d2W+FYiF hMe6V933ssIaIxT1SifCDS+Spmkqn5LW8V4PBLsPEqOoHlD8MIcpIijZ3xffO3GgE4wm Ig8HtzEbnh/xyqE4a2HCK/y+XzMSjIihID+mYbgoycpVp1oTlLjEI3wXOxKad+onjM3l c0sFKTN+/fVHrV7hXH/d0qoPpvY4Hvcrn0DTfb4HZ0F5o3nY28Or2pW0KlYO05pvz4W9 LlLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ze+JuOa60vVGBhQnjigFdC6hHooPXhlwZbRqSD5pVzA=; b=xUREsD0SyboS7TJBWnC+lxbcx2Jc6p0ZJavB83cTBvN/5v8xWuiM27fdNxPR9Mb510 OV2g8r6TKWuaQuANTq77yKISFGvsRDzqXXwzc6pRcH7nlV2eLWQ6JFO5ffR+PxaJgpMZ iVgVQwfu5Xf6uSPewwF04RysIKHUjFAts/Gz+tL0PTglN4VL+BKQXc4Cte9CTh1jMekI DSaPjq1MLP5lkJZnu+ubMfOZ6e+QsQu3AXlem7PSVdDZbPKt4+C5PeCO1uChGcCCf1tT fyK1wXhPv2dtn0uHPHWmxlNm01A0izR4v/TvXIC30eBn4kHVmWTzyU3E+YpFoHt32YH8 a9vg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=HaX8jmkf; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b16si12303840pff.393.2017.12.19.19.23.58; Tue, 19 Dec 2017 19:23:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=HaX8jmkf; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754163AbdLTDX6 (ORCPT + 6 others); Tue, 19 Dec 2017 22:23:58 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:34573 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754066AbdLTDXz (ORCPT ); Tue, 19 Dec 2017 22:23:55 -0500 Received: by mail-pf0-f193.google.com with SMTP id a90so12044556pfk.1; Tue, 19 Dec 2017 19:23:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=qVQjG69OVGroY4sMhtMvjqc4NJ8LxXjPbh0xVWvmdE8=; b=HaX8jmkfEtqXzRs+rWKaJ2SK1DAT0/po5yJjKpMmLJA0VDkmiOCiIrC5+VS86FEt3J OFST8smdM2R24YJ63Jr0UWRAEN8NUpoQ7Go4KFGIF5Um84SBOfK+aPUuO+nX6fie5jy5 zhzTuZ+cpAMfnC4h/LaXJjb57KHJSQ2p0yy7gwxxfgmZGEx2+aIkm7lR+wFEnbECVlHl TLzt9G0v0B68QLGbTBJgUj8GSBrCKUmqMiSQgYNUmv7BkInyOC90c7GPBw4a3abS3HtT bwT0C+9/09Gks7VK8Cx8H1lJYkZlARRo4FchHKp7BS+lrOhbYhagQIKc3X4soUP0HoIp mhcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=qVQjG69OVGroY4sMhtMvjqc4NJ8LxXjPbh0xVWvmdE8=; b=H0FdK8oJXGBX2gFSSOUZc9Bg6/6M54Orjuua1tPv/Vno0ah4ut/EFgaKyWIoYcbmf2 jy7HGGvFC61LEtrn2dZbRywbF9orcq8oIND0DYa2fEB6lOqDXiWpjQ2+oe0daYaLn5D2 MJDIcw0jQ8L15jbc+OvHfe2eR/MCRVTPLGJFmwOL4GSD8+Qt1//PAnWEJ2z6Sy29iXLh s3Jc+3TLUXL8zGN6NYbNksfi26JQ0IhVbkmXknTGgLdUv6yF+PZq4SDB0SE39iEJBw5b glT2gzdhVqhySwUgmk1yzmVOkBj+1x2imC0vfbTPDTzmvQrdU3RZZMAVlo01CjwivZSO o3yQ== X-Gm-Message-State: AKGB3mJX18YIACuB7NMZar4Bpj2sHNjldcq7qVAX2BbxAD0ZPszg8bWw mp4qR/wA86Wrc1gglgKpRWM= X-Received: by 10.99.95.13 with SMTP id t13mr5044073pgb.235.1513740235014; Tue, 19 Dec 2017 19:23:55 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.15]) by smtp.gmail.com with ESMTPSA id m25sm35179465pfk.37.2017.12.19.19.23.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Dec 2017 19:23:53 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 20 Dec 2017 13:53:43 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 01/20] dt-bindings: clock: Add ASPEED constants Date: Wed, 20 Dec 2017 13:53:09 +1030 Message-Id: <20171220032328.30584-2-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171220032328.30584-1-joel@jms.id.au> References: <20171220032328.30584-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These will be used by the clock driver. This commit is included so the tree will build without the clock series being applied. Reviewed-by: Rob Herring Signed-off-by: Joel Stanley --- v3: - Clarify that the clock defines will be merged as part of the dt changes, so that the device tree merge will not depend on the clock tree v2: - remove NUM_CLKS define. There's no need for it to be part of ABI --- include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..d3558d897a4d --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 + +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + +#endif From patchwork Wed Dec 20 03:23:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122427 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5023464qgn; Tue, 19 Dec 2017 19:24:22 -0800 (PST) X-Google-Smtp-Source: ACJfBouoPVKP+iSGgLjgtsbcfycPXN80YtTvW63j8ZuBFVX//h4UFGeYvkFlP7GrKAZ/VZ646Wvp X-Received: by 10.101.77.201 with SMTP id q9mr4910355pgt.226.1513740262596; Tue, 19 Dec 2017 19:24:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513740262; cv=none; d=google.com; s=arc-20160816; b=TVgH8pmTL6NhB8L7C/upvPzzd3Yxnt5mOGsiPB0TRP77y3DtTJ6eORdQ76UPOChYir ImUbVKeRX56/r9frJ6QNnFDjpRk+H6WgI5wU60EVEAgVePTBF7YbmPQhaKkapSOwxM2d cFmA1vs31Nps/R3PympWB2r3wBrAVdHtVbr+5y2BYmKKklcnV7RyBoaeqrduS88QsMOQ l26zFjMnqITykKwGwaZnk8xUKwahmEhP0ZhXFrW0yWOEEg+p2imoXBGtaaIgyHuBD59i ADtVMmR27yD7bc+705Xr7ggG0Trf4FbgBeqYTUJ14ePSMBjlufQb2Z9LWf0lp5M5a428 En3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=oSWOOggDCmccZCnPlc3Xky09lMfjcTdZ37Sg649AkyE=; b=kvSmG1EJuvpm/W3YNNNJIS+sHREPRAHrM/wHe0dGoQvL6J6quw6AYBFokXN6URylQh bmgra//VZoNhjX4K6tOeuh+qHlHmYW8CnWLdIcYm99wlTcCFJ4zqdReP0ZtgMJiaqnZS wtlRTwZs5YGG5p5L407s9YU5fpOxejpIt2TCquvjbuVxEy2cI44cK7f8JpFGx2q0zpVY N8cGFBa22hgxXviQd6hpaFMMfuSYRif863d+vbOX2aFl56jndktWHkDdZ10wnFhRx5EF mgc9OU6UvMwuyAQ0lgirNev8RGRGi88U/rYjujAZINSw5wkpmt/jC0hQjyhJxn/v5/hH haVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=oRanezNK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u123si5906703pgb.688.2017.12.19.19.24.22; Tue, 19 Dec 2017 19:24:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=oRanezNK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754221AbdLTDYV (ORCPT + 6 others); Tue, 19 Dec 2017 22:24:21 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:38996 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754219AbdLTDYS (ORCPT ); Tue, 19 Dec 2017 22:24:18 -0500 Received: by mail-pl0-f67.google.com with SMTP id bi12so8248407plb.6; Tue, 19 Dec 2017 19:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Uc41YSmCbf9e/JHG4oPWkJ4qmL2lsMQJg7WfyPdtuTk=; b=oRanezNK5m4DuLDENcc7rND1xgy23jf+c4OBRJG/Ha8GkCUTgpvAsog8Cj0f5ECACN rdTK50X2+UeT/99hBkb2EmstGUXRRaMKQNV/1UIdE89qb5/05rHlN71ILSq2fv0396Mv +Nj1fFxugDwVZ9EclXv9NyFMD1Yc+bN4SpKfLU7m1UB8U8mdl+l8QJS3AOgT6knX+gcv PDfrP3NOg2Yxw3PyTtUQCvhGcUq+qnqgpoOITM6qTgSfu5rfRx5WUrVNjmK6WDVlaBuF gQ5rF7GFuCH0cb0wOb1VOY0+oa0kcLam8Q1IWzbbdXZCoRbkYAJ3kukLgoHU5xYQ8TIh Llhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Uc41YSmCbf9e/JHG4oPWkJ4qmL2lsMQJg7WfyPdtuTk=; b=V+oYex6GthCbQHyoWqqoR+QFrDbTdOVrLxXDuuXALzZyrLgshzH+K9SGBguaCV3ZRb ZGpdAty8p3qCAvxHg4pxtrlG3IDkzK4YBx5OTg8NPrchngMQjOxGXBmnt6ycX1tPxu99 XsyFHWzqQHe+PcevuLraLHa+Sg1UBFkzzKu/MDsPPpvNXjRTZbZFNMjVG2WCaPkYt7p3 kH2BRllX0zN8JuqPWjbLRmuAVCjTpBWHp5ko97U8FOJLEfFX9zFEi6WifdbpHPwVap7a ylTdoWhZGOqFh01urq2AxiXqtK7J8Z81sPUMbPk/OlhZv2+6U1p2EdcmsdJhkd9ne+co uQxw== X-Gm-Message-State: AKGB3mIN3FfDbCYzX6E1wRMCwWa+412J3GKvAJIlpUlUfuAvn0emOmUm y0yiVJA2Rset0IobKzVarYQ= X-Received: by 10.84.128.45 with SMTP id 42mr5482357pla.44.1513740257858; Tue, 19 Dec 2017 19:24:17 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.15]) by smtp.gmail.com with ESMTPSA id k2sm28577205pff.150.2017.12.19.19.24.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Dec 2017 19:24:16 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 20 Dec 2017 13:54:07 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 03/20] ARM: dts: aspeed: Add LPC and child devices Date: Wed, 20 Dec 2017 13:53:11 +1030 Message-Id: <20171220032328.30584-4-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171220032328.30584-1-joel@jms.id.au> References: <20171220032328.30584-1-joel@jms.id.au> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Andrew Jeffery Ensure the ordering is correct and add all of the children in the SoC device trees for the ast2400 and ast2500. Signed-off-by: Andrew Jeffery Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- v3: - Fix ast2400 compatible string --- arch/arm/boot/dts/aspeed-g4.dtsi | 35 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/aspeed-g5.dtsi | 27 +++++++++++++++++---------- 2 files changed, 52 insertions(+), 10 deletions(-) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 45d815a86d42..9422f9cb1e11 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -225,6 +225,41 @@ status = "disabled"; }; + lpc: lpc@1e789000 { + compatible = "aspeed,ast2400-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2400-lpc-bmc"; + reg = <0x0 0x80>; + }; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; + + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2400-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; + }; + + lhc: lhc@20 { + compatible = "aspeed,ast2400-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + }; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 5c4ecdba3a6b..069f13df19d1 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -265,6 +265,16 @@ status = "disabled"; }; + vuart: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + lpc: lpc@1e789000 { compatible = "aspeed,ast2500-lpc", "simple-mfd"; reg = <0x1e789000 0x1000>; @@ -288,6 +298,13 @@ reg-io-width = <4>; + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2500-lpc-ctrl"; + reg = <0x0 0x80>; + status = "disabled"; + }; + + lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; reg = <0x20 0x24 0x48 0x8>; @@ -295,16 +312,6 @@ }; }; - vuart: serial@1e787000 { - compatible = "aspeed,ast2500-vuart"; - reg = <0x1e787000 0x40>; - reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; - no-loopback-test; - status = "disabled"; - }; - uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; From patchwork Wed Dec 20 03:23:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122428 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5023614qgn; Tue, 19 Dec 2017 19:24:34 -0800 (PST) X-Google-Smtp-Source: ACJfBouHfe+m4TiZDYy+8CiSPfQoIdARLbawcLp+WVkVgxgdY4KIgvhb435x5nRaavLb6SpGh9lQ X-Received: by 10.101.66.204 with SMTP id l12mr4943174pgp.430.1513740274866; Tue, 19 Dec 2017 19:24:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513740274; cv=none; d=google.com; s=arc-20160816; b=Wic0e8kct3BQmEvzHQtIt1F3hqDYc81oiBYTbLJiCuSZBXyvjt331r5IxwG5VtEHw+ Q/HaWoTKhavn4hAWRuDAUFlkxNauqeZx/HLdnfMR/hbCyJnOY5yav2horZERdIGsxKD5 Y9ZzEKYCItpvsWJcyS6kIm+UoxV27O6QqdonboW/XwuDViYboO0n332cIf2M3hIJ7Ks1 QE1FFYHWjh2Vo5YMUQiMRWHOjj233i2tOQddTQJaNZO8QEbxnlvIU/AsaFtgabh3FR+9 wowMaMG3xz08/VxCq8iuv/cOVz1toIezs2f5GVjS5Zi0y1k2/g0Zg/zJ2uxW6cfx62im VrAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GNWwkzvabox/am+E0rOSgCT1aUk8JgNhRzlQLrPC/xs=; b=rQnq7JO/+FNxHvTUTwURAyOlRQfeUWDWvvV1UFdZGcmk3RCw9YICU9w93pjA0Dgd5B LQTjhH6hsVy1VpT8luoKyReJryMCyQSHptl+8VQFXynuavIDDdrukLKgTt+mrwV50Tl6 ktrCvwoMUitjPooJS6aAWmpb5wPUmumr8pIMAy28EjmkJCnlZJq2Y4zNlQWpn3arcpWg 8UW28OqafAgHQojvpUVZNAPhCPwoi1/Fq3otSo2XpevKbQiOtUQZGAHidMqQ9ghPM9Ch aZiBM/hdf0PSVB8qgbUVvI5vQcRwgJxkoYN4sQd9GKICqOqGRUEoFulB/ckTm6U5dOWT TIVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=cpGN7PsW; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e33si1179459pld.518.2017.12.19.19.24.34; Tue, 19 Dec 2017 19:24:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=cpGN7PsW; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754258AbdLTDYc (ORCPT + 6 others); Tue, 19 Dec 2017 22:24:32 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:35128 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754134AbdLTDYa (ORCPT ); Tue, 19 Dec 2017 22:24:30 -0500 Received: by mail-pl0-f65.google.com with SMTP id b96so8253507pli.2; Tue, 19 Dec 2017 19:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=YAFk32UXsC8ypS5D+i4dSXTON91rgfD/GAp8lMYWs0A=; b=cpGN7PsWFSnYsKm8saZsLvcgM1eyZILw3SJnZBI6P0n3GkLmkN4YbMLZT2HxASeZu9 l+aVeq2aj7hp+GnSlUIUd0KysBhQIohavQonpccIL2XtjPFOrMMmOJWVurdGWcQ/hpIo 883rW7olY03GRMCv+5wPtlRZk3546rPrbGzxmaRMo/sQF7q+MjjhTjiveYqyauRXeHzN PF3VKezcqpdX5blcv/mYXhWftzKUlEVp+RaQY0eGRRKHvoNifAaNX68aUdfAq/iQp0I+ YpnWrUy0nFI7CqyMRkN0+IKLjKdft/GAJ4LheILYLeKV+N5W3+D1FVbbKVjgzsxga1Tv iyYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=YAFk32UXsC8ypS5D+i4dSXTON91rgfD/GAp8lMYWs0A=; b=DbedK7JfNSbDMYDwL2c8rgzkRyYEoQwDrmNtfvLrMc1qZ6pnT6YAcBP30FJtQYw9iU oCoMOhMj95dUElO1xuR0lELJJHKFlbiNan1TJ+wuF+xko9ShR9DWfRMdu9XPM0LZWp0h nbtB8EE/2Gbu90EmwghmRA8ebh+NHStGb444izRlsFQ41WvQT6yJMOdRPmstphf/hAld niCdLkrnnojCJmyifz9k/nN1e+pRewewqFhDAytpLTI+eH0jhxQbXYXjPEZYRRlWE4rH q8wRBTselOImxSFMmWz4ZSzGdVbh+PKjqqWcZJqTowDVUIYkZvaUbH8hHHqP0eBvdI8a XwWw== X-Gm-Message-State: AKGB3mKBB0Bqv5yC6dOD2gUBZLuLfivZreBKgT4OYFkzwPwF4vcAKjVj m5zD27RgaFFRYzsC2gzRh8o= X-Received: by 10.84.133.132 with SMTP id f4mr5572591plf.413.1513740269342; Tue, 19 Dec 2017 19:24:29 -0800 (PST) Received: from aurora.jms.id.au ([45.124.203.15]) by smtp.gmail.com with ESMTPSA id 68sm30850161pfx.186.2017.12.19.19.24.22 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 19 Dec 2017 19:24:28 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Wed, 20 Dec 2017 13:54:18 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Benjamin Herrenschmidt , Jeremy Kerr , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org Subject: [PATCH v3 04/20] ARM: dts: aspeed: Add proper clock references Date: Wed, 20 Dec 2017 13:53:12 +1030 Message-Id: <20171220032328.30584-5-joel@jms.id.au> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171220032328.30584-1-joel@jms.id.au> References: <20171220032328.30584-1-joel@jms.id.au> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This device tree will break existing kernels that do not have the clk patches applied (no clocksource, as we don't know the speed of the APB clock. You can boot if you pass a lpj value on the command line, but won't have a uart). Older device trees running with the newer kernel will function as well as pre-4.16 kernels. That is, that some IP blocks (i2c, pwm/tach, adc) will not work as the kernel lacks reset controller and clock enabling. This is being changed as existing device trees use fixed-clocks in order to boot without a clk driver. The newly added clk driver provides proper clock support, including gating, so we move the device trees over to properly request clocks. The SCU compatible string is updated as the g4-scu string made it into the tree before we decided on aspeed,astX000- as the format for the strings. The old string will be removed from the bindings in a future patch. Signed-off-by: Joel Stanley --- v3: - Add reset phandle to ADC node v2: - Add more detail to the commit message adc reset Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 103 ++++++++++++++++---------------------- arch/arm/boot/dts/aspeed-g5.dtsi | 105 ++++++++++++++++----------------------- 2 files changed, 84 insertions(+), 124 deletions(-) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 9422f9cb1e11..b938759f799e 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "skeleton.dtsi" +#include / { model = "Aspeed BMC"; @@ -106,47 +107,12 @@ ranges; syscon: syscon@1e6e2000 { - compatible = "aspeed,g4-scu", "syscon", "simple-mfd"; + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; #address-cells = <1>; #size-cells = <0>; - - clk_clkin: clk_clkin { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <48000000>; - }; - - clk_hpll: clk_hpll@70 { - #clock-cells = <0>; - compatible = "aspeed,g4-hpll-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_clkin>; - clock-frequency = <384000000>; - }; - - clk_ahb: clk_ahb@70 { - #clock-cells = <0>; - compatible = "aspeed,g4-ahb-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_hpll>; - clock-frequency = <192000000>; - }; - - clk_apb: clk_apb@8 { - #clock-cells = <0>; - compatible = "aspeed,g4-apb-clock", "fixed-clock"; - reg = <0x08>; - clocks = <&clk_hpll>; - clock-frequency = <48000000>; - }; - - clk_uart: clk_uart@2c{ - #clock-cells = <0>; - compatible = "aspeed,g4-uart-clock", "fixed-clock"; - reg = <0x2c>; - clock-frequency = <24000000>; - }; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,g4-pinctrl"; @@ -156,7 +122,8 @@ adc: adc@1e6e9000 { compatible = "aspeed,ast2400-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; status = "disabled"; }; @@ -181,7 +148,7 @@ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; clock-names = "PCLK"; }; @@ -190,7 +157,7 @@ reg = <0x1e783000 0x20>; reg-shift = <2>; interrupts = <9>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; no-loopback-test; status = "disabled"; }; @@ -200,7 +167,7 @@ reg = <0x1e784000 0x20>; reg-shift = <2>; interrupts = <10>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; no-loopback-test; status = "disabled"; }; @@ -219,8 +186,8 @@ compatible = "aspeed,ast2400-vuart"; reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; status = "disabled"; }; @@ -265,7 +232,7 @@ reg = <0x1e78d000 0x20>; reg-shift = <2>; interrupts = <32>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; no-loopback-test; status = "disabled"; }; @@ -275,7 +242,7 @@ reg = <0x1e78e000 0x20>; reg-shift = <2>; interrupts = <33>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; no-loopback-test; status = "disabled"; }; @@ -285,7 +252,7 @@ reg = <0x1e78f000 0x20>; reg-shift = <2>; interrupts = <34>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; no-loopback-test; status = "disabled"; }; @@ -316,7 +283,8 @@ reg = <0x40 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; @@ -331,7 +299,8 @@ reg = <0x80 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <1>; interrupt-parent = <&i2c_ic>; @@ -346,7 +315,8 @@ reg = <0xc0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <2>; interrupt-parent = <&i2c_ic>; @@ -362,7 +332,8 @@ reg = <0x100 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <3>; interrupt-parent = <&i2c_ic>; @@ -378,7 +349,8 @@ reg = <0x140 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <4>; interrupt-parent = <&i2c_ic>; @@ -394,7 +366,8 @@ reg = <0x180 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <5>; interrupt-parent = <&i2c_ic>; @@ -410,7 +383,8 @@ reg = <0x1c0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <6>; interrupt-parent = <&i2c_ic>; @@ -426,7 +400,8 @@ reg = <0x300 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <7>; interrupt-parent = <&i2c_ic>; @@ -442,7 +417,8 @@ reg = <0x340 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <8>; interrupt-parent = <&i2c_ic>; @@ -458,7 +434,8 @@ reg = <0x380 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <9>; interrupt-parent = <&i2c_ic>; @@ -474,7 +451,8 @@ reg = <0x3c0 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <10>; interrupt-parent = <&i2c_ic>; @@ -490,7 +468,8 @@ reg = <0x400 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <11>; interrupt-parent = <&i2c_ic>; @@ -506,7 +485,8 @@ reg = <0x440 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <12>; interrupt-parent = <&i2c_ic>; @@ -522,7 +502,8 @@ reg = <0x480 0x40>; compatible = "aspeed,ast2400-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <13>; interrupt-parent = <&i2c_ic>; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 069f13df19d1..1af600b48475 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include "skeleton.dtsi" +#include / { model = "Aspeed BMC"; @@ -140,55 +141,18 @@ ranges; syscon: syscon@1e6e2000 { - compatible = "aspeed,g5-scu", "syscon", "simple-mfd"; + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; #address-cells = <1>; #size-cells = <0>; - - clk_clkin: clk_clkin@70 { - #clock-cells = <0>; - compatible = "aspeed,g5-clkin-clock", "fixed-clock"; - reg = <0x70>; - clock-frequency = <24000000>; - }; - - clk_hpll: clk_hpll@24 { - #clock-cells = <0>; - compatible = "aspeed,g5-hpll-clock", "fixed-clock"; - reg = <0x24>; - clocks = <&clk_clkin>; - clock-frequency = <792000000>; - }; - - clk_ahb: clk_ahb@70 { - #clock-cells = <0>; - compatible = "aspeed,g5-ahb-clock", "fixed-clock"; - reg = <0x70>; - clocks = <&clk_hpll>; - clock-frequency = <198000000>; - }; - - clk_apb: clk_apb@8 { - #clock-cells = <0>; - compatible = "aspeed,g5-apb-clock", "fixed-clock"; - reg = <0x08>; - clocks = <&clk_hpll>; - clock-frequency = <24750000>; - }; - - clk_uart: clk_uart@2c { - #clock-cells = <0>; - compatible = "aspeed,uart-clock", "fixed-clock"; - reg = <0x2c>; - clock-frequency = <24000000>; - }; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,g5-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; }; - }; gfx: display@1e6e6000 { @@ -200,7 +164,8 @@ adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_ADC>; #io-channel-cells = <1>; status = "disabled"; }; @@ -225,7 +190,7 @@ compatible = "aspeed,ast2400-timer"; reg = <0x1e782000 0x90>; interrupts = <16 17 18 35 36 37 38 39>; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; clock-names = "PCLK"; }; @@ -234,7 +199,7 @@ reg = <0x1e783000 0x20>; reg-shift = <2>; interrupts = <9>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; no-loopback-test; status = "disabled"; }; @@ -244,7 +209,7 @@ reg = <0x1e784000 0x20>; reg-shift = <2>; interrupts = <10>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; no-loopback-test; status = "disabled"; }; @@ -269,8 +234,8 @@ compatible = "aspeed,ast2500-vuart"; reg = <0x1e787000 0x40>; reg-shift = <2>; - interrupts = <10>; - clocks = <&clk_uart>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; no-loopback-test; status = "disabled"; }; @@ -317,7 +282,7 @@ reg = <0x1e78d000 0x20>; reg-shift = <2>; interrupts = <32>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; no-loopback-test; status = "disabled"; }; @@ -327,7 +292,7 @@ reg = <0x1e78e000 0x20>; reg-shift = <2>; interrupts = <33>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; no-loopback-test; status = "disabled"; }; @@ -337,7 +302,7 @@ reg = <0x1e78f000 0x20>; reg-shift = <2>; interrupts = <34>; - clocks = <&clk_uart>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; no-loopback-test; status = "disabled"; }; @@ -368,7 +333,8 @@ reg = <0x40 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <0>; interrupt-parent = <&i2c_ic>; @@ -383,7 +349,8 @@ reg = <0x80 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <1>; interrupt-parent = <&i2c_ic>; @@ -398,7 +365,8 @@ reg = <0xc0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <2>; interrupt-parent = <&i2c_ic>; @@ -414,7 +382,8 @@ reg = <0x100 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <3>; interrupt-parent = <&i2c_ic>; @@ -430,7 +399,8 @@ reg = <0x140 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <4>; interrupt-parent = <&i2c_ic>; @@ -446,7 +416,8 @@ reg = <0x180 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <5>; interrupt-parent = <&i2c_ic>; @@ -462,7 +433,8 @@ reg = <0x1c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <6>; interrupt-parent = <&i2c_ic>; @@ -478,7 +450,8 @@ reg = <0x300 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <7>; interrupt-parent = <&i2c_ic>; @@ -494,7 +467,8 @@ reg = <0x340 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <8>; interrupt-parent = <&i2c_ic>; @@ -510,7 +484,8 @@ reg = <0x380 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <9>; interrupt-parent = <&i2c_ic>; @@ -526,7 +501,8 @@ reg = <0x3c0 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <10>; interrupt-parent = <&i2c_ic>; @@ -542,7 +518,8 @@ reg = <0x400 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <11>; interrupt-parent = <&i2c_ic>; @@ -558,7 +535,8 @@ reg = <0x440 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <12>; interrupt-parent = <&i2c_ic>; @@ -574,7 +552,8 @@ reg = <0x480 0x40>; compatible = "aspeed,ast2500-i2c-bus"; - clocks = <&clk_apb>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_I2C>; bus-frequency = <100000>; interrupts = <13>; interrupt-parent = <&i2c_ic>; From patchwork Wed Dec 20 03:23:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122444 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5025834qgn; Tue, 19 Dec 2017 19:27:23 -0800 (PST) X-Google-Smtp-Source: ACJfBov6kazErutaRgBVfA4VmaLUcZ2W8BxSL5DQCRfC5ddF13ZH6sIqWBU9D9ilw1yaTcqOmuHk X-Received: by 10.84.193.129 with SMTP id f1mr5346019pld.363.1513740443631; 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Add the unit name to the memory node to fix a warning with W=1. Reviewed-by: Cédric Le Goater Signed-off-by: Joel Stanley --- v3: - Added memory node unit name --- arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index a8f0c046e83e..4379d09a261f 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -12,7 +12,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@40000000 { reg = <0x40000000 0x20000000>; }; @@ -34,6 +34,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; +#include "openbmc-flash-layout.dtsi" }; }; From patchwork Wed Dec 20 03:23:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 122445 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5025962qgn; Tue, 19 Dec 2017 19:27:34 -0800 (PST) X-Google-Smtp-Source: ACJfBovsDoQIslDgij+JNv6xkCRJgDRIbK4JrpJcR5/jQhGBSThY1xl4k5jMuwnf7RPLXk6gaaZT X-Received: by 10.99.60.23 with SMTP id j23mr4913094pga.256.1513740454759; Tue, 19 Dec 2017 19:27:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513740454; cv=none; d=google.com; s=arc-20160816; b=t83NVEGj0afnHqZSgER+UGg8TLTJpwOK/WqwbOg5bJuZ1d16tsHwf1Yv/DeXaD61WZ mAhUVfq3Cq6tX2HH1C+wbjsMP3xg8LZUQg8AnpTnPpMdG7Et7u9cCzb4SRyccrurUuyI D8XPIZbk6aFDxKAKjLYUPF1nRcuhAedGEKn8gq5kNM/cUEkqyx6ByP/4cQQnFkFO9zAw sf7r7kslMT/dbaVNWC7ud82/jFEC2KUZP4PUtOfXZunlvJJlNrbNhJh4S6ZpMLyqeg9Y qWs0WPWuwCR1mBMSOUsoBREL31CaVNsXOoehpT05AOxFvjiTzA2IE9KvsS258YyLNUWl ue0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=GERG+KJtTIMIzADFRrxXJLXvHfk6hMgiatWlIl43rOQ=; b=IqXniwEYCrhr7UHsiY0p9JhJcL0zNvEtx7nUx1ZirB62xMDzsCYzRfHlHcEYJ7l4gJ Hf8PooZZcIg2z5ypnbkwZvuEgoYG6eVZQxbdkImAbRamW58y4Bt97CkNgEgp5M/YnlJP moRT/FY0yL6RzFyggzkWqNpOIl0VvqS8ogY+AK019qgpzbxtI9+fKU9rJF3OrIVcBB/Y HIgij755G70sUdn6OmfofSKdcvsQGMVltOU339xdlufWLqqlttw+UChwzQYt9PZ41GkW xUeICDUd/zHe31q9PZUHR9F77s6TuY3lB/vecPsfoB07CQ+oceT6OIrI4kxI/yVYOaKs CzUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=OFMeUbF1; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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All of the ASPEED device trees build without warnings now. Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.15.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 3e6f38e5d5d0..91a36c1f029b 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -16,7 +16,7 @@ bootargs = "console=ttyS4,115200 earlyprintk"; }; - memory { + memory@80000000 { reg = <0x80000000 0x20000000>; }; };