From patchwork Mon Sep 28 11:44:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 313641 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3208857ilg; Mon, 28 Sep 2020 04:45:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxJW4NKW9Y1fMXibvl0X7zV+mziHoLQmFvZTOtYypdZJG1Rd3iXdD/E4MMgbqcFqbBbdzon X-Received: by 2002:a50:cfc5:: with SMTP id i5mr1214794edk.151.1601293508196; Mon, 28 Sep 2020 04:45:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601293508; cv=none; d=google.com; s=arc-20160816; b=riALVeptPd0RtuiKDvVx5NWW0gEm9DEjEJ5J6qkc/QhrqMWw9bIssDD50Xsm26nIcr nrK1QxhY86BiPROflmtCvnzgFuxXZhd7wxuBIoZeDphmzC71gGKa4Xoyar2Wk6m0tyh0 doSZxkzwosa/mHHXFmIK4kDLnhKKDTA0PcqayJNzzhaS7qGADoujUxCj3VRgpUDauC6D FysqZU8FV8DX2gDvXnI7bYeOzFshJg6z2JGa5Y9fqnVi2zfvTNhmhZG3+zUqSj+HlXSI bRN1KPWW1mCMKyt4Q1z8yOHTkxdEOr2TFCM1w+PevOSQmRzl5Irsjk9MmoHPIkkfNUUW An5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=bF5gXXr+ssmc7bZu2xeC0A/E2MTwIXKkSJH63heuYHo=; b=Ss+mp4Vk0/nlnerR7+XtXlbqZeGH4h/UGHz1HUdUFVzjUQbyWJP5onsfKzikJTl1ya 0ukXoDp5O9/H8igBH9mFf+etYcaIJW5sJbJuMefHNGbDiJDdAlcw9yppyLXrqnuK7xsJ Hmza4fKd3qUMmvto/yxQuecDI3IUiq2uRxRTRderR4yLKaXEQXTMvOxnDUVxSW1zac6t Olh5xnflRUQMFUYDnezV0jHoD1taGzealRTPnB8crvaYrAT4BkRcUTkfLeKRdbNiM6QD 7IuM1ccd6mtQl/AiOG3+ic8Ai6Jb8ILfHhYR+Ji0CPtvBSOmeLFpoRVvlz8qvfw++qNv wYIg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si426233edv.488.2020.09.28.04.45.08; Mon, 28 Sep 2020 04:45:08 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726667AbgI1Lo6 (ORCPT + 6 others); Mon, 28 Sep 2020 07:44:58 -0400 Received: from foss.arm.com ([217.140.110.172]:50010 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726566AbgI1Loz (ORCPT ); Mon, 28 Sep 2020 07:44:55 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DEA14113E; Mon, 28 Sep 2020 04:44:54 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 59EF43F6CF; Mon, 28 Sep 2020 04:44:53 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH 1/4] dt-bindings: mailbox : arm,mhu: Convert to Json-schema Date: Mon, 28 Sep 2020 12:44:42 +0100 Message-Id: <20200928114445.19689-2-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928114445.19689-1-sudeep.holla@arm.com> References: <20200928114445.19689-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Viresh Kumar Convert the DT binding over to Json-schema. Reviewed-by: Rob Herring Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/mailbox/arm-mhu.txt | 43 --------- 2 files changed, 87 insertions(+), 43 deletions(-) create mode 100644 Documentation/devicetree/bindings/mailbox/arm,mhu.yaml delete mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml new file mode 100644 index 000000000000..2c8df7979c22 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/arm,mhu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM MHU Mailbox Controller + +maintainers: + - Jassi Brar + +description: | + The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3 + independent channels/links to communicate with remote processor(s). MHU links + are hardwired on a platform. A link raises interrupt for any received data. + However, there is no specified way of knowing if the sent data has been read + by the remote. This driver assumes the sender polls STAT register and the + remote clears it after having read the data. The last channel is specified to + be a 'Secure' resource, hence can't be used by Linux running NS. + +# We need a select here so we don't match all nodes with 'arm,primecell' +select: + properties: + compatible: + contains: + const: arm,mhu + required: + - compatible + +properties: + compatible: + items: + - const: arm,mhu + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + items: + - description: low-priority non-secure + - description: high-priority non-secure + - description: Secure + maxItems: 3 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + '#mbox-cells': + description: Index of the channel. + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuA: mailbox@2b1f0000 { + #mbox-cells = <1>; + compatible = "arm,mhu", "arm,primecell"; + reg = <0 0x2b1f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scb: scb@2e000000 { + compatible = "fujitsu,mb86s70-scb-1.0"; + reg = <0 0x2e000000 0 0x4000>; + mboxes = <&mhuA 1>; /* HP-NonSecure */ + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt deleted file mode 100644 index 4971f03f0b33..000000000000 --- a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt +++ /dev/null @@ -1,43 +0,0 @@ -ARM MHU Mailbox Driver -====================== - -The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has -3 independent channels/links to communicate with remote processor(s). - MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. -The last channel is specified to be a 'Secure' resource, hence can't be -used by Linux running NS. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "arm,mhu" & "arm,primecell" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 3 links of MHU. - -Example: --------- - - mhu: mailbox@2b1f0000 { - #mbox-cells = <1>; - compatible = "arm,mhu", "arm,primecell"; - reg = <0 0x2b1f0000 0x1000>; - interrupts = <0 36 4>, /* LP-NonSecure */ - <0 35 4>, /* HP-NonSecure */ - <0 37 4>; /* Secure */ - clocks = <&clock 0 2 1>; - clock-names = "apb_pclk"; - }; - - mhu_client: scb@2e000000 { - compatible = "fujitsu,mb86s70-scb-1.0"; - reg = <0 0x2e000000 0x4000>; - mboxes = <&mhu 1>; /* HP-NonSecure */ - }; From patchwork Mon Sep 28 11:44:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 313639 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3208754ilg; Mon, 28 Sep 2020 04:44:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzKat6CgnvfhqScuatfYj+XrUWav5uaj2fJ7zrBWX3NnAoLgaXhzS7LJr7jHNPpiKLG0+TI X-Received: by 2002:a17:906:3ac5:: with SMTP id z5mr1225512ejd.46.1601293499283; Mon, 28 Sep 2020 04:44:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601293499; cv=none; d=google.com; s=arc-20160816; b=gg4YVTDF+CsNgoK3D3+teA4PQ7aVMj7YAE8FJUnT8vKfENcfTDFWQg667Au4XBJkqi 41qybsSFwOt4bjnLs+k1jC8I0AuXDd9AEPmgfmP3rVIpU+pJnLrkm4xGGPfwGUpeJGB4 bX0eQ3lKkP4Majla2LxIuEQIpPVJwKxXS2oKclPA6AieHWpna2sChUcQgAjD23UViW78 traMFbJSNmiXxLnOqQsrcjtboV87GRJmMOSXzmxREYEiyZpgS5S4yFtU2jWnNq1QXRH8 94hTz2GfJDOl8r/gNgxC3GpK68FrbtaI22xob81puAXYEr7T0IbS9qmj1qeg1/yD1b+P X0FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=76oPjUgbJRwqgwHcwk60j6uv3w0FZYuw4+zw5UdLA88=; b=aA2s294Djgl8WrTOUrDr74/wRKoMIsz6N5hg96sD4qYmmMVBDfztJZX7/J1DnkCKEQ ZC98uL3DQ5xJGm21SDGC9Wva7tfmjlCT023dvlsNy0GViC1IF+BtFGb7/OZNAe9fOxNs 7bMbvpWU20GQ75eQyagMGkrn5+OrVs3NbsO6TDmYQ5S2xQAWmIpSjiQdihBlgX165ekI WcuL5bFW9Pd5ajRvkarZjrka1/KEFl8Yop22BAf/ssC4VGR6d7wBoqVwAh8TeYfSXEwA DTm7h1LFFlBNngBpte0GbPnElRWLJSubLKhjTfT+FJh39DbfOeBu/Xhp8cmyGnUDQ/++ isng== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id h11si402182edw.573.2020.09.28.04.44.58; Mon, 28 Sep 2020 04:44:59 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726558AbgI1Lo6 (ORCPT + 6 others); Mon, 28 Sep 2020 07:44:58 -0400 Received: from foss.arm.com ([217.140.110.172]:50024 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726625AbgI1Lo5 (ORCPT ); Mon, 28 Sep 2020 07:44:57 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A387231B; Mon, 28 Sep 2020 04:44:56 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1F0D23F6CF; Mon, 28 Sep 2020 04:44:55 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH 2/4] dt-bindings: mailbox: add doorbell support to ARM MHU Date: Mon, 28 Sep 2020 12:44:43 +0100 Message-Id: <20200928114445.19689-3-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928114445.19689-1-sudeep.holla@arm.com> References: <20200928114445.19689-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ARM MHU's reference manual states following: "The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt." This patch thus extends the MHU controller's DT binding to add support for doorbell mode. Though the same MHU hardware controller is used in the two modes, A new compatible string is added here to represent the combination of the MHU hardware and the firmware sitting on the other side (which expects each bit to represent a different signal now). Reviewed-by: Rob Herring Acked-by: Arnd Bergmann Co-developed-by: Viresh Kumar Signed-off-by: Viresh Kumar Signed-off-by: Sudeep Holla --- .../devicetree/bindings/mailbox/arm,mhu.yaml | 60 +++++++++++++++++-- 1 file changed, 54 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml index 2c8df7979c22..d43791a2dde7 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml @@ -18,20 +18,40 @@ description: | remote clears it after having read the data. The last channel is specified to be a 'Secure' resource, hence can't be used by Linux running NS. + The MHU hardware also allows operations in doorbell mode. The MHU drives the + interrupt signal using a 32-bit register, with all 32-bits logically ORed + together. It provides a set of registers to enable software to set, clear and + check the status of each of the bits of this register independently. The use + of 32 bits per interrupt line enables software to provide more information + about the source of the interrupt. For example, each bit of the register can + be associated with a type of event that can contribute to raising the + interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote + processor. + # We need a select here so we don't match all nodes with 'arm,primecell' select: properties: compatible: contains: - const: arm,mhu + enum: + - arm,mhu + - arm,mhu-doorbell required: - compatible properties: compatible: - items: - - const: arm,mhu - - const: arm,primecell + oneOf: + - description: Data transfer mode + items: + - const: arm,mhu + - const: arm,primecell + + - description: Doorbell mode + items: + - const: arm,mhu-doorbell + - const: arm,primecell + reg: maxItems: 1 @@ -51,8 +71,11 @@ description: | - const: apb_pclk '#mbox-cells': - description: Index of the channel. - const: 1 + description: | + Set to 1 in data transfer mode and represents index of the channel. + Set to 2 in doorbell mode and represents index of the channel and doorbell + number. + enum: [ 1, 2 ] required: - compatible @@ -63,6 +86,7 @@ description: | additionalProperties: false examples: + # Data transfer mode. - | soc { #address-cells = <2>; @@ -85,3 +109,27 @@ additionalProperties: false mboxes = <&mhuA 1>; /* HP-NonSecure */ }; }; + + # Doorbell mode. + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mhuB: mailbox@2b2f0000 { + #mbox-cells = <2>; + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0 0x2b2f0000 0 0x1000>; + interrupts = <0 36 4>, /* LP-NonSecure */ + <0 35 4>, /* HP-NonSecure */ + <0 37 4>; /* Secure */ + clocks = <&clock 0 2 1>; + clock-names = "apb_pclk"; + }; + + mhu_client_scpi: scpi@2f000000 { + compatible = "arm,scpi"; + reg = <0 0x2f000000 0 0x200>; + mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */ + }; + }; From patchwork Mon Sep 28 11:44:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 313640 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3208836ilg; Mon, 28 Sep 2020 04:45:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyQYR5y0MiPuzFpqKW9vUmDx1USXuxgQz95Ec7bHFkawitqg+7e8RIvcHgAij7FDrBB5Hi0 X-Received: by 2002:a17:907:1042:: with SMTP id oy2mr1183947ejb.64.1601293506576; Mon, 28 Sep 2020 04:45:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601293506; cv=none; d=google.com; s=arc-20160816; b=lXCmRHZSBrTBoh3pWo/tjjHjzwuxIjK+5CZG415Y263F/N2+GTcUf2SlMicsb2Xj8w pk5I9iDGuaal4htCKj+h34gDyYAzz6MBQsDiqnlBoxXCLVbFKlqEoMiY42NgTkdHuSuN utOR7BOvse5PsaovNstN3SPDeh0FNA2VquT8F5Lvi8sQcu3octTyTkGJXzfZQ4IR1h8J bazJIonc66qCkN/Z3VAbN1TqkZa7fgrNgcGlBDWSrymV+oh4x7JuQq9oU5mJRp+SMAPH GcYxjhKuLrhoytsvdKAPNNiBWDU2X48F2jyNs4uQZVFsQaHkQE+jGMXgaFjyLZ09U8DT r7vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=UUwJs4P1DqFLb+/9QcgvuwdxLm4ikSjENMblrccvMV8=; b=rXmmaEJERZuc3cU5x9eNRKUfYtR1VCvNXEo1zwJfDlSu6rw/E7AeJOTi6vuE3k7y9F aLnpYNpGyJDxRy4hSjeNIsTfLoDdidyhU2MwV9fa8fHdIZgo3TlgNORErWIU7ZHA8baZ mqQVho6ZmAmllc2uu3Kz2Am7YbTbbpRAuxYjDq+TJWB1dIjlxsJIYjlZ7VShe3MjtZK2 K5cdQ2lZp7tVcy6cZrg1AY7+Q++4GkjIW1mkWblTUcdKM0EXZ1u8Tb1cW9DmssC1U6RM 0qgvdEway8OayyiP3Mb4C3d1ubBfL8NHTs5wOHP4Pxv6/kq3RqMUCO+m6Q92fOKfKLGE PnuQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si426233edv.488.2020.09.28.04.45.06; Mon, 28 Sep 2020 04:45:06 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbgI1Lo7 (ORCPT + 6 others); Mon, 28 Sep 2020 07:44:59 -0400 Received: from foss.arm.com ([217.140.110.172]:50032 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726672AbgI1Lo7 (ORCPT ); Mon, 28 Sep 2020 07:44:59 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 703FE113E; Mon, 28 Sep 2020 04:44:58 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D7BF63F6CF; Mon, 28 Sep 2020 04:44:56 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH 3/4] mailbox: arm_mhu: Match only if compatible is "arm, mhu" Date: Mon, 28 Sep 2020 12:44:44 +0100 Message-Id: <20200928114445.19689-4-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928114445.19689-1-sudeep.holla@arm.com> References: <20200928114445.19689-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since we will be soon adding a separate driver based on this ARM MHU driver to support doorbell mode, let us add explicit check to match the default compatible for this driver. This is needed as the probe and match reuses the AMBA device ids currently and don't have any explicit compatible check. Signed-off-by: Sudeep Holla --- drivers/mailbox/arm_mhu.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c index 9da236552bd7..b7fbf276eb62 100644 --- a/drivers/mailbox/arm_mhu.c +++ b/drivers/mailbox/arm_mhu.c @@ -113,6 +113,9 @@ static int mhu_probe(struct amba_device *adev, const struct amba_id *id) struct device *dev = &adev->dev; int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET}; + if (!of_device_is_compatible(dev->of_node, "arm,mhu")) + return -ENODEV; + /* Allocate memory for device */ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); if (!mhu) From patchwork Mon Sep 28 11:44:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 313642 Delivered-To: patch@linaro.org Received: by 2002:a92:5ad1:0:0:0:0:0 with SMTP id b78csp3208876ilg; Mon, 28 Sep 2020 04:45:10 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxaz4q7mW5KPP/5ZWtllreUgjX60PDIGG+OIi/hn+RDM4xeNqNHeplpcTaeLxcyar9ShlUA X-Received: by 2002:a17:906:288d:: with SMTP id o13mr1248536ejd.195.1601293509891; Mon, 28 Sep 2020 04:45:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601293509; cv=none; d=google.com; s=arc-20160816; b=uZiuRR4bIwLErYrV+1Q171Utu0g8yDB2p6r5yh6ZwLZKvahnbHqNaaqt1lyqGmlBYJ mwa5vXrEY3UrMlejmNlH36SRoN55GApVqJrXAj8OQ/7TaB93vu4qkempNXy8BTwmrCqz Q412QeqZ/74sI4kn0DaAlx40de9fzrGW5jC/ycm542ke3S1F8TftKUXvSmu4A23uLxTQ Cupym6BXMUB5pOniTh/Qb7RjA4TZ0itk9OvOz65dKAzmj7z7yxUJZSFjnPe9rpBY6BOi ZBKHM4Yos8CnV3PQZdbNBDcdoIH1Fv2FNMOsgPGJgdP9qYCpLHvOrKCwuhlIFn9qiHNh aaXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=VRxjDKT/a7YKEfa1CP5pM01lwuLPk3Sc18YS3nyb4OE=; b=vyAy2/JTVfT7bheaBQoNNHriCaKRQgJ93Gw5GLPA0KtzBCLkCrJ81wyvBmDNx1J8Er l+8l7HE59YAmUV0lhzlOuEkGNUeC26WSahvzKb1OTF3I07vCTESp/bWnzApjlOI95k5g ULXVDdH1rK8NTFbLK32Xj1bHNG77reJ6ZulAW6ncjw6+yQ2GuTuHxA5GVmV7RjbYp2tJ GZUNQ9CJA5WYAwtLeqExbj/XAnXSpPci/o3leMw/ECE/ow4ChaKN55I0NPV9S4toFPWg wU3PvK/ur05ImjItPLBsPrDlNYe7XX2i55Y1Amgz9cuUtPKXuWYMkTCoTTmg/hzJoh6C OcZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si426233edv.488.2020.09.28.04.45.09; Mon, 28 Sep 2020 04:45:09 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726610AbgI1LpJ (ORCPT + 6 others); Mon, 28 Sep 2020 07:45:09 -0400 Received: from foss.arm.com ([217.140.110.172]:50044 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726721AbgI1LpB (ORCPT ); Mon, 28 Sep 2020 07:45:01 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 34B3031B; Mon, 28 Sep 2020 04:45:00 -0700 (PDT) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A497E3F6CF; Mon, 28 Sep 2020 04:44:58 -0700 (PDT) From: Sudeep Holla To: Jassi Brar , Jassi Brar , Viresh Kumar , ALKML , DTML , LKML Cc: Sudeep Holla , Vincent Guittot , Frank Rowand , Bjorn Andersson , Rob Herring , Rob Herring Subject: [PATCH 4/4] mailbox: arm_mhu: Add ARM MHU doorbell driver Date: Mon, 28 Sep 2020 12:44:45 +0100 Message-Id: <20200928114445.19689-5-sudeep.holla@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200928114445.19689-1-sudeep.holla@arm.com> References: <20200928114445.19689-1-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt. This patch adds a separate the MHU controller driver for doorbel mode of operation using the extended DT binding to add support the same. Signed-off-by: Sudeep Holla --- drivers/mailbox/Makefile | 2 +- drivers/mailbox/arm_mhu_db.c | 359 +++++++++++++++++++++++++++++++++++ 2 files changed, 360 insertions(+), 1 deletion(-) create mode 100644 drivers/mailbox/arm_mhu_db.c -- 2.17.1 diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 60d224b723a1..2e06e02b2e03 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_MAILBOX) += mailbox.o obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o -obj-$(CONFIG_ARM_MHU) += arm_mhu.o +obj-$(CONFIG_ARM_MHU) += arm_mhu.o arm_mhu_db.o obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o diff --git a/drivers/mailbox/arm_mhu_db.c b/drivers/mailbox/arm_mhu_db.c new file mode 100644 index 000000000000..ef5fba4ed54c --- /dev/null +++ b/drivers/mailbox/arm_mhu_db.c @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd. + * Copyright (C) 2015 Linaro Ltd. + * Based on ARM MHU driver by Jassi Brar + * Copyright (C) 2020 ARM Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTR_STAT_OFS 0x0 +#define INTR_SET_OFS 0x8 +#define INTR_CLR_OFS 0x10 + +#define MHU_LP_OFFSET 0x0 +#define MHU_HP_OFFSET 0x20 +#define MHU_SEC_OFFSET 0x200 +#define TX_REG_OFFSET 0x100 + +#define MHU_CHANS 3 /* Secure, Non-Secure High and Low Priority */ +#define MHU_CHAN_MAX 20 /* Max channels to save on unused RAM */ +#define MHU_NUM_DOORBELLS 32 + +struct mhu_db_link { + unsigned int irq; + void __iomem *tx_reg; + void __iomem *rx_reg; +}; + +struct arm_mhu { + void __iomem *base; + struct mhu_db_link mlink[MHU_CHANS]; + struct mbox_controller mbox; + struct device *dev; +}; + +/** + * ARM MHU Mailbox allocated channel information + * + * @mhu: Pointer to parent mailbox device + * @pchan: Physical channel within which this doorbell resides in + * @doorbell: doorbell number pertaining to this channel + */ +struct mhu_db_channel { + struct arm_mhu *mhu; + unsigned int pchan; + unsigned int doorbell; +}; + +static inline struct mbox_chan * +mhu_db_mbox_to_channel(struct mbox_controller *mbox, unsigned int pchan, + unsigned int doorbell) +{ + int i; + struct mhu_db_channel *chan_info; + + for (i = 0; i < mbox->num_chans; i++) { + chan_info = mbox->chans[i].con_priv; + if (chan_info && chan_info->pchan == pchan && + chan_info->doorbell == doorbell) + return &mbox->chans[i]; + } + + dev_err(mbox->dev, + "Channel not registered: physical channel: %d doorbell: %d\n", + pchan, doorbell); + + return NULL; +} + +static void mhu_db_mbox_clear_irq(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].rx_reg; + + writel_relaxed(BIT(chan_info->doorbell), base + INTR_CLR_OFS); +} + +static unsigned int mhu_db_mbox_irq_to_pchan_num(struct arm_mhu *mhu, int irq) +{ + unsigned int pchan; + + for (pchan = 0; pchan < MHU_CHANS; pchan++) + if (mhu->mlink[pchan].irq == irq) + break; + return pchan; +} + +static struct mbox_chan * +mhu_db_mbox_irq_to_channel(struct arm_mhu *mhu, unsigned int pchan) +{ + unsigned long bits; + unsigned int doorbell; + struct mbox_chan *chan = NULL; + struct mbox_controller *mbox = &mhu->mbox; + void __iomem *base = mhu->mlink[pchan].rx_reg; + + bits = readl_relaxed(base + INTR_STAT_OFS); + if (!bits) + /* No IRQs fired in specified physical channel */ + return NULL; + + /* An IRQ has fired, find the associated channel */ + for (doorbell = 0; bits; doorbell++) { + if (!test_and_clear_bit(doorbell, &bits)) + continue; + + chan = mhu_db_mbox_to_channel(mbox, pchan, doorbell); + if (chan) + break; + } + + return chan; +} + +static irqreturn_t mhu_db_mbox_rx_handler(int irq, void *data) +{ + struct mbox_chan *chan; + struct arm_mhu *mhu = data; + unsigned int pchan = mhu_db_mbox_irq_to_pchan_num(mhu, irq); + + while (NULL != (chan = mhu_db_mbox_irq_to_channel(mhu, pchan))) { + mbox_chan_received_data(chan, NULL); + mhu_db_mbox_clear_irq(chan); + } + + return IRQ_HANDLED; +} + +static bool mhu_db_last_tx_done(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; + + if (readl_relaxed(base + INTR_STAT_OFS) & BIT(chan_info->doorbell)) + return false; + + return true; +} + +static int mhu_db_send_data(struct mbox_chan *chan, void *data) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + void __iomem *base = chan_info->mhu->mlink[chan_info->pchan].tx_reg; + + /* Send event to co-processor */ + writel_relaxed(BIT(chan_info->doorbell), base + INTR_SET_OFS); + + return 0; +} + +static int mhu_db_startup(struct mbox_chan *chan) +{ + mhu_db_mbox_clear_irq(chan); + return 0; +} + +static void mhu_db_shutdown(struct mbox_chan *chan) +{ + struct mhu_db_channel *chan_info = chan->con_priv; + struct mbox_controller *mbox = &chan_info->mhu->mbox; + int i; + + for (i = 0; i < mbox->num_chans; i++) + if (chan == &mbox->chans[i]) + break; + + if (mbox->num_chans == i) { + dev_warn(mbox->dev, "Request to free non-existent channel\n"); + return; + } + + /* Reset channel */ + mhu_db_mbox_clear_irq(chan); + chan->con_priv = NULL; +} + +static struct mbox_chan *mhu_db_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *spec) +{ + struct arm_mhu *mhu = dev_get_drvdata(mbox->dev); + struct mhu_db_channel *chan_info; + struct mbox_chan *chan = NULL; + unsigned int pchan = spec->args[0]; + unsigned int doorbell = spec->args[1]; + int i; + + /* Bounds checking */ + if (pchan >= MHU_CHANS || doorbell >= MHU_NUM_DOORBELLS) { + dev_err(mbox->dev, + "Invalid channel requested pchan: %d doorbell: %d\n", + pchan, doorbell); + return ERR_PTR(-EINVAL); + } + + for (i = 0; i < mbox->num_chans; i++) { + chan_info = mbox->chans[i].con_priv; + + /* Is requested channel free? */ + if (chan_info && + mbox->dev == chan_info->mhu->dev && + pchan == chan_info->pchan && + doorbell == chan_info->doorbell) { + dev_err(mbox->dev, "Channel in use\n"); + return ERR_PTR(-EBUSY); + } + + /* + * Find the first free slot, then continue checking + * to see if requested channel is in use + */ + if (!chan && !chan_info) + chan = &mbox->chans[i]; + } + + if (!chan) { + dev_err(mbox->dev, "No free channels left\n"); + return ERR_PTR(-EBUSY); + } + + chan_info = devm_kzalloc(mbox->dev, sizeof(*chan_info), GFP_KERNEL); + if (!chan_info) + return ERR_PTR(-ENOMEM); + + chan_info->mhu = mhu; + chan_info->pchan = pchan; + chan_info->doorbell = doorbell; + + chan->con_priv = chan_info; + + dev_dbg(mbox->dev, "mbox: created channel phys: %d doorbell: %d\n", + pchan, doorbell); + + return chan; +} + +static const struct mbox_chan_ops mhu_db_ops = { + .send_data = mhu_db_send_data, + .startup = mhu_db_startup, + .shutdown = mhu_db_shutdown, + .last_tx_done = mhu_db_last_tx_done, +}; + +static int mhu_db_probe(struct amba_device *adev, const struct amba_id *id) +{ + u32 cell_count; + int i, err, max_chans; + struct arm_mhu *mhu; + struct mbox_chan *chans; + struct device *dev = &adev->dev; + struct device_node *np = dev->of_node; + int mhu_reg[MHU_CHANS] = { + MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET, + }; + + if (!of_device_is_compatible(np, "arm,mhu-doorbell")) + return -ENODEV; + + err = of_property_read_u32(np, "#mbox-cells", &cell_count); + if (err) { + dev_err(dev, "failed to read #mbox-cells in '%pOF'\n", np); + return err; + } + + if (cell_count == 2) { + max_chans = MHU_CHAN_MAX; + } else { + dev_err(dev, "incorrect value of #mbox-cells in '%pOF'\n", np); + return -EINVAL; + } + + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL); + if (!mhu) + return -ENOMEM; + + mhu->base = devm_ioremap_resource(dev, &adev->res); + if (IS_ERR(mhu->base)) { + dev_err(dev, "ioremap failed\n"); + return PTR_ERR(mhu->base); + } + + chans = devm_kcalloc(dev, max_chans, sizeof(*chans), GFP_KERNEL); + if (!chans) + return -ENOMEM; + + mhu->dev = dev; + mhu->mbox.dev = dev; + mhu->mbox.chans = chans; + mhu->mbox.num_chans = max_chans; + mhu->mbox.txdone_irq = false; + mhu->mbox.txdone_poll = true; + mhu->mbox.txpoll_period = 1; + + mhu->mbox.of_xlate = mhu_db_mbox_xlate; + amba_set_drvdata(adev, mhu); + + mhu->mbox.ops = &mhu_db_ops; + + err = devm_mbox_controller_register(dev, &mhu->mbox); + if (err) { + dev_err(dev, "Failed to register mailboxes %d\n", err); + return err; + } + + for (i = 0; i < MHU_CHANS; i++) { + int irq = mhu->mlink[i].irq = adev->irq[i]; + + if (irq <= 0) { + dev_dbg(dev, "No IRQ found for Channel %d\n", i); + continue; + } + + mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i]; + mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET; + + err = devm_request_threaded_irq(dev, irq, NULL, + mhu_db_mbox_rx_handler, + IRQF_ONESHOT, "mhu_db_link", mhu); + if (err) { + dev_err(dev, "Can't claim IRQ %d\n", irq); + mbox_controller_unregister(&mhu->mbox); + return err; + } + } + + dev_info(dev, "ARM MHU Doorbell mailbox registered\n"); + return 0; +} + +static struct amba_id mhu_ids[] = { + { + .id = 0x1bb098, + .mask = 0xffffff, + }, + { 0, 0 }, +}; +MODULE_DEVICE_TABLE(amba, mhu_ids); + +static struct amba_driver arm_mhu_db_driver = { + .drv = { + .name = "mhu-doorbell", + }, + .id_table = mhu_ids, + .probe = mhu_db_probe, +}; +module_amba_driver(arm_mhu_db_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("ARM MHU Doorbell Driver"); +MODULE_AUTHOR("Sudeep Holla ");