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[206.248.184.2]) by smtp.gmail.com with ESMTPSA id f24sm5370433qkk.136.2020.09.29.11.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 11:52:22 -0700 (PDT) From: Ralph Siemsen To: Ley Foon Tan Cc: Dinh Nguyen , Marek Vasut , Simon Goldschmidt , u-boot@lists.denx.de, Tom Rini , Ralph Siemsen Subject: [PATCH v1] arm: socfpga: fix Gen5 enable of EMAC via FPGA Date: Tue, 29 Sep 2020 14:52:05 -0400 Message-Id: <20200929145152.v1.1.I7900a579743ce0fc5fe382213612b5af29e3706f@changeid> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen --- I reviewed the other #defines for gen5 and they seem correct. I have NOT checked the defines for Arria 10 or Stratix 10! arch/arm/mach-socfpga/include/mach/system_manager_gen5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 Reviewed-by: Ley Foon Tan diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h index 90cb465d13..a63a4ee27d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -26,9 +26,9 @@ void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #define SYSMGR_GEN5_ECCGRP_OCRAM 0x144 #define SYSMGR_GEN5_EMACIO 0x400 #define SYSMGR_GEN5_NAND_USEFPGA 0x6f0 -#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8 +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x6f8 #define SYSMGR_GEN5_SDMMC_USEFPGA 0x708 -#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704 +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x714 #define SYSMGR_GEN5_SPIM1_USEFPGA 0x730 #define SYSMGR_GEN5_SPIM0_USEFPGA 0x738