From patchwork Wed Nov 4 16:48:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56550C2D0A3 for ; Wed, 4 Nov 2020 16:54:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 11905207BB for ; Wed, 4 Nov 2020 16:54:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="GIW9qAMd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731404AbgKDQte (ORCPT ); Wed, 4 Nov 2020 11:49:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731297AbgKDQtd (ORCPT ); Wed, 4 Nov 2020 11:49:33 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 079F4C0613D4; Wed, 4 Nov 2020 08:49:33 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id s30so5744292lfc.4; Wed, 04 Nov 2020 08:49:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=crJJm+NJzX9nNGfEw3yeviT1h3BYRo8BzSQA7+fLOns=; b=GIW9qAMdCMH2xtWA68F2XwDqytaBnWVGD1ga01N0NTSOrl8CxFhZbSLz8FlPcfkY4K bxTV5U0FHL8cHzww8fIOe8gSlFw/OLqA3ZpsoY409KGElyH+1hlYCoraDe34iD1UD6R5 wwS184NUI/ja1ZjaVJ6YMG2H6jFK9vLQbEAJc9gSwL6Scp8P6H94gezgbYiX6Nk8ZD6J 3UuP+REx+n65fzrGi4UjHJynleoqj1NAnotzHg79F9IUHz+bCPkmM7DBtenNvsEsszkI QoMas1l7Z27AQ8YN7AONii81cQbJBeladQanNyUuzDn1hUY9lRjzOSPlxEfAoqwr30qS 4P3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=crJJm+NJzX9nNGfEw3yeviT1h3BYRo8BzSQA7+fLOns=; b=o++xsp8g+mXxOnZy5+TTQJp51ofVU9mP0X4Vt4UmDBdwTxvGUDzNimGeJwxsZJq9br 9OGvocz7H2xFSPfHLFUbGKjmItQtNovgVLX856fRXnSvJnB7Ocnl0W51FBvxpPg2UjrX +Q1dycZoMEk0RyB3zeNBfkCI7u4RBaUrHHvzY9VYGMO/VvisjLESeVfuADaW1CtqzXH4 EZsySl/aFaK9bBu0QRZO+PKyPCEL+0WhtYuL6I5zhPf8ktKuvaw2efrkSsk49KiHZaww K91PXsOufwae8j3kjwveemi2pVZXJAxGRmzDZOoz4uzDTOD3q0efowYNM7HSFrApkSNv qKWg== X-Gm-Message-State: AOAM531MvILm5H+p53r/MOXVTRx3sMJYIN3SdmypgNqo+3OcRKzU0nvm Pyrb6OwGKLyXfJIZdPNm3mk= X-Google-Smtp-Source: ABdhPJxOl7/JqZ7qhE8E22tCWDcsvDG+RX5n/zXPK169JDaNrnMVeePskTl+GlbctB+qjSNT8+N+vQ== X-Received: by 2002:ac2:5938:: with SMTP id v24mr9168385lfi.228.1604508571556; Wed, 04 Nov 2020 08:49:31 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:31 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 01/47] clk: tegra: Export Tegra20 EMC kernel symbols Date: Wed, 4 Nov 2020 19:48:37 +0300 Message-Id: <20201104164923.21238-2-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org We're going to modularize Tegra EMC drivers and some of the EMC-clock driver symbols need to be exported, let's export them. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20-emc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20-emc.c b/drivers/clk/tegra/clk-tegra20-emc.c index 03bf0009a33c..dd74b8543bf1 100644 --- a/drivers/clk/tegra/clk-tegra20-emc.c +++ b/drivers/clk/tegra/clk-tegra20-emc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -235,6 +236,7 @@ void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, emc->cb_arg = cb_arg; } } +EXPORT_SYMBOL_GPL(tegra20_clk_set_emc_round_callback); bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw) { @@ -291,3 +293,4 @@ int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) return 0; } +EXPORT_SYMBOL_GPL(tegra20_clk_prepare_emc_mc_same_freq); From patchwork Wed Nov 4 16:48:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318260 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6285BC388F9 for ; Wed, 4 Nov 2020 16:54:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CAAD2072C for ; Wed, 4 Nov 2020 16:54:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="E4fVzzEb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731780AbgKDQyA (ORCPT ); Wed, 4 Nov 2020 11:54:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731426AbgKDQtj (ORCPT ); Wed, 4 Nov 2020 11:49:39 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14313C0613D3; Wed, 4 Nov 2020 08:49:39 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id 23so23664751ljv.7; Wed, 04 Nov 2020 08:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1bx8gx8+d1g03DAKla/SIGpVTuVq7snjdNHpSyCav3o=; b=E4fVzzEbN2YOZaT7L0YMq0MzZmwK0d5G6U1UdsHOygRHeg4qD9/kMAl31z/C7UvzgG 3wfNw+SsSCew6J8BJc1FkTG6ol/t1QiIa1Ix/1hrZilYXxIBY4jsknB+cNHgZMWOJTA1 LTytMvkcgBF8OEXqBMsuC5+boAbL6idy3aCojRnyMjNUn4VzjFvuIi1/qV8lMIsR3tjG Rklpa7X8zpedENSm9wa+kGSTC1tRrCSwsnqPBtDYo0M/PxgPvpCMC3lTZx6Vx3zR8JLi ituiJ3sgD8uk5s6N4B7KHODv4BIgVUZh8uuDolNZcIpSB4tutXKVidPdcwIjV5eBO8J+ ebjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1bx8gx8+d1g03DAKla/SIGpVTuVq7snjdNHpSyCav3o=; b=NDUbA5yU8vD64UV3EOcXCLs2pxB7wVR79hLCJr6cw7hHqiZi5oEIhkKsk+PidKwrtH iOK/MDCTJjR9FtICx5yAYhOSzXwWuKf/x07ftuATtVPcE1Ed41qdxnotJBarkLqDywyw I8naSLW+Btamdz88/GSClSkCMqwwhm6xR/OzFiZaTw8Uk7Vhbca9yaQ0T2aSpHaV/ene 9+/sQqBL6Z+mSr2gIaXgHCpwsZ1imAwzjV61nk10lvthrksfXGfOwMJ14U+y/oZ61kfu vptI893LgXe82C/FoeKJOiick2vWs7+lR3/cYJzrDVDLqIdlIO50/jQsT4dQ/eRX3ZSK rXHA== X-Gm-Message-State: AOAM532mSc8yj10Gw3LYLlTGI/Q+ZT9aIBN/oSJRRebqK5AlPilbDWKi 3gyVDNFAyjd5sacjWtrb3rQ= X-Google-Smtp-Source: ABdhPJwGNgNsjt7GM+mUEmujJb3ulRATwMxAQBV2JYiJ+8jaEaSL5rtWnNfZYbAIRZqj86M0zhzGjw== X-Received: by 2002:a2e:8041:: with SMTP id p1mr6607807ljg.460.1604508577584; Wed, 04 Nov 2020 08:49:37 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:37 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 06/47] dt-bindings: memory: tegra20: mc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:42 +0300 Message-Id: <20201104164923.21238-7-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file . Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 { From patchwork Wed Nov 4 16:48:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99D7BC4742C for ; Wed, 4 Nov 2020 16:53:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48E4B2072C for ; Wed, 4 Nov 2020 16:53:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DEbFYKMc" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731465AbgKDQtp (ORCPT ); Wed, 4 Nov 2020 11:49:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731442AbgKDQtl (ORCPT ); Wed, 4 Nov 2020 11:49:41 -0500 Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64C98C0613D3; Wed, 4 Nov 2020 08:49:41 -0800 (PST) Received: by mail-lj1-x243.google.com with SMTP id l10so2704107lji.4; Wed, 04 Nov 2020 08:49:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0FVv3BbkAu5vijvZy0/g8D/gSJwLwAaxtQyTiLpi4B8=; b=DEbFYKMcdoH48FN2/uyXUSKvK0hCwgs9jDu+ko+KosDrC62VOnUtAL/3lEG+UwTtTP CRRI84LwRW1IqzJ1qVLNHGzelsTrjKI13WiIYf0t9MJXDrgYs+LdiblQYIbQ5YiaSa78 R/fC75sA6xgcPx0AjKdHm+/jXFgBrxjsxXQocUq38LrRsEDQaMN2eRB1gAr9bHzI0ye6 p4yCRU+itdACg1YMCB4JYW0hYdlNm2I0VbGJUr1Se3mSy+LasQ9xc0LG1Mnl/knF9Xkh nGf7OUjL1fNakCeZSqPOavJMScyiXtPR9huMzU6AmR+yQZlDnbSbYeJgptPGZQR5GjT5 mz5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0FVv3BbkAu5vijvZy0/g8D/gSJwLwAaxtQyTiLpi4B8=; b=LrDjb4Ac/+OkPmrIjj7rx3Bp59MUuXgH+9Iu3F0CMOCKY9VN54nDuISEmrscV2rpGt WPw4uvVdYMRhHAJVq+F8h6QvgwFGLWvMR6J78TsIAZk32fZ/sZvtn/0iZvtPvWGg6e8c 5z9WJcbAD5U3+9Z9CIJaC7q05jh/eghleHmGSDLUfPp3Y/XUnfBV8RoibZEpkJOjgwrT j1N5S6F+Xd0HMvvVLvJ5TPmv7txdKpZvwOoAgyefyJs3jAffEQPng93B49OSTyHKwtC5 NfMsGpXtRjRxvClJBZKoPTL4HUiikwMM4LJnEpKSvaYDq2ixTluLhCQ9hgq+ZxyMxOXl CHTg== X-Gm-Message-State: AOAM533QBGIfomeHgoyEugI8xw0VS+tGKuVxA/NKCq7+XJroQVX/vDD7 iBsoBqoBcSIzMQrpMh862/U= X-Google-Smtp-Source: ABdhPJwyAlb0a8HWHX8gVPMOoMubt/guWwT7XX6botKnEiM48IOWNSbdR9Xn4p979LWrEeFoDHl99w== X-Received: by 2002:a2e:580a:: with SMTP id m10mr2371255ljb.167.1604508579935; Wed, 04 Nov 2020 08:49:39 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:39 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 08/47] dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator Date: Wed, 4 Nov 2020 19:48:44 +0300 Message-Id: <20201104164923.21238-9-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional because some boards may have a fixed core regulator and still frequency scaling may be desired to have. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring --- .../memory-controllers/nvidia,tegra20-emc.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 82bc5b2ae7e5..67ac8d1297da 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -14,11 +14,25 @@ Properties: - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. - #interconnect-cells : Should be 0. +- operating-points-v2: See ../bindings/opp/opp.txt for details. + +Optional properties: +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. Child device nodes describe the memory settings for different configurations and clock rates. Example: + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + }; + ... + }; + memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; @@ -28,6 +42,8 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; + core-supply = <&core_vdd_reg>; + operating-points-v2 = <&opp_table>; } From patchwork Wed Nov 4 16:48:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B307C388F9 for ; Wed, 4 Nov 2020 16:53:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FE7A21734 for ; Wed, 4 Nov 2020 16:53:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="t+6XmamO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731457AbgKDQtp (ORCPT ); Wed, 4 Nov 2020 11:49:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731450AbgKDQtn (ORCPT ); Wed, 4 Nov 2020 11:49:43 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 931CBC061A4A; Wed, 4 Nov 2020 08:49:42 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id h6so28020936lfj.3; Wed, 04 Nov 2020 08:49:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=13zJHfR9di8Ydxi+LOybO5H+JCALzXt2g6wK8WiSzjg=; b=t+6XmamOufud85gfyMGuCbFRnXH/pka7+DXkYhQq3VCFFSEvuLsvT/RYOOG2zit/v+ DH/OLrTipaYalni61+oeoO3/7u84O5R5Phy9YzK2RevmSVcp2gnlyfZfAhm7h4/ZH8cd 7DpxAk2by+O/uw6YAq8CfQYoCdQ7umQiL8Zzf+xuUMXXYMUpTKZDso8ez+UT2MVdbbr7 7piRmA6pTCTWJxwwNiFAWxGPBZWfbwBU6mCWoo+b06xnj05+hqgiklRggG3uEah/2aqz Rj0ADEcNQAJ2XRayKBWGOhvMriNvkkapI1ud+5e1wQ/jr0Lcs3IUVjwrTb6+uaBT2JZX Ee7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=13zJHfR9di8Ydxi+LOybO5H+JCALzXt2g6wK8WiSzjg=; b=N6B3U7WJVyNngfChmQzjO3jM8Wtz+28ZWf/7bvlqj8FS37ygsbNETbfMKFJRJrbkKw 2IXtRAFjeL91IcUG2DolbNkj/hDcNNbhJwbeWQUCKJC2H2250fB4PUtn7e6u7IyPT3yA D69S4rJtO9rbySB0k/qM6htqZ9cpHd7pO79HTmnOf1oeIZl/TSsK/OhBTlDMTucWXWkM ygS0dJoX69SIr+2DoqEV6ZsCCm8cHuD4YoQnncwqnNInkXpOHbGpun/ckc8qoXTeUvfX fcv5aRIjo675AyAza8fvNRV5F1LBF1GYikIy1a2Y6E6MYsfdRQ725bB+oghDiKHCg5QQ bvow== X-Gm-Message-State: AOAM531GPv9T0QSkJK1WMleNtK28lNjoYBKEFa5sKxIy3vGELrl+doEg T5CFq1hA73r/SGgLK0LvcAQ= X-Google-Smtp-Source: ABdhPJx3MXf1ifZHHtSGhKEXSuUOoWS5aH6HQ2rKgpVEkQPSr1h0IPaDi1gyerE0+/GxhDL58Mu8tQ== X-Received: by 2002:ac2:592f:: with SMTP id v15mr6582641lfi.512.1604508581136; Wed, 04 Nov 2020 08:49:41 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:40 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 09/47] dt-bindings: memory: tegra30: mc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:45 +0300 Message-Id: <20201104164923.21238-10-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..5436e6d420bc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -120,6 +123,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -135,6 +139,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; From patchwork Wed Nov 4 16:48:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318261 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A45ACC2D0A3 for ; Wed, 4 Nov 2020 16:53:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 551C9207BB for ; Wed, 4 Nov 2020 16:53:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jU1LtOKT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731499AbgKDQxv (ORCPT ); Wed, 4 Nov 2020 11:53:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731453AbgKDQto (ORCPT ); Wed, 4 Nov 2020 11:49:44 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7A94C0613D3; Wed, 4 Nov 2020 08:49:43 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id 126so27996521lfi.8; Wed, 04 Nov 2020 08:49:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YaLXEDjIP3Iag/w2fX7ni9eaMug2cPZsxsXqnpeU2P0=; b=jU1LtOKTa1OCnxA2EvAhw8VWIKlCBTqza86WrKpewfv5UDC4XuW4u/3tUQtoiUPSbV 0qmW5Gbz8IsaDineQtGolE4RHswCgvWUGdN4KfLiwdXip/wQxKn+R/N0StmVgZyqC8lk d8BRY3PVEFm4RnqQR1ImZw2IqCL4yRG9VHt+EFVYvKx5pYkxOEy62Gb/UiOMK9WbfMC7 N0ZS3gGan9v+0JaIAdbEpAmRdy3puZkqFl3nMBmUtJgfBEM4sBx2z05vcxf4w2ybUy2X dRtYXwip9CaGjL95VhkB5n8W8ZfO0Q+I7yuDnIyBhRDpM64M99+PH2Mrfe5Q4OripU61 dMJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YaLXEDjIP3Iag/w2fX7ni9eaMug2cPZsxsXqnpeU2P0=; b=KUOVVjV5xoAtinubtPxbFg4zKJqBQxhD+xj/2FmspIKGb1mIMseSFYJw9RJniLI+EG 8JXAWnTXI9xJNQLIn1hgQrK/eGhaIFDDtk5pLGojCKTuDSg9RZjf+WsG9PoEQ1Yzuyst iNeo970BUz6cSrj69R/D2leNN0kKwoypKdv3tMUESPzTYnvmcdX74lBs/QYKuWfGvV7N NTBCpb/VGTyd9L/G1Mvdgf7SXdfcvOIU/sGuYEE4opTkStPeYxD5gwyLX3fgIXUgTiAy 4in55eEX40NLcybz+kKMxVemZLdQoZqV8WbFfc4/2lEOxnT4im5t9tGKpPbrCwC2tp29 9UBA== X-Gm-Message-State: AOAM533y4Y6VOpWHurHYQIEcdRhQMo89rQuVXqJgjQVC8Iy4TNMVTuyb qCC7gkFYONraqHcMIZmDzrFWOLrBMjE= X-Google-Smtp-Source: ABdhPJw14MqYybDzcLqjY71bV/g9tODhxZ1LoCGsAysETlILk8YtOaRXbvBh3Mjq4ifD3OezTNn9Lg== X-Received: by 2002:a19:e0c:: with SMTP id 12mr10739491lfo.328.1604508582300; Wed, 04 Nov 2020 08:49:42 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:41 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 10/47] dt-bindings: memory: tegra30: emc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:46 +0300 Message-Id: <20201104164923.21238-11-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Acked-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 112bae2fcbbd..c243986db420 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -214,6 +217,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -227,6 +231,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>; From patchwork Wed Nov 4 16:48:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0025FC2D0A3 for ; Wed, 4 Nov 2020 16:49:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 93D772071A for ; Wed, 4 Nov 2020 16:49:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ccWrihjA" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731425AbgKDQtr (ORCPT ); Wed, 4 Nov 2020 11:49:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731472AbgKDQtq (ORCPT ); Wed, 4 Nov 2020 11:49:46 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16455C0613D3; Wed, 4 Nov 2020 08:49:46 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id 126so27996673lfi.8; Wed, 04 Nov 2020 08:49:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G/gWaZVsDrg+B7oJiO/GfuEeS3ySH7bEMjaW24T/nJE=; b=ccWrihjAHhkulHQ70bzhiZSEnQyNp//mzVPgwLNcwy58NU6x6EHVJXt0bg7H6ckfjp 6nxWy9kxJDTswhw1vbgY69ZlPIWn8zLR0vDx22Z4oyvOnr2gpUcJVJ6s9i3EszAX6y+H aMXYnXrhWsGnk+1HvI8BWAVMXIkP6KFNgDeQAEYOmgWb1kFz8S4VJxK6Z/dtuSDGU7t7 sub9cu89dZMxY/tjGhByjNWvOq4aPZjZVFJ0GKmdzMbQign8sgF1rn6HOighSZ4q2RjQ w8odjDAWB5scMsfGMgVpoLONwh6ORbFmatrsRPGPkWSM4+Cd8OrliotngJALQLxnLvQn UhNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G/gWaZVsDrg+B7oJiO/GfuEeS3ySH7bEMjaW24T/nJE=; b=KQlOl2QupCJawXby7nAViDjescpoFUX8WRX12f2CzSP10d58JmGWZzCnIaYBvY899N 9+FWi6Lj1ldtMPy6ID0+ziWMHf9gQCgrk8Oq4qogI0UiqRcXGzlhwbXEksv4zE4r7AqA Xu8clp4tL+7Vrer6QPCEaxTusj5X6peE3X7+ZqyxCzwWlL6t3wJVj+97lsz7Nsa7wa5c pw+9yZ7cdp50nI1+Wv6wXZUR+jBoCDMBreyNzLNeVXAZ6UU3/UIMQvqHvvwfw47sHUKJ lGnBq70dS0aj7ZiB7ZVc/AsorlZywYNzG0J3rQkOkSa6bhqJ2IyK4JwX7OZCkO1Zhq67 qGXA== X-Gm-Message-State: AOAM530BodGZtDcgYzguAk2XWTtnPl9U34YMqHar6A0qbONZvIPu5J5v PkEnhcHGwL2Yqqs4xK0cTnY= X-Google-Smtp-Source: ABdhPJxeuKyJpt41bYMUa63HVmZKLXHDeIqS5FU59NXW9QJP9vR3xVUp6iPAf5ojcqJ1hR07YmjErw== X-Received: by 2002:a19:c97:: with SMTP id 145mr10418006lfm.81.1604508584629; Wed, 04 Nov 2020 08:49:44 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:44 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 12/47] dt-bindings: memory: tegra124: mc: Document new interconnect property Date: Wed, 4 Nov 2020 19:48:48 +0300 Message-Id: <20201104164923.21238-13-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 + .../bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 278549f9e051..8ae3dae42d6e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -345,6 +345,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; external-memory-controller@7001b000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 84d0339505b1..7b18b4d11e0a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -40,6 +40,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -104,6 +107,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -119,6 +123,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-3 { nvidia,ram-code = <3>; From patchwork Wed Nov 4 16:48:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02565C388F9 for ; Wed, 4 Nov 2020 16:49:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A56772071A for ; Wed, 4 Nov 2020 16:49:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l0gsx/WO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731504AbgKDQtw (ORCPT ); Wed, 4 Nov 2020 11:49:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731490AbgKDQtt (ORCPT ); Wed, 4 Nov 2020 11:49:49 -0500 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93A8EC0613D3; Wed, 4 Nov 2020 08:49:48 -0800 (PST) Received: by mail-lf1-x142.google.com with SMTP id b1so27962111lfp.11; Wed, 04 Nov 2020 08:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RsEiBNqevS137X8EgsTINN66YSPI6dqy0hGSUXN1Nl4=; b=l0gsx/WOIi+QcOSWIQOGjzVyqftIJLUglBlpPJ+plhlETQraCIxv2lVoACM/kgHZxa siE771TZn8MJ6Xi6lXvO2L0NXhWsDbevsF/Z8vfotFQbjb/3YZwUi0idR6s1e39T1T3N c9Qt0/JexF7OHne5CT/8NdKAx6zc6qhNgCRc7YajWDLGoRidLr24pGHvZgMYgqgr9/pS 2lEXNGHw9o2ltXvvPv0yzy1Awe/1+MilQwzp1RCyXnlIsJnPhXQ4YA6EjflowAYuVWyO i7iyg17ZOs7yHYNNhzVZX5JTcHeCkFmnWFjad7pnt6HCMcY5PKx9xZJMJGuZgEtCKkjZ HwSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RsEiBNqevS137X8EgsTINN66YSPI6dqy0hGSUXN1Nl4=; b=G90YxhDKqOxEV7FUUMn0P2jaNA33azrdLjf5dS+A1bV0/RwSt+Ysw3DP1IU/ltRtpg Y4khDuXw08hC9Acgx4w+WwbVkMa9USmDogyOjfsFl51qp2lM1H7V7kc6LniTGb4omIan eq+7X2t+7D+Ep4Ok6kXUWknIeUk2NTnFJiSe6rYb31KpUS8VMKddhv9m50rpThp+Azvt bzALQ2XQcdTbLU+Xm2FLDpM8UqyVbVzBW8ZO3C2kAUfI8GqLcSPrRhxQus6mHVNRtSdj /A+aTJV6qVSBVaogpG5YpADacK7r13ovdMgoUPzM8rE0vIlzc34rBBAtzXwCt/bduOQi Tp/w== X-Gm-Message-State: AOAM530mOnAjfhsZiLCMv8k2Jy+hwWolk/Z54D+kk/IXQcXPMGoVrK4f EqTy9NzX7V5lZZSsPcbxjus= X-Google-Smtp-Source: ABdhPJz8Dwjo5uSb78kKmSUyVRABa9SgfHctcnMFRcKzAvnBpwfjqTfXnzmZYZRynjQu1olS+RUcQQ== X-Received: by 2002:a19:e014:: with SMTP id x20mr9473796lfg.444.1604508586969; Wed, 04 Nov 2020 08:49:46 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:46 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 14/47] dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Date: Wed, 4 Nov 2020 19:48:50 +0300 Message-Id: <20201104164923.21238-15-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../memory-controllers/nvidia,tegra124-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index ac00832ceac1..09bde65e1955 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,6 +37,15 @@ properties: description: phandle of the memory controller node + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -331,6 +340,7 @@ required: - clock-names - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -359,6 +369,8 @@ examples: clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; From patchwork Wed Nov 4 16:48:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318264 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBEF6C2D0A3 for ; Wed, 4 Nov 2020 16:53:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 695292074B for ; Wed, 4 Nov 2020 16:53:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l3LKe/mp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731500AbgKDQtv (ORCPT ); Wed, 4 Nov 2020 11:49:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731493AbgKDQtu (ORCPT ); Wed, 4 Nov 2020 11:49:50 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BF12C0613D4; Wed, 4 Nov 2020 08:49:49 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id y16so23729252ljk.1; Wed, 04 Nov 2020 08:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d/Sk3dwc3ZzPQh0+4njd7Ejlh1IFm+rB1ccMwqr+vGE=; b=l3LKe/mpPu0S8/dCOq6M2kz5lSPjJIkDiZkJ392mXO0421xd0wR0g+uOXZu3Dp6GNh tig0xwfVmcWuRwSddNabK0tKmD9eiUiHmMnpBBpYyQsiolkHs6ybryKNoGIVmvUoj6mT ZoVdAYiceuqcnDB8+mK/Y52+5BOgvmMeR8RuFYe5GfwIbOlNfG7+BJWLe6WZpsli+6Pf JdpL/bqxj2ePobj0I6x+B4d6skuRAUZdvSHHxJhupeFc3dDdE3n0DFN/kYXJWmBqH0GV 6PBYnodpQBz72zJUvr33uIEYqRK5w81me4rBiefPXZLOBAHDnuZCa6+wdwuq0NWJzPtm LWEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d/Sk3dwc3ZzPQh0+4njd7Ejlh1IFm+rB1ccMwqr+vGE=; b=qKfTEtsSWSrWgctAWYgOXQ4Jyjah02Nlt4J54rryEd/wAXEM+UYAw2RlsaIugtEbWV CPHSeTaek1Mmjt9PyMO0ImsHrrZGciSb2a7F88XoSyz6ie3fTlh4e9yAXsBg3O5Cmzxz CBIa9/LNz5PQn8LKLncZawHivQt0sWB+ADyClsj4jL8rkzJhSZ1ma6nHmkhd7yx7ITuK ziKT/c5sr0tfmNOBm8vPhONKwz5ER1EQDjqhT6z0eWWHtWW+lro6n00Pk6IVCrGn/KOY yxGC5TfXsjirY+a61vk9PIZv7PCckoHuS2kpZkva65lbvBZ9vt8YvmNEezIQvzL0TC6F npTQ== X-Gm-Message-State: AOAM530IG87kQ5oJPmWL0til37cryXF8AgJthnZZjK/coHApI+w4su8v fv2CPrNJ21WKSa/Ww9IWqsI= X-Google-Smtp-Source: ABdhPJzOM97kyPaLdS5FBsoSI5pNCOmFXgHHRAlsYMvgYsazvVkHm7oOeCMGO/mgd30CUSSL1TDgdg== X-Received: by 2002:a2e:3a08:: with SMTP id h8mr11610597lja.125.1604508588138; Wed, 04 Nov 2020 08:49:48 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:47 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 15/47] dt-bindings: tegra30-actmon: Document OPP and interconnect properties Date: Wed, 4 Nov 2020 19:48:51 +0300 Message-Id: <20201104164923.21238-16-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared voltage scaling in addition to the frequency scaling. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../arm/tegra/nvidia,tegra30-actmon.txt | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt index ea670a5d7ee3..897eedfa2bc8 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details. ../../reset/reset.txt for details. - reset-names: Must include the following entries: - actmon +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- interconnects: Should contain entries for memory clients sitting on + MC->EMC memory interconnect path. +- interconnect-names: Should include name of the interconnect path for each + interconnect entry. Consult TRM documentation for + information about available memory clients, see MEMORY + CONTROLLER section. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: bitfield indicating SoC speedo ID mask +- opp-peak-kBps: peak bandwidth of the memory channel Example: + dfs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <51000>; + }; + ... + }; + actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; @@ -29,4 +51,7 @@ Example: clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu"; }; From patchwork Wed Nov 4 16:48:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25B28C4741F for ; Wed, 4 Nov 2020 16:53:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D97202072C for ; Wed, 4 Nov 2020 16:53:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="l28eK///" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731821AbgKDQxM (ORCPT ); Wed, 4 Nov 2020 11:53:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731519AbgKDQty (ORCPT ); Wed, 4 Nov 2020 11:49:54 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 578F2C0613D3; Wed, 4 Nov 2020 08:49:54 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id l2so28079515lfk.0; Wed, 04 Nov 2020 08:49:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Wup0jgVqkx9Z2UtrB2UQcATbTsL4I5PHiSg5IeKsK8=; b=l28eK///7thfjpdLXMWhiHHWDQvoZhEFc21hkIrW2nmkPIUnISNVVRI5Q5kttUvAbX HefPgitvaywJSbF6hjkjoFVpJ+2vLQ1/dFZZpb+bUt+Bd4DxzoTw2p8Pvp7REtz56vUg ZHVZ9iLdALzbjUUucAR9l9J4mD4IGqTTlPq5tydYJ76/GVhIfZOufiSYBwQZddQyZRYj wFlNveXYjeo+wcTWahXrWJxKYwnXBLjx0voygI6w+I9jYZCnW5VCNLXRbvFT2K06PAWJ fm3BMEPBOl8NH1mb3ry3IqtrsJjEFsAz9jQEW2dapu+g01OSIcXuz6T6tcfI9l3+G+ju OpdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Wup0jgVqkx9Z2UtrB2UQcATbTsL4I5PHiSg5IeKsK8=; b=Edx1ekzz88sMMTdMKhb2GDEEa2qulL5GMCX79EcKLMB7t4QvlupgUtnK9Yzky9/FID d0I3uK0bCP1fuRAkk98cEkBhV6nL9gqKBjZXoNrx1cPUESzwepWCH8vLFokvE3oaLg6V cbhmRtZSw7hbELL8x4bzikUhc2HmKBEbddp8C/sNIn+KJu7O+O5ksioeHueGXN6WwZcl 0R2FvVHL7zEQcijBuHfGHcae+/Xzg8c4m9TeB69p0wpKfRCYwpyc3U18gobQmrEu5Lnh h1V6alzEI8ZmBed3EnO8tACiB5qcizO9kXzY3+ZD35fTMqm5JgP8jL+oPRfkGGfCwZFP BMXQ== X-Gm-Message-State: AOAM531C6u8ihrYmXmrPlqRZN9R75OyvuEEgZcV7GInCmfRGiYu0v3ft uvJDyuUFMRx4XUbaiXJfJTE= X-Google-Smtp-Source: ABdhPJxEeFZ6vuDc7FfaiND2otyL3xiZBcK7Vgh1+tUpTMHt4Cy8mql9zhsl6OV8nvicmg7VAmJMHw== X-Received: by 2002:a19:c8c6:: with SMTP id y189mr3343699lff.502.1604508592892; Wed, 04 Nov 2020 08:49:52 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:52 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 19/47] dt-bindings: memory: tegra124: Add memory client IDs Date: Wed, 4 Nov 2020 19:48:55 +0300 Message-Id: <20201104164923.21238-20-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Each memory client has unique hardware ID, add these IDs. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Acked-by: Krzysztof Kozlowski --- include/dt-bindings/memory/tegra124-mc.h | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h index 186e6b7e9b35..7e73bb400eca 100644 --- a/include/dt-bindings/memory/tegra124-mc.h +++ b/include/dt-bindings/memory/tegra124-mc.h @@ -54,4 +54,72 @@ #define TEGRA124_MC_RESET_ISP2B 22 #define TEGRA124_MC_RESET_GPU 23 +#define TEGRA124_MC_PTCR 0 +#define TEGRA124_MC_DISPLAY0A 1 +#define TEGRA124_MC_DISPLAY0AB 2 +#define TEGRA124_MC_DISPLAY0B 3 +#define TEGRA124_MC_DISPLAY0BB 4 +#define TEGRA124_MC_DISPLAY0C 5 +#define TEGRA124_MC_DISPLAY0CB 6 +#define TEGRA124_MC_AFIR 14 +#define TEGRA124_MC_AVPCARM7R 15 +#define TEGRA124_MC_DISPLAYHC 16 +#define TEGRA124_MC_DISPLAYHCB 17 +#define TEGRA124_MC_HDAR 21 +#define TEGRA124_MC_HOST1XDMAR 22 +#define TEGRA124_MC_HOST1XR 23 +#define TEGRA124_MC_MSENCSRD 28 +#define TEGRA124_MC_PPCSAHBDMAR 29 +#define TEGRA124_MC_PPCSAHBSLVR 30 +#define TEGRA124_MC_SATAR 31 +#define TEGRA124_MC_VDEBSEVR 34 +#define TEGRA124_MC_VDEMBER 35 +#define TEGRA124_MC_VDEMCER 36 +#define TEGRA124_MC_VDETPER 37 +#define TEGRA124_MC_MPCORELPR 38 +#define TEGRA124_MC_MPCORER 39 +#define TEGRA124_MC_MSENCSWR 43 +#define TEGRA124_MC_AFIW 49 +#define TEGRA124_MC_AVPCARM7W 50 +#define TEGRA124_MC_HDAW 53 +#define TEGRA124_MC_HOST1XW 54 +#define TEGRA124_MC_MPCORELPW 56 +#define TEGRA124_MC_MPCOREW 57 +#define TEGRA124_MC_PPCSAHBDMAW 59 +#define TEGRA124_MC_PPCSAHBSLVW 60 +#define TEGRA124_MC_SATAW 61 +#define TEGRA124_MC_VDEBSEVW 62 +#define TEGRA124_MC_VDEDBGW 63 +#define TEGRA124_MC_VDEMBEW 64 +#define TEGRA124_MC_VDETPMW 65 +#define TEGRA124_MC_ISPRA 68 +#define TEGRA124_MC_ISPWA 70 +#define TEGRA124_MC_ISPWB 71 +#define TEGRA124_MC_XUSB_HOSTR 74 +#define TEGRA124_MC_XUSB_HOSTW 75 +#define TEGRA124_MC_XUSB_DEVR 76 +#define TEGRA124_MC_XUSB_DEVW 77 +#define TEGRA124_MC_ISPRAB 78 +#define TEGRA124_MC_ISPWAB 80 +#define TEGRA124_MC_ISPWBB 81 +#define TEGRA124_MC_TSECSRD 84 +#define TEGRA124_MC_TSECSWR 85 +#define TEGRA124_MC_A9AVPSCR 86 +#define TEGRA124_MC_A9AVPSCW 87 +#define TEGRA124_MC_GPUSRD 88 +#define TEGRA124_MC_GPUSWR 89 +#define TEGRA124_MC_DISPLAYT 90 +#define TEGRA124_MC_SDMMCRA 96 +#define TEGRA124_MC_SDMMCRAA 97 +#define TEGRA124_MC_SDMMCR 98 +#define TEGRA124_MC_SDMMCRAB 99 +#define TEGRA124_MC_SDMMCWA 100 +#define TEGRA124_MC_SDMMCWAA 101 +#define TEGRA124_MC_SDMMCW 102 +#define TEGRA124_MC_SDMMCWAB 103 +#define TEGRA124_MC_VICSRD 108 +#define TEGRA124_MC_VICSWR 109 +#define TEGRA124_MC_VIW 114 +#define TEGRA124_MC_DISPLAYD 115 + #endif From patchwork Wed Nov 4 16:48:56 2020 Content-Type: text/plain; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:53 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 20/47] ARM: tegra: Correct EMC registers size in Tegra20 device-tree Date: Wed, 4 Nov 2020 19:48:56 +0300 Message-Id: <20201104164923.21238-21-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Fix the size of Tegra20 EMC registers, which should be twice bigger. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 72a4211a618f..9347f7789245 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -634,7 +634,7 @@ mc: memory-controller@7000f000 { memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; - reg = <0x7000f400 0x200>; + reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; From patchwork Wed Nov 4 16:48:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9923CC56201 for ; Wed, 4 Nov 2020 16:52:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 405E22072C for ; Wed, 4 Nov 2020 16:52:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Af0j9cQy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731540AbgKDQt6 (ORCPT ); Wed, 4 Nov 2020 11:49:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731533AbgKDQt5 (ORCPT ); Wed, 4 Nov 2020 11:49:57 -0500 Received: from mail-lf1-x144.google.com (mail-lf1-x144.google.com [IPv6:2a00:1450:4864:20::144]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9BA4CC0613D3; Wed, 4 Nov 2020 08:49:56 -0800 (PST) Received: by mail-lf1-x144.google.com with SMTP id l28so27978649lfp.10; Wed, 04 Nov 2020 08:49:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXc6alv2GyhB3hhhLZedHDIUdftmQRoQ6V9Gv1leNe8=; b=Af0j9cQyYfqwGbLNFMo8DQIbaHxPcvuBSdMbyhlOHUzt5ONJ9XckN8qb/gJe8W0Kax 8dqF6rNmTRvckvxhSt5vUrX9Fz5POWuCbXtXka2MhNt4wm0+lj2gJk7ZaFPlxGEVw2jh t/2wgt+iBONe4r/ISY4f2E4A6CvXXg7FotjG8H8XZI6DrKz7iiIte2dowE9Y2KEyZA7a 8e4kFZjJRTS2mANq/Grexnd1PzuveBBsFv8E35PY/EmpiNLwIXUrMPX05yVBLYFCEN/J 9VUUGVugNuyC7Z8tKrS4DtpEWHjTiwHX5DxHTVSrVrgBGoTzscatoKUltYZRN3M60QSc s+Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXc6alv2GyhB3hhhLZedHDIUdftmQRoQ6V9Gv1leNe8=; b=CpTIGKPDE/eUWpfvyT4JuEy0RtmAyoI59fNs5sf2VVJd4ckSNiENH8o6XFSeFeFZpL wK5/VH2cSrjat3Ym4zjDr5FMnXHXCITeVYsCXFgEt9uGot7uD4DdUwQE5OXvvY4BejFW WzrdNkwV1rE6agvEneekvE4wWRdNFQz5wsgsNEr4KF69x7J1/XXdz5h9PFbLW5l2YWdl eLciXfL7MunE8YtA7TctwR+7wwhGFhCecIM786mpeetYdjPwIFaCwYGGtcHDMB5oxBvd rXI8/6T58cUBmozB9dzwlcrb4r0ZZwTeSnObIAv7M6a7iaX0E4/BfoZODWZbw9lrksOe Vm9g== X-Gm-Message-State: AOAM531fnkibHlb0Y4RmcvWw9F0CS7cO7fTPno4jE7PW06j7sJHUTj3v DZ+vniT0mxz7EQuO3WwKJs8= X-Google-Smtp-Source: ABdhPJzbvyLORoXyQj3/KlGwtfFDf00kuQbn6UHu0zwxqEPLW3MMMC/l9l2xEy8HWSLg8WtRXbvnjA== X-Received: by 2002:a19:441:: with SMTP id 62mr9370540lfe.304.1604508595182; Wed, 04 Nov 2020 08:49:55 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:54 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 21/47] ARM: tegra: Add interconnect properties to Tegra20 device-tree Date: Wed, 4 Nov 2020 19:48:57 +0300 Message-Id: <20201104164923.21238-22-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add interconnect properties to the Memory Controller, External Memory Controller and the Display Controller nodes in order to describe hardware interconnection. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 9347f7789245..2e1304493f7d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -111,6 +111,17 @@ dc@54200000 { nvidia,head = <0>; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY1B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -128,6 +139,17 @@ dc@54240000 { nvidia,head = <1>; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY1BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winb-vfilter", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -630,15 +652,17 @@ mc: memory-controller@7000f000 { interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; - memory-controller@7000f400 { + emc: memory-controller@7000f400 { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = ; clocks = <&tegra_car TEGRA20_CLK_EMC>; #address-cells = <1>; #size-cells = <0>; + #interconnect-cells = <0>; }; fuse@7000f800 { From patchwork Wed Nov 4 16:49:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C368C4742C for ; Wed, 4 Nov 2020 16:52:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3EADF2072C for ; Wed, 4 Nov 2020 16:52:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TVwZDsUp" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731202AbgKDQwm (ORCPT ); Wed, 4 Nov 2020 11:52:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731558AbgKDQuA (ORCPT ); Wed, 4 Nov 2020 11:50:00 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DE4CC0613D3; Wed, 4 Nov 2020 08:50:00 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id k25so23706211lji.9; Wed, 04 Nov 2020 08:50:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eN3ruYqKrfAyq4fQITxNWZN/YF+MM8QbZauHCJzUFj8=; b=TVwZDsUpQtOop2WOQclHYZgdwB7KxiVA6R6b6Ka6vX6hiO11aEcyyoBglrOZaHUTV0 FBlAlfcq+LI3Lw8ROniDVBNNCexeo6GJZPw2yPf3ZmoTk/w08Nqj1PKSZO6RSFwz/vuG ZutKiRKbxKlOBUWZtceiMYEVekzmXhMZNgNKhbYpYws5gJY2CyEpjFvwMQe1mnXKLz0u qJuT1Dta0VmZqpT/9sZh4DHE++xDLJWMe5MTqUfl0RkJfGV4j+chzYmRqt5hAcAt9Pja jx097eDN8hxh3YgkAQ6KTzHe0sawnGRD9q8InlTq6NfD74dox4c1vCBimo6BzFUM940S MDmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eN3ruYqKrfAyq4fQITxNWZN/YF+MM8QbZauHCJzUFj8=; b=uBEGSGS2omkRnazv5oymrch7GM9U9UzJ+GrQqQB+qFROmYsKSQvetkbOOjxtvHbTiE TDAogMy9u/skGXKMgrjz3jhXG+jWtdI/4jcU+4f+eb8lkVQxSw3EFjCZT63WNYElxxmd +cDnJUHY2NDUs47ChtwsIXvJ7nnGkkcfstbefLM/CohlreG66xorn7pizeKftKSERrYi YhCBlkNtgfhKNF+gD/zZm4N77SFM0IBzsGIJQz8PE4jDB7IjAqsbxBj7CxnDs69el/h6 7xaXPKIs4prbwn4oCw9zP6hp1i8HKOzCLtJYL2i5D0vfxaG+0cKaQofNEQZ25mroFHMy mwkg== X-Gm-Message-State: AOAM530LjWH70n5G7+FWeoz4ejU3uW3yJVG+xKaOSj+HqLgxONXmoPJy eOn2v4zqNZWiNj+5ny2vaso= X-Google-Smtp-Source: ABdhPJz8F2nqtehxzpqUUCA/aUcL85BZ1uvq8mFaFu09xmcHZWeIbOxWl/DYJLu5VQOKGJT5Wkuh6Q== X-Received: by 2002:a05:651c:112a:: with SMTP id e10mr11726956ljo.411.1604508599056; Wed, 04 Nov 2020 08:49:59 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.49.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:49:58 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 24/47] ARM: tegra: Add nvidia, memory-controller phandle to Tegra20 EMC device-tree Date: Wed, 4 Nov 2020 19:49:00 +0300 Message-Id: <20201104164923.21238-25-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add nvidia,memory-controller to the Tegra20 External Memory Controller node. This allows to perform a direct lookup of the Memory Controller instead of walking up the whole tree. This puts Tegra20 device-tree on par with Tegra30+. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2e1304493f7d..8f8ad81916e7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -663,6 +663,8 @@ emc: memory-controller@7000f400 { #address-cells = <1>; #size-cells = <0>; #interconnect-cells = <0>; + + nvidia,memory-controller = <&mc>; }; fuse@7000f800 { From patchwork Wed Nov 4 16:49:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01554C388F9 for ; Wed, 4 Nov 2020 16:52:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9ADB92074B for ; Wed, 4 Nov 2020 16:52:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WkXM3DJZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731542AbgKDQwa (ORCPT ); Wed, 4 Nov 2020 11:52:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731578AbgKDQuE (ORCPT ); Wed, 4 Nov 2020 11:50:04 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 674D7C0613D3; Wed, 4 Nov 2020 08:50:04 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id i6so28060906lfd.1; Wed, 04 Nov 2020 08:50:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+t0DsU6My3tVxrD7Qav6SIahBsjxD5Qw2s4eUzqdGNQ=; b=WkXM3DJZpbpSnCdi4yI8wQF6f9BrMWMhqsOZgL2zHvULDlDWlu4jLi2R2pfW7jW7BK Dqb0BaDoTGu1UV0LeLVNGJdi/kS1I1NihnUo6PamXE1/EGl/QPfimEaEza4DaWo9CNbz y8AUmxp35Tc3QAb4FgplFCSityng7LxVMErWcDD8rFWGARJsLRtwW0Hi9OleawLXJNXh +VedqCCEuZ8aN7MDCuZyBV2gOoqey0e7Q7uI2nFI2MrqJT+6f9DnXB8mMSXun8t1m/ZG aVj0JnzmUKcXEHYVfEHEZF1Fhc1gxOYWeMEOYN032mSbAL6kxKSYVBUYqb5O0Q8MlJO3 EVqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+t0DsU6My3tVxrD7Qav6SIahBsjxD5Qw2s4eUzqdGNQ=; b=YOLkVUog74nlMt7EzfC+NOnmXwyoyoGSM+HReKZh+ZiZjfhx0vJkd/E0TuFbR7qV0N RUDQQRJYDCEijl4QwHgzbqesYBw6ZX2+L+PGHn+rm1/jlsEUYcny9ECfNfUF8jPYkPGs 2PM6mvCKR80McKkDjkS6NG/01ed3iDAdUFcIVYR5H25K2Miwzn40MsebJyjavV+Kaw2p 1/6Cc8CMFWllevnTM0t40UGB7avL/bQb3DbprbEm8FJQnhxrgOsilbGHJEDXV5qf2kGk bO0SiTw5EtoTI+2XX8x0RpFndo7Po6j+ACuI2ypahyh3zAbe489k4pom2A/1raxIErOm rwMQ== X-Gm-Message-State: AOAM532csZ27XTQRF78MhR0+276S3UK2jpuhYfmD6rYMZE/pblYZ3bE0 j29rJZuLWcuxAJGggi17Q8Y= X-Google-Smtp-Source: ABdhPJxjRwPm3/FCNhHoiprA+/pMldPxGg+SakrPRMlSdIUNbY6uSU/rrqXSaCWic/NFBTtUkQ3GBg== X-Received: by 2002:ac2:4569:: with SMTP id k9mr10939869lfm.327.1604508602608; Wed, 04 Nov 2020 08:50:02 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:02 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 27/47] ARM: tegra: Add DVFS properties to Tegra124 EMC and ACTMON device-tree nodes Date: Wed, 4 Nov 2020 19:49:03 +0300 Message-Id: <20201104164923.21238-28-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for dynamic memory bandwidth scaling based on memory utilization statistics. Remove unsupported EMC OPPs from board device-trees. Note that ACTMON watches all memory interconnect paths, but we use a single CPU-READ interconnect path for driving memory bandwidth, for simplicity. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra124-apalis-emc.dtsi | 8 + .../arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 8 + arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi | 10 + .../arm/boot/dts/tegra124-nyan-blaze-emc.dtsi | 10 + .../boot/dts/tegra124-peripherals-opp.dtsi | 419 ++++++++++++++++++ arch/arm/boot/dts/tegra124.dtsi | 6 + 6 files changed, 461 insertions(+) create mode 100644 arch/arm/boot/dts/tegra124-peripherals-opp.dtsi diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 32401457ae71..a7ac805eeed5 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -1465,3 +1465,11 @@ timing-924000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 861d3f22116b..df4e463afbd1 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -2420,3 +2420,11 @@ timing-924000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index c91647d13a50..a0f56cc9da5c 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -6649,3 +6649,13 @@ timing-792000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index d2beea0bd15f..35c98734d35f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -2048,3 +2048,13 @@ timing-792000000 { }; }; }; + +&emc_icc_dvfs_opp_table { + /delete-node/ opp@924000000,1100; + /delete-node/ opp@1200000000,1100; +}; + +&emc_bw_dfs_opp_table { + /delete-node/ opp@924000000; + /delete-node/ opp@1200000000; +}; diff --git a/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi new file mode 100644 index 000000000000..49d9420a3289 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-peripherals-opp.dtsi @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + emc_icc_dvfs_opp_table: emc-dvfs-opp-table { + compatible = "operating-points-v2"; + + opp@12750000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0003>; + }; + + opp@12750000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0008>; + }; + + opp@12750000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0010>; + }; + + opp@12750000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x0004>; + }; + + opp@20400000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0003>; + }; + + opp@20400000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0008>; + }; + + opp@20400000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0010>; + }; + + opp@20400000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x0004>; + }; + + opp@40800000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0003>; + }; + + opp@40800000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0008>; + }; + + opp@40800000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0010>; + }; + + opp@40800000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x0004>; + }; + + opp@68000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0003>; + }; + + opp@68000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0008>; + }; + + opp@68000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0010>; + }; + + opp@68000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x0004>; + }; + + opp@102000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0003>; + }; + + opp@102000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0008>; + }; + + opp@102000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0010>; + }; + + opp@102000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x0004>; + }; + + opp@204000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0003>; + }; + + opp@204000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0008>; + }; + + opp@204000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0010>; + }; + + opp@204000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x0004>; + }; + + opp@264000000,800 { + opp-microvolt = <800000 800000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0003>; + }; + + opp@264000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0008>; + }; + + opp@264000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0010>; + }; + + opp@264000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x0004>; + }; + + opp@300000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0003>; + }; + + opp@300000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0008>; + }; + + opp@300000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0010>; + }; + + opp@300000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x0004>; + }; + + opp@348000000,850 { + opp-microvolt = <850000 850000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0003>; + }; + + opp@348000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0008>; + }; + + opp@348000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0010>; + }; + + opp@348000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x0004>; + }; + + opp@396000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0008>; + }; + + opp@396000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0003>; + }; + + opp@396000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0010>; + }; + + opp@396000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x0004>; + }; + + opp@528000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0008>; + }; + + opp@528000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0003>; + }; + + opp@528000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0010>; + }; + + opp@528000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x0004>; + }; + + opp@600000000,950 { + opp-microvolt = <950000 950000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0008>; + }; + + opp@600000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0003>; + }; + + opp@600000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0010>; + }; + + opp@600000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x0004>; + }; + + opp@792000000,1000 { + opp-microvolt = <1000000 1000000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x000B>; + }; + + opp@792000000,1050 { + opp-microvolt = <1050000 1050000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0010>; + }; + + opp@792000000,1110 { + opp-microvolt = <1110000 1110000 1150000>; + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x0004>; + }; + + opp@924000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + }; + + opp@1200000000,1100 { + opp-microvolt = <1100000 1100000 1150000>; + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + }; + }; + + emc_bw_dfs_opp_table: emc-bandwidth-opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <204000>; + }; + + opp@20400000 { + opp-hz = /bits/ 64 <20400000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <326400>; + }; + + opp@40800000 { + opp-hz = /bits/ 64 <40800000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <652800>; + }; + + opp@68000000 { + opp-hz = /bits/ 64 <68000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1088000>; + }; + + opp@102000000 { + opp-hz = /bits/ 64 <102000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <1632000>; + }; + + opp@204000000 { + opp-hz = /bits/ 64 <204000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <3264000>; + }; + + opp@264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4224000>; + }; + + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <4800000>; + }; + + opp@348000000 { + opp-hz = /bits/ 64 <348000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <5568000>; + }; + + opp@396000000 { + opp-hz = /bits/ 64 <396000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <6336000>; + }; + + opp@528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <8448000>; + }; + + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <9600000>; + }; + + opp@792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-supported-hw = <0x001F>; + opp-peak-kBps = <12672000>; + }; + + opp@924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-supported-hw = <0x0013>; + opp-peak-kBps = <14784000>; + }; + + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-supported-hw = <0x0003>; + opp-peak-kBps = <19200000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 1801e30b1d3a..46441d10a3fc 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -8,6 +8,8 @@ #include #include +#include "tegra124-peripherals-opp.dtsi" + / { compatible = "nvidia,tegra124"; interrupt-parent = <&lic>; @@ -290,6 +292,9 @@ actmon@6000c800 { clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&emc_bw_dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu-read"; }; gpio: gpio@6000d000 { @@ -660,6 +665,7 @@ emc: external-memory-controller@7001b000 { clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&emc_icc_dvfs_opp_table>; #interconnect-cells = <0>; }; From patchwork Wed Nov 4 16:49:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF8BDC55179 for ; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:03 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 28/47] memory: tegra: Add and use devm_tegra_memory_controller_get() Date: Wed, 4 Nov 2020 19:49:04 +0300 Message-Id: <20201104164923.21238-29-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. Add new devm_tegra_memory_controller_get() helper to remove the code's duplication and to fix put_device() which was missed in the duplicated code. Make EMC drivers to use the new helper. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/mc.c | 48 ++++++++++++++++++++++++ drivers/memory/tegra/tegra124-emc.c | 18 ++------- drivers/memory/tegra/tegra210-emc-core.c | 39 +++++-------------- drivers/memory/tegra/tegra30-emc.c | 18 ++------- include/soc/tegra/mc.h | 10 +++++ 5 files changed, 74 insertions(+), 59 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..a72cdcafc933 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -42,6 +42,54 @@ static const struct of_device_id tegra_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); +static void tegra_mc_devm_action_put_device(void *data) +{ + struct tegra_mc *mc = data; + + put_device(mc->dev); +} + +/** + * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle + * @dev: device pointer for the consumer device + * + * This function will search for the Memory Controller node in a device-tree + * and retrieve the Memory Controller handle. + * + * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. + */ +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) +{ + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + int err; + + np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); + if (!np) + return ERR_PTR(-ENOENT); + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return ERR_PTR(-ENODEV); + + mc = platform_get_drvdata(pdev); + if (!mc) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc); + if (err) { + put_device(mc->dev); + return ERR_PTR(err); + } + + return mc; +} +EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); + static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 76ace42a688a..35dbceb7f841 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1177,7 +1177,6 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; struct resource *res; @@ -1195,20 +1194,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); ram_code = tegra_read_ram_code(); diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index cdd663ba4733..5f224796e32e 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -1828,7 +1828,6 @@ static int tegra210_emc_probe(struct platform_device *pdev) { struct thermal_cooling_device *cd; unsigned long current_rate; - struct platform_device *mc; struct tegra210_emc *emc; struct device_node *np; unsigned int i; @@ -1846,35 +1845,19 @@ static int tegra210_emc_probe(struct platform_device *pdev) spin_lock_init(&emc->lock); emc->dev = &pdev->dev; - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) { - put_device(&mc->dev); - return -EPROBE_DEFER; - } + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(emc->regs)) { - err = PTR_ERR(emc->regs); - goto put_mc; - } + if (IS_ERR(emc->regs)) + return PTR_ERR(emc->regs); for (i = 0; i < 2; i++) { emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i); - if (IS_ERR(emc->channel[i])) { - err = PTR_ERR(emc->channel[i]); - goto put_mc; - } + if (IS_ERR(emc->channel[i])) + return PTR_ERR(emc->channel[i]); + } tegra210_emc_detect(emc); @@ -1884,7 +1867,7 @@ static int tegra210_emc_probe(struct platform_device *pdev) err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal"); if (err < 0) { dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err); - goto put_mc; + return err; } err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated"); @@ -2015,8 +1998,7 @@ static int tegra210_emc_probe(struct platform_device *pdev) tegra210_clk_emc_detach(emc->clk); release: of_reserved_mem_device_release(emc->dev); -put_mc: - put_device(emc->mc->dev); + return err; } @@ -2027,7 +2009,6 @@ static int tegra210_emc_remove(struct platform_device *pdev) debugfs_remove_recursive(emc->debugfs.root); tegra210_clk_emc_detach(emc->clk); of_reserved_mem_device_release(emc->dev); - put_device(emc->mc->dev); return 0; } diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 055af0e08a2e..c58cf31cb27b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1258,7 +1258,6 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; int err; @@ -1269,17 +1268,6 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENODEV; } - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller node\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - np = emc_find_node_by_ram_code(&pdev->dev); if (!np) return -EINVAL; @@ -1290,9 +1278,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENOMEM; } - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..d9395af98143 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -184,4 +184,14 @@ struct tegra_mc { int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); +#ifdef CONFIG_TEGRA_MC +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); +#else +static inline struct tegra_mc * +devm_tegra_memory_controller_get(struct device *dev) +{ + ERR_PTR(-ENODEV); +} +#endif + #endif /* __SOC_TEGRA_MC_H__ */ From patchwork Wed Nov 4 16:49:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318278 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C059DC56201 for ; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:06 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 31/47] memory: tegra: Add missing latency allowness entry for Page Table Cache Date: Wed, 4 Nov 2020 19:49:07 +0300 Message-Id: <20201104164923.21238-32-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra114.c | 6 ++++++ drivers/memory/tegra/tegra124.c | 6 ++++++ drivers/memory/tegra/tegra30.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 48ef01c3ff90..ed376ba2d2fe 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 0cede24479bf..e2389573d3c0 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index fcdd812eed80..b1990b4133d8 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -36,6 +36,12 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", From patchwork Wed Nov 4 16:49:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9628C56202 for ; Wed, 4 Nov 2020 16:52:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C2CE2074B for ; Wed, 4 Nov 2020 16:52:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UE6ahmZU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731627AbgKDQuM (ORCPT ); Wed, 4 Nov 2020 11:50:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731614AbgKDQuK (ORCPT ); Wed, 4 Nov 2020 11:50:10 -0500 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22AC2C0613D4; Wed, 4 Nov 2020 08:50:10 -0800 (PST) Received: by mail-lf1-x143.google.com with SMTP id y184so26066572lfa.12; Wed, 04 Nov 2020 08:50:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xF3849VzaoUkwlJVQxMK0p9EE4An5iO4TNW5KJUNqkI=; b=UE6ahmZUXgLanUgmwbF1+Kd66O+g7zjrTXzmDdlckuUHhusQSlWDArUYNSyxEO9mBg p9DTK3RPcrOKbkp4WVtFIyRjUIYh+zG04OEDAj8SR7PIsP0G5w//GxalgPcJ7iIGnAS7 Bsnuw7azSvuq+HkpLF6+JuSlVN+jDrewSBMSrFKS3kMzT7mquDt7y4KZdxCOCJ++Xzot /HXkQiStUWUKjAOkBMUTZdU3YEcDq9/V8mP2/QqqfJRlrKoO4VPZycbqygy2csUsu2r/ dA11SxFk9K0LYanmtP5jr4I4hq/QQlY0xR6dTHl+gMMXa5+1jotKsGk067DesV+lXOTT sQyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xF3849VzaoUkwlJVQxMK0p9EE4An5iO4TNW5KJUNqkI=; b=Yz0aVdMiRS18TB5f6HgOP/3QYSNOAj1mQd912KQxgfcnE3j+Fh2IRaHMM4b2NlUkQL d82VfOUBdW6Q7w0W0NIUQN8DKeQKTVUjfrfr9cuKCpK0oxb26pnenxAKDw2bKzK14GWn JLNoCZYu+yJfWXr4RE1ciDyuRTz0nkKcwfTP8gU23E4YhpLTGejPnHW4MvTaB8S4JOWN LkrPirKKz79aOVb222arWOi8MU4E+a4cRePX27K4hQUX5OiRAJnGfDGlOBCAdr71tAlk Ib4tpLR/NM4nxJyujV87l2x5d15CQoefWa/54Qv7zjaVnLbHNyDLe0G9sA5ofMTn7rnT pfOQ== X-Gm-Message-State: AOAM530L4nofMYon2UyO2FKBxt5cw7e9agt4WsqXPK3vHeokA2KwZjr0 1glyfTYMrU5TfWyW5KPVVf4= X-Google-Smtp-Source: ABdhPJyIRbpopM66GwgNH/xaZzCBjvCrNQQGoQ0QhDsmeMrJWLANUvsikptUHHjPcycTxkBTX+YRyw== X-Received: by 2002:a19:3ce:: with SMTP id 197mr13207lfd.364.1604508608569; Wed, 04 Nov 2020 08:50:08 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:08 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 32/47] memory: tegra-mc: Add interconnect framework Date: Wed, 4 Nov 2020 19:49:08 +0300 Message-Id: <20201104164923.21238-33-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 22 ++++++++ include/soc/tegra/mc.h | 17 ++++++ 4 files changed, 140 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 9f0a96bf9ccc..b38e5255effe 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 998f9148ecb8..a7e6a8e4c95a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -639,6 +639,101 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_node *node; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!device_property_present(mc->dev, "#interconnect-cells") || + !mc->soc->icc_ops) + return 0; + + mc->provider.dev = mc->dev; + mc->provider.data = &mc->provider; + mc->provider.set = mc->soc->icc_ops->set; + mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < mc->soc->num_clients; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + } + + /* + * MC driver is registered too early, so early that generic driver + * syncing doesn't work for the MC. But it doesn't really matter + * since syncing works for the EMC drivers, hence we can sync the + * MC driver by ourselves and then EMC will complete syncing of + * the whole ICC state. + */ + icc_sync_state(mc->dev); + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -727,6 +822,11 @@ static int tegra_mc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + err = tegra_mc_interconnect_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); if (IS_ERR(mc->smmu)) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..33e40d600592 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -78,6 +78,20 @@ #define MC_TIMING_UPDATE BIT(0) +static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) +{ + val = val * percents; + do_div(val, 100); + + return min_t(u64, val, U32_MAX); +} + +static inline struct tegra_mc * +icc_provider_to_tegra_mc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_mc, provider); +} + static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -115,4 +129,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra ICC drivers. The ID numbers are + * chosen such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_MC 1000 +#define TEGRA_ICC_EMC 1001 +#define TEGRA_ICC_EMEM 1002 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d9395af98143..43876216de34 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -6,7 +6,9 @@ #ifndef __SOC_TEGRA_MC_H__ #define __SOC_TEGRA_MC_H__ +#include #include +#include #include #include @@ -141,6 +143,17 @@ struct tegra_mc_reset_ops { const struct tegra_mc_reset *rst); }; +#define TEGRA_MC_ICC_TAG_DEFAULT 0 +#define TEGRA_MC_ICC_TAG_ISO BIT(0) + +struct tegra_mc_icc_ops { + int (*set)(struct icc_node *src, struct icc_node *dst); + int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, + void *data); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -160,6 +173,8 @@ struct tegra_mc_soc { const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; unsigned int num_resets; + + const struct tegra_mc_icc_ops *icc_ops; }; struct tegra_mc { @@ -178,6 +193,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; From patchwork Wed Nov 4 16:49:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03C32C2D0A3 for ; Wed, 4 Nov 2020 16:52:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FBE02080D for ; Wed, 4 Nov 2020 16:52:18 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="tnVjUemh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731491AbgKDQwM (ORCPT ); Wed, 4 Nov 2020 11:52:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731623AbgKDQuL (ORCPT ); Wed, 4 Nov 2020 11:50:11 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B9BAC061A4A; Wed, 4 Nov 2020 08:50:11 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id l28so27979777lfp.10; Wed, 04 Nov 2020 08:50:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xT24YybZ9ESCUzYgdGCxIPBX3gyhxeGvxD42woUTjp4=; b=tnVjUemha3ft441R6cHZarZDnvpO3jI+yLR26WM4VdGva6bOHWI1NSLO+Zp3h/iOr3 uE9svPHNVMKaQoLP/0ekpVZ0tKKI9Hw0dSaImzIqUCcrRzDbn9VUmanH6I0TzpBBxstZ WtckXa9nAXWgwhVlOsECB5/M90E7JkP8MTobICLfHGcQd9aa3qOWJhYoJwIaZ+1u+SLg eaVbg9YBU3pgbUQQCdgaUpULNa1ujdp4tQX2uPEeM4ricWugMwxgfaIUJ4uy+LbNvGtx BdUFMFJ3NuP+QGTgxgGunCYHimKMyL3jlIG/pyqj/2hfVmhghKjLoj/eWumXn7E6O5Bx IWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xT24YybZ9ESCUzYgdGCxIPBX3gyhxeGvxD42woUTjp4=; b=jBldAqmr/eV6Lqwd/WjtbxJPkgvuT0puub6DtYpbd7bS//dLducF7Y1hSAEEUBDze1 lEIwoJuB/NSRZbzGmAvo69YvHkOo1f0W7iOOtvdN0PK8ZmNl/BnbCITMcU5kdVAiMmxS wMFYrch148isyZ305ZUmzYGFEvq41eRJ3n2Y+mfNyivkfni+AKVo9NxkC2sqw0Zbf6LG 9gOZz90ajdTA8prv4ZbPTjaWdn2kXXMjTmPDWsXe9lxYwKkw4gCVobDjoXFrC1NaU0BU Z9t82SWz1saYS8F0dP/KASfnjq5QLkxdWQAL9TW1GrbVWqzixP8wOgoAQeXCxMI51ZzV 45TQ== X-Gm-Message-State: AOAM530mcG5mfhZIVBxR76J0jmNQoLzWHd1dirZHfIC0BxItZR9OD8fq qrf8mP23JWeJTCD/sR0yjBY= X-Google-Smtp-Source: ABdhPJzBVgcu5tqRSkCoQPWfnMYlkh8Bf1SUYRqiEau5NByTFy2W61uGqqDNsNINaJKset+Q4hRvdg== X-Received: by 2002:a19:3fd6:: with SMTP id m205mr9540980lfa.1.1604508609726; Wed, 04 Nov 2020 08:50:09 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:09 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 33/47] memory: tegra20-emc: Make driver modular Date: Wed, 4 Nov 2020 19:49:09 +0300 Message-Id: <20201104164923.21238-34-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index b38e5255effe..ff426747cd7d 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -9,7 +9,7 @@ config TEGRA_MC NVIDIA Tegra SoCs. config TEGRA20_EMC - bool "NVIDIA Tegra20 External Memory Controller driver" + tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on ARCH_TEGRA_2x_SOC help diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index c9fe58a724ee..88619e3ec435 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -721,6 +721,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -733,6 +740,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -742,9 +750,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Nov 4 16:49:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFD91C2D0A3 for ; Wed, 4 Nov 2020 16:51:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 707C9206FA for ; Wed, 4 Nov 2020 16:51:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UuiLj6/s" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731655AbgKDQuQ (ORCPT ); Wed, 4 Nov 2020 11:50:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731646AbgKDQuP (ORCPT ); Wed, 4 Nov 2020 11:50:15 -0500 Received: from mail-lj1-x241.google.com (mail-lj1-x241.google.com [IPv6:2a00:1450:4864:20::241]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D4608C061A4A; Wed, 4 Nov 2020 08:50:14 -0800 (PST) Received: by mail-lj1-x241.google.com with SMTP id l10so2706116lji.4; Wed, 04 Nov 2020 08:50:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kCuTBwtWaV5rTPzoo97NAJ/dzAFCROA+rv3htyyQcDo=; b=UuiLj6/s+EbDYa/k+dq5ICVHOVkfl+n+aBMKyJdQroB1c7U/3wlg8tbKMa9NufljZz 1qqywuQhA7+ARKHWT23DNmeSg5KwQlgWhrqYAnL2Y9fU3A8V0MWzD+RtbYaXVu7dYbAR YMFifnmzQMZPFMtIKJTi3/+7lxsZP5TzL7GMUDSC1+kiZlhyz7K6Vt7oEbZV5o6Swv/9 wW2FJhZ5rRxPclHHaYwDcrqxQktl8h4NNiXop+M0L4WMLMDHCQ1MStAauHYFooiApJ0X /v9iT7aRlkQeaJedAcWHrDfLrI+Y+od8DlrhQGMR6X/SvRt838FuuYRoRcws8v0CzCWk DFLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kCuTBwtWaV5rTPzoo97NAJ/dzAFCROA+rv3htyyQcDo=; b=DFugnHoUBG+PPqbn1kXItY5H87Qs5qZLn9VqWj1/bkB3+YMKAT9UcppfdAoPX/LmJV T6tSxi+D7jznBc71Rp+bCre7fo+TlVZOO8TYLIYhErlK4OgTzjro/YW7Szrgd32ZjIMg 6186iNHVp3ol/C8tjyduO1VIpHbzKMqIlTvFrEikgJSYLAL3KH7gXID8WB5C+oelhZdl c4AAM5pygz40bab5Lhu09s6DvtKj6tcrDS78WcdkrHTwVuUzBaJDuLKfCHxyksn2JAs9 IP8rpQIU++g5LEmUdCpInI7Qx+nBPjqN5BylJaqdgMiBrzre/8jRk5YiZK4G6GzVAW6h sEKw== X-Gm-Message-State: AOAM533xMhHWmig0gyTdpaezj6IYg4ZJWCB65lR2280hsYJ2sodxhGIV rc2gdNt5p/V8ILAlq85CfFE= X-Google-Smtp-Source: ABdhPJyBUPK9Ebs2gdg0YBD5JQIDXdruDICmmtpi6jK+P/Q54GwEGbgCzW/PrSD2DKRzlIHw8ZM3rA== X-Received: by 2002:a2e:9c84:: with SMTP id x4mr10585644lji.326.1604508613360; Wed, 04 Nov 2020 08:50:13 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:12 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 36/47] memory: tegra20-emc: Add devfreq support Date: Wed, 4 Nov 2020 19:49:12 +0300 Message-Id: <20201104164923.21238-37-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 2 + drivers/memory/tegra/tegra20-emc.c | 92 ++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ac3dfe155505..76e9a3b10839 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -12,6 +12,8 @@ config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select PM_DEVFREQ select PM_OPP help This driver is for the External Memory Controller (EMC) found on diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5e10aa97809f..9946b957bb01 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,10 @@ #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) +#define EMC_PWR_GATHER_CLEAR (1 << 8) +#define EMC_PWR_GATHER_DISABLE (2 << 8) +#define EMC_PWR_GATHER_ENABLE (3 << 8) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -157,6 +162,7 @@ struct emc_timing { }; enum emc_rate_request_type { + EMC_RATE_DEVFREQ, EMC_RATE_DEBUG, EMC_RATE_ICC, EMC_RATE_TYPE_MAX, @@ -193,6 +199,9 @@ struct tegra_emc { /* protect shared rate-change code path */ struct mutex rate_lock; + + struct devfreq_simple_ondemand_data ondemand_data; + struct devfreq *devfreq; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -952,6 +961,88 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) return err; } +static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + unsigned long rate; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) { + dev_err(dev, "failed to find opp for %lu Hz\n", *freq); + return PTR_ERR(opp); + } + + rate = dev_pm_opp_get_freq(opp); + dev_pm_opp_put(opp); + + return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); +} + +static int tegra_emc_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + + /* freeze counters */ + writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); + + /* + * busy_time: number of clocks EMC request was accepted + * total_time: number of clocks PWR_GATHER control was set to ENABLE + */ + stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); + stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); + stat->current_frequency = clk_get_rate(emc->clk); + + /* clear counters and restart */ + writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); + + return 0; +} + +static struct devfreq_dev_profile tegra_emc_devfreq_profile = { + .polling_ms = 30, + .target = tegra_emc_devfreq_target, + .get_dev_status = tegra_emc_devfreq_get_dev_status, +}; + +static int tegra_emc_devfreq_init(struct tegra_emc *emc) +{ + int err; + + /* + * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold + * should be less than 50. Secondly, multiple active memory clients + * may cause over 20% of lost clock cycles due to stalls caused by + * competing memory accesses. This means that threshold should be + * set to a less than 30 in order to have a properly working governor. + */ + emc->ondemand_data.upthreshold = 20; + + /* + * Reset statistic gathers state, select global bandwidth for the + * statistics collection mode and set clocks counter saturation + * limit to maximum. + */ + writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); + writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); + + emc->devfreq = devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &emc->ondemand_data); + if (IS_ERR(emc->devfreq)) { + err = PTR_ERR(emc->devfreq); + dev_err(emc->dev, "failed to initialize devfreq: %d", err); + return err; + } + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1019,6 +1110,7 @@ static int tegra_emc_probe(struct platform_device *pdev) tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); tegra_emc_interconnect_init(emc); + tegra_emc_devfreq_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some From patchwork Wed Nov 4 16:49:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D5ADC4741F for ; Wed, 4 Nov 2020 16:51:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 342BB207BB for ; Wed, 4 Nov 2020 16:51:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZSbhPJy+" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731383AbgKDQvo (ORCPT ); Wed, 4 Nov 2020 11:51:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731679AbgKDQuT (ORCPT ); Wed, 4 Nov 2020 11:50:19 -0500 Received: from mail-lj1-x242.google.com (mail-lj1-x242.google.com [IPv6:2a00:1450:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 687D2C0613D3; Wed, 4 Nov 2020 08:50:18 -0800 (PST) Received: by mail-lj1-x242.google.com with SMTP id 11so4152096ljf.2; Wed, 04 Nov 2020 08:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=izp2ksHAO+wXie+2l0gXWSi66nlfDA4Ls06awQYimtk=; b=ZSbhPJy+i9CAPke/+CZhzWgL4z8f/nhLEmTxqV30f5j/UX/6kn3yKfAyThktTI58mX dJl7hyeuu1c7/ReyASCZGnojEGiZzh4o8BuBewRzvY8L7acG37GZwnkfclWf730/zruD kYzq1BrFrEbL8kKSTnuXM3qGFBJnuYq5rGXWaLtccngDz2RmSeyzVf54h+4RqVd3Skcu v1/mnJuCkYfv8I0DLUgXyoG5I1jSBXYN7DkqgmNMEk245hy9LYVGgwnUrlnCQAe0Gdo7 eDtYt/En8kuE/JatU/1FLfm5+mHi5m2ymaAYI9SvRhOnvbHwAP4DEAB0h5A5QhIyssuh 4HEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=izp2ksHAO+wXie+2l0gXWSi66nlfDA4Ls06awQYimtk=; b=q52h1/oZ/pzFYc5IyqU/7aQkuqsQek7OVwrXvPjLJa+Lu9Urp9cW9uW+yQdNR0Q9te yRZZPDSyJe4+0R3J5ps+9/jGuOwOd1axw0mBR2p+V5Whz9K3820YANgFildn6TDK/VDt p+h3y6KkBxG794v1Olq0r2kN0o/PbuaS+0sC+USMCUWJ+mbv50qsrCvSfCzENnyp2eKX 77lTA49fObPcinRnTV+U/od++J5iGWUPVyxal70Isk/z0Z+3ziwI4EKGTj3wzLlFTm7c pHCKl20T5dWaDtpJdGO7hYsCJenAWJYz28Z2IsunwNORrZvtD6h4AybNg0wMwXgASUpK dfoA== X-Gm-Message-State: AOAM533xaKwywP1KahTtA2xQ8kwvA9LlN3i6L343Dnywef/8QQMRyNbM wFkPQeHSPf4DcceW38Rsdao= X-Google-Smtp-Source: ABdhPJypy/YRT5SviNbc5zSng8+8YgyICH7R9f1F0Gr28hWR6kAn7+N6hfwHyRQR/bOT8kYsV4qq9w== X-Received: by 2002:a2e:9015:: with SMTP id h21mr11349743ljg.450.1604508616906; Wed, 04 Nov 2020 08:50:16 -0800 (PST) Received: from localhost.localdomain (109-252-192-83.dynamic.spd-mgts.ru. [109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:16 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 39/47] memory: tegra30-emc: Continue probing if timings are missing in device-tree Date: Wed, 4 Nov 2020 19:49:15 +0300 Message-Id: <20201104164923.21238-40-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index d0926088360a..3488786da03b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -988,6 +988,11 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + ram_code = tegra_read_ram_code(); for_each_child_of_node(dev->of_node, np) { @@ -1057,6 +1062,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -1262,16 +1270,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int err; - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "device-tree node doesn't have memory timings\n"); - return -ENODEV; - } - - np = emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); if (!emc) { of_node_put(np); @@ -1285,10 +1283,13 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) From patchwork Wed Nov 4 16:49:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4A2C2D0A3 for ; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:17 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 40/47] memory: tegra30: Support interconnect framework Date: Wed, 4 Nov 2020 19:49:16 +0300 Message-Id: <20201104164923.21238-41-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Tested-by: Peter Geis Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra30-emc.c | 292 ++++++++++++++++++++++++++++- drivers/memory/tegra/tegra30.c | 173 ++++++++++++++++- 3 files changed, 463 insertions(+), 3 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 6779a2201fe4..e7c295d50734 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -25,6 +25,7 @@ config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra30 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 3488786da03b..6b20ce9f16af 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,16 +14,21 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #include +#include #include #include "mc.h" @@ -323,9 +328,21 @@ struct emc_timing { bool emc_cfg_dyn_self_ref; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; struct tegra_mc *mc; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; @@ -352,6 +369,15 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; static int emc_seq_update_timing(struct tegra_emc *emc) @@ -1094,6 +1120,83 @@ static long emc_round_rate(unsigned long rate, return timing->rate; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -1177,7 +1280,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1207,7 +1310,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1264,6 +1367,181 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + const unsigned int dram_data_bus_width_bytes = 4; + const unsigned int ddr = 2; + int err; + + /* + * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc = emc->mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(emc->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1280,6 +1558,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (IS_ERR(emc->mc)) return PTR_ERR(emc->mc); + mutex_init(&emc->rate_lock); emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; @@ -1328,8 +1607,14 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); + tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -1340,6 +1625,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -1397,6 +1684,7 @@ static struct platform_driver tegra_emc_driver = { .of_match_table = tegra_emc_of_match, .pm = &tegra_emc_pm_ops, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index d0314f29608d..ea849003014b 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -4,7 +4,8 @@ */ #include -#include +#include +#include #include @@ -1083,6 +1084,175 @@ static const struct tegra_mc_reset tegra30_mc_resets[] = { TEGRA30_MC_RESET(VI, 0x200, 0x204, 17), }; +static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, + const struct tegra_mc_client *client, + unsigned int bandwidth_mbytes_sec) +{ + u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div; + const struct tegra_mc_la *la = &client->la; + unsigned int fifo_size = client->fifo_size; + u32 arb_nsec, la_ticks, value; + + /* see 18.4.1 Client Configuration in Tegra3 TRM v03p */ + if (bandwidth_mbytes_sec) + arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec; + else + arb_nsec = U32_MAX; + + /* + * Latency allowness should be set with consideration for the module's + * latency tolerance and internal buffering capabilities. + * + * Display memory clients use isochronous transfers and have very low + * tolerance to a belated transfers. Hence we need to compensate the + * memory arbitration imperfection for them in order to prevent FIFO + * underflow condition when memory bus is busy. + * + * VI clients also need a stronger compensation. + */ + switch (client->swgroup) { + case TEGRA_SWGROUP_MPCORE: + case TEGRA_SWGROUP_PTC: + /* + * We always want lower latency for these clients, hence + * don't touch them. + */ + return; + + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 2; + break; + + case TEGRA_SWGROUP_VI: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 1; + break; + + default: + arb_tolerance_compensation_nsec = 150; + arb_tolerance_compensation_div = 1; + break; + } + + if (arb_nsec > arb_tolerance_compensation_nsec) + arb_nsec -= arb_tolerance_compensation_nsec; + else + arb_nsec = 0; + + arb_nsec /= arb_tolerance_compensation_div; + + /* + * Latency allowance is a number of ticks a request from a particular + * client may wait in the EMEM arbiter before it becomes a high-priority + * request. + */ + la_ticks = arb_nsec / mc->tick; + la_ticks = min(la_ticks, la->mask); + + value = mc_readl(mc, la->reg); + value &= ~(la->mask << la->shift); + value |= la_ticks << la->shift; + mc_writel(mc, value, la->reg); +} + +static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider); + const struct tegra_mc_client *client = &mc->soc->clients[src->id]; + u64 peak_bandwidth = icc_units_to_bps(src->peak_bw); + + /* + * Skip pre-initialization that is done by icc_node_add(), which sets + * bandwidth to maximum for all clients before drivers are loaded. + * + * This doesn't make sense for us because we don't have drivers for all + * clients and it's okay to keep configuration left from bootloader + * during boot, at least for today. + */ + if (src == dst) + return 0; + + /* convert bytes/sec to megabytes/sec */ + do_div(peak_bandwidth, 1000000); + + tegra30_mc_tune_client_latency(mc, client, peak_bandwidth); + + return 0; +} + +static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + const struct tegra_mc_client *client; + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + client = &mc->soc->clients[idx]; + ndata->node = node; + + switch (client->swgroup) { + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + case TEGRA_SWGROUP_PTC: + case TEGRA_SWGROUP_VI: + /* these clients are isochronous by default */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + break; + + default: + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + break; + } + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = { + .xlate_extended = tegra30_mc_of_icc_xlate_extended, + .aggregate = tegra30_mc_icc_aggreate, + .set = tegra30_mc_icc_set, +}; + const struct tegra_mc_soc tegra30_mc_soc = { .clients = tegra30_mc_clients, .num_clients = ARRAY_SIZE(tegra30_mc_clients), @@ -1097,4 +1267,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra30_mc_resets, .num_resets = ARRAY_SIZE(tegra30_mc_resets), + .icc_ops = &tegra30_mc_icc_ops, }; From patchwork Wed Nov 4 16:49:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 318274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BBD7C63699 for ; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:20 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 42/47] memory: tegra124: Support interconnect framework Date: Wed, 4 Nov 2020 19:49:18 +0300 Message-Id: <20201104164923.21238-43-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra124-emc.c | 325 +++++++++++++++++++++++++++- drivers/memory/tegra/tegra124.c | 82 ++++++- 3 files changed, 396 insertions(+), 12 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index b5824c6cf664..7c3c6467b9db 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -36,6 +36,7 @@ config TEGRA124_EMC tristate "NVIDIA Tegra124 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_124_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra124 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index edfbf6d6d357..0cc4efbce975 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -12,20 +12,26 @@ #include #include #include +#include #include #include +#include #include #include #include +#include #include #include #include #include +#include "mc.h" + #define EMC_FBIO_CFG5 0x104 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 +#define EMC_FBIO_CFG5_DRAM_WIDTH_X64 BIT(4) #define EMC_INTSTATUS 0x0 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) @@ -461,6 +467,17 @@ struct emc_timing { u32 emc_zcal_interval; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; @@ -471,6 +488,7 @@ struct tegra_emc { struct clk *clk; enum emc_dram_type dram_type; + unsigned int dram_bus_width; unsigned int dram_num; struct emc_timing last_timing; @@ -482,6 +500,17 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + struct icc_provider provider; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; /* Timing change sequence functions */ @@ -870,6 +899,14 @@ static void emc_read_current_timing(struct tegra_emc *emc, static int emc_init(struct tegra_emc *emc) { emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); + + if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64) + emc->dram_bus_width = 64; + else + emc->dram_bus_width = 32; + + dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; @@ -1009,6 +1046,83 @@ tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) return NULL; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -1081,7 +1195,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1111,7 +1225,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1129,15 +1243,6 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) unsigned int i; int err; - emc->clk = devm_clk_get(dev, "emc"); - if (IS_ERR(emc->clk)) { - if (PTR_ERR(emc->clk) != -ENODEV) { - dev_err(dev, "failed to get EMC clock: %ld\n", - PTR_ERR(emc->clk)); - return; - } - } - emc->debugfs.min_rate = ULONG_MAX; emc->debugfs.max_rate = 0; @@ -1177,6 +1282,182 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes; + const unsigned int ddr = 2; + int err; + + /* + * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + dram_data_bus_width_bytes = emc->dram_bus_width / 8; + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc = emc->mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); + struct opp_table *opp_table, *hw_opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(emc->dev, "failed to set supported HW: %d\n", err); + goto put_table; + } + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_hw; + } + + dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_hw: + dev_pm_opp_put_supported_hw(opp_table); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1188,6 +1469,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!emc) return -ENOMEM; + mutex_init(&emc->rate_lock); emc->dev = &pdev->dev; emc->regs = devm_platform_ioremap_resource(pdev, 0); @@ -1231,9 +1513,24 @@ static int tegra_emc_probe(struct platform_device *pdev) tegra124_clk_set_emc_callbacks(tegra_emc_prepare_timing_change, tegra_emc_complete_timing_change); + emc->clk = devm_clk_get(&pdev->dev, "emc"); + if (IS_ERR(emc->clk)) { + err = PTR_ERR(emc->clk); + dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err); + goto unset_cb; + } + + err = tegra_emc_opp_table_init(emc); + if (err) + goto unset_cb; + + tegra_emc_rate_requests_init(emc); + if (IS_ENABLED(CONFIG_DEBUG_FS)) emc_debugfs_init(&pdev->dev, emc); + tegra_emc_interconnect_init(emc); + /* * Don't allow the kernel module to be unloaded. Unloading adds some * extra complexity which doesn't really worth the effort in a case of @@ -1242,6 +1539,11 @@ static int tegra_emc_probe(struct platform_device *pdev) try_module_get(THIS_MODULE); return 0; + +unset_cb: + tegra124_clk_set_emc_callbacks(NULL, NULL); + + return err; }; static struct platform_driver tegra_emc_driver = { @@ -1250,6 +1552,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index e2389573d3c0..459211f50c08 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -4,7 +4,8 @@ */ #include -#include +#include +#include #include @@ -1010,6 +1011,83 @@ static const struct tegra_mc_reset tegra124_mc_resets[] = { TEGRA124_MC_RESET(GPU, 0x970, 0x974, 2), }; +static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* TODO: program PTSA */ + return 0; +} + +static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + const struct tegra_mc_client *client; + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + client = &mc->soc->clients[idx]; + ndata->node = node; + + switch (client->swgroup) { + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + case TEGRA_SWGROUP_PTC: + case TEGRA_SWGROUP_VI: + /* these clients are isochronous by default */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + break; + + default: + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + break; + } + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = { + .xlate_extended = tegra124_mc_of_icc_xlate_extended, + .aggregate = tegra124_mc_icc_aggreate, + .set = tegra124_mc_icc_set, +}; + #ifdef CONFIG_ARCH_TEGRA_124_SOC static const unsigned long tegra124_mc_emem_regs[] = { MC_EMEM_ARB_CFG, @@ -1061,6 +1139,7 @@ const struct tegra_mc_soc tegra124_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), + .icc_ops = &tegra124_mc_icc_ops, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ @@ -1091,5 +1170,6 @@ const struct tegra_mc_soc tegra132_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra124_mc_resets, .num_resets = ARRAY_SIZE(tegra124_mc_resets), + .icc_ops = &tegra124_mc_icc_ops, }; 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:21 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 43/47] drm/tegra: dc: Support memory bandwidth management Date: Wed, 4 Nov 2020 19:49:19 +0300 Message-Id: <20201104164923.21238-44-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. Let's wire up the interconnect API support to the DC driver in order to fix the distorted display output on T30 Ouya, T124 TK1 and other Tegra devices. Tested-by: Peter Geis Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/Kconfig | 1 + drivers/gpu/drm/tegra/dc.c | 349 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dc.h | 14 ++ drivers/gpu/drm/tegra/drm.c | 14 ++ drivers/gpu/drm/tegra/hub.c | 3 + drivers/gpu/drm/tegra/plane.c | 121 ++++++++++++ drivers/gpu/drm/tegra/plane.h | 15 ++ 7 files changed, 517 insertions(+) diff --git a/drivers/gpu/drm/tegra/Kconfig b/drivers/gpu/drm/tegra/Kconfig index 5043dcaf1cf9..1650a448eabd 100644 --- a/drivers/gpu/drm/tegra/Kconfig +++ b/drivers/gpu/drm/tegra/Kconfig @@ -9,6 +9,7 @@ config DRM_TEGRA select DRM_MIPI_DSI select DRM_PANEL select TEGRA_HOST1X + select INTERCONNECT select IOMMU_IOVA select CEC_CORE if CEC_NOTIFIER help diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 2d86627b0d4e..14168f792977 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -616,6 +617,9 @@ static int tegra_plane_atomic_check(struct drm_plane *plane, struct tegra_dc *dc = to_tegra_dc(state->crtc); int err; + plane_state->peak_memory_bandwidth = 0; + plane_state->avg_memory_bandwidth = 0; + /* no need for further checks if the plane is being disabled */ if (!state->crtc) return 0; @@ -802,6 +806,12 @@ static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, formats = dc->soc->primary_formats; modifiers = dc->soc->modifiers; + err = tegra_plane_interconnect_init(plane); + if (err) { + kfree(plane); + return ERR_PTR(err); + } + err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, &tegra_plane_funcs, formats, num_formats, modifiers, type, NULL); @@ -833,9 +843,13 @@ static const u32 tegra_cursor_plane_formats[] = { static int tegra_cursor_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { + struct tegra_plane_state *plane_state = to_tegra_plane_state(state); struct tegra_plane *tegra = to_tegra_plane(plane); int err; + plane_state->peak_memory_bandwidth = 0; + plane_state->avg_memory_bandwidth = 0; + /* no need for further checks if the plane is being disabled */ if (!state->crtc) return 0; @@ -973,6 +987,12 @@ static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); formats = tegra_cursor_plane_formats; + err = tegra_plane_interconnect_init(plane); + if (err) { + kfree(plane); + return ERR_PTR(err); + } + err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, &tegra_plane_funcs, formats, num_formats, NULL, @@ -1087,6 +1107,12 @@ static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, num_formats = dc->soc->num_overlay_formats; formats = dc->soc->overlay_formats; + err = tegra_plane_interconnect_init(plane); + if (err) { + kfree(plane); + return ERR_PTR(err); + } + if (!cursor) type = DRM_PLANE_TYPE_OVERLAY; else @@ -1204,6 +1230,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) { struct tegra_dc_state *state = to_dc_state(crtc->state); struct tegra_dc_state *copy; + unsigned int i; copy = kmalloc(sizeof(*copy), GFP_KERNEL); if (!copy) @@ -1215,6 +1242,9 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) copy->div = state->div; copy->planes = state->planes; + for (i = 0; i < ARRAY_SIZE(state->plane_peak_bw); i++) + copy->plane_peak_bw[i] = state->plane_peak_bw[i]; + return ©->base; } @@ -1741,6 +1771,106 @@ static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) return -ETIMEDOUT; } +static void +tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, + struct drm_atomic_state *state, + bool prepare_bandwidth_transition) +{ + const struct tegra_plane_state *old_tegra_state, *new_tegra_state; + const struct tegra_dc_state *old_dc_state, *new_dc_state; + u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw; + const struct drm_plane_state *old_plane_state; + const struct drm_crtc_state *old_crtc_state; + struct tegra_dc_window window, old_window; + struct tegra_dc *dc = to_tegra_dc(crtc); + struct tegra_plane *tegra; + struct drm_plane *plane; + + if (dc->soc->has_nvdisplay) + return; + + old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); + old_dc_state = to_const_dc_state(old_crtc_state); + new_dc_state = to_const_dc_state(crtc->state); + + if (!crtc->state->active) { + if (!old_crtc_state->active) + return; + + /* + * When CRTC is disabled on DPMS, the state of attached planes + * is kept unchanged. Hence we need to enforce removal of the + * bandwidths from the ICC paths. + */ + drm_atomic_crtc_for_each_plane(plane, crtc) { + tegra = to_tegra_plane(plane); + + icc_set_bw(tegra->icc_mem, 0, 0); + icc_set_bw(tegra->icc_mem_vfilter, 0, 0); + } + + return; + } + + for_each_old_plane_in_state(old_crtc_state->state, plane, + old_plane_state, i) { + old_tegra_state = to_const_tegra_plane_state(old_plane_state); + new_tegra_state = to_const_tegra_plane_state(plane->state); + tegra = to_tegra_plane(plane); + + /* + * We're iterating over the global atomic state and it contains + * planes from another CRTC, hence we need to filter out the + * planes unrelated to this CRTC. + */ + if (tegra->dc != dc) + continue; + + new_avg_bw = new_tegra_state->avg_memory_bandwidth; + old_avg_bw = old_tegra_state->avg_memory_bandwidth; + + new_peak_bw = new_dc_state->plane_peak_bw[tegra->index]; + old_peak_bw = old_dc_state->plane_peak_bw[tegra->index]; + + /* + * See the comment related to !crtc->state->active above, + * which explains why bandwidths need to be updated when + * CRTC is turning ON. + */ + if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw && + old_crtc_state->active) + continue; + + window.src.h = drm_rect_height(&plane->state->src) >> 16; + window.dst.h = drm_rect_height(&plane->state->dst); + + old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; + old_window.dst.h = drm_rect_height(&old_plane_state->dst); + + /* + * During the preparation phase (atomic_begin), the memory + * freq should go high before the DC changes are committed + * if bandwidth requirement goes up, otherwise memory freq + * should to stay high if BW requirement goes down. The + * opposite applies to the completion phase (post_commit). + */ + if (prepare_bandwidth_transition) { + new_avg_bw = max(old_avg_bw, new_avg_bw); + new_peak_bw = max(old_peak_bw, new_peak_bw); + + if (tegra_plane_use_vertical_filtering(tegra, &old_window)) + window = old_window; + } + + icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); + + if (tegra_plane_use_vertical_filtering(tegra, &window)) + icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); + else + icc_set_bw(tegra->icc_mem_vfilter, 0, 0); + } +} + static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -1922,6 +2052,8 @@ static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, { unsigned long flags; + tegra_crtc_update_memory_bandwidth(crtc, state, true); + if (crtc->state->event) { spin_lock_irqsave(&crtc->dev->event_lock, flags); @@ -1952,7 +2084,212 @@ static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); } +static bool tegra_plane_is_cursor(const struct drm_plane_state *state) +{ + const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; + const struct drm_format_info *fmt = state->fb->format; + unsigned int src_w = drm_rect_width(&state->src) >> 16; + unsigned int dst_w = drm_rect_width(&state->dst); + + if (state->plane->type != DRM_PLANE_TYPE_CURSOR) + return false; + + if (soc->supports_cursor) + return true; + + if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) + return false; + + return true; +} + +static unsigned long +tegra_plane_overlap_mask(struct drm_crtc_state *state, + const struct drm_plane_state *plane_state) +{ + const struct drm_plane_state *other_state; + const struct tegra_plane *tegra; + unsigned long overlap_mask = 0; + struct drm_plane *plane; + struct drm_rect rect; + + if (!plane_state->visible || !plane_state->fb) + return 0; + + drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { + rect = plane_state->dst; + + tegra = to_tegra_plane(other_state->plane); + + if (!other_state->visible || !other_state->fb) + continue; + + /* + * Ignore cursor plane overlaps because it's not practical to + * assume that it contributes to the bandwidth in overlapping + * area if window width is small. + */ + if (tegra_plane_is_cursor(other_state)) + continue; + + if (drm_rect_intersect(&rect, &other_state->dst)) + overlap_mask |= BIT(tegra->index); + } + + /* + * Data prefetch FIFO will easily help to overcome temporal memory + * pressure if other plane overlaps with the cursor plane. + */ + if (tegra_plane_is_cursor(plane_state) && overlap_mask) + return 0; + + return overlap_mask; +} + +static struct drm_plane * +tegra_crtc_get_plane_by_index(struct drm_crtc *crtc, unsigned int index) +{ + struct drm_plane *plane; + + drm_atomic_crtc_for_each_plane(plane, crtc) { + if (to_tegra_plane(plane)->index == index) + return plane; + } + + return NULL; +} + +static int tegra_crtc_check_bandwidth_state(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; + u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; + bool all_planes_overlap_simultaneously = true; + const struct tegra_plane_state *tegra_state; + const struct drm_plane_state *plane_state; + const struct tegra_dc_state *old_dc_state; + struct tegra_dc *dc = to_tegra_dc(crtc); + const struct drm_crtc_state *old_state; + struct tegra_dc_state *new_dc_state; + struct drm_crtc_state *new_state; + struct tegra_plane *tegra; + struct drm_plane *plane; + u32 i, k, overlap_bw; + + /* + * The nv-display uses shared planes. The algorithm below assumes + * maximum 3 planes per-CRTC, this assumption isn't applicable to + * the nv-display. Note that T124 support has additional windows, + * but currently they aren't supported by the driver. + */ + if (dc->soc->has_nvdisplay) + return 0; + + new_state = drm_atomic_get_new_crtc_state(state, crtc); + new_dc_state = to_dc_state(new_state); + + /* + * For overlapping planes pixel's data is fetched for each plane at + * the same time, hence bandwidths are accumulated in this case. + * This needs to be taken into account for calculating total bandwidth + * consumed by all planes. + * + * Here we get the overlapping state of each plane, which is a + * bitmask of plane indices telling with what planes there is an + * overlap. Note that bitmask[plane] includes BIT(plane) in order + * to make further code nicer and simpler. + */ + drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { + tegra_state = to_const_tegra_plane_state(plane_state); + tegra = to_tegra_plane(plane); + + plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; + mask = tegra_plane_overlap_mask(new_state, plane_state); + overlap_mask[tegra->index] = mask; + + if (hweight_long(mask) != 3) + all_planes_overlap_simultaneously = false; + } + + old_state = drm_atomic_get_old_crtc_state(state, crtc); + old_dc_state = to_const_dc_state(old_state); + + /* + * Then we calculate maximum bandwidth of each plane state. + * The bandwidth includes the plane BW + BW of the "simultaneously" + * overlapping planes, where "simultaneously" means areas where DC + * fetches from the planes simultaneously during of scan-out process. + * + * For example, if plane A overlaps with planes B and C, but B and C + * don't overlap, then the peak bandwidth will be either in area where + * A-and-B or A-and-C planes overlap. + * + * The plane_peak_bw[] contains peak memory bandwidth values of + * each plane, this information is needed by interconnect provider + * in order to set up latency allowness based on the peak BW, see + * tegra_crtc_update_memory_bandwidth(). + */ + for (i = 0; i < ARRAY_SIZE(plane_peak_bw); i++) { + overlap_bw = 0; + + for_each_set_bit(k, &overlap_mask[i], 3) { + if (k == i) + continue; + + if (all_planes_overlap_simultaneously) + overlap_bw += plane_peak_bw[k]; + else + overlap_bw = max(overlap_bw, plane_peak_bw[k]); + } + + new_dc_state->plane_peak_bw[i] = plane_peak_bw[i] + overlap_bw; + + /* + * If plane's peak bandwidth changed (for example plane isn't + * overlapped anymore) and plane isn't in the atomic state, + * then add plane to the state in order to have the bandwidth + * updated. + */ + if (old_dc_state->plane_peak_bw[i] != + new_dc_state->plane_peak_bw[i]) { + plane = tegra_crtc_get_plane_by_index(crtc, i); + if (!plane) + continue; + + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + } + } + + return 0; +} + +static int tegra_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + int err; + + err = tegra_crtc_check_bandwidth_state(crtc, state); + if (err) + return err; + + return 0; +} + +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + /* + * Display bandwidth is allowed to go down only once hardware state + * is known to be armed, i.e. state was committed and VBLANK event + * received. + */ + tegra_crtc_update_memory_bandwidth(crtc, state, false); +} + static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { + .atomic_check = tegra_crtc_atomic_check, .atomic_begin = tegra_crtc_atomic_begin, .atomic_flush = tegra_crtc_atomic_flush, .atomic_enable = tegra_crtc_atomic_enable, @@ -2243,7 +2580,9 @@ static const struct tegra_dc_soc_info tegra20_dc_soc_info = { .overlay_formats = tegra20_overlay_formats, .modifiers = tegra20_modifiers, .has_win_a_without_filters = true, + .has_win_b_vfilter_mem_client = true, .has_win_c_without_vert_filter = true, + .plane_tiled_memory_bandwidth_x2 = false, }; static const struct tegra_dc_soc_info tegra30_dc_soc_info = { @@ -2262,7 +2601,9 @@ static const struct tegra_dc_soc_info tegra30_dc_soc_info = { .overlay_formats = tegra20_overlay_formats, .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, + .has_win_b_vfilter_mem_client = true, .has_win_c_without_vert_filter = false, + .plane_tiled_memory_bandwidth_x2 = true, }; static const struct tegra_dc_soc_info tegra114_dc_soc_info = { @@ -2281,7 +2622,9 @@ static const struct tegra_dc_soc_info tegra114_dc_soc_info = { .overlay_formats = tegra114_overlay_formats, .modifiers = tegra20_modifiers, .has_win_a_without_filters = false, + .has_win_b_vfilter_mem_client = false, .has_win_c_without_vert_filter = false, + .plane_tiled_memory_bandwidth_x2 = true, }; static const struct tegra_dc_soc_info tegra124_dc_soc_info = { @@ -2300,7 +2643,9 @@ static const struct tegra_dc_soc_info tegra124_dc_soc_info = { .overlay_formats = tegra124_overlay_formats, .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, + .has_win_b_vfilter_mem_client = false, .has_win_c_without_vert_filter = false, + .plane_tiled_memory_bandwidth_x2 = false, }; static const struct tegra_dc_soc_info tegra210_dc_soc_info = { @@ -2319,7 +2664,9 @@ static const struct tegra_dc_soc_info tegra210_dc_soc_info = { .overlay_formats = tegra114_overlay_formats, .modifiers = tegra124_modifiers, .has_win_a_without_filters = false, + .has_win_b_vfilter_mem_client = false, .has_win_c_without_vert_filter = false, + .plane_tiled_memory_bandwidth_x2 = false, }; static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { @@ -2368,6 +2715,7 @@ static const struct tegra_dc_soc_info tegra186_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra186_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), + .plane_tiled_memory_bandwidth_x2 = false, }; static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { @@ -2416,6 +2764,7 @@ static const struct tegra_dc_soc_info tegra194_dc_soc_info = { .has_nvdisplay = true, .wgrps = tegra194_dc_wgrps, .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), + .plane_tiled_memory_bandwidth_x2 = false, }; static const struct of_device_id tegra_dc_of_match[] = { diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h index 051d03dcb9b0..0d7bdf66a1ec 100644 --- a/drivers/gpu/drm/tegra/dc.h +++ b/drivers/gpu/drm/tegra/dc.h @@ -15,6 +15,8 @@ struct tegra_output; +#define TEGRA_DC_LEGACY_PLANES_NUM 6 + struct tegra_dc_state { struct drm_crtc_state base; @@ -23,6 +25,8 @@ struct tegra_dc_state { unsigned int div; u32 planes; + + unsigned long plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM]; }; static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) @@ -33,6 +37,12 @@ static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) return NULL; } +static inline const struct tegra_dc_state * +to_const_dc_state(const struct drm_crtc_state *state) +{ + return to_dc_state((struct drm_crtc_state *)state); +} + struct tegra_dc_stats { unsigned long frames; unsigned long vblank; @@ -65,7 +75,9 @@ struct tegra_dc_soc_info { unsigned int num_overlay_formats; const u64 *modifiers; bool has_win_a_without_filters; + bool has_win_b_vfilter_mem_client; bool has_win_c_without_vert_filter; + unsigned int plane_tiled_memory_bandwidth_x2; }; struct tegra_dc { @@ -151,6 +163,8 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, struct drm_crtc_state *crtc_state, struct clk *clk, unsigned long pclk, unsigned int div); +void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, + struct drm_atomic_state *state); /* from rgb.c */ int tegra_dc_rgb_probe(struct tegra_dc *dc); diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index f0f581cd345e..4c96b2435859 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -20,6 +20,7 @@ #include #include +#include "dc.h" #include "drm.h" #include "gem.h" @@ -59,6 +60,17 @@ static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { .atomic_commit = drm_atomic_helper_commit, }; +static void tegra_atomic_post_commit(struct drm_device *drm, + struct drm_atomic_state *old_state) +{ + struct drm_crtc_state *old_crtc_state; + struct drm_crtc *crtc; + unsigned int i; + + for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) + tegra_crtc_atomic_post_commit(crtc, old_state); +} + static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) { struct drm_device *drm = old_state->dev; @@ -75,6 +87,8 @@ static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) } else { drm_atomic_helper_commit_tail_rpm(old_state); } + + tegra_atomic_post_commit(drm, old_state); } static const struct drm_mode_config_helper_funcs diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c index 22a03f7ffdc1..4fa338dc7eb2 100644 --- a/drivers/gpu/drm/tegra/hub.c +++ b/drivers/gpu/drm/tegra/hub.c @@ -344,6 +344,9 @@ static int tegra_shared_plane_atomic_check(struct drm_plane *plane, struct tegra_dc *dc = to_tegra_dc(state->crtc); int err; + plane_state->peak_memory_bandwidth = 0; + plane_state->avg_memory_bandwidth = 0; + /* no need for further checks if the plane is being disabled */ if (!state->crtc || !state->fb) return 0; diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.c index 539d14935728..1e589c5af143 100644 --- a/drivers/gpu/drm/tegra/plane.c +++ b/drivers/gpu/drm/tegra/plane.c @@ -4,6 +4,7 @@ */ #include +#include #include #include @@ -64,6 +65,8 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *plane) copy->reflect_x = state->reflect_x; copy->reflect_y = state->reflect_y; copy->opaque = state->opaque; + copy->peak_memory_bandwidth = state->peak_memory_bandwidth; + copy->avg_memory_bandwidth = state->avg_memory_bandwidth; for (i = 0; i < 2; i++) copy->blending[i] = state->blending[i]; @@ -212,6 +215,87 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, tegra_dc_unpin(dc, to_tegra_plane_state(state)); } +static int tegra_plane_check_memory_bandwidth(struct drm_plane_state *state) +{ + struct tegra_plane_state *tegra_state = to_tegra_plane_state(state); + unsigned int i, bpp, bpp_plane, dst_w, src_w, src_h, mul; + const struct tegra_dc_soc_info *soc; + const struct drm_format_info *fmt; + struct drm_crtc_state *crtc_state; + u32 avg_bandwidth, peak_bandwidth; + + if (!state->visible) + return 0; + + crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); + if (!crtc_state) + return -EINVAL; + + src_w = drm_rect_width(&state->src) >> 16; + src_h = drm_rect_height(&state->src) >> 16; + dst_w = drm_rect_width(&state->dst); + + fmt = state->fb->format; + soc = to_tegra_dc(state->crtc)->soc; + + /* + * Note that real memory bandwidth vary depending on format and + * memory layout, we are not taking that into account because small + * estimation error isn't important since bandwidth is rounded up + * anyway. + */ + for (i = 0, bpp = 0; i < fmt->num_planes; i++) { + bpp_plane = fmt->cpp[i] * 8; + + /* + * Sub-sampling is relevant for chroma planes only and vertical + * readouts are not cached, hence only horizontal sub-sampling + * matters. + */ + if (i > 0) + bpp_plane /= fmt->hsub; + + bpp += bpp_plane; + } + + /* + * Horizontal downscale takes extra bandwidth which roughly depends + * on the scaled width. + */ + if (src_w > dst_w) + mul = (src_w - dst_w) * bpp / 2048 + 1; + else + mul = 1; + + /* average bandwidth in bytes/s */ + avg_bandwidth = src_w * src_h * bpp / 8 * mul; + avg_bandwidth *= drm_mode_vrefresh(&crtc_state->mode); + + /* mode.clock in kHz, peak bandwidth in kbit/s */ + peak_bandwidth = crtc_state->mode.clock * bpp * mul; + + /* ICC bandwidth in kbyte/s */ + peak_bandwidth = kbps_to_icc(peak_bandwidth); + avg_bandwidth = Bps_to_icc(avg_bandwidth); + + /* + * Tegra30/114 Memory Controller can't interleave DC memory requests + * and DC uses 16-bytes atom for the tiled windows, while DDR3 uses 32 + * bytes atom. Hence there is x2 memory overfetch for tiled framebuffer + * and DDR3 on older SoCs. + */ + if (soc->plane_tiled_memory_bandwidth_x2 && + tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) { + peak_bandwidth *= 2; + avg_bandwidth *= 2; + } + + tegra_state->peak_memory_bandwidth = peak_bandwidth; + tegra_state->avg_memory_bandwidth = avg_bandwidth; + + return 0; +} + int tegra_plane_state_add(struct tegra_plane *plane, struct drm_plane_state *state) { @@ -230,6 +314,10 @@ int tegra_plane_state_add(struct tegra_plane *plane, if (err < 0) return err; + err = tegra_plane_check_memory_bandwidth(state); + if (err < 0) + return err; + tegra = to_dc_state(crtc_state); tegra->planes |= WIN_A_ACT_REQ << plane->index; @@ -595,3 +683,36 @@ int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, return 0; } + +static const char * const tegra_plane_icc_names[] = { + "wina", "winb", "winc", "", "", "", "cursor", +}; + +int tegra_plane_interconnect_init(struct tegra_plane *plane) +{ + const char *icc_name = tegra_plane_icc_names[plane->index]; + struct device *dev = plane->dc->dev; + struct tegra_dc *dc = plane->dc; + int err; + + plane->icc_mem = devm_of_icc_get(dev, icc_name); + err = PTR_ERR_OR_ZERO(plane->icc_mem); + if (err) { + dev_err_probe(dev, err, "failed to get %s interconnect\n", + icc_name); + return err; + } + + /* plane B on T20/30 has a dedicated memory client for a 6-tap vertical filter */ + if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) { + plane->icc_mem_vfilter = devm_of_icc_get(dev, "winb-vfilter"); + err = PTR_ERR_OR_ZERO(plane->icc_mem_vfilter); + if (err) { + dev_err_probe(dev, err, "failed to get %s interconnect\n", + "winb-vfilter"); + return err; + } + } + + return 0; +} diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.h index c691dd79b27b..f2731aae7d01 100644 --- a/drivers/gpu/drm/tegra/plane.h +++ b/drivers/gpu/drm/tegra/plane.h @@ -8,6 +8,7 @@ #include +struct icc_path; struct tegra_bo; struct tegra_dc; @@ -16,6 +17,9 @@ struct tegra_plane { struct tegra_dc *dc; unsigned int offset; unsigned int index; + + struct icc_path *icc_mem; + struct icc_path *icc_mem_vfilter; }; struct tegra_cursor { @@ -52,6 +56,10 @@ struct tegra_plane_state { /* used for legacy blending support only */ struct tegra_plane_legacy_blending_state blending[2]; bool opaque; + + /* bandwidths are in ICC units, i.e. kbytes/sec */ + u32 peak_memory_bandwidth; + u32 avg_memory_bandwidth; }; static inline struct tegra_plane_state * @@ -63,6 +71,12 @@ to_tegra_plane_state(struct drm_plane_state *state) return NULL; } +static inline const struct tegra_plane_state * +to_const_tegra_plane_state(const struct drm_plane_state *state) +{ + return to_tegra_plane_state((struct drm_plane_state *)state); +} + extern const struct drm_plane_funcs tegra_plane_funcs; int tegra_plane_prepare_fb(struct drm_plane *plane, @@ -77,5 +91,6 @@ int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); bool tegra_plane_format_is_yuv(unsigned int format, bool *planar); int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, struct tegra_plane_state *state); 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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m2sm454587lfo.25.2020.11.04.08.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 08:50:26 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , Krzysztof Kozlowski Cc: linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v7 47/47] PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver Date: Wed, 4 Nov 2020 19:49:23 +0300 Message-Id: <20201104164923.21238-48-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104164923.21238-1-digetx@gmail.com> References: <20201104164923.21238-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Remove tegra20-devfreq in order to replace it with a EMC_STAT based devfreq driver. Previously we were going to use MC_STAT based tegra20-devfreq driver because EMC_STAT wasn't working properly, but now that problem is resolved. This resolves complications imposed by the removed driver since it was depending on both EMC and MC drivers simultaneously. Signed-off-by: Dmitry Osipenko Acked-by: Chanwoo Choi --- drivers/devfreq/Kconfig | 10 -- drivers/devfreq/Makefile | 1 - drivers/devfreq/tegra20-devfreq.c | 210 ------------------------------ 3 files changed, 221 deletions(-) delete mode 100644 drivers/devfreq/tegra20-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 0ee36ae2fa79..00704efe6398 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -121,16 +121,6 @@ config ARM_TEGRA_DEVFREQ It reads ACTMON counters of memory controllers and adjusts the operating frequencies and voltages with OPP support. -config ARM_TEGRA20_DEVFREQ - tristate "NVIDIA Tegra20 DEVFREQ Driver" - depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST - depends on COMMON_CLK - select DEVFREQ_GOV_SIMPLE_ONDEMAND - help - This adds the DEVFREQ driver for the Tegra20 family of SoCs. - It reads Memory Controller counters and adjusts the operating - frequencies and voltages with OPP support. - config ARM_RK3399_DMC_DEVFREQ tristate "ARM RK3399 DMC DEVFREQ Driver" depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 3ca1ad0ecb97..a16333ea7034 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o -obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/tegra20-devfreq.c b/drivers/devfreq/tegra20-devfreq.c deleted file mode 100644 index fd801534771d..000000000000 --- a/drivers/devfreq/tegra20-devfreq.c +++ /dev/null @@ -1,210 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * NVIDIA Tegra20 devfreq driver - * - * Copyright (C) 2019 GRATE-DRIVER project - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "governor.h" - -#define MC_STAT_CONTROL 0x90 -#define MC_STAT_EMC_CLOCK_LIMIT 0xa0 -#define MC_STAT_EMC_CLOCKS 0xa4 -#define MC_STAT_EMC_CONTROL 0xa8 -#define MC_STAT_EMC_COUNT 0xb8 - -#define EMC_GATHER_CLEAR (1 << 8) -#define EMC_GATHER_ENABLE (3 << 8) - -struct tegra_devfreq { - struct devfreq *devfreq; - struct clk *emc_clock; - void __iomem *regs; -}; - -static int tegra_devfreq_target(struct device *dev, unsigned long *freq, - u32 flags) -{ - struct tegra_devfreq *tegra = dev_get_drvdata(dev); - struct devfreq *devfreq = tegra->devfreq; - struct dev_pm_opp *opp; - unsigned long rate; - int err; - - opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) - return PTR_ERR(opp); - - rate = dev_pm_opp_get_freq(opp); - dev_pm_opp_put(opp); - - err = clk_set_min_rate(tegra->emc_clock, rate); - if (err) - return err; - - err = clk_set_rate(tegra->emc_clock, 0); - if (err) - goto restore_min_rate; - - return 0; - -restore_min_rate: - clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); - - return err; -} - -static int tegra_devfreq_get_dev_status(struct device *dev, - struct devfreq_dev_status *stat) -{ - struct tegra_devfreq *tegra = dev_get_drvdata(dev); - - /* - * EMC_COUNT returns number of memory events, that number is lower - * than the number of clocks. Conversion ratio of 1/8 results in a - * bit higher bandwidth than actually needed, it is good enough for - * the time being because drivers don't support requesting minimum - * needed memory bandwidth yet. - * - * TODO: adjust the ratio value once relevant drivers will support - * memory bandwidth management. - */ - stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); - stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; - stat->current_frequency = clk_get_rate(tegra->emc_clock); - - writel_relaxed(EMC_GATHER_CLEAR, tegra->regs + MC_STAT_CONTROL); - writel_relaxed(EMC_GATHER_ENABLE, tegra->regs + MC_STAT_CONTROL); - - return 0; -} - -static struct devfreq_dev_profile tegra_devfreq_profile = { - .polling_ms = 500, - .target = tegra_devfreq_target, - .get_dev_status = tegra_devfreq_get_dev_status, -}; - -static struct tegra_mc *tegra_get_memory_controller(void) -{ - struct platform_device *pdev; - struct device_node *np; - struct tegra_mc *mc; - - np = of_find_compatible_node(NULL, NULL, "nvidia,tegra20-mc-gart"); - if (!np) - return ERR_PTR(-ENOENT); - - pdev = of_find_device_by_node(np); - of_node_put(np); - if (!pdev) - return ERR_PTR(-ENODEV); - - mc = platform_get_drvdata(pdev); - if (!mc) - return ERR_PTR(-EPROBE_DEFER); - - return mc; -} - -static int tegra_devfreq_probe(struct platform_device *pdev) -{ - struct tegra_devfreq *tegra; - struct tegra_mc *mc; - unsigned long max_rate; - unsigned long rate; - int err; - - mc = tegra_get_memory_controller(); - if (IS_ERR(mc)) { - err = PTR_ERR(mc); - dev_err(&pdev->dev, "failed to get memory controller: %d\n", - err); - return err; - } - - tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); - if (!tegra) - return -ENOMEM; - - /* EMC is a system-critical clock that is always enabled */ - tegra->emc_clock = devm_clk_get(&pdev->dev, "emc"); - if (IS_ERR(tegra->emc_clock)) - return dev_err_probe(&pdev->dev, PTR_ERR(tegra->emc_clock), - "failed to get emc clock\n"); - - tegra->regs = mc->regs; - - max_rate = clk_round_rate(tegra->emc_clock, ULONG_MAX); - - for (rate = 0; rate <= max_rate; rate++) { - rate = clk_round_rate(tegra->emc_clock, rate); - - err = dev_pm_opp_add(&pdev->dev, rate, 0); - if (err) { - dev_err(&pdev->dev, "failed to add opp: %d\n", err); - goto remove_opps; - } - } - - /* - * Reset statistic gathers state, select global bandwidth for the - * statistics collection mode and set clocks counter saturation - * limit to maximum. - */ - writel_relaxed(0x00000000, tegra->regs + MC_STAT_CONTROL); - writel_relaxed(0x00000000, tegra->regs + MC_STAT_EMC_CONTROL); - writel_relaxed(0xffffffff, tegra->regs + MC_STAT_EMC_CLOCK_LIMIT); - - platform_set_drvdata(pdev, tegra); - - tegra->devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile, - DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); - if (IS_ERR(tegra->devfreq)) { - err = PTR_ERR(tegra->devfreq); - goto remove_opps; - } - - return 0; - -remove_opps: - dev_pm_opp_remove_all_dynamic(&pdev->dev); - - return err; -} - -static int tegra_devfreq_remove(struct platform_device *pdev) -{ - struct tegra_devfreq *tegra = platform_get_drvdata(pdev); - - devfreq_remove_device(tegra->devfreq); - dev_pm_opp_remove_all_dynamic(&pdev->dev); - - return 0; -} - -static struct platform_driver tegra_devfreq_driver = { - .probe = tegra_devfreq_probe, - .remove = tegra_devfreq_remove, - .driver = { - .name = "tegra20-devfreq", - }, -}; -module_platform_driver(tegra_devfreq_driver); - -MODULE_ALIAS("platform:tegra20-devfreq"); -MODULE_AUTHOR("Dmitry Osipenko "); -MODULE_DESCRIPTION("NVIDIA Tegra20 devfreq driver"); -MODULE_LICENSE("GPL v2");