From patchwork Thu Jan 4 12:50:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123409 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389327qgn; Thu, 4 Jan 2018 04:51:09 -0800 (PST) X-Google-Smtp-Source: ACJfBovDN7ZM5rvM06SR9v5SdYWIZCug7P1+BHFsyBO42Xhvkk47d49rhzM7C9vA5W875qeOKcnr X-Received: by 10.99.140.83 with SMTP id q19mr3917512pgn.230.1515070269246; Thu, 04 Jan 2018 04:51:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070269; cv=none; d=google.com; s=arc-20160816; b=vNT7mpv0J/Om2C8Mrei9uoBmaTsCysKzw/B74RoyttREPToiTr+MpopYEVyVAeoCP2 XUt4WFl983uy/+HtTNVZq7DUi+EhqjlcbmzHFeNgH9q0UWM5igd25KEt3IGWFATjfF/S lzSmAjDGSeqvo/VopP0l+9Jw63nNKKdhtCywnkQUuNhlP/A2sNNp/VoGLX/eKsHWZ08k yr76kwtxxL9vsxhHcpGBa/MarF2V3C9YJHlGBHYK7BKrbW3UuxWlOsfp2zj6XjxvVcSK tODUjJtIoXj5BaKyNX6y8q6nJbOzLtCunnrpjezTdCxBmf0GottkdtyQqsR7k2ZfxFAE W3Ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=k8iW1gmaR89FbbhKKjmo7bisZ5FPPfJlYckZ3ehXc3o=; b=ui7lLInFm5lr6IuK8rNjRct+4PWCA03Onu1D9xLISuU8K9LapWTbiNkjuqHeP5HUa1 os6JJA8cBfkgrZmAmCFklD1AhlGPtA+JEwzpyfAfOuiDjY02FppZrW9uaSi4Ub/DD/SV reFIEMJbGi3J0aPF5j5jaqbcRoXjiwj27srGGFKFfdN/iVjLD4OSgi/0+sdNj65tVbc4 XfKtJn36QzbsZo/9w/+hYMFWaa4UWHqqJCxQBQvAI2eyWM5beYE8eM9kC5CO1Cb8oGB7 qbd0G/pZtoF7JUwQgX/4MYUyvbXUwyEATluqQyt+Hh4kI97Zbyz0/HQIEBBH0ylftzML srqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UViljjD8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c80si2283237pfb.307.2018.01.04.04.51.08; Thu, 04 Jan 2018 04:51:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UViljjD8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752582AbeADMvF (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:05 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:37587 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752460AbeADMvE (ORCPT ); Thu, 4 Jan 2018 07:51:04 -0500 Received: by mail-wm0-f68.google.com with SMTP id f140so3227878wmd.2 for ; Thu, 04 Jan 2018 04:51:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k8iW1gmaR89FbbhKKjmo7bisZ5FPPfJlYckZ3ehXc3o=; b=UViljjD8XQTyRMHYeWGJUQVFsqcZP2/Ikdj550M+XfwgJ/n4Gyum97USK0KOafsdXf jpDshUSLuCcvdayiGV3CmLqCQH/KoeTpx+M+LkKia4hZulde6Qdr2mf8Xf5M5vxDOKq0 yqu02NVsrtkps1g9geFEM4Bcgh0LKFM+alNH0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k8iW1gmaR89FbbhKKjmo7bisZ5FPPfJlYckZ3ehXc3o=; b=ooNW6uARPCot+TOD890GI7TkGJa2pRvbofnzm3KfbWf+jxAt98fQhOT8ezRwA3H9O0 7WcnP/d0nuZoWNI3ttNKjsToX3fc+G0fEvXPqBc1Jt1dELCC8ivabo0oQzoW/qzxNFBN r1WFB71qD5jF9nWCC2tP0wgpWqetKOpa1cSreirlEy+PR11CzrAGG6Y4M5CAtsFVgNTq HCI6sXbq3T3lVxIjabTXh6+Q7oPOHNz0dx5uA+yH5V2/VFMZBFSmBJwsN+3Vm+tdSLQM SotYe5mFcolzJcw0v3UiE08pBiA9787G4jfFByZg/fLFWby6i0KE+LP6+KsS0go8SzM1 Hfsw== X-Gm-Message-State: AKGB3mL5Cv+mTaLfQrWbKMG6w/fxY1HBqPFrc7Wd40UZP3j013ShNSSb Qj09yGWtaVk5CuLe87VBgyiPRA== X-Received: by 10.28.61.87 with SMTP id k84mr3833581wma.48.1515070262991; Thu, 04 Jan 2018 04:51:02 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:02 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org Subject: [PATCH 01/12] clocksource/drivers/timer-of: Store the device node pointer Date: Thu, 4 Jan 2018 13:50:17 +0100 Message-Id: <1515070228-10481-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Under certain circumstances, some specific operations must be done with the device node pointer, that forces the timer code to propagate the pointer to the functions which need it. In order to consolidate the function signatures in the different drivers by using the timer-of structure, let's store it in the timer-of structure as a handy pointer when it is needed. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-of.c | 3 +++ drivers/clocksource/timer-of.h | 1 + 2 files changed, 4 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index 2af8b8a..2ae348b 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -201,6 +201,9 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) if (!to->clkevt.name) to->clkevt.name = np->name; + + to->np = np; + return ret; out_fail: diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index f521477..2efa8ec 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -32,6 +32,7 @@ struct of_timer_clk { struct timer_of { unsigned int flags; + struct device_node *np; struct clock_event_device clkevt; struct of_timer_base of_base; struct of_timer_irq of_irq; From patchwork Thu Jan 4 12:50:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123410 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389482qgn; Thu, 4 Jan 2018 04:51:17 -0800 (PST) X-Google-Smtp-Source: ACJfBotraOGw0Pi9bs6le7QKjo9vUuqYkzrCgBl8h1c/6ce+Xw3CW3NlD/zAX5TiV2ejCaEey4Kb X-Received: by 10.84.131.65 with SMTP id 59mr4505198pld.156.1515070277677; Thu, 04 Jan 2018 04:51:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070277; cv=none; d=google.com; s=arc-20160816; b=q22wed3sFnC41bVSBhKuLoNYYMZU9lrk2ewfZ8Rfn2UUp6u7fhScG7w+1nhCxfMTWY UPS5m9JSSePDuTeGccMH0Ke3wZ0IBMHJj7Ut6tez+i9Lo3Hlzsbbj9zEd5DWn41Q71EJ BZeO4eTdz0QCUgBlofZbEINNNWJW/NSHKUKgtxaiIrpDy5XjgTl5faTmLeYmv2cqu84f CcW/e4ec8JjSJa5xGbBq0yLg29tC7Gjev7s4FiBIlA7RIncWY/jR/UUat+QbZeUAkzKY cs+3AS53EcdGCoKc89PuYK9ia2BD25H5muPQNMY5pbFl8Th1aexJv8Lc9Z8nW8ZawKg6 U1tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=DTJ6y5+9Ch8yOfmLDv0vXLpCj+GzPWWs1Aacq3oRjMM=; b=Tz2JeDojPY+8pbvUzSXawWAkci1IveHCw0zlmjpGRDtaHxQiIUQlHqf2YE5UYoOPUp /PnAxcYc9k5dPKbOgEcPvIFDW7ekF/7OavfbsXvKjUpbe1YlPhSuRZyQ//ly7hUt/7bu I1LmYUIO0V7628KJH2EzrrcorF325Zxzi+X8UAAL3QtNwznJ/nbWY77TTUtOD6sC94Q/ UUqBQwftzpCplTnoJOkPr75EVQCNxhqTGPAHJG1QDM7TWJZr6SQ/ygkDMtqnyqMHdA7O N54t8gWShzEellW9641VD0ahQ+F/ElLR2wdFPrUtcunyIp5UmPc41QvZANX+EEnJOn4B 0DEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AyPydhN8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c80si2283237pfb.307.2018.01.04.04.51.17; Thu, 04 Jan 2018 04:51:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AyPydhN8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752657AbeADMvN (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:13 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:43819 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752587AbeADMvL (ORCPT ); Thu, 4 Jan 2018 07:51:11 -0500 Received: by mail-wm0-f67.google.com with SMTP id n138so3289572wmg.2 for ; Thu, 04 Jan 2018 04:51:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DTJ6y5+9Ch8yOfmLDv0vXLpCj+GzPWWs1Aacq3oRjMM=; b=AyPydhN8wtE/YPA/EdllQx0lHREgYGHjnDALKv8kgcw7Wn5ZQ5L+J/9zNPS86vTNdy omdmN8Sg2OV/cJtwrRTL6Di/zudP7e4yxN6OGC+1Ma+Rw8JH/rnR9/b9M0xRpEnuj0nz j3BF+gwEQmaxGJ4YmiaxmiVz8im0z1UTNWtiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DTJ6y5+9Ch8yOfmLDv0vXLpCj+GzPWWs1Aacq3oRjMM=; b=V/ryKUlbiO69fZlR+hUJ2HSgVnSNVW+GOvhUA3+3pu0jKrnoYQ5+vauAQLGOLhHVHM FoQnmGcilLLsG11T2Vuf+4lntEBThk3FcmXCrgscjCafuHSiG+Pz6D5ATzqzQnu69iuH 3Hli0GTyawZpM2GTTs3qbgNPN5IYWL+Byu2QAaOj1YOe7fMaIM8UKvQftZ5G7LIpoGOj sxnOqMVWAgOURQUapu5HLEnMPemw/hLT15AqtL/TqssrHZeCtmhhzkr+CRYiQOe5cxf3 Il2mdSB51H7AVjUihi0Y9WP263gqqbMEBXdWJXaa0lyaSYQNbL5+7GM73bY2i/1wh/vM tYmw== X-Gm-Message-State: AKGB3mI7INSyPDtoFXT+AQnl2H3mCxc9t8Be71OKlwVK2fnR3hbRhWVw ONwYcQzwTXmH7jflfUVdBEmjuBBi/UA= X-Received: by 10.28.71.76 with SMTP id u73mr3743948wma.77.1515070269970; Thu, 04 Jan 2018 04:51:09 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:09 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org Subject: [PATCH 02/12] clocksource/drivers/timer-of: Don't request the resource by name Date: Thu, 4 Jan 2018 13:50:18 +0100 Message-Id: <1515070228-10481-3-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the driver does not specify a name for the resource, don't use of_io_request_and_map but of_iomap. That prevents resource name allocation conflict on some platforms which have the same name than the node. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-of.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index 2ae348b..5aa7dcd 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -162,11 +162,11 @@ static __init void timer_of_base_exit(struct of_timer_base *of_base) static __init int timer_of_base_init(struct device_node *np, struct of_timer_base *of_base) { - const char *name = of_base->name ? of_base->name : np->full_name; - - of_base->base = of_io_request_and_map(np, of_base->index, name); + of_base->base = of_base->name ? + of_io_request_and_map(np, of_base->index, of_base->name) : + of_iomap(np, of_base->index); if (IS_ERR(of_base->base)) { - pr_err("Failed to iomap (%s)\n", name); + pr_err("Failed to iomap (%s)\n", of_base->name); return PTR_ERR(of_base->base); } From patchwork Thu Jan 4 12:50:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123411 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389575qgn; Thu, 4 Jan 2018 04:51:24 -0800 (PST) X-Google-Smtp-Source: ACJfBotep8kt+DZOM8UD4V0gWhe2s07NJTafS1xhlZPhrwqZn5Fv6vqL+xn2TBtz+Isk/UZqeIf6 X-Received: by 10.99.179.6 with SMTP id i6mr3898975pgf.77.1515070283925; Thu, 04 Jan 2018 04:51:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070283; cv=none; d=google.com; s=arc-20160816; b=f7E+Urw9jmKjMRWnvToUfAMmyT8nwRbdOVLe705RklS2NpJ/ErSLa39z9Uc7qMmeAZ iQfll95CfSHPERjsuGoJ7EYJVRyQKvGh/yXi0OJ4Ml8yaxMrgopGHu0nFZn+hKucCcDo 3uH1kZ7K0a8Luvjymd1VeZXc5+SrKKTOA1KMDRWJZfgNHM90PXi7VxY1BC+fi9X4OI/G MmS+ORYPZwbeq9wLkDqYP7MpQX01xiNBguoOWa9iBJ8VUgyIfHnGgfPd7JsOegVEqF5v B7j0pvzUgoR6LfdrJTEeqXSGizqS6YRK+C1jRUkULYEpYiMl3qnMRb6yEgBJwgp/k7AW lxUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lmEr5E+Ci/rbmrsMGX5Vi4ZmyVsHhrCVFOoM4NLfSdc=; b=BcKOtoocNXxA+vZ30S9pfchIS1qc3x262IET+JMmnb1P+DtfsmS/UqNvy7ZWvJq2ni KSfqUEOqniL/bo7f6YJnngkaVVMNSRsJur9Eu9+8NQgnNBKPnf6NqwEDhll/Uk+M/E5o DPy1SMGAsn43Wm6h6nzACUqw4C3daybq44ww5/CRsLnj69hewYkNBOMR70CzirLI7ExO Mm7dppxivcx8VnL2DLYKLs+U6zfcbOHxZEYUUhjHPgTM3y0rtOD1Zql3fWiAiCMRQDQa fxTsTl7w0ioor2eA5vniS0zoJVgc5wDogMSn14dHysc8LEJnpJg5N15aYhjol2Ylsh6m ufDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DCWxcKSt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c80si2283237pfb.307.2018.01.04.04.51.23; Thu, 04 Jan 2018 04:51:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DCWxcKSt; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752740AbeADMvV (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:21 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:33998 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752671AbeADMvS (ORCPT ); Thu, 4 Jan 2018 07:51:18 -0500 Received: by mail-wr0-f193.google.com with SMTP id 36so1396148wrh.1 for ; Thu, 04 Jan 2018 04:51:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lmEr5E+Ci/rbmrsMGX5Vi4ZmyVsHhrCVFOoM4NLfSdc=; b=DCWxcKStHWQKAUYLVoFDRWOnW2XLOxKSNq60H4+kuePZvvXaome9GaUkhF0RoZTwh2 Wv3whQEc50RuVcB8yHkUILXexlGwHNeTgUGbyZNE6d+FHkm2DpuIn+1jIqz8jUTCpklE UfSTNI+U3+mihoK9GMpsGo3wW+21TzybiCY3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lmEr5E+Ci/rbmrsMGX5Vi4ZmyVsHhrCVFOoM4NLfSdc=; b=R4u+OdHW9uFaJRe6rozHD0Smh7Ef6kL9ueq1JTJuRkpGV2XKMOxEvZiPIVJIMkE+La VCYKCKnVdQejyNy8lixQjTanhJC8i6EmDZv95L3+7L7lH5CFiC4x6DLeh/EgKJh/6ZZd /j3HF2bZeaOSWojqqJVM95eNgYYSWgv42ZtwECFSTMSYJN/koY9a3lEYBq+9UvCfzNIE CbBSEHGNrBDo9CQ3w5UkLvvdMH+lh361+GpM4iJZ9p8W2hptiMsGLbhDC74Qv7N76KE6 Yphha8FoGQ0/cKrLdPXWIEOh4JUUasmickEEh7n+vt7JJht8dsi1CxY5DFOYpWUeJG/T fHjA== X-Gm-Message-State: AKGB3mJMO6nO1iZd7lkQWMNV0IYZcci1eER3QeADt2psaivUtCiO86lg ZOxSd/mVSar3Ny0r1T3jZ8ijkg== X-Received: by 10.223.134.134 with SMTP id 6mr4410125wrx.17.1515070277374; Thu, 04 Jan 2018 04:51:17 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:16 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, stable@vger.kernel.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 03/12] clocksource/drivers/stm32: Fix kernel panic with multiple timers Date: Thu, 4 Jan 2018 13:50:19 +0100 Message-Id: <1515070228-10481-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current code hides a couple of bugs. - The global variable 'clock_event_ddata' is overwritten each time the init function is invoked. This is fixed with a kmemdup instead of assigning the global variable. That prevents a memory corruption when several timers are defined in the DT. - The clockevent's event_handler is NULL if the time framework does not select the clockevent when registering it, this is fine but the init code generates in any case an interrupt leading to dereference this NULL pointer. The stm32 timer works with shadow registers, a mechanism to cache the registers. When a change is done in one buffered register, we need to artificially generate an event to force the timer to copy the content of the register to the shadowed register. The auto-reload register (ARR) is one of the shadowed register as well as the prescaler register (PSC), so in order to force the copy, we issue an event which in turn leads to an interrupt and the NULL dereference. This is fixed by inverting two lines where we clear the status register before enabling the update event interrupt. As this kernel crash is resulting from the combination of these two bugs, the fixes are grouped into a single patch. Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..4bfeb99 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -106,6 +106,10 @@ static int __init stm32_clockevent_init(struct device_node *np) unsigned long rate, max_delta; int irq, ret, bits, prescaler = 1; + data = kmemdup(&clock_event_ddata, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + clk = of_clk_get(np, 0); if (IS_ERR(clk)) { ret = PTR_ERR(clk); @@ -156,8 +160,8 @@ static int __init stm32_clockevent_init(struct device_node *np) writel_relaxed(prescaler - 1, data->base + TIM_PSC); writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); @@ -184,6 +188,7 @@ static int __init stm32_clockevent_init(struct device_node *np) err_clk_enable: clk_put(clk); err_clk_get: + kfree(data); return ret; } From patchwork Thu Jan 4 12:50:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123412 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389654qgn; Thu, 4 Jan 2018 04:51:28 -0800 (PST) X-Google-Smtp-Source: ACJfBouHoZ7J+X+sDRsG6lNDfNHPUmXo3ffGsZrVXVILwKCDXCXGXzz/ZYmkxrhjEYr4DVlrrjDX X-Received: by 10.98.29.83 with SMTP id d80mr4610492pfd.156.1515070288684; Thu, 04 Jan 2018 04:51:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070288; cv=none; d=google.com; s=arc-20160816; b=iYZlFweYn/NKTf3GUhj5iZwJbf9AO7QZsig3wUmfne1V7vAbTSD+WGuAB3Lq4NDTbD 4u0zLmdTvGvHirgBDFN3RI3ptjcoQvgGQlNj3udagMjjQvAg8oNdXZMPqCb0tMPZdrNU YB7OA/52Zaw5BDse2eajD+V3xnR5MwIde4Deynql98i+IXLTtXYfEet17Hz1ltc/zv06 hRXJEUilhSxmUCaEYB2dFLhP0Pkh4n98TrhOBBgY7FkImg9u/lpqT77N2vLvWISA+EtR MLc6befVZ7SJo62vRxuDndGOLjH4fAoCc6lx3eRBEnQt3lRdbxv+uLYCXd+8wNkU9G3X dfVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=dxVMmNjgwig7WccXNQoWYETDvmdYMoC/B8tRQzze1FU=; b=iL1t+H+DVoKYtSVbDGjKw0J0ini+KsFvJ9d5rWnOoWu+EVa2J3TWPZUxBxwyWAWokX qUcvQX6TKKc1npBuo7cgS76Vao07DrPEJ6pIo8lq8D9TjbRdIW6P2su0vOicUg/PHJHJ epvWNcF8G0uDzdfNh7a+PFulYHOeI2nFd40HX1UyAdH9bLvMy21tFRyPgJjYLABwBMp5 MKXtNV5uhZsHnHN+khZyyzoJCaHQ2iJqtuQFKz0rqih6KMZfhFfDpg7UPOJT7YryfIKQ Ta0FYX/2jBIcuUlTEnFIDpF1ZS+7oN4SsYfRa4lls/3F5v0Kvcmd0zw6Wz+FcMKq6y09 I9ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eadh9tgJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.28; Thu, 04 Jan 2018 04:51:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eadh9tgJ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752807AbeADMvY (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:24 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34003 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752713AbeADMvV (ORCPT ); Thu, 4 Jan 2018 07:51:21 -0500 Received: by mail-wr0-f195.google.com with SMTP id 36so1396266wrh.1 for ; Thu, 04 Jan 2018 04:51:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dxVMmNjgwig7WccXNQoWYETDvmdYMoC/B8tRQzze1FU=; b=eadh9tgJUVvoK9clwPguND10Wdw/6+ZGJYcubSITKXtG/pWi4fup6BMqh0p7nqYe1y vBd1sdpQI3uNAzCMsx2XNL65NJQSM1tMEy3FK4gyEow0mSQxeA1LDRBsJs4E4sRt0k+q pZ+G5BoUALN8B2pWF199a3x+OekILw+x13Vew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dxVMmNjgwig7WccXNQoWYETDvmdYMoC/B8tRQzze1FU=; b=lezBoKYH2D2afS5CypT2yvSYxVmgTDZbG2OgBrbitCt31pyYxk2lrUsiVS5xnJXLVO n4lWoDVEJpV1vDprVTjRgCJUrLGpOtNUgCYQqDYOEFilp4jFObvGvKhJrhlkB6fnGcaB OpAqR1yjfn+vqddK691tvsEIRaKzHBhcfp2Xsio1ehu2fDXAIYuF/tpwfkq6juO8HoBi Jq+gbIDBA/VW/iGUV+7jaTKA20OTBn4+MwYy68D2hI6itQKoGd+Wh7a/ctPIMEhP6/Jx WPNE9XvoS22BE30kPdD2F2FcjKrbGsVEBLaR5RffOxfWo5LPgm/aqEQO/u9rlBGgXU9+ RPDQ== X-Gm-Message-State: AKGB3mIoIoU9LABjV167LPKr9bh+6mzo9iMTVYteK0O638dKXiPyPdMu v4AHmN54n4EkED3IKGow3SNfL4kWK0I= X-Received: by 10.223.177.143 with SMTP id q15mr4372293wra.42.1515070280051; Thu, 04 Jan 2018 04:51:20 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:19 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 04/12] clocksource/drivers/stm32: Convert the driver to timer-of Date: Thu, 4 Jan 2018 13:50:20 +0100 Message-Id: <1515070228-10481-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard Convert the driver to use the timer_of helpers. This allows to remove custom proprietary structure, factors out and simplifies the code. [Daniel Lezcano] : Respin against the critical fix patch and massaged the changelog. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 187 +++++++++++++++----------------------- 2 files changed, 74 insertions(+), 114 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 9a6b087..786db7a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -269,6 +269,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 4bfeb99..3e4ab07 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,9 @@ #include #include #include +#include + +#include "timer-of.h" #define TIM_CR1 0x00 #define TIM_DIER 0x0c @@ -34,162 +37,118 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(clkevt); + + writel_relaxed(0, timer_of_base(to) + TIM_CR1); - writel_relaxed(0, base + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(clkevt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *clkevt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + clkevt->event_handler(clkevt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static void __init stm32_clockevent_init(struct timer_of *to) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; - struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - data = kmemdup(&clock_event_ddata, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); - if (!IS_ERR(rstc)) { - reset_control_assert(rstc); - reset_control_deassert(rstc); - } - - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } + unsigned long max_delta; + int prescaler; - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } + to->clkevt.name = "stm32_clockevent"; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; - bits = 32; + to->clkevt.rating = 250; } else { prescaler = 1024; - bits = 16; + to->clkevt.rating = 100; } - writel_relaxed(0, data->base + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(0, data->base + TIM_SR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + /* Adjust rate and period given the prescaler value */ + to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x1, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + to->np, max_delta == UINT_MAX ? 32 : 16); +} - return ret; +static int __init stm32_timer_init(struct device_node *node) +{ + struct reset_control *rstc; + struct timer_of *to; + int ret; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: - kfree(data); + rstc = of_reset_control_get(node, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); + } + + stm32_clockevent_init(to); + return 0; +err: + kfree(to); return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Thu Jan 4 12:50:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123420 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11391102qgn; Thu, 4 Jan 2018 04:53:02 -0800 (PST) X-Google-Smtp-Source: ACJfBosfbCdgzWyDIPYG7ZndGFebrpV9AAYpS3EYi3EbSs/UepvLK2gb2obrQ8j0bSiyRugJuPns X-Received: by 10.98.133.155 with SMTP id m27mr4671902pfk.69.1515070382578; Thu, 04 Jan 2018 04:53:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070382; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id b3si1999070pgr.829.2018.01.04.04.53.02; Thu, 04 Jan 2018 04:53:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZT5KrbDK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753161AbeADMxA (ORCPT + 27 others); Thu, 4 Jan 2018 07:53:00 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:37625 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752671AbeADMvX (ORCPT ); Thu, 4 Jan 2018 07:51:23 -0500 Received: by mail-wm0-f66.google.com with SMTP id f140so3229343wmd.2 for ; Thu, 04 Jan 2018 04:51:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vbjV4u+k0hFu1msvk9qaIYmYriutJ/nDft76EE9W54g=; b=ZT5KrbDKl2l/3VO/wKwaBrTxCHqhtzWd7/jIS4zPXNyZW5C5coFGzDR4sb82Z7FuAR aL1ETSgPykEt8ea07eXe/TC9FVx1C0acY6x1v8SAiUzYaXcUP2XkHRnR0a+u8S04fX+N RXekLHzN30+8L8YSArbm6wrjCTzNHrAymOvXo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vbjV4u+k0hFu1msvk9qaIYmYriutJ/nDft76EE9W54g=; b=aZx313896Fxi6gACywQdAAkJ4G51QlDaOzYI7Qf8FiPLQJCAC4sKjdgovuV5lPZEmL I9yljIWo04dAAtzusHa0suM6wRrtpt/Ri5RZ1IcS/eooxuk+NszYg1cYrfVfKX0gl3yT h3vkpKG9ydj2Qi2gEqBH5lqo12MM25JH/QU1hUR2DSOmixypcfc8QwoS0f9wDnvKn9A7 MQHBzOU0sV7IvXYRMMIZz1DE5mat418qaBkOeBr+vf51wcIwvH7/TIiHKp50qHLXidIL 1xQ7Bk5E2lhJezOtWsNyyAQstWkelQjNgfDo7GbmnbOQ0hRuRkCc2h8SauD5eSxMMm7f 3p1g== X-Gm-Message-State: AKGB3mI6lzGXnyC6qA4uErkhWgIFI0ccUcdpTGk5bgwXYdivov+0wl/b 3NPDyfHF0pQi1tWWMhRDS9Dgxw== X-Received: by 10.28.209.141 with SMTP id i135mr3690862wmg.153.1515070282120; Thu, 04 Jan 2018 04:51:22 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:21 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 05/12] clocksource/drivers/stm32: Use the node name as timer name Date: Thu, 4 Jan 2018 13:50:21 +0100 Message-Id: <1515070228-10481-6-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As there are different timers on the stm32, use the node name for the timer name in order to give the indication of which timer the kernel is using. The /proc/timer_list gives all the information with the right name, otherwise we end up digging in the kernel log and /proc/interrupt to do the connection between the used timer. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 3e4ab07..14b7a2b 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -85,7 +85,7 @@ static void __init stm32_clockevent_init(struct timer_of *to) unsigned long max_delta; int prescaler; - to->clkevt.name = "stm32_clockevent"; + to->clkevt.name = to->np->full_name; to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; From patchwork Thu Jan 4 12:50:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123413 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389761qgn; Thu, 4 Jan 2018 04:51:36 -0800 (PST) X-Google-Smtp-Source: ACJfBovNFlJmixHxt6O06vEPlCD0/TLu/y29psHaJOHt8TgBG7gek/LveuAWotjqLxUQutiF1mRi X-Received: by 10.98.156.204 with SMTP id u73mr4662960pfk.8.1515070296536; Thu, 04 Jan 2018 04:51:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070296; cv=none; d=google.com; s=arc-20160816; b=dA1++4fUXDCrDUNHLO88Dcyc4I2hggVpK7aQ/C2iMQj3cJYkctHk8UDDa/Rfpwp88w j7AP9i8r8Ol2KS8Ckhdn0D2vXaoHH0AESWWFUNju4U0wMcY9ZFAjPmwsvkmH/IAh/LgB BOOWCgjDXJyIcy28fCZUqsMKAVIIBJWPWvdTgRyUZLUliESIEUp7w/qdVAYBiqqPNfw9 /BAE7HNCITwn9BQaRK4asq9yNZpAkLKvky5j+vuKFaGj9qOPBVK6mrW0iL9HJWTrkL71 EbOfoFZh76pm8knyrSwcx0c4eef1p8NHYxkqHg42/fVGcb5+b/Ve5a3AtoDNu1UqFUyH yCpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=PLG8kARqZXa4MD2U7sA+bP9p4ZfenOQtJbQ2PkO9Zys75z/ZoW9dddqYlXukT3Udfw 6LcvOgeWFVBeB2Tu/UfROtKtpO1hteIrvyr7/wz1jOup/dDR4JaHV/A7Ddi89E2hz7Ci 0YrOOtyy3FFhHjY2IAZYBF29TeFQMrUOpX0k5ob6kqXTNZCQjxgoh9gFZZqAb4RaTuQa g/h+naKJrots3LzW/HuWM8HIOxrhUZtN0DsiCfvu9V93yCjdJRZhUvJCsfDM9FuROzZF CDn6Y4p4GX6bj7siCAIz6/LNIZZOUAfzEEJpBA41gH9uU1GLbhDBOvbDDna6OaagpT0O Q1sQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j88nY+oI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.36; Thu, 04 Jan 2018 04:51:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j88nY+oI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752931AbeADMvc (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:32 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46444 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752713AbeADMvZ (ORCPT ); Thu, 4 Jan 2018 07:51:25 -0500 Received: by mail-wm0-f68.google.com with SMTP id r78so3295801wme.5 for ; Thu, 04 Jan 2018 04:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=j88nY+oITtOCKiIUsG1wfaWuvTjJaHbNZG9QDMI2AcXZ1MP/UBH8PHC9x6FQa1gSSq 0U5aSXXWV3e+JU7LMKdTKqfEiDASCxwFy4UDlLfnhn9qxcKP4GMBrUeWsOT/+9bF20/B MzF2t0+8F2IWwjNSlXdu+qOWegJh9I/k26+As= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ISYh0PkE1j9BwfAi+cGjUoGaBFRtbCXSQ5n7YU7T+jA=; b=Bo0WmpV3foSl34v4UWPMsqmrQt5J+3re2P5l4xwdPKS+qPNDUQPrctwwXmp4CXPL95 6uG0+bqRIauqat23Dd7xm8+R3asD7mZjR2eRlXN7xtuYNEOkCo3qhEW+Twjdiqmsa3bi AfDpUZ7eiL616CWmDGhf7NTA11KHGRm/qFUUUlcwyXsm7Jr2wSu0+6NQeaqVJcJgB+BT 524K6GsspetEjBjdvXdA2llecVaC+4uJUkHsQMe3XZZa3nA0BTmY5TKeo1AWYMNoIl0/ foOADKPe9+TBd5GngHJsCDiHAKtApwgXn4FJCvsSzKvps4JvVFRiD6685Sn3HUhxa3jK 1tMg== X-Gm-Message-State: AKGB3mI5+PCzxByS9smlis9eQ1C/oQ1hJHVQZLFjClP+QBWQTBBI9pEh I0p4k8qYFYLLCBK2g8h7oT7R7A== X-Received: by 10.28.140.206 with SMTP id o197mr3623274wmd.43.1515070284183; Thu, 04 Jan 2018 04:51:24 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:23 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 06/12] clocksource/drivers/stm32: Encapsulate the timer width sorting out function Date: Thu, 4 Jan 2018 13:50:22 +0100 Message-Id: <1515070228-10481-7-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to clarify and encapsulate the code for the next changes move the timer width check into a function and add some documentation. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 14b7a2b..862134e 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -80,9 +80,27 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * stm32_timer_width - Sort out the timer width (32/16) + * @to: a pointer to a timer-of structure + * + * Write the 32bits max value and read/return the result. If the timer + * is a 32bits width, the result will be UINT_MAX, otherwise it will + * be truncated by the 16bits register to USHRT_MAX. + * + * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a + * 16bits width. + */ +static u32 __init stm32_timer_width(struct timer_of *to) +{ + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); + + return readl_relaxed(timer_of_base(to) + TIM_ARR); +} + static void __init stm32_clockevent_init(struct timer_of *to) { - unsigned long max_delta; + u32 width = 0; int prescaler; to->clkevt.name = to->np->full_name; @@ -93,10 +111,8 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { + width = stm32_timer_width(to); + if (width == UINT_MAX) { prescaler = 1; to->clkevt.rating = 250; } else { @@ -115,10 +131,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + timer_of_rate(to), 0x1, width); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, max_delta == UINT_MAX ? 32 : 16); + to->np, width == UINT_MAX ? 32 : 16); } static int __init stm32_timer_init(struct device_node *node) From patchwork Thu Jan 4 12:50:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123419 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11390886qgn; Thu, 4 Jan 2018 04:52:48 -0800 (PST) X-Google-Smtp-Source: ACJfBou0JGtMyz5kcUoPkJ1VjEV+ZFfYXRaUpi+sJRU8hBx0bgqwq3HpE3oLVXvatlBEX3Ibb096 X-Received: by 10.84.240.139 with SMTP id z11mr4556713plk.348.1515070368874; Thu, 04 Jan 2018 04:52:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070368; cv=none; d=google.com; s=arc-20160816; b=Idn0Zxq3nDyy1mic03F4/Kzk8gVdxUYDgxQzOFocqffvf4qQ/LJjfbSAaqWPhHiqWr AoEm+ohJbpV1c3UlEL18E39okZnE/NS4BMsg3gnMia4sp3UaiAO5qpz2hI0lW/xi6IwQ gaMQCG7sQmeBqWjb6e6FKTr6HH+LxXrQtNibFN3OBHG+U5GRATojHHW15qqk0e4HfLyi VzxPvF9G+22JIkcVZU7CFN5kUljK3XSDPHVbX7wtOvYJzZtFb2sSm3QPO3YLc3E6SIiE Qp/t7bNej8BLAeE2zYjw4FVbaOJRpYY+6KPdFvZwa3k3VFaarXXgZaQH/qR9AxW2LeTF lkPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=W1UN4RiKQIqNn9o0WibTbGzXVi2IFRoGRjTvmPwfcoI=; b=Epfsp4WpzxKfcS3QxsjtYw9B5i4gCJ7vGluVGemApE35rKvYZ2OArSmEJfB4QQgpNn kSl4u2IBkOqHsycGcLHzaPfEQ39UJK0ChElkHBi0SpIKvx3VSajmc/E6e1c3CDCaAwWO rLQEGXEqjQengdkDVI0Q+Ifd+I16t9dTlW8uG0OPslCcVwTE9bv20PztJM8FkqbqydFZ zXCRZuo4J1MO22J55ZURgDjKQxy5f2ZwkxzjhgsODuhHDpxglfOpL/L/MaSGhbLZB9hC Xn6eGLI5q0Yrc86uu15q+NBOC6lglATsk5v+UcIUPA9uBggCkk9YI9B7oBhKTewflSXH M0EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LSrmbEnd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b3si1999070pgr.829.2018.01.04.04.52.48; Thu, 04 Jan 2018 04:52:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LSrmbEnd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752889AbeADMva (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:30 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:46559 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752820AbeADMv1 (ORCPT ); Thu, 4 Jan 2018 07:51:27 -0500 Received: by mail-wr0-f194.google.com with SMTP id g17so1382037wrd.13 for ; Thu, 04 Jan 2018 04:51:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W1UN4RiKQIqNn9o0WibTbGzXVi2IFRoGRjTvmPwfcoI=; b=LSrmbEndDA+7Vqu9FbRTqoeP1yTEMLjNJTD/fSMYJsIPhAv0AlmTOupwJvTQUuNnbl 7tKZZnsxbOGr5a+dzluT7OS/SxzvRQyP3OkOUjSZK+KT5qhMAgk314GQ8+kDucaluGhF QF4DkOBQ1eTM4aYeyn+YZqIijdWo6bPbbTHYE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W1UN4RiKQIqNn9o0WibTbGzXVi2IFRoGRjTvmPwfcoI=; b=EAkV5QCvSYlJb2FYU6FQfMS7QUajZKp5KOXMJc069Q6fD+JniOEB79E3SI4M/nHzkI zvKIIqFr0dF0MpIroU9GZ5bYwyn4ph6M476qHKx35wtmbb2vs4OksTbu3GYxcahgN8HI VPI7KrceLsvGfKXn+ek+fCTdIhNwi4EglFzBTLGV0GcBs98ts4fZunCAVhpfeREYiESw y9DBwwLqZoH3gVrYZI0jT4GHj+e6Xwzo7eChGMVHFQwq8Q42LOll/qWubuOEu/OOPZOS c4dqCsUNFsp2pwWV+mMWpOCehoc4ctOjeebsHwfwcZurV53tDP8D3GJWlaTv2eoF1Ndc te/w== X-Gm-Message-State: AKGB3mIdr6tY26RqT0sQyCAO/jhboKvmbaMg9vzXRiOi3VpI4ONMT/j8 FNoSF4pM8r22HP2FXYtETt+qEg== X-Received: by 10.223.134.115 with SMTP id 48mr4561068wrw.213.1515070286117; Thu, 04 Jan 2018 04:51:26 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:25 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 07/12] clocksource/drivers/stm32: Compute a prescaler value with a targeted rate Date: Thu, 4 Jan 2018 13:50:23 +0100 Message-Id: <1515070228-10481-8-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The prescaler value is arbitrarily set to 1024 without any regard to the timer frequency. For 32bits timers, there is no need to set a prescaler value as they wrap in an acceptable interval and give the opportunity to have precise timers on this platform. However, for 16bits timers a prescaler value is needed if we don't want to wrap too often per second which is unefficient and adds more and more error margin. With a targeted clock of 10MHz, the 16bits are precise enough whatever the timer frequency is as we will compute the prescaler. [Daniel Lezcano]: Massaged the changelog and added comment. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 862134e..ac55896 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -37,6 +37,9 @@ #define TIM_EGR_UG BIT(0) +#define TIM_PSC_MAX USHRT_MAX +#define TIM_PSC_CLKRATE 10000 + static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); @@ -116,7 +119,14 @@ static void __init stm32_clockevent_init(struct timer_of *to) prescaler = 1; to->clkevt.rating = 250; } else { - prescaler = 1024; + prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to), + TIM_PSC_CLKRATE); + /* + * The prescaler register is an u16, the variable + * can't be greater than TIM_PSC_MAX, let's cap it in + * this case. + */ + prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; to->clkevt.rating = 100; } writel_relaxed(0, timer_of_base(to) + TIM_ARR); From patchwork Thu Jan 4 12:50:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123418 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11390744qgn; Thu, 4 Jan 2018 04:52:39 -0800 (PST) X-Google-Smtp-Source: ACJfBovf+qgjlpXZHEk2UXnXQ6Ofla7vrZemIfu9W8Kb+rDtMdnhsNQLZRGiAX8cw8ZMk3vWv8pV X-Received: by 10.159.198.1 with SMTP id f1mr4542376plo.450.1515070359604; Thu, 04 Jan 2018 04:52:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070359; cv=none; d=google.com; s=arc-20160816; b=F0EavMlOQNTJ8e9mDiHHiRuFcj+R8f2af8eWqZyjkxhwRkxyPrt7rO9XVxDIBSC5UF w/beQ3sfdSznl6pnlqHPPQ/AfMb02gc+Wd/PUUVweyLVg1fRWR9HXBNHD6i7f/Ijjtto /WYRL3WvHyFZjO6PgTnssjz5BM37xzKa6yuJMN56Y2U1TG9i1YID40GyDx5PkziHvaii K9xYEi4pjbTD8YeqEPbA/d3V6PjLNNSTTGnNKIbPM3jmDnlMBRP8NY7DhmlnKLsgvlt8 Q4uleyvkNlKdmQxr46iy2W9RSEG/sAVvesSqnv3UKNIoFTb1tTv81ab84KQnDcTSv0Np YOsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=migRDHJdxnkLgsjmJtEkASHxaZfMp7VL85o/Dq6lDaI=; b=PLDkCSsDLHjmFrjK01oaWQO1tztSdCQ9X8Kt3XMUU9vLXevDM7zVl2iI2jIZNJECEk szAxW6/jlvBLrGPcBZ8ZQGyDCp2cVCauTcAWvSdufgZZPK8+AmxqBSV7CMsS+1yz511I IQgjS/iS1PnPyKdgRMRhIHqiHAPSjeS15ebrXhZDErynL+/8u4FTqm0NnCtIKFZGXgyM Xc8Zn8V1RBGLt7BY2AkdlcviVea1gilizXTLjsV02BnO8usF3NBA4q/N4kcYxcTAYUN1 pNzjpGLzbjbW0qNxCSbbDQZOvli2JzRxj3+avg05asC+x7mJRtRhOr+E7MUKzsv/eA0x Nzlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YDuZ4TaH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b3si1999070pgr.829.2018.01.04.04.52.39; Thu, 04 Jan 2018 04:52:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YDuZ4TaH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753145AbeADMwf (ORCPT + 27 others); Thu, 4 Jan 2018 07:52:35 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:32794 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752837AbeADMva (ORCPT ); Thu, 4 Jan 2018 07:51:30 -0500 Received: by mail-wm0-f66.google.com with SMTP id g130so2063042wme.0 for ; Thu, 04 Jan 2018 04:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=migRDHJdxnkLgsjmJtEkASHxaZfMp7VL85o/Dq6lDaI=; b=YDuZ4TaHsZ61jI6/gwSwo4Eerw76/jbeNLZdbY8mKPoj+3We/bxFnClqe68fhzAEUW qzoVHfWnt2ZfGsE/egM5v5KX8Bwe88MHb7hb3UXtlSlp1hDQqFqJX7SIumI56AR2Dzrj PosuQacCqLUsWFz42zdCbnisWYxF9p+VCTqr4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=migRDHJdxnkLgsjmJtEkASHxaZfMp7VL85o/Dq6lDaI=; b=igIfeN2aFZ7XEFJD7xAYeCwgNXjsQI4Ffq1pIwIJDGl8nQ+M4jFIo4u0KrchZ2691A AYXmQcaqYyvFqi6SPQIBPGn2Rin+DsgAuBRNFv8qp4nyB5OLm0q2HBdJMBcNFtv0SjKu KJepzEjrBh2MWr19Cgv2eYlWkKVJomWsmXFBOZjXvPCdhyMowKFf94aOypCDmRKzZWNT +z53KTO32iiTZ1EeDfn8YVy3xDX0Hrs8s1iwjPMt0oymwlIORKKama6Pa37V2Qx+npZ6 7ewGtS4644XNLOdVmy42cQ/sNK3N7gRL/d6BBlvnis9Abtw8b2b+9N1Ofdw0PD4rjc6s dmOA== X-Gm-Message-State: AKGB3mKB3A9Gv4jCBdRL+dghm2fv9XSD5u26SvZE88KtFZ45GFe9MyJi K9l0qA6aaJedEicD8swNDkGiAQ== X-Received: by 10.28.213.2 with SMTP id m2mr3684087wmg.141.1515070288282; Thu, 04 Jan 2018 04:51:28 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:27 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 08/12] clocksource/drivers/stm32: Add the oneshot mode Date: Thu, 4 Jan 2018 13:50:24 +0100 Message-Id: <1515070228-10481-9-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The stm32 timer block is able to have a counter and a comparator. Instead of using the auto-reload register for periodic event, we switch to the oneshot mode by using the comparator register. The timer is able to generate an interrupt when the counter overflows but we don't want that as this counter will be use as a clocksource in the next patches. So it is disabled by the UDIS bit of the control register. [Daniel Lezcano]: Modified the changelog and splitted the oneshot mode from the original patch in order to provide one feature at a time. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 56 ++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index ac55896..baca42c 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -24,14 +24,18 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_OPM BIT(3) #define TIM_CR1_ARPE BIT(7) #define TIM_DIER_UIE BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_SR_UIF BIT(0) @@ -40,33 +44,57 @@ #define TIM_PSC_MAX USHRT_MAX #define TIM_PSC_CLKRATE 10000 +static void stm32_clock_event_disable(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); +} + +static void stm32_clock_event_enable(struct timer_of *to) +{ + writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); +} + static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + stm32_clock_event_disable(to); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; + + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + stm32_clock_event_enable(to); + + return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + stm32_clock_event_enable(to); return 0; } @@ -78,6 +106,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(clkevt)) + stm32_clock_event_set_periodic(clkevt); + else + stm32_clock_event_shutdown(clkevt); + clkevt->event_handler(clkevt); return IRQ_HANDLED; @@ -108,9 +141,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.name = to->np->full_name; to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -129,12 +163,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; to->clkevt.rating = 100; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(0, timer_of_base(to) + TIM_SR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); From patchwork Thu Jan 4 12:50:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123417 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11390454qgn; Thu, 4 Jan 2018 04:52:21 -0800 (PST) X-Google-Smtp-Source: ACJfBov809FNjlXd4zRh44pUKz4YlTCzzRhykw2W7MSObxKwdmFvlnGnoilkp5q4shD4eFLQS5td X-Received: by 10.98.162.20 with SMTP id m20mr4726360pff.6.1515070341008; Thu, 04 Jan 2018 04:52:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070341; cv=none; d=google.com; s=arc-20160816; b=X6jWBSo/ysZH1tIWSOk3ozbJgZXKB+mJL0yhsSxkpVz8xT6rOQjp8Cxboiw9nN2cW1 lpv1QP9Vu2kgAPHt6v7HNie7fvCNNPqh158/0rEwnKx/irBekok8arM+WspsuOAC6j0K Z5321YtbsXEft7MHRx2VWu6RieoDQh9PiezcGygbbysHbKxw2MxCkIrmSuafDR5KwIpc Z8tLBUiXVxDhm8FZxQLda0kG7u7Nt7y1QvJF5zK7/Gxcw0lS6m5g+3CIHSSdDdmpgIPN yZeL97hh7P3EIylNZVKbSQPNA17LXsYxQe32o5LuUK/DFZW5HSjScnicIb6mUPHjPtSf 5Vwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=kLZbY857xM7DtopOtBg3KCSvCVvbCDMp6H75OglVrWA=; b=v2rIxUIk8tnpJ7a3btFi/vybTDJn4SglnvQP18U8ZE2D04xa+30G9znesmj02IW7Gd zBMuw8UTzidUGooqBTFSWdYbUjC2sWHK6PAljZCqfvcx12i+ASRudjSlWWBvpKWY1N8U TI5xcr6XFZzFuZ5yTNe/1hU3aPdNV9Fb2LdwFVrCj+d3uLmU1rB6PGY0gpfcqIgfNV6Z ptPOEdj+roqrq2R4no7/Fep10Ln2HZRlKFvH9L3My3wcoVGpW7wYmxNBmA7N1jS2+z0p TuSbVVy76+XB2DuOE7V22ZXeaLr4krMce3WpDvdpTbrDvyLS/6LDK81IdmxNBgeRqk9y sRgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i3adswEg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o7si2028497pgr.567.2018.01.04.04.52.20; Thu, 04 Jan 2018 04:52:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i3adswEg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753134AbeADMwS (ORCPT + 27 others); Thu, 4 Jan 2018 07:52:18 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36349 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752820AbeADMvb (ORCPT ); Thu, 4 Jan 2018 07:51:31 -0500 Received: by mail-wm0-f67.google.com with SMTP id b76so3278965wmg.1 for ; Thu, 04 Jan 2018 04:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kLZbY857xM7DtopOtBg3KCSvCVvbCDMp6H75OglVrWA=; b=i3adswEgdFnUSKSIoQMu+0/1RvjCoQ1MtiSe+eHTGO2WrcF5RFT3b5DkZxNFiAt1+I TVWEjnVO1GO0lMcY2RuSOhJdFvCbxKbuKIe6j3MPHoSACqabdKZkrorTxOI2eipY/874 Rm620fRt5qvqIVpnySpk7+czS3kHtl8qs4lAk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kLZbY857xM7DtopOtBg3KCSvCVvbCDMp6H75OglVrWA=; b=QDG3E7CtQT1mL1z0br/qY5DNcRx52Pv/hs5AsIaGlb2aogdK48JyinkM5VKRCH42e6 LOsVDpycno8GDA+ccA5fD1lwaiza0QMvL3BA1Ci9PBkXQiySdJiCjprs9GhrJiwpkkoo T1GlvRDHHhvg7ODY14DgVAfLIY/FES4P7+d5amCWUS70miw6EC07XYRCiAcA5M13gNDx gqlZs5HUD0+ac+QYmrfE9cSs+l2bggDIQ7wPlZgvG+Vq0p6g0FFSp9yCG0SOLX+ataEB scLNPcPWt7qQ+60Hcc/yl8SwxK5MGgaMwsV8oO19I0H3JK1ooUq0VTHyCafhLzG9zUVV je8Q== X-Gm-Message-State: AKGB3mKvR7HcAXFgmkaN9lo5NaEBIwOG6y02aqFisfIK9L5Vcufq3G3S OvCy2dEXLHABBn6S+RTCeQ6ngg== X-Received: by 10.28.16.144 with SMTP id 138mr3773874wmq.155.1515070290400; Thu, 04 Jan 2018 04:51:30 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:29 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 09/12] clocksource/drivers/stm32: Encapsulate more the clockevent code Date: Thu, 4 Jan 2018 13:50:25 +0100 Message-Id: <1515070228-10481-10-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In order to prepare the clocksource code, let's encapsulate the clockevent code, split the prescaler and timer width code into separate functions. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 107 +++++++++++++++++++++++++++++--------- 1 file changed, 82 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index baca42c..1891924 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -44,6 +44,42 @@ #define TIM_PSC_MAX USHRT_MAX #define TIM_PSC_CLKRATE 10000 +struct stm32_timer_private { + int bits; +}; + +/** + * stm32_timer_of_bits_set - set accessor helper + * @to: a timer_of structure pointer + * @bits: the number of bits (16 or 32) + * + * Accessor helper to set the number of bits in the timer-of private + * structure. + * + */ +static void stm32_timer_of_bits_set(struct timer_of *to, int bits) +{ + struct stm32_timer_private *pd = to->private_data; + + pd->bits = bits; +} + +/** + * stm32_timer_of_bits_get - get accessor helper + * @to: a timer_of structure pointer + * + * Accessor helper to get the number of bits in the timer-of private + * structure. + * + * Returns an integer corresponding to the number of bits. + */ +static int stm32_timer_of_bits_get(struct timer_of *to) +{ + struct stm32_timer_private *pd = to->private_data; + + return pd->bits; +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -124,35 +160,31 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) * is a 32bits width, the result will be UINT_MAX, otherwise it will * be truncated by the 16bits register to USHRT_MAX. * - * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a - * 16bits width. */ -static u32 __init stm32_timer_width(struct timer_of *to) +static void __init stm32_timer_set_width(struct timer_of *to) { + u32 width; + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); - return readl_relaxed(timer_of_base(to) + TIM_ARR); + width = readl_relaxed(timer_of_base(to) + TIM_ARR); + + stm32_timer_of_bits_set(to, width == UINT_MAX ? 32 : 16); } -static void __init stm32_clockevent_init(struct timer_of *to) +/** + * stm32_timer_set_prescaler - Compute and set the prescaler register + * @to: a pointer to a timer-of structure + * + * Depending on the timer width, compute the prescaler to always + * target a 10MHz timer rate for the 16bits. 32bits timers are + * considered precise and long enough to not use the prescaler. + */ +static void __init stm32_timer_set_prescaler(struct timer_of *to) { - u32 width = 0; - int prescaler; + int prescaler = 1; - to->clkevt.name = to->np->full_name; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; - to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; - to->clkevt.tick_resume = stm32_clock_event_shutdown; - to->clkevt.set_next_event = stm32_clock_event_set_next_event; - - width = stm32_timer_width(to); - if (width == UINT_MAX) { - prescaler = 1; - to->clkevt.rating = 250; - } else { + if (stm32_timer_of_bits_get(to) != 32) { prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to), TIM_PSC_CLKRATE); /* @@ -161,7 +193,6 @@ static void __init stm32_clockevent_init(struct timer_of *to) * this case. */ prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; - to->clkevt.rating = 100; } writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); @@ -171,12 +202,26 @@ static void __init stm32_clockevent_init(struct timer_of *to) /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); +} + +static void __init stm32_clockevent_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); - clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, width); + to->clkevt.name = to->np->full_name; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + to->clkevt.rating = bits == 32 ? 250 : 100; + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 0x1, + (1 << bits) - 1); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, width == UINT_MAX ? 32 : 16); + to->np, bits); } static int __init stm32_timer_init(struct device_node *node) @@ -196,14 +241,26 @@ static int __init stm32_timer_init(struct device_node *node) if (ret) goto err; + to->private_data = kzalloc(sizeof(struct stm32_timer_private), + GFP_KERNEL); + if (!to->private_data) + goto deinit; + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } + stm32_timer_set_width(to); + + stm32_timer_set_prescaler(to); + stm32_clockevent_init(to); return 0; + +deinit: + timer_of_cleanup(to); err: kfree(to); return ret; From patchwork Thu Jan 4 12:50:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123414 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389837qgn; Thu, 4 Jan 2018 04:51:40 -0800 (PST) X-Google-Smtp-Source: ACJfBot/SJU0NFQndqxiaphSuA5ux3EVfWJvyTj55tX106CrGh3Y2HG5mNWYGJcRCGhnHfLB8CM0 X-Received: by 10.84.128.67 with SMTP id 61mr4422982pla.265.1515070300447; Thu, 04 Jan 2018 04:51:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070300; cv=none; d=google.com; s=arc-20160816; b=WXqwxj7/sUMCRkgWM97ldajsm2clIqGfUfk5A4k2hxHuxnjugYWeahZ6jcGegrTNoC G92t/FrXqktZL+G+mcm7M9SSDIOFfca2OleAaFvvxyfNehkrWRRVtRFkMLYVZaj3Ngo3 Zi+MzZTQAD9cxYFuVEh24aJb+p0PB8O8X+Xt5Pc3MSdnfkxz6mcNiD9V2jTUC5kVn8bh +bQQ7e9U+u9oFkwaQ7SsYkkdCVdw/g/cZSbkNYS1S1luhx+pQrgNPbqo4WtG8gBp/mkn lYUQal4pC2Yp9e34AY/dbc3RTC1s5BHME2yZcVbMUlnk8rMasTt+9u+YHV/GP63cd9qk UPZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=m2yDyigNDAmtp+cR1ZbB507rIbAENcswABrZPPwEXx4atNMZlmb52tLiQATs/e3nF4 TcRLLp0K5q+zlBA9sgRfzxuZrx6j/yN3RfFEW4W9fV9av25zI6naZK47Q4hgw7vBoZLd 5c8TUd4CpjfUxtddl+fCtzqIA2C/IRmfUgIn4NxkgQNnTxeA7Wubd3nNr3o8Mi0yUj+g rWTCitIi1Hm83rr5YBtzup9phrUYVZGz7rkfT3RQ9fyk6W4i5hc70SO0NpxcZTirrNIy jMf4a7djPqfyViscV+SFVMSgutbN+p/EuKkggz9dcy7i8z5R37fOyujQF5xdBFrTlYhB dHbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RvQnB+zl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.40; Thu, 04 Jan 2018 04:51:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RvQnB+zl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752992AbeADMvh (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:37 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:36394 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752941AbeADMvd (ORCPT ); Thu, 4 Jan 2018 07:51:33 -0500 Received: by mail-wr0-f195.google.com with SMTP id b76so1402200wrd.3 for ; Thu, 04 Jan 2018 04:51:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=RvQnB+zlOz7nAyXzX3xkzao5ods8v3Jm/thCc1XPGiZZ5F2VofC25aOMhrupwoewW0 WHG0Cq7qQtEZKDutPrELrWQBnzG824f4h6n9LJjMGO4I4n/jiu2daV9vDByWd28g33GH 5sbwqgzV3WvsbiM3IYGqvCWJ3fajZSEMqN3p4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=59YpHz0KXK8f+Jk40YI5lOXnrPdf6Mawb7LZI5Zho7s=; b=bHQewwCKSsI/8SdkThZ6tXP1yF4716HjtWFY+lXSdKChj+MfwvCgfRow+326bw1PA+ B4gDlofWZcFGU320wC/+c+y1v8uwpuV0vBNdYPVwOkk+JcnTRNGNfqF3Od4an44W/4d7 xX/T9HaBY8pXDsjmdjPvc/qHVzKS2mqk6SvTAbEyQdTRpIHBJ9O93cHyXJp8kpbe1mt1 hhrLMTM0HKltd4Sa9rz0eH1HMvkurvHdC5+j9TIBEnthVUxuOahBfFMEIUV17ZBogFRE 2c7FGLOw0E1axCSlnNIEu6qM9OeeXNzlLjBtd9DWKZf3bRAXoM9PdN4xYtV6ftczPBvb S+Cg== X-Gm-Message-State: AKGB3mLK6BlN8ihTlws3pEUZNVZaIjgXxcrroXJRAG67SjwV6bQUHiEn wDNv8olIVpiWlfjBOe8PVQP/mq5RlNI= X-Received: by 10.223.134.134 with SMTP id 6mr4410711wrx.17.1515070292447; Thu, 04 Jan 2018 04:51:32 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:31 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 10/12] clocksource/drivers/stm32: Add the clocksource Date: Thu, 4 Jan 2018 13:50:26 +0100 Message-Id: <1515070228-10481-11-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The scene is set for the clocksource, let's add it for this driver. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 1891924..4634f4d 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -80,6 +81,13 @@ static int stm32_timer_of_bits_get(struct timer_of *to) return pd->bits; } +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -204,6 +212,31 @@ static void __init stm32_timer_set_prescaler(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); } +static int __init stm32_clocksource_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); + const char *name = to->np->full_name; + + /* + * This driver allows to register several timers and relies on + * the generic time framework to select the right one. + * However, nothing allows to do the same for the + * sched_clock. We are not interested in a sched_clock for the + * 16bits timers but only for the 32bits, so if no 32bits + * timer registered yet, we select this 32bits timer as a + * sched_clock. + */ + if (bits == 32 && !stm32_timer_cnt) { + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + pr_info("%s: STM32 sched_clock registered\n", name); + } + + return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, + timer_of_rate(to), bits == 32 ? 250 : 100, + bits, clocksource_mmio_readl_up); +} + static void __init stm32_clockevent_init(struct timer_of *to) { u32 bits = stm32_timer_of_bits_get(to); @@ -256,6 +289,10 @@ static int __init stm32_timer_init(struct device_node *node) stm32_timer_set_prescaler(to); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0; From patchwork Thu Jan 4 12:50:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123416 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11390222qgn; Thu, 4 Jan 2018 04:52:05 -0800 (PST) X-Google-Smtp-Source: ACJfBottTocKDeUI5c3V1pF7Ml9LJ1jovOFnulLU9eIBaUDpLzQ7/k8P8CKjW8f6l4AEn5GjdxW5 X-Received: by 10.99.0.86 with SMTP id 83mr4001891pga.326.1515070325632; Thu, 04 Jan 2018 04:52:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070325; cv=none; d=google.com; s=arc-20160816; b=Ho6gpZ/qD/7RfAlwrLAyAC4x8RLi0z7ubICVWRU9i6pkV4eVxrJSO9If31AcqAbSDJ 63Cb/CxfVsXuWw5f+X02AsMxqUOKzPFlkP7JF+hwUO72OhhUlTzvttEKO/PupyOwg8D5 iuFU/gdXBQD3K8zFVUueoOosZWpq8KpTMknPXPTooEIyBIzdg4PyMxZInv1qXtCekAEP lZIzKKr2DY3/gsWh/CHoeMLUW4eNuISGzKV7UPHuXCB1ElBLt0BZsibd8Q60KNkdOqnH ABOKD5i9B2XBRUvdYh2WJq6pOxSY3LsQIeL7E/nXLiybQs8VyR7U0cIpHld/lUaxTbGd WK2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SW+UXwe3FOrgHdI3u4Vqm7du18NRC6xC7iv/sadwviw=; b=kH9vHm6FoH8A9CIxjiwh8HDNrdpAVHEvjken42UXFronpkxGRAAwtCDHOQB4xnAKRa JYgFnMX+gOFMroky9fAr1pf48EfpWeC3Plye69Xc+Hev7eKURQPxuR2wBQDRGy7BCcGf UxW1cyx2qv/WQk161L+E3rAGtNByQbfdfIrZvNO2IJ+yPMfn7oFYzjlDmS5NiYrYyDKn MkSGobYTmV60NrlSL7z90An2LO9jGLaPVPkEPksnUN3fTwBkMBie+rGCEF+bA5cW3K5c iDEHR7tA81P3TK0hBMVwu/+Oahqc/mELKPSktvKZzcEckwtr7Jtqq15VNCc1EQk9oovI l7bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FCY/dBky; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.52.05; Thu, 04 Jan 2018 04:52:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FCY/dBky; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753093AbeADMwC (ORCPT + 27 others); Thu, 4 Jan 2018 07:52:02 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:35260 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752949AbeADMvf (ORCPT ); Thu, 4 Jan 2018 07:51:35 -0500 Received: by mail-wr0-f195.google.com with SMTP id l19so1397874wrc.2 for ; Thu, 04 Jan 2018 04:51:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SW+UXwe3FOrgHdI3u4Vqm7du18NRC6xC7iv/sadwviw=; b=FCY/dBky1d/tYFjy2vleroFTBGc/469v/Y80muAuhcPMrZjoNNqAcMQN7wmrDfhUew HlC8Ycxk91ump8zxPqeqV5fsqCo7ubJhknW9Nc+T3V0RuoQSq6bMe+7o80SIlTYcUICm fxgKdwUHJSYLOyRPFDFKKhglnrNsD8+kofmVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SW+UXwe3FOrgHdI3u4Vqm7du18NRC6xC7iv/sadwviw=; b=YyuZ/15VR1VDR8wOD/Njlf2lAu7t+MVRYhUqBtv2UkIdOfTQCtURbOAHgBFXEAJilE 0l47wJZj7rcknkpLToU1LQvSQnrclH9z8usgmFtnmaplfJCqVtXwCb3uz0blnOuvu8Tn +PSaN9ar60P2UmxLxtppA2Q55CnrBYmrBLYniZotWNJocQtTNYnk3BLjhy6uCeEAHa6q ek/xvdU3bAp0uP8ji3JIPsfmfZRS9TTSWc/+Kwk53zFZXb0FlksPcKIKSzdndsE0bcUF vK9TyFUFgRrBIpf0HbNfhzxE2fuGWxeXJkKKmq7ckfDxkmcZ/10FgOkpVrmIk5l/vZ7m gTfw== X-Gm-Message-State: AKGB3mKT9283cpSSFOPOQXsNBZBqsfQRYXEMZUeWZUgXDV/4R2TvlKf5 DOvm56Cd/dqO7/0VGQ6sEQXwXg== X-Received: by 10.223.169.4 with SMTP id u4mr1020472wrc.185.1515070294418; Thu, 04 Jan 2018 04:51:34 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:33 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 11/12] clocksource/drivers/stm32: Add the timer delay Date: Thu, 4 Jan 2018 13:50:27 +0100 Message-Id: <1515070228-10481-12-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the timer delay, that saves us ~90ms of boot time. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 4634f4d..dcf8445 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,13 @@ static u64 notrace stm32_read_sched_clock(void) return readl_relaxed(stm32_timer_cnt); } +static struct delay_timer stm32_timer_delay; + +static unsigned long stm32_read_delay(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -230,6 +238,11 @@ static int __init stm32_clocksource_init(struct timer_of *to) stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name); + + stm32_timer_delay.read_current_timer = stm32_read_delay; + stm32_timer_delay.freq = timer_of_rate(to); + register_current_timer_delay(&stm32_timer_delay); + pr_info("%s: STM32 delay timer registered\n", name); } return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, From patchwork Thu Jan 4 12:50:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123415 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp11389891qgn; Thu, 4 Jan 2018 04:51:44 -0800 (PST) X-Google-Smtp-Source: ACJfBos8FI66JEXDu3lWe17DF/WO+u3emq/hfOpnJvP06K9vjd6WjRtIjM4/OwmGBUwdQ1Blmcz6 X-Received: by 10.98.156.204 with SMTP id u73mr4663270pfk.8.1515070304026; Thu, 04 Jan 2018 04:51:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515070304; cv=none; d=google.com; s=arc-20160816; b=X+vxP2boZo0vFwbkAE+D2Yp/2BfK56jO1vMiX0+dLTzya1f2wPLOTpckrReFs08yvr 87hBLZp0OeThm14HDufOHtwDHtq0W5tYDIe6YHNb050X90jvq5rclZCqOGA/DzD0d/O2 frlbV7GiUMjsQXISltebkyuXXM4WHP8mtKDlQh+Ld7YRR4voWvLwiFW2Eo1bwkjFCv/w 0sb680O4m9DS7HpH0UvJeWWVyMGhduWD5NknkW9U3pZ5o0oARbFFzMGBbng/QYU3b2MV YwFmTot6R0VnVKBS2d1w92LRKN6fBFnmTOG2CfYcwzS9OPXgRFuZFMnSurSkpUlV/yxw cqAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=eL5bvzHTZ4AFS3ok+8f+9iOVrDMHQXywi0pp/m5364g=; b=ZfkViaKAm2qY9bGZdwr2ntj8V3u6boypIf+uZ2oyuqkKdEca8TdPrYOLyb4zlfcZ1+ oERXn65NvMAtwg90MqLCaRa0EOdX/gbL2YpsoPZa7rTUIeaTnWHfIdxOvpif+V7jF34T jtbvLzRllBF7P2yYh528KNG7nJDUp3tDs0Q6lfA6IS2pyu8fINGBF+KczPCp0qizRMZ5 rt0RC7Iwy83wO0pyvcRqE0Q5fA/l+4G7AcsJl9Fjj5jqLT7MYx3UeqE2PTa8t15rFv+1 3krdWTwF80RabyhQNfLEgMxYoWK0wZB4gZSdvj+pJ2zy7JOhaqtXC5bL+Z2tMbLI+Zga 1Zng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NNGDscNc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i186si2288929pfg.286.2018.01.04.04.51.43; Thu, 04 Jan 2018 04:51:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NNGDscNc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753032AbeADMvk (ORCPT + 27 others); Thu, 4 Jan 2018 07:51:40 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34036 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752990AbeADMvh (ORCPT ); Thu, 4 Jan 2018 07:51:37 -0500 Received: by mail-wr0-f195.google.com with SMTP id 36so1396960wrh.1 for ; Thu, 04 Jan 2018 04:51:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eL5bvzHTZ4AFS3ok+8f+9iOVrDMHQXywi0pp/m5364g=; b=NNGDscNcwWqvHAZbTEl8EGsDxzFr4MOC1GZJNFrF7WCpoiAA8R0Jk7+Y+f5vLL1Sce f98gJqtkUJR714GmzoSkWrqUw1J3nmXgnKXB6yEHvJqmbaMsZJiCtNqTKIX4kbIFi1m5 8rsaXlbMXlIxLjOPpBpz+6sB7mlxBalNtXOA0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eL5bvzHTZ4AFS3ok+8f+9iOVrDMHQXywi0pp/m5364g=; b=ahR9DASw7JjziEBABp7zmZLhuAfZI9Bh7DZ6EAbLqj//rYezvjYHOumGWEZDONnR1K JVZTSsaPhE/+BS+LudnJzovI2pqB/CQv2sNQG9coPR0rfH2/hghUvjYop8PM10Ri+EfL GWsAvor2iU3BE+KzLjkjjEvnhBfGNsx/3y9wgvwLXbhJV/O/tJoah0UFrq6mSg+Yl9dW LBoWHnZ751zEk+OnfGVtiAoQ/o2cZCCGyEOt+j+hzxfw/38C9JAVa4w3+TIhZYbgFjlo XWnACTbCQZsMWcUBm4Gcyg1SOl6gWQhSk8YkU82DxvSmieLzIz5RZB76ulsSNg+QZYeA iksg== X-Gm-Message-State: AKGB3mIlRoSggcOWuGzpPJg0D8vv70bsuyqvbf3n0u706HwW0Avenmy4 BnwG09jzWkFDV/89KS7vG6cdOw== X-Received: by 10.223.134.115 with SMTP id 48mr4561493wrw.213.1515070296438; Thu, 04 Jan 2018 04:51:36 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:c10d:405d:d60:60bb]) by smtp.gmail.com with ESMTPSA id d71sm3668348wma.7.2018.01.04.04.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 04 Jan 2018 04:51:35 -0800 (PST) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, benjamin.gaignard@linaro.org, Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 12/12] clocksource/drivers/stm32: Start the timer's counter sooner Date: Thu, 4 Jan 2018 13:50:28 +0100 Message-Id: <1515070228-10481-13-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> References: <1515070228-10481-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As we have a lot of timers on this platform, we can have potentially all the timers enabled in the DT, so we don't want to start the timer for every probe otherwise they will be running for nothing as only one will be used. Start the timer only when setting the mode or when the clocksource is enabled. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-stm32.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index dcf8445..4ce2345 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -101,7 +101,15 @@ static void stm32_clock_event_disable(struct timer_of *to) writel_relaxed(0, timer_of_base(to) + TIM_DIER); } -static void stm32_clock_event_enable(struct timer_of *to) +/** + * stm32_timer_start - Start the counter without event + * @to: a timer_of structure pointer + * + * Start the timer in order to have the counter reset and start + * incrementing but disable interrupt event when there is a counter + * overflow. By default, the counter direction is used as upcounter. + */ +static void stm32_timer_start(struct timer_of *to) { writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); } @@ -137,7 +145,7 @@ static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); } @@ -146,7 +154,7 @@ static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return 0; } @@ -235,6 +243,13 @@ static int __init stm32_clocksource_init(struct timer_of *to) * sched_clock. */ if (bits == 32 && !stm32_timer_cnt) { + + /* + * Start immediately the counter as we will be using + * it right after. + */ + stm32_timer_start(to); + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name);