From patchwork Thu Nov 5 17:35:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 320644 Delivered-To: patch@linaro.org Received: by 2002:a92:7b12:0:0:0:0:0 with SMTP id w18csp634226ilc; Thu, 5 Nov 2020 09:35:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJzgTiuXX1QVtcb8o/I7T3ouy+tn2rWA8eOShC9zNQgeapTjfcYI68f6JyCZpTMot28mIA2I X-Received: by 2002:aa7:c054:: with SMTP id k20mr3856790edo.224.1604597748645; Thu, 05 Nov 2020 09:35:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1604597748; cv=none; d=google.com; s=arc-20160816; b=uH1uFgzccM7B9sz8OSMQc0lGaUk2DX+UU64dyQNOxrOzn4E3mVOBGu7WkJgC5iLz77 nH7sDCi0UP4llImeyk6pyRowyVBLzBFAXsYON1eZcqHXfHwmOz8dXlH1rKnTEqY6cK38 ba5aGiwHCKv/pjsSBS5AZ11wcCEw9KnBB1bTbPBKjJgjPknzvQUn8VNDcexQ5pObmCYz zMvBudzy2sv3H69mm4qQFa0H6OsJh4/RczT+ocg7QO0i4KZPt4lHdujk9LWbJGMjNXJM r4yW0lExEGfHbYOUJhpgLN9BZV7pk8QAm/DLbbvJEcKVvAndQI7YGa3kfA0y5S5lnh2f y6Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=CTDBGsI3XNy8TqvvEs40B0Jh8hL+Y0beBfxYnNuBx6o=; b=S/brt/O+VIg5YxiJJcT1YI97xoaefhhERhtGUui8Re+7Ab/neUIWMeq2axsi/9Il5N cNaP82vUCKIi3HDgvLeYhYR6ZFSBpQcGrSZ7zZ628dDhAW1zGSY9NNJY8mrw3IJX8TmY IRNH6/FM+qdpvWa2Fr6LmliIATPr9OLDj7/urN2Td0pKHB9fMomSP42bmGDnYzHyJ3V2 81TgeqkmkhSSJ/+78lDVZ20xtd0kALXd09pL5zFnLZSyPfjoCwltLC34BX+yFsLbtKua QRhC5pCr98MzqoTCzj7hLivodbNBYyddxnHDwStK6HVSZO+0+Zw7XMTCBPZOQnpF3iZ6 MVcQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id m2si1528354eja.161.2020.11.05.09.35.48; Thu, 05 Nov 2020 09:35:48 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730854AbgKERfr (ORCPT + 6 others); Thu, 5 Nov 2020 12:35:47 -0500 Received: from foss.arm.com ([217.140.110.172]:38314 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726777AbgKERfr (ORCPT ); Thu, 5 Nov 2020 12:35:47 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF75E142F; Thu, 5 Nov 2020 09:35:46 -0800 (PST) Received: from usa.arm.com (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 79C013F719; Thu, 5 Nov 2020 09:35:45 -0800 (PST) From: Sudeep Holla To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Sudeep Holla , Rob Herring , Manivannan Sadhasivam , Hector Yuan , Viresh Kumar , Bjorn Andersson , Rob Herring Subject: [PATCH] dt-bindings: dvfs: Add support for generic performance domains Date: Thu, 5 Nov 2020 17:35:39 +0000 Message-Id: <20201105173539.1426301-1-sudeep.holla@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CLKSCREW attack [0] exposed security vulnerabilities in energy management implementations where untrusted software had direct access to clock and voltage hardware controls. In this attack, the malicious software was able to place the platform into unsafe overclocked or undervolted configurations. Such configurations then enabled the injection of predictable faults to reveal secrets. Many Arm-based systems used to or still use voltage regulator and clock frameworks in the kernel. These frameworks allow callers to independently manipulate frequency and voltage settings. Such implementations can render systems susceptible to this form of attack. Attacks such as CLKSCREW are now being mitigated by not having direct and independent control of clock and voltage in the kernel and moving that control to a trusted entity, such as the SCP firmware or secure world firmware/software which are to perform sanity checking on the requested performance levels, thereby preventing any attempted malicious programming. With the advent of such an abstraction, there is a need to replace the generic clock and regulator bindings used by such devices with a generic performance domains bindings. [0] https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/tang Cc: Rob Herring Signed-off-by: Sudeep Holla --- .../bindings/dvfs/performance-domain.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/dvfs/performance-domain.yaml -- 2.25.1 diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml new file mode 100644 index 000000000000..fa0151f63ac9 --- /dev/null +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic performance domains + +maintainers: + - Sudeep Holla + +description: |+ + This binding is intended for performance management of groups of devices or + CPUs that run in the same performance domain. Performance domains must not + be confused with power domains. A performance domain is defined by a set + of devices that always have to run at the same performance level. For a given + performance domain, there is a single point of control that affects all the + devices in the domain, making it impossible to set the performance level of + an individual device in the domain independently from other devices in + that domain. For example, a set of CPUs that share a voltage domain, and + have a common frequency control, is said to be in the same performance + domain. + + This device tree binding can be used to bind performance domain consumer + devices with their performance domains provided by performance domain + providers. A performance domain provider can be represented by any node in + the device tree and can provide one or more performance domains. A consumer + node can refer to the provider by a phandle and a set of phandle arguments + (so called performance domain specifiers) of length specified by the + \#performance-domain-cells property in the performance domain provider node. + +properties: + "#performance-domain-cells": + description: + Number of cells in a performance domain specifier. Typically 0 for nodes + representing a single performance domain and 1 for nodes providing + multiple performance domains (e.g. performance controllers), but can be + any value as specified by device tree binding documentation of particular + provider. + + performance-domains: + description: + A phandle and performance domain specifier as defined by bindings of the + performance controller/provider specified by phandle. + +required: + - "#performance-domain-cells" + +additionalProperties: true + +examples: + - | + performance: performance-controller@12340000 { + compatible = "foo,performance-controller"; + reg = <0x12340000 0x1000>; + #performance-domain-cells = <1>; + }; + + // The node above defines a performance controller that is a performance + // domain provider and expects one cell as its phandle argument. + + device1: foo@56780000 { + compatible = "foo,bar-controller"; + reg = <0x56780000 0x1000>; + performance-domains = <&performance 1>; + }; +