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[209.132.180.67]) by mx.google.com with ESMTP id i87si8424735pfi.301.2018.01.08.05.34.46; Mon, 08 Jan 2018 05:34:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bq/0Qb2U; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933515AbeAHNeo (ORCPT + 28 others); Mon, 8 Jan 2018 08:34:44 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:45442 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932384AbeAHN3Z (ORCPT ); Mon, 8 Jan 2018 08:29:25 -0500 Received: by mail-wr0-f193.google.com with SMTP id o15so10737244wrf.12 for ; Mon, 08 Jan 2018 05:29:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ehOJUyYFI8ZHB3P/xMSYNTnaMlFEBDdPatAcIxuqu5g=; b=bq/0Qb2UH742YAU+Gna0O+FKKridknq7mNeDgcJzhVRnG4GrAkEgF13yjroLtWpFl6 DUW8LeXd0KR4wIG6vKaSCSzZu7VbDM8dSliRRj/GF9eSu9zAasye2gSNMWQsrmvdp5Tj OgRpF1da3KaNBVUfua0oNp22G+jNA59F997Dw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ehOJUyYFI8ZHB3P/xMSYNTnaMlFEBDdPatAcIxuqu5g=; b=aaxMzqhR8ECqmfvNru2rNd6vf/b5rM4HU69ABUuvEQFlBfxsyl1Kg2vrDB+lq5l6go wolWgnAj3T648GehrhaMLKHED+1KhWDMzqzlBjTm25gOMEUk9zEe1egwY/s3H4LHKy2u M+va/DB3+HTnTdz7ltt+PUZXW6stOWxMkFa4GHYme8t3KnmANxpFO+U6/1XpDgodF8EJ 3ERBxOIZ8RyjseHbv7N/N636pJ+V9sUT5XbDMzp14Y9/+8B5YPKqmKtd3hH+kdDos6Xl lkVLOXHJ/JeGdxStjIqY1BvWYJXi7WE6h0qyIObcMjktMJ4sbyjqRZBViUpUIy0aO8vF EDAw== X-Gm-Message-State: AKGB3mKJfE3cszwCMR0RVMAsATqC4rqbmWscxzvhThH6SESDIJphaahH OXTSq/V+Ci1U+7enbrX/1jl11A== X-Received: by 10.223.146.69 with SMTP id 63mr3489006wrj.22.1515418164051; Mon, 08 Jan 2018 05:29:24 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:23 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , linux-arm-kernel@lists.infradead.org (moderated list:ARM/ACTIONS SEMI ARCHITECTURE) Subject: [PATCH 02/20] clocksource/drivers/owl: Adopt TIMER_OF_DECLARE() Date: Mon, 8 Jan 2018 14:28:41 +0100 Message-Id: <1515418139-23276-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andreas Färber Commit 1727339590fdb5a1ded881b540cd32121278d414 ("clocksource/drivers: Rename CLOCKSOURCE_OF_DECLARE to TIMER_OF_DECLARE") deprecated CLOCKSOURCE_OF_DECLARE(), so adopt the new macro TIMER_OF_DECLARE(). Reported-by: Daniel Lezcano Signed-off-by: Andreas Färber Signed-off-by: Daniel Lezcano --- drivers/clocksource/owl-timer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c index c686305..9fb4333 100644 --- a/drivers/clocksource/owl-timer.c +++ b/drivers/clocksource/owl-timer.c @@ -168,5 +168,5 @@ static int __init owl_timer_init(struct device_node *node) return 0; } -CLOCKSOURCE_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init); -CLOCKSOURCE_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init); +TIMER_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init); +TIMER_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init); From patchwork Mon Jan 8 13:28:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123709 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2726589qgn; Mon, 8 Jan 2018 05:29:33 -0800 (PST) X-Google-Smtp-Source: ACJfBotvCuW6Oomj6Ck7zeTCcDoemF0gt5RK2msgF5BeUODJqJPjQRQl1pVrVpf1gvOkDXJlBceW X-Received: by 10.99.104.200 with SMTP id d191mr5958592pgc.98.1515418173178; Mon, 08 Jan 2018 05:29:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418173; cv=none; d=google.com; s=arc-20160816; b=Vxjhx0vVSCKka0kyqE6jQmS1rGFYgWBLgW8GE0bMXLScJaWe0QDdtcugMfwnRk2tZ7 lqzaZ4rE9DHR5UrluKbaif91Vgqvt5bgfUdSpOBCdl+MOEVBKcp2kSDnuPo5GWFkDRoM 0TH9FQdCoQBqyNps9XRisEraZeK+KPphehvwSbvSJKsD9L7Ho/cNIdear6q4dlLnoJ+B d078SgC85nEln/PXoI89+feAu4Zt6wTgohnYKP+mQUDNt7WdJji//uwOSyDZH67/uxvn 3lUPiR6h99UfeSsJjD4LmWaGAJPSKePTpTWiud6qxBDY6pfqN2+7rsweSgLKRRiHNwRT Jo3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=7BcWhLeByVsA9ctBJ4KTDGX0WrTdtg2NFU0tTyKcYqo=; b=NoH87y0SFgOhMlNMiOEAHJyF6ylDE4G4gEAAKeQ4VZAcrY1bsAuLt8VxGdB+ZYg/A/ lPTAaTtmxD9DhFxTFrchw+gBu15N1ujTGozTfJDq8HJXFnYvI8O0RIgiSNdGvA3I5wLD ReTXEmj2TqDymdIO3enTL868TgqHRww35JThnILLCHgne18SJUH1IOFiYUkuRxGbMpBy bmVpqHAn4+Oxvjq276pzKY6nrNqfVJ+/UvFi3OjrrM41diRTWHHNIl6Luan9yG88eS5W 53foXLQgrljAkfF6Ggp+apizZjRR5tKFENMNWwoiHafkdLWZeAids1ZrCafBBdPJZs2u ogZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RExLNHia; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Andreas Färber Signed-off-by: Daniel Lezcano --- drivers/clocksource/owl-timer.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.4 diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c index 9fb4333..ea00a5e 100644 --- a/drivers/clocksource/owl-timer.c +++ b/drivers/clocksource/owl-timer.c @@ -169,4 +169,5 @@ static int __init owl_timer_init(struct device_node *node) return 0; } TIMER_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init); +TIMER_OF_DECLARE(owl_s700, "actions,s700-timer", owl_timer_init); TIMER_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init); From patchwork Mon Jan 8 13:28:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123726 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2732452qgn; Mon, 8 Jan 2018 05:34:22 -0800 (PST) X-Google-Smtp-Source: ACJfBotrzWqF2gfs6M6ntQRgDy0gNWDGeTm3MQ80pyjBnOA5kASKEOwqLWN7lpIYsxegjIwe2xnT X-Received: by 10.101.81.7 with SMTP id f7mr9479441pgq.443.1515418462541; Mon, 08 Jan 2018 05:34:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418462; cv=none; d=google.com; s=arc-20160816; b=PK8AgZ28sRl+iaGjpy7CwQ9mBPp4bE6MBRbpQ8QHJB949DLBrwdW1aIyt/l5S+GL12 JJduy7OYOIr2uqz5DRSfnXfY/d22UNG/4WsNEum18kqvH/Icj5DComqJtAlgUjaOPUSs A5Iyi6wfNQZJNYGNNwyz+gzDZoz1pITTsKjICpxdvyuRyVJmJuLaNNpmy3O94AlSvP/6 g9TiFt40qT4Bp9n9ghHpHtKBvZrIBTx8IHMo1i8OcTd9sH6r4IHWU04ooT+izn0LsxSO 1/4YL5sOK/fEYcuSfazVKJFSki3oEAVl7H6hC3vKvtf6q0EUUlvcto4BiCmyujajE7YI idpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nS1WftPS2VO8reepCIodpX2vqtSPaUVOgmti5xMpgxg=; b=KhpjdtnFWRrnq9XRMGcXUe9qI+zR6qQ89Qe89VBxI8WkeboWoQ06AjMD2VknQ1YLNs hgM6kKci3ZHvl14bpCsgWFYIoBWhFujTI95id0imZJp7CXBFiYzOJ0fejG9u/o+ptB/I OOlJQ/L+4gKUrkSwXMdBrIX/2yhk82D/P/uhDW1XFOzt94ZEyzRi9xgwZu/9+inFdQ7A 2oZcSJAOUbyGxoBCMhQL6sGyFFy6XtURdOwWoxVm3bGAECs6g8IR8dCnTuY3zChOWNsZ p2G6AgsHBtxhib5xq1HfQwWhqrJ0u3I/jlX9bj/lV1Rx7bWo2SkADfCrDj0Vmd5ZTFsc oHjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NwbmV4bF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l1si8389004pff.236.2018.01.08.05.34.22; Mon, 08 Jan 2018 05:34:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NwbmV4bF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933493AbeAHNeU (ORCPT + 28 others); Mon, 8 Jan 2018 08:34:20 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36406 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932692AbeAHN32 (ORCPT ); Mon, 8 Jan 2018 08:29:28 -0500 Received: by mail-wm0-f67.google.com with SMTP id b76so14338692wmg.1 for ; Mon, 08 Jan 2018 05:29:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nS1WftPS2VO8reepCIodpX2vqtSPaUVOgmti5xMpgxg=; b=NwbmV4bFOFaA6ulIBkGsTKgNrafsukMyOwyDgM9slfvyNjSUwLJh0OA6+AaZAaQpAd 5Mwj4watYfHfyoTSwgA0OUzvHb9h1g2XdB9d7/LWgUG+kwUD2CrRHslDp7Ek172i1I9k xWHDVXq2Fre9DG2eVkaJD8yIviIakJ85HbRA0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nS1WftPS2VO8reepCIodpX2vqtSPaUVOgmti5xMpgxg=; b=j7IqG/lNOiNByrCHub7wXvpcPKQKnwmjPopG4DQ2wMY9NuqNnQa/iiK2q7pwfCgB36 /7eHta3thi6NIC8OE7dBCU2AdNVKTCuo/YTekgS8Zds6HMqzS1wKwoTj591rmmFSEiYU Rs5KIQUhl+auYSIydcLKQ5COxjJbXHlxHqpRFzxp3NF9QP/mlO/zjeaIvT18cSuWdrY2 CxXS9J82y9hIg1HH7vsx4TekYn1IG+zsIL6q3L9Q6ygDKcjnCqDXALcixBIZ7LxTkaW7 CpjSea5+sKYRh4XSD8VvcmFcqSt+RCg8xlV4seVK1tsmnyje7LspxTze0oZK/r1mE00d GVig== X-Gm-Message-State: AKGB3mKgy8XlrNmuykJdpdJBxWQXsPHCg0k8YH6NF4iI7wvC64FXT/Mr YrC8sEW7hhEeSKOx4qoFKSLwP9MEj90= X-Received: by 10.28.145.67 with SMTP id t64mr9282121wmd.83.1515418167165; Mon, 08 Jan 2018 05:29:27 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:26 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Romain Izard , Nicolas Ferre , linux-arm-kernel@lists.infradead.org (moderated list:ATMEL Timer Counter (TC) AND CLOCKSOURCE DRIVERS) Subject: [PATCH 04/20] clocksource/drivers/tcb_clksrc: Fix clock speed message Date: Mon, 8 Jan 2018 14:28:43 +0100 Message-Id: <1515418139-23276-4-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Romain Izard The clock speed displayed at boot in an information message was 500 kHz too high compared to its real value. As the value is not used anywhere, there is no functional impact. Fix the rounding formula to display the correct value. Signed-off-by: Romain Izard Acked-by: Nicolas Ferre Signed-off-by: Daniel Lezcano --- drivers/clocksource/tcb_clksrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 9de47d4..43f4d5c 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -384,7 +384,7 @@ static int __init tcb_clksrc_init(void) printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK, divided_rate / 1000000, - ((divided_rate + 500000) % 1000000) / 1000); + ((divided_rate % 1000000) + 500) / 1000); if (tc->tcb_config && tc->tcb_config->counter_width == 32) { /* use apropriate function to read 32 bit counter */ From patchwork Mon Jan 8 13:28:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123710 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2726773qgn; Mon, 8 Jan 2018 05:29:41 -0800 (PST) X-Google-Smtp-Source: ACJfBou+bO7F2lDwn7gPmA+bli6Ulq/yPt0n5x91loVYVqq8lX+KRyoYvxHYMvrxdlu6vkEGZMnx X-Received: by 10.99.116.19 with SMTP id p19mr9378539pgc.143.1515418180996; Mon, 08 Jan 2018 05:29:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418180; cv=none; d=google.com; s=arc-20160816; b=SIY/khSxDd1dRGyDa2kc0PQDyI8uetg8yDg+2kkgSw3H3ZaLMa52FDTaNBIcQWoNEQ n8P8P4ebMShnOzUtA1l/GGuqZTeVv1OUb7CGRTfcx94WMFJW+6Ilef66NZYYho5aTZbh AwBadzScIwED/oC2LqYP5RUv9VqOV8Xq7ayxWJxIRKfvBOE7PS5mBIq2Ax8xRwGs18KO ehicKDJRoW4JWxwKLuGAaSzs6HGXndVYITANELdy/Ty4UlJBqD2HO5nFW5BebZ1U7OTt fCHRvzlfjLzaJwEhXKoIQaSOHft9m+YNSM5kYbEO/Bzw2U3q/OScmQ6q2RzXAW/3JOVG JuoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=IVQaqwbxR1fDeDz1QidnqgoKkiNpgkC+wjXwfvimFDM=; b=Ia0Ml+7a3heXmjy96OFbVAptXbIVFl9e5IrsFoI59a6MlWc67OW6ic1hGgsw81G2Js uRxcf0y+YGSKqIunugTm7Aq9GAoadj0FdCTMG98NeWrX1/lnC+o/q6EMkGssC8RrA10v Lsu9SqhSWGY8BU0SBseqVoLBEbXLnx7sC8iiSze9j9prRNTberQxWsaOQWSUgKQEASxk FYMPkzOtQyCPwyEZkeG7rY2IM9cHFzNYFlQ2dMJBysiSfLdnc3yC8hS321t66nFCNvP4 w5EQ+1PFzRZHTuiLUUzCUluHADLU7zdYpp3LCHhJMwMDRdRhRdbdCh8RXuzD6hZWf4MV IUcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rh1LHXxo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e10si8363767pfi.337.2018.01.08.05.29.40; Mon, 08 Jan 2018 05:29:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rh1LHXxo; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933331AbeAHN3i (ORCPT + 28 others); Mon, 8 Jan 2018 08:29:38 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:41776 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932921AbeAHN3a (ORCPT ); Mon, 8 Jan 2018 08:29:30 -0500 Received: by mail-wm0-f66.google.com with SMTP id g75so14218503wme.0 for ; Mon, 08 Jan 2018 05:29:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IVQaqwbxR1fDeDz1QidnqgoKkiNpgkC+wjXwfvimFDM=; b=Rh1LHXxolU6MHcn4k1XQwwG8+XbCaepUfTS4EjIzZTQv9k+/eEl5nJoTMIpxYwmxYu IDxRxFhHEyPdHjoJ9giGbjp+FBXzs41FyDmlJDrUCuC8S7d/OFQWONdE4wFf0bH+qmj+ He7CMLf7wPw5djtfmYnkWTdeoI4BFj148rnk4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IVQaqwbxR1fDeDz1QidnqgoKkiNpgkC+wjXwfvimFDM=; b=qG6c1Ei/sTYWJHhn5WIM155fIqSY2pWWllnJigJsZHGXV7k+CPTyEcHoWmon+bRiy2 t8uVGYIFDiI9gu4iQYFgu+goQr171iEZ9RRlyyKkyAHGfUp0mskD/C2K5ljWC+PRPj3A iPQ6n1GmmeeeFSu45Zgw7K/bUEm9S0QPf4nsjb+UHBre4VGbUumvvw8d9w68CQ/VlfSv gteLYjBs1ATpN06nkP8yjOGC7RGgjnlGSWxG1ADexgbCP8rqLD8/mzhfP0qEihJmjt6c HvFro30SIl2/0VLbl4rByxwhAUCEQ/wL07l92HYEasC5rM88P1UysRCOWDbJ57LfrVZz TWpA== X-Gm-Message-State: AKGB3mIn7QdqjFeVV95zleb5aU4kYHg2WtGxdGeUVR6P86u7GU6SEMUk 6tga9nWjmyNGIQ/lqi6gbuz5qQ== X-Received: by 10.28.235.10 with SMTP id j10mr8435358wmh.54.1515418168818; Mon, 08 Jan 2018 05:29:28 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:28 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 05/20] clocksource/drivers/timer-of: Fix function names Date: Mon, 8 Jan 2018 14:28:44 +0100 Message-Id: <1515418139-23276-5-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All the functions are not prefixed with 'timer_of_', fix the naming in order to have the code consistent. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-of.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index a319904..ad55654 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -24,7 +24,7 @@ #include "timer-of.h" -static __init void timer_irq_exit(struct of_timer_irq *of_irq) +static __init void timer_of_irq_exit(struct of_timer_irq *of_irq) { struct timer_of *to = container_of(of_irq, struct timer_of, of_irq); @@ -34,8 +34,8 @@ static __init void timer_irq_exit(struct of_timer_irq *of_irq) free_irq(of_irq->irq, clkevt); } -static __init int timer_irq_init(struct device_node *np, - struct of_timer_irq *of_irq) +static __init int timer_of_irq_init(struct device_node *np, + struct of_timer_irq *of_irq) { int ret; struct timer_of *to = container_of(of_irq, struct timer_of, of_irq); @@ -72,15 +72,15 @@ static __init int timer_irq_init(struct device_node *np, return 0; } -static __init void timer_clk_exit(struct of_timer_clk *of_clk) +static __init void timer_of_clk_exit(struct of_timer_clk *of_clk) { of_clk->rate = 0; clk_disable_unprepare(of_clk->clk); clk_put(of_clk->clk); } -static __init int timer_clk_init(struct device_node *np, - struct of_timer_clk *of_clk) +static __init int timer_of_clk_init(struct device_node *np, + struct of_timer_clk *of_clk) { int ret; @@ -116,13 +116,13 @@ static __init int timer_clk_init(struct device_node *np, goto out; } -static __init void timer_base_exit(struct of_timer_base *of_base) +static __init void timer_of_base_exit(struct of_timer_base *of_base) { iounmap(of_base->base); } -static __init int timer_base_init(struct device_node *np, - struct of_timer_base *of_base) +static __init int timer_of_base_init(struct device_node *np, + struct of_timer_base *of_base) { const char *name = of_base->name ? of_base->name : np->full_name; @@ -141,21 +141,21 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) int flags = 0; if (to->flags & TIMER_OF_BASE) { - ret = timer_base_init(np, &to->of_base); + ret = timer_of_base_init(np, &to->of_base); if (ret) goto out_fail; flags |= TIMER_OF_BASE; } if (to->flags & TIMER_OF_CLOCK) { - ret = timer_clk_init(np, &to->of_clk); + ret = timer_of_clk_init(np, &to->of_clk); if (ret) goto out_fail; flags |= TIMER_OF_CLOCK; } if (to->flags & TIMER_OF_IRQ) { - ret = timer_irq_init(np, &to->of_irq); + ret = timer_of_irq_init(np, &to->of_irq); if (ret) goto out_fail; flags |= TIMER_OF_IRQ; @@ -167,13 +167,13 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) out_fail: if (flags & TIMER_OF_IRQ) - timer_irq_exit(&to->of_irq); + timer_of_irq_exit(&to->of_irq); if (flags & TIMER_OF_CLOCK) - timer_clk_exit(&to->of_clk); + timer_of_clk_exit(&to->of_clk); if (flags & TIMER_OF_BASE) - timer_base_exit(&to->of_base); + timer_of_base_exit(&to->of_base); return ret; } @@ -187,11 +187,11 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) void __init timer_of_cleanup(struct timer_of *to) { if (to->flags & TIMER_OF_IRQ) - timer_irq_exit(&to->of_irq); + timer_of_irq_exit(&to->of_irq); if (to->flags & TIMER_OF_CLOCK) - timer_clk_exit(&to->of_clk); + timer_of_clk_exit(&to->of_clk); if (to->flags & TIMER_OF_BASE) - timer_base_exit(&to->of_base); + timer_of_base_exit(&to->of_base); } From patchwork Mon Jan 8 13:28:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123724 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2731684qgn; Mon, 8 Jan 2018 05:33:40 -0800 (PST) X-Google-Smtp-Source: ACJfBots+6kzY+Fx6jxRFBeGA5c6Y/bxaBNFgSt/fbwPhvCUWlX07juyRD0Ytx/q54S36YAuD1WQ X-Received: by 10.99.97.9 with SMTP id v9mr3642562pgb.412.1515418419908; Mon, 08 Jan 2018 05:33:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418419; cv=none; d=google.com; s=arc-20160816; b=iMI8IGX5Y6jC/JhedV3qH/tYhwCmZory3DnkmlaznPWzQ5n8iOnqnh6Qr0ZkDZXOom mGQdomtiz6wWKJGAXWfrdfSOPw31pGDMx2PaBTU0aHjjKzmTnpm3ayCQEaKsFnJCo1KN beKLP5HFvtWshu4SJneL26Jgjbh2aGRNlbvUDMBClNPllV6+/SSL9wGHBLGlsCK2su77 Pfg3GmjPbzV5IKyVvkwJQxWy0Xeyp5hqj9zkIXfdaNy4czyZRlBNXrKnDUk96xeTWZ06 65B5GxyfIKPh3ytlNOMTr2WNEvNFWVc6cazfW6Pg+D78sGSEL5LKAwHACE17pAIslR7n SaTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=dSB+IkOqYpOGOVJihNnHQgBmEZMvmwiwduTzEz9K0SU=; b=Yf1xYWKoFcKj/XbT9l5x78CyNWaYfwpREhR70WY4zS/fnR8chdPRNEmG65ju9DWGOG ultJTbDkG5QErDaN9YHTidpakRwSl/+DqtlaBigDrkknS8HVYozshAlJpyEIiRJ9oIwV LGAP5ApcLk+IiIVorkbh2hkPfUh4yjmGlBy4cuGX73JM0INNmRVzNTIqqNGSQ6JDJs0b ENeBTfKrKY21fG9L51VE19dCmnxlOJ0+tToKAm/ZTZrYRV41oZ6p/W64uGW5CWEX2R0e PeY2o6qWgb7YjSyPfBq9aWzu2QuXKulaiLUuyb7mghNRxugZbICMDkdaHD68k1Adfxfm onfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RXY9Rgy9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fix this by adding a kernel doc format for the function description. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-of.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index ad55654..2af8b8a 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -24,6 +24,12 @@ #include "timer-of.h" +/** + * timer_of_irq_exit - Release the interrupt + * @of_irq: an of_timer_irq structure pointer + * + * Free the irq resource + */ static __init void timer_of_irq_exit(struct of_timer_irq *of_irq) { struct timer_of *to = container_of(of_irq, struct timer_of, of_irq); @@ -34,6 +40,22 @@ static __init void timer_of_irq_exit(struct of_timer_irq *of_irq) free_irq(of_irq->irq, clkevt); } +/** + * timer_of_irq_init - Request the interrupt + * @np: a device tree node pointer + * @of_irq: an of_timer_irq structure pointer + * + * Get the interrupt number from the DT from its definition and + * request it. The interrupt is get by fallbacking as follow: + * + * - Get interrupt number by name + * - Get interrupt number by index + * + * When the interrupt is per cpu, 'request_percpu_irq' is called + * otherwise, 'request_irq' is used. + * + * Returns 0 on success, < 0 otherwise + */ static __init int timer_of_irq_init(struct device_node *np, struct of_timer_irq *of_irq) { @@ -72,6 +94,13 @@ static __init int timer_of_irq_init(struct device_node *np, return 0; } +/** + * timer_of_clk_exit - Release the clock resources + * @of_clk: a of_timer_clk structure pointer + * + * Disables and release the refcount on the clk + * + */ static __init void timer_of_clk_exit(struct of_timer_clk *of_clk) { of_clk->rate = 0; @@ -79,6 +108,15 @@ static __init void timer_of_clk_exit(struct of_timer_clk *of_clk) clk_put(of_clk->clk); } +/** + * timer_of_clk_init - Initialize the clock resources + * @np: a device tree node pointer + * @of_clk: a of_timer_clk structure pointer + * + * Get the clock by name or by index, enables it and get the rate + * + * Returns 0 on success, < 0 otherwise + */ static __init int timer_of_clk_init(struct device_node *np, struct of_timer_clk *of_clk) { From patchwork Mon Jan 8 13:28:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123723 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2731232qgn; Mon, 8 Jan 2018 05:33:16 -0800 (PST) X-Google-Smtp-Source: ACJfBovKyf0yMOHEx3TfKfJQa2wOKJN0puenn9BoSJ0Vh40SSqm5q2iKSimUI/PslfoBFoZdQ1iX X-Received: by 10.98.15.203 with SMTP id 72mr10781437pfp.104.1515418395924; Mon, 08 Jan 2018 05:33:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418395; cv=none; d=google.com; s=arc-20160816; b=e/vACr4sVJBB6UWdsrA5GeIhpSR7RMDWvzm/INbEW8Cw6GZMHesnwOgwlwvpzrMJfl VnuMRk761EdoZiiQOPC8a/04ZA6yP493+y8QxFCK9yH9Jn0S6ASWbBcOGres+kF/lmD/ pOloBN6GkRoKkvaz87wvGuQWqfHxkrOSuRXqWkLzL3ehZ8b4ArBBhzwG1udMArvoyXj9 As1pRIJogPuMkZdkZ3bJuL0Ww36doAfurEoqer7XnfDP7QweEuG3L0BA3bc7lVt3toZ6 1jRHu71yIn0wgMVLNJe3hUVcl2/IMxWyn5khRthP5MCazIqiHmBRY9eMOQwa8gk1BsNa GOGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=KtKnQtNbgW+IKfNTkd60KftUovM7POKqMLM8kupjL9k=; b=eKllmVlxcltzITMWU3vNQ3tBAxDR/5pvjahKh5nIsue4oD4giIqkFnkgTICJ+t/C6l q7NIy15U4MQD31KlkB4L6/+gMcusdG5uxEOZ7nDg81Z7vP2shoZuMLk9HW6P1U5mPx2f 1Nbw+0dJJy3+kt0oLf37jz6Q1ST6/tw+clMyeGkr0yjc8O+RfhlJFQUYoHZBExzf19vB Zyy8IxUPWDPW2Z6cyRVE4UlNPD93mblmBd+6msqCPn5pSgtVgXrJfUYuA4OMXny9iJ6s PLx+RzAS1tRsZ1+bAecnlSShYYzvsw58yE3lZlEJRbEUZMfFInDIfrmTFMrGp7pYkvxL LBFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YZ3TCxA5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The Spreadtrum timer can support 32bit or 64bit counter, as well as supporting period mode or one-shot mode. Signed-off-by: Baolin Wang Acked-by: Philippe Ombredanne Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 7 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-sprd.c | 159 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 drivers/clocksource/timer-sprd.c -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index c729a88..9a6b087 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -441,6 +441,13 @@ config MTK_TIMER help Support for Mediatek timer driver. +config SPRD_TIMER + bool "Spreadtrum timer driver" if COMPILE_TEST + depends on HAS_IOMEM + select TIMER_OF + help + Enables the support for the Spreadtrum timer driver. + config SYS_SUPPORTS_SH_MTU2 bool diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 72711f1..d6dec44 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += owl-timer.o +obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/timer-sprd.c b/drivers/clocksource/timer-sprd.c new file mode 100644 index 0000000..ef9ebea --- /dev/null +++ b/drivers/clocksource/timer-sprd.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Spreadtrum Communications Inc. + */ + +#include +#include + +#include "timer-of.h" + +#define TIMER_NAME "sprd_timer" + +#define TIMER_LOAD_LO 0x0 +#define TIMER_LOAD_HI 0x4 +#define TIMER_VALUE_LO 0x8 +#define TIMER_VALUE_HI 0xc + +#define TIMER_CTL 0x10 +#define TIMER_CTL_PERIOD_MODE BIT(0) +#define TIMER_CTL_ENABLE BIT(1) +#define TIMER_CTL_64BIT_WIDTH BIT(16) + +#define TIMER_INT 0x14 +#define TIMER_INT_EN BIT(0) +#define TIMER_INT_RAW_STS BIT(1) +#define TIMER_INT_MASK_STS BIT(2) +#define TIMER_INT_CLR BIT(3) + +#define TIMER_VALUE_SHDW_LO 0x18 +#define TIMER_VALUE_SHDW_HI 0x1c + +#define TIMER_VALUE_LO_MASK GENMASK(31, 0) + +static void sprd_timer_enable(void __iomem *base, u32 flag) +{ + u32 val = readl_relaxed(base + TIMER_CTL); + + val |= TIMER_CTL_ENABLE; + if (flag & TIMER_CTL_64BIT_WIDTH) + val |= TIMER_CTL_64BIT_WIDTH; + else + val &= ~TIMER_CTL_64BIT_WIDTH; + + if (flag & TIMER_CTL_PERIOD_MODE) + val |= TIMER_CTL_PERIOD_MODE; + else + val &= ~TIMER_CTL_PERIOD_MODE; + + writel_relaxed(val, base + TIMER_CTL); +} + +static void sprd_timer_disable(void __iomem *base) +{ + u32 val = readl_relaxed(base + TIMER_CTL); + + val &= ~TIMER_CTL_ENABLE; + writel_relaxed(val, base + TIMER_CTL); +} + +static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles) +{ + writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO); + writel_relaxed(0, base + TIMER_LOAD_HI); +} + +static void sprd_timer_enable_interrupt(void __iomem *base) +{ + writel_relaxed(TIMER_INT_EN, base + TIMER_INT); +} + +static void sprd_timer_clear_interrupt(void __iomem *base) +{ + u32 val = readl_relaxed(base + TIMER_INT); + + val |= TIMER_INT_CLR; + writel_relaxed(val, base + TIMER_INT); +} + +static int sprd_timer_set_next_event(unsigned long cycles, + struct clock_event_device *ce) +{ + struct timer_of *to = to_timer_of(ce); + + sprd_timer_disable(timer_of_base(to)); + sprd_timer_update_counter(timer_of_base(to), cycles); + sprd_timer_enable(timer_of_base(to), 0); + + return 0; +} + +static int sprd_timer_set_periodic(struct clock_event_device *ce) +{ + struct timer_of *to = to_timer_of(ce); + + sprd_timer_disable(timer_of_base(to)); + sprd_timer_update_counter(timer_of_base(to), timer_of_period(to)); + sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE); + + return 0; +} + +static int sprd_timer_shutdown(struct clock_event_device *ce) +{ + struct timer_of *to = to_timer_of(ce); + + sprd_timer_disable(timer_of_base(to)); + return 0; +} + +static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *ce = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(ce); + + sprd_timer_clear_interrupt(timer_of_base(to)); + + if (clockevent_state_oneshot(ce)) + sprd_timer_disable(timer_of_base(to)); + + ce->event_handler(ce); + return IRQ_HANDLED; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = TIMER_NAME, + .rating = 300, + .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = sprd_timer_shutdown, + .set_state_periodic = sprd_timer_set_periodic, + .set_next_event = sprd_timer_set_next_event, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .handler = sprd_timer_interrupt, + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static int __init sprd_timer_init(struct device_node *np) +{ + int ret; + + ret = timer_of_init(np, &to); + if (ret) + return ret; + + sprd_timer_enable_interrupt(timer_of_base(&to)); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + 1, UINT_MAX); + + return 0; +} + +TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init); From patchwork Mon Jan 8 13:28:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123720 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2730292qgn; Mon, 8 Jan 2018 05:32:27 -0800 (PST) X-Google-Smtp-Source: ACJfBovZonIzbPxPNSykOA5vGyFBn6ReCwL7NisFNZgY5XX31MLeCffuGB03xWPCfdNb//wVgkXV X-Received: by 10.98.155.203 with SMTP id e72mr6561108pfk.170.1515418347050; Mon, 08 Jan 2018 05:32:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418347; cv=none; d=google.com; s=arc-20160816; b=p6rjWM0+hdIOl/oWOog22Cy4/K7AMnoTv6t3aKvl8125+cy594pHIzAIqBeTop1NJu J5LpUqFvRpeXE6Hc0AP33szyubcluCYmcdM98zppKBtqB0cGCsGyzw1mFsA10OSEGBMU sqMnu01Nh0IrOQpIcUBcMztNhhmgdKMDtaowrf0fcMMTA/YhVVOVpXybsXOt9VZ3ZXYF nhQmx376ejAE4CGYSpLPnaOBGYntLJ01B/Hn/k9QPstBudYhXEcVcQJhX7piYE21IfnW 10Dt3JlXHkVUp+3VXtr1ZNK2163G6wpnbOOvIkYbUwGJVV0xSDqi0muZ2EoYKCQTrDR/ MVHw== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id l15si5731640pgs.19.2018.01.08.05.32.26; Mon, 08 Jan 2018 05:32:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZgO/oRMK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933376AbeAHN3q (ORCPT + 28 others); Mon, 8 Jan 2018 08:29:46 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:40246 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933350AbeAHN3j (ORCPT ); Mon, 8 Jan 2018 08:29:39 -0500 Received: by mail-wm0-f67.google.com with SMTP id f206so14201320wmf.5 for ; Mon, 08 Jan 2018 05:29:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s6TxSizBqumWA/Vt79xloB5Yp2mzrmWhzusNe6bUM6k=; b=ZgO/oRMKUg/0a1Fg2uETJhiEUwgNQ16GiVtGXu96bbgU9NcOGzJIt6zCug1gYmO2Rj eKS0xJ0k1udLCoySk6Sb4XV/hx3YSSswsp6cZTVSL1A8+LVm6kcBfuw/n217LVcBMBnP 1SmgcPBm2PoWYwoikiiiKNnmJ1UrHqP8W77ew= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s6TxSizBqumWA/Vt79xloB5Yp2mzrmWhzusNe6bUM6k=; b=l+FEo6Pjjagn7rW2VNySLnNeMXFutgB+xqOZGHPXC1b2bPGcQrPLa1fpMrQgehBl+Q 2/KZTV2YS5kVtgpm0To1v2ZEpA1YDJ2rPBo4svUUGi1omyUnIJx+fD3JFSpE/fXg7z6e lSmTvEHgvwI/Iq6K3wBJB9BPopGEegzapjXPbrBZI+V4y++skoxQw9ZCABLnsaXmWN34 EwPP4IU9MjZHISJqZimLP+3ezG6joIuuyLj62wi1UZmT2wxlh342SS4k8D6uc1lSGePl 4p78J5S0W7yjf9t3E6PlUqzrzVKf/aqy7zfD3On62DnhqTYmuFc7iqDegmJPkmHwgTzH jy4A== X-Gm-Message-State: AKGB3mL6Dn5XzW337JkVwlWe0ekIrU+PYWprequ209loWxlfb9ozcqmt OcKjLFpKG3h202mzw3nqcJIAtEY/WOg= X-Received: by 10.28.9.77 with SMTP id 74mr8575988wmj.107.1515418178633; Mon, 08 Jan 2018 05:29:38 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:38 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 09/20] clocksource/drivers/timer-of: Store the device node pointer Date: Mon, 8 Jan 2018 14:28:48 +0100 Message-Id: <1515418139-23276-9-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Under certain circumstances, some specific operations must be done with the device node pointer, that forces the timer code to propagate the pointer to the functions which need it. In order to consolidate the function signatures in the different drivers by using the timer-of structure, let's store it in the timer-of structure as a handy pointer when it is needed. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-of.c | 3 +++ drivers/clocksource/timer-of.h | 1 + 2 files changed, 4 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index 2af8b8a..2ae348b 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -201,6 +201,9 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to) if (!to->clkevt.name) to->clkevt.name = np->name; + + to->np = np; + return ret; out_fail: diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h index 3f708f1..a5478f3 100644 --- a/drivers/clocksource/timer-of.h +++ b/drivers/clocksource/timer-of.h @@ -33,6 +33,7 @@ struct of_timer_clk { struct timer_of { unsigned int flags; + struct device_node *np; struct clock_event_device clkevt; struct of_timer_base of_base; struct of_timer_irq of_irq; From patchwork Mon Jan 8 13:28:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123711 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2726949qgn; Mon, 8 Jan 2018 05:29:50 -0800 (PST) X-Google-Smtp-Source: ACJfBoukKkq7SF7mkRpUS2HIHPNc+DEOISSz21EjsMhUFDFy1MYWrcXiPb+y5sA40nUjrP59qsTa X-Received: by 10.84.244.2 with SMTP id g2mr6514891pll.206.1515418190576; Mon, 08 Jan 2018 05:29:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418190; cv=none; d=google.com; s=arc-20160816; b=zXQvqGAFhB67tRS/YngsDdAJScQ5rrd3LQ6TZEP5UztbiJ9KtdeadsspFTKD6whGo0 KIHldGhGjOT4elpArue8b1GHapfp63HWQLQYEXB4ODLAVSKQfKAwJV1vjWcUGj4cbTil uVsjRnwe37T9DeqOY0svWhJx+c8urKCTXxrTizyvzWWeCDC32kU/O23Yl//mCw/waUu3 g6VbROhtEh1Ae+5TDut7pjyXu1/+Kifd78rUfs+j1Q0pNZ/U5+YpXdEA1NDgSKVMopKW lzlDPLSlUqfgCVcqE/HB20XhfKH+1ENzuuV6iuBy2N1YlNr18gBxNzZOQVnFH+M9Kyga 2oNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=J9V9u5gzR2uoPykGLsgQl9f26d1ZZq2awKorbIZ53vM=; b=i2YJ6CiJU5tFB322VBzt5PiPo0JR8b/5y5rafqX/IKr2vK1Jvfl4iV2AHNehxWKpgr NPVZjekeiYgfyWs+pjneVvGO8IMr6+2TRhFx6ngVlPSC9EVJGAvmkR3NOjY3sBe8k6ql W4KzdNzd01r2ezvu0ejUnro1zJsWi8yJbPuVt3y6k0EbIKuM3RJ8/swLeBwb14oXyXkB llmo0d1N5v8wqhPlRrel3gyaDXk/On3RVWXK48GLO8s2zyf69jPOnd+pc45HDL4sZ7p5 ihUBEqvp5Aa+dPBGwx0UGKSMN5NEiMbBzwCQWQL08HjIAGQQdTPorN4sBJ8RL2sdJrNO PGwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZeNOwRti; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c16si8730673plo.46.2018.01.08.05.29.50; Mon, 08 Jan 2018 05:29:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZeNOwRti; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933391AbeAHN3s (ORCPT + 28 others); Mon, 8 Jan 2018 08:29:48 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:34311 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932821AbeAHN3l (ORCPT ); Mon, 8 Jan 2018 08:29:41 -0500 Received: by mail-wr0-f193.google.com with SMTP id 36so10742584wrh.1 for ; Mon, 08 Jan 2018 05:29:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J9V9u5gzR2uoPykGLsgQl9f26d1ZZq2awKorbIZ53vM=; b=ZeNOwRtiehLzb3jwrw51H4mBdM2Ot70pyUQCsb4iPmAPlLhwEn/G37K8E+s6Sg9SKF MdbVP+2UPTlTHVlqf9hRqpfLBHByDqGXmJOH8R3HxOf86gAPxcct606yK4E4FCQ3mRfM dxs2KE1qv2hgIU/A2B9ZPvg+pnOv3bA9qO4SI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J9V9u5gzR2uoPykGLsgQl9f26d1ZZq2awKorbIZ53vM=; b=dDcT9dO+3LLAM9Y8E7RMdkzdN9dwWjPkXK06fAFdn3XA0b+13CjPYjGDH96SqpiyfO tjS2iSLT8CDtlXGOD3oO53l45JnxB+XAqJRLo0pN31UTxNzGDcv9S7J9agqj3y15KvZh VrW+GVfES7LHH/qukUBl6PzPISYZy0xNQWwhgI2TS1tJTc7KQvHL5ww9WdvoeCdzNp4b PiyrqlKYFclF8z3maknFd78Zd+Z+sEa7Enl7Np+iNcvyYx1N2FU2WfhrmSi2OAdVTrbb +qPYm0iw4JzcfW2XGpICtBWy6TtF7MPqbUtJ+ERMxCb6UkFiTGQmGcm7fKfOEs6WdTVP TARQ== X-Gm-Message-State: AKGB3mKgymCSawn/f4AvnzdYNAathJ599chnZ/tHIoXRadAfom5FEfhT qRFBdVXNXqWtbidwwP7bKitnxQ== X-Received: by 10.223.193.11 with SMTP id r11mr3178041wre.175.1515418180128; Mon, 08 Jan 2018 05:29:40 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:39 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH 10/20] clocksource/drivers/timer-of: Don't request the resource by name Date: Mon, 8 Jan 2018 14:28:49 +0100 Message-Id: <1515418139-23276-10-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the driver does not specify a name for the resource, don't use of_io_request_and_map but of_iomap. That prevents resource name allocation conflict on some platforms which have the same name than the node. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-of.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c index 2ae348b..5aa7dcd 100644 --- a/drivers/clocksource/timer-of.c +++ b/drivers/clocksource/timer-of.c @@ -162,11 +162,11 @@ static __init void timer_of_base_exit(struct of_timer_base *of_base) static __init int timer_of_base_init(struct device_node *np, struct of_timer_base *of_base) { - const char *name = of_base->name ? of_base->name : np->full_name; - - of_base->base = of_io_request_and_map(np, of_base->index, name); + of_base->base = of_base->name ? + of_io_request_and_map(np, of_base->index, of_base->name) : + of_iomap(np, of_base->index); if (IS_ERR(of_base->base)) { - pr_err("Failed to iomap (%s)\n", name); + pr_err("Failed to iomap (%s)\n", of_base->name); return PTR_ERR(of_base->base); } From patchwork Mon Jan 8 13:28:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123722 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2730765qgn; Mon, 8 Jan 2018 05:32:52 -0800 (PST) X-Google-Smtp-Source: ACJfBosTR/OhFUgkP+fzBm0xxw6ByESEaRvrqPR4Gqn4s2djV/dQHjCOOkdGkUu7P7wWl77DzFZ4 X-Received: by 10.99.165.80 with SMTP id r16mr8963207pgu.382.1515418372847; Mon, 08 Jan 2018 05:32:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418372; cv=none; d=google.com; s=arc-20160816; b=Mdc6BndPQopFP3kKvEA4O0/HdE6MPX9yZ73Nvr1ghEr0G1RvTRbFm+Wyq63Cd8EVds tb0/18CsGb1p938VjODy0Zk5pkiNTK5U4+DsHk4AQZKMkN+kDsBS/vgEa+g972wBNMPZ 4c72dJJsSVvY1bbgvrh0U+SHXHPGbZyudKbUq4Jq1//rLKmIw+fW/ZrOMldEyia6Vbtn X40RdpiZJMvNbjkcCwmm3S1EyrM2E7I70xEWdVxsc+afXl9qt+ukLY6WsP+DQVEI7xlE SFM4VTzbHyu8ESd6TtruXTKyKEWOBhw5coCqS6j+WHdtexwMd8mPwxlokXulBle8EFMx 2GfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=dvLnzOk0r+Y0lU6cqlJZCJcFZ16TE9y1s6sJ2FFf0gA=; b=IZa032kUQ+W8TYxrpV5x/MMSXZrMqYXxiB8KPHkBnyz5s/tllGIQpEE5a8p9hYZPoJ /z7mAe532FA5E/LQi5pIiBH1UqKQT8VkM0Dv4dW47qdq1nnSk54ulyO04RwUkSZ3frYs /7aT3YO83+KaFpHTrMfRE9hSJReHRZcvt9Otsinslbv72MfSTKzoBT/OGKSK41JfiXkL LiDX+a5WQNdbVVRcl4V/N783hh9+si3R+TR007NfT3drS3ro13FLYP5ba9qHV3OZsC0Z a7dEnGjQnWB3eXMMvv4LFX4qkL/Kqx27QIKzUauPjysMLWHGhxHgHfIw39Jc8xMnspN0 rAog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TwtXvkEQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g7si7482755pgq.707.2018.01.08.05.32.52; Mon, 08 Jan 2018 05:32:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TwtXvkEQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933535AbeAHNcu (ORCPT + 28 others); Mon, 8 Jan 2018 08:32:50 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35158 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933359AbeAHN3n (ORCPT ); Mon, 8 Jan 2018 08:29:43 -0500 Received: by mail-wm0-f66.google.com with SMTP id a79so14216337wma.0 for ; Mon, 08 Jan 2018 05:29:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dvLnzOk0r+Y0lU6cqlJZCJcFZ16TE9y1s6sJ2FFf0gA=; b=TwtXvkEQGqi5WPnnafzxNJjfQs/MLqJmEfWMT/g4/LY8tYleo8k6oJVwS/h8HxXw7Y 4s/h2NLgzbDPzBX1tLUf8yOR6fd18bGq4jiAUN5iQGtX1R/giFYuTz7sqRG51i15k/lA HEjlIvhaNIpaeN1wnD38ZzDbED4Y9EKyPCXCo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dvLnzOk0r+Y0lU6cqlJZCJcFZ16TE9y1s6sJ2FFf0gA=; b=tJXOL7/Z30Pv71yfHsoq5JVn5UJbt63zZ1d07DB8rvU9xxnNtibBhcdmtulvdSZGos 07gMWVVLu6VgEDrQjuq+UL4GNGWkw48XaFs+P2lWAo8NQ2XXDwdNnENU2s9m6p2fJTox Sxim8EXMcpJ56Z0LVM3FI7bmF8CkgXKSmcIEJmv1J1MXrDffQoMvs+RmacHvRnwIcVnW u3dfUzKtRi88uYOq2Vx8SFOoCQZV4goq3KC/ApM7LEu2g2UhAsF9P3VkKtYDgv4PHiig MF+YR7wD0c/dh+cfkLnmdKbg/qStES2vzs6Du4B5+fklJ3QsrpPDKOdBz7Fm3TTv5b31 aSwg== X-Gm-Message-State: AKGB3mJOw98YHuatmUMsMi82W1bqQLLaAJoHuC9pcp31bsj+HZER7Ees zStJBOoDJvVqFSbxrVzck4ZQIQ== X-Received: by 10.28.229.194 with SMTP id c185mr8652130wmh.142.1515418181938; Mon, 08 Jan 2018 05:29:41 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:41 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, stable@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 11/20] clocksource/drivers/stm32: Fix kernel panic with multiple timers Date: Mon, 8 Jan 2018 14:28:50 +0100 Message-Id: <1515418139-23276-11-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current code hides a couple of bugs. - The global variable 'clock_event_ddata' is overwritten each time the init function is invoked. This is fixed with a kmemdup instead of assigning the global variable. That prevents a memory corruption when several timers are defined in the DT. - The clockevent's event_handler is NULL if the time framework does not select the clockevent when registering it, this is fine but the init code generates in any case an interrupt leading to dereference this NULL pointer. The stm32 timer works with shadow registers, a mechanism to cache the registers. When a change is done in one buffered register, we need to artificially generate an event to force the timer to copy the content of the register to the shadowed register. The auto-reload register (ARR) is one of the shadowed register as well as the prescaler register (PSC), so in order to force the copy, we issue an event which in turn leads to an interrupt and the NULL dereference. This is fixed by inverting two lines where we clear the status register before enabling the update event interrupt. As this kernel crash is resulting from the combination of these two bugs, the fixes are grouped into a single patch. Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 8f24237..4bfeb99 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -106,6 +106,10 @@ static int __init stm32_clockevent_init(struct device_node *np) unsigned long rate, max_delta; int irq, ret, bits, prescaler = 1; + data = kmemdup(&clock_event_ddata, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + clk = of_clk_get(np, 0); if (IS_ERR(clk)) { ret = PTR_ERR(clk); @@ -156,8 +160,8 @@ static int __init stm32_clockevent_init(struct device_node *np) writel_relaxed(prescaler - 1, data->base + TIM_PSC); writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); @@ -184,6 +188,7 @@ static int __init stm32_clockevent_init(struct device_node *np) err_clk_enable: clk_put(clk); err_clk_get: + kfree(data); return ret; } From patchwork Mon Jan 8 13:28:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123721 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2730334qgn; Mon, 8 Jan 2018 05:32:29 -0800 (PST) X-Google-Smtp-Source: ACJfBotHVzx9wwvDZvoKDUHbowh71uJ1/gyDzMnS1lzZKCYaQPkK+bTqMkYG3f+D9DLabZlM+t+C X-Received: by 10.101.65.203 with SMTP id b11mr9432727pgq.44.1515418349425; Mon, 08 Jan 2018 05:32:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418349; cv=none; d=google.com; s=arc-20160816; b=DOOyKBKnWdcaSzvDtZS2twZsMgibXg1+48P1WeZjOhPfHgvDyRFqnGh0T0qqV/w5CI WUwK6ZL0xWLCkEgPTTG3+1l9TpuqHbODT3NDYRdMH2F/hX44JDWdz7fioG/B658D1mDH Zag3nuc7QpbV/cH34fUEmfOXjFprDbGFtKq2JyWQhXKPuvZaiLCXPyZEmTMWO7uu8oJh O5es2YjhX4PbX8A9z80p+jdelXZJ4m50w6gtaQHLge9dTbnGpNYYmJmSizMAdR2cYcWY r0Mqh5qEoaCMQf2LC4JsXgQjVcJDOYjwLT0a3KuG0yWM8CVbtogv3DhJRdYAjNVEKoRE mzBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=bAqSJg6B/9mFbyWq7dzKzvOBigjafA6EQKB/6HykHxM=; b=Lbo5OhwXQXJ1Yzh48reAUtBzCk1ROrQUuQXUyDLJhw2/I7za3767ASUb3UzCt2LI3M nFQnr89X1bYEwniX4AEJ3KH4akCO/ARsle+HIXOAkB5Y7RkgI8wv4uZfwMTVAQQUpMU7 jcowZahOpf0QNHap+2o6AEM72aNfKy71qKlAQgqXsrgYNvVmtVBjB2N4WQCPRvICayB6 GzFpwTr5cvRgMNYLtt25SnuSHKa2vl5rH5UOy9VxF1lPRr/XgKDwfd4Ks2Pjr6pfwQOI /pA7fHWbu2QSWt+h1PZYq+ld+QpSSLojMm+R+woX47svBfp5f1VPq+D78/LqyUsp3+ns Io5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ca9ElJD9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This allows to remove custom proprietary structure, factors out and simplifies the code. [Daniel Lezcano] : Respin against the critical fix patch and massaged the changelog. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/Kconfig | 1 + drivers/clocksource/timer-stm32.c | 187 +++++++++++++++----------------------- 2 files changed, 74 insertions(+), 114 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 9a6b087..786db7a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -269,6 +269,7 @@ config CLKSRC_STM32 bool "Clocksource for STM32 SoCs" if !ARCH_STM32 depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST) select CLKSRC_MMIO + select TIMER_OF config CLKSRC_MPS2 bool "Clocksource for MPS2 SoCs" if COMPILE_TEST diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 4bfeb99..3e4ab07 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,9 @@ #include #include #include +#include + +#include "timer-of.h" #define TIM_CR1 0x00 #define TIM_DIER 0x0c @@ -34,162 +37,118 @@ #define TIM_EGR_UG BIT(0) -struct stm32_clock_event_ddata { - struct clock_event_device evtdev; - unsigned periodic_top; - void __iomem *base; -}; - -static int stm32_clock_event_shutdown(struct clock_event_device *evtdev) +static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(clkevt); + + writel_relaxed(0, timer_of_base(to) + TIM_CR1); - writel_relaxed(0, base + TIM_CR1); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev) +static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); - void *base = data->base; + struct timer_of *to = to_timer_of(clkevt); + + writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); + writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); - writel_relaxed(data->periodic_top, base + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); return 0; } static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *evtdev) + struct clock_event_device *clkevt) { - struct stm32_clock_event_ddata *data = - container_of(evtdev, struct stm32_clock_event_ddata, evtdev); + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, data->base + TIM_ARR); + writel_relaxed(evt, timer_of_base(to) + TIM_ARR); writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - data->base + TIM_CR1); + timer_of_base(to) + TIM_CR1); return 0; } static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) { - struct stm32_clock_event_ddata *data = dev_id; + struct clock_event_device *clkevt = (struct clock_event_device *)dev_id; + struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(0, data->base + TIM_SR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); - data->evtdev.event_handler(&data->evtdev); + clkevt->event_handler(clkevt); return IRQ_HANDLED; } -static struct stm32_clock_event_ddata clock_event_ddata = { - .evtdev = { - .name = "stm32 clockevent", - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_state_shutdown = stm32_clock_event_shutdown, - .set_state_periodic = stm32_clock_event_set_periodic, - .set_state_oneshot = stm32_clock_event_shutdown, - .tick_resume = stm32_clock_event_shutdown, - .set_next_event = stm32_clock_event_set_next_event, - .rating = 200, - }, -}; - -static int __init stm32_clockevent_init(struct device_node *np) +static void __init stm32_clockevent_init(struct timer_of *to) { - struct stm32_clock_event_ddata *data = &clock_event_ddata; - struct clk *clk; - struct reset_control *rstc; - unsigned long rate, max_delta; - int irq, ret, bits, prescaler = 1; - - data = kmemdup(&clock_event_ddata, sizeof(*data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - ret = PTR_ERR(clk); - pr_err("failed to get clock for clockevent (%d)\n", ret); - goto err_clk_get; - } - - ret = clk_prepare_enable(clk); - if (ret) { - pr_err("failed to enable timer clock for clockevent (%d)\n", - ret); - goto err_clk_enable; - } - - rate = clk_get_rate(clk); - - rstc = of_reset_control_get(np, NULL); - if (!IS_ERR(rstc)) { - reset_control_assert(rstc); - reset_control_deassert(rstc); - } - - data->base = of_iomap(np, 0); - if (!data->base) { - ret = -ENXIO; - pr_err("failed to map registers for clockevent\n"); - goto err_iomap; - } + unsigned long max_delta; + int prescaler; - irq = irq_of_parse_and_map(np, 0); - if (!irq) { - ret = -EINVAL; - pr_err("%pOF: failed to get irq.\n", np); - goto err_get_irq; - } + to->clkevt.name = "stm32_clockevent"; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, data->base + TIM_ARR); - max_delta = readl_relaxed(data->base + TIM_ARR); + writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); + max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); if (max_delta == ~0U) { prescaler = 1; - bits = 32; + to->clkevt.rating = 250; } else { prescaler = 1024; - bits = 16; + to->clkevt.rating = 100; } - writel_relaxed(0, data->base + TIM_ARR); + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, data->base + TIM_PSC); - writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); - writel_relaxed(0, data->base + TIM_SR); - writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); + writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); + writel_relaxed(0, timer_of_base(to) + TIM_SR); + writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); - data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); + /* Adjust rate and period given the prescaler value */ + to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); + to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); - clockevents_config_and_register(&data->evtdev, - DIV_ROUND_CLOSEST(rate, prescaler), - 0x1, max_delta); - - ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, - "stm32 clockevent", data); - if (ret) { - pr_err("%pOF: failed to request irq.\n", np); - goto err_get_irq; - } + clockevents_config_and_register(&to->clkevt, + timer_of_rate(to), 0x1, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - np, bits); + to->np, max_delta == UINT_MAX ? 32 : 16); +} - return ret; +static int __init stm32_timer_init(struct device_node *node) +{ + struct reset_control *rstc; + struct timer_of *to; + int ret; + + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE; + to->of_irq.handler = stm32_clock_event_handler; + + ret = timer_of_init(node, to); + if (ret) + goto err; -err_get_irq: - iounmap(data->base); -err_iomap: - clk_disable_unprepare(clk); -err_clk_enable: - clk_put(clk); -err_clk_get: - kfree(data); + rstc = of_reset_control_get(node, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); + } + + stm32_clockevent_init(to); + return 0; +err: + kfree(to); return ret; } -TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); +TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_timer_init); From patchwork Mon Jan 8 13:28:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123719 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2729927qgn; Mon, 8 Jan 2018 05:32:11 -0800 (PST) X-Google-Smtp-Source: ACJfBotf5lmF/Fac9c1Yu4/bNkUpA67hXiQEHh4z1ulINjsF6bBNcp8h6I7HGlyG04ZTWPN0W7Sc X-Received: by 10.98.38.199 with SMTP id m190mr10532539pfm.24.1515418331035; Mon, 08 Jan 2018 05:32:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418331; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id c187si8416771pfa.90.2018.01.08.05.32.10; Mon, 08 Jan 2018 05:32:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jU2MFACO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933524AbeAHNcJ (ORCPT + 28 others); Mon, 8 Jan 2018 08:32:09 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:46596 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933350AbeAHN3r (ORCPT ); Mon, 8 Jan 2018 08:29:47 -0500 Received: by mail-wr0-f194.google.com with SMTP id g21so4951774wrb.13 for ; Mon, 08 Jan 2018 05:29:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IIwRqDmquDqgK0FMDrwldHX2nmgazqM5/WnK6PktmIo=; b=jU2MFACO/TNaoqB5k85BwQfYy2C2JhjPHMBjXVZr6+fLJ21sWFGa9v120tiHNMlnvT dF1PKbodo9/KCIxB1FF4d9Cl5KOKm6kJ0AvDXArVYPj+m5KvXC9y/c++XbW0+6a1ll6F s/YOe66eg+/ILlem7h2mHdjd1xxqvFSUbdGpc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IIwRqDmquDqgK0FMDrwldHX2nmgazqM5/WnK6PktmIo=; b=h8XKbKnmdbTKGMppO2etY+a11ie8p9JZWUIAaw8ytXdmXteeTPGeSj2M6ZwsF0QX/7 045EgKEOHOeo9QdpOZAdz9oxnzfDMcC9ldaWXHgzV3sHtGu+6ZCNfTi9dBEA/H3n+QDD 1BDlnin1EMG7WNzHyefmgifP1uXFVsbELXKGbujfCf2EsucdzVdfbSZdSXx6RePsXTN+ +TGBKMTjWjWH+NKWpXBX4yCbS4d0o1aLtZwmkaKDf89q8w1ZMxsJD/MMmyVnpP7LidC1 FTjJOEAlIiuBSNSQTJH8hlsIjNZORU27PQUXRHiYGxYA3JyrB7F/UWbZ/Q+DWhawizVG TP7g== X-Gm-Message-State: AKwxytebQro9i9W/YIkN9jOYH4FrTf9Fn7WvT0eCUlQy/+FgPMnazZhM rkUgP57Zknc4asXHt8M7/gFXhdxclWM= X-Received: by 10.223.196.147 with SMTP id m19mr93385wrf.56.1515418185942; Mon, 08 Jan 2018 05:29:45 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:45 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 13/20] clocksource/drivers/stm32: Use the node name as timer name Date: Mon, 8 Jan 2018 14:28:52 +0100 Message-Id: <1515418139-23276-13-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As there are different timers on the stm32, use the node name for the timer name in order to give the indication of which timer the kernel is using. The /proc/timer_list gives all the information with the right name, otherwise we end up digging in the kernel log and /proc/interrupt to do the connection between the used timer. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 3e4ab07..14b7a2b 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -85,7 +85,7 @@ static void __init stm32_clockevent_init(struct timer_of *to) unsigned long max_delta; int prescaler; - to->clkevt.name = "stm32_clockevent"; + to->clkevt.name = to->np->full_name; to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; From patchwork Mon Jan 8 13:28:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123712 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727004qgn; Mon, 8 Jan 2018 05:29:54 -0800 (PST) X-Google-Smtp-Source: ACJfBotBjWTXmPzIabHCrMxoq7oDz930SkyJwEGxnOna0dlC2zjDBCCuVjnQ9A9kd3oURTRYKfG0 X-Received: by 10.159.207.129 with SMTP id z1mr11907010plo.18.1515418194314; Mon, 08 Jan 2018 05:29:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418194; cv=none; d=google.com; s=arc-20160816; b=Yf34D013lJTJzQslEoZDwAAPb3icF1udGRT4LtsVD8B7GjXJcAdHDaTgh9j7M31i5A gZwl3nzsE78FUIVacSCZXw5o23tfGMEpnHCQg36gY4n5CsRq5TGrnceAr/lC2RfU2/CX 0T9/MjGR9U6bZ/Ukrq5s9K+55u+uXsSpw/Fq2IQJYOy/zGZW4wP4du+1mYQPu7nBrsyR tfoLIrFA+7U+Rfvnc6zh2DSPInicRVA6o0gHMX+q8rYBTTitLv+950VMKPzlF2BkmatW HRNfAp//ZDGNcNkNH27NE2/8/XjM+8BEy9exNFaAhtPmT5QNapgpPAjLnGPuQ3GI2Yoy faYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=nDOEEh5UOozwDUN/iFWwB3KodhOX8zynnknLsAj1HYg=; b=ZWKNzK3OGVz7OfHkDHVwJ1/OjHY1h623zI2v/gpbdMNns+5VDuKA+UoIzZYQcnyyq3 CPM2kxEPBQR/uOfljqDeW3ZJ8Yx/Q8r3rBpeh3z0n5bDLXi+IFoOVIkkJ7Nnl4lrfLH5 DJ2hB2SG/qkO5v98AJ5B9EZJYbXhYPywh4JSWkS5X4z1JqXH0HCwjQ6udcpMWzAGheuO 65gGfJo3IM3HgOQ5oS0T4v5iYQWpJ4dwmoKlEkxv671+RHS3LLi4w2RyVyjo8ymHoOVJ kMJ8Vo0us81pDJRXgfe0sbSbq1lnctJHWUhGblw+TIQpd5WeYEBXPMxkdQ77+/NM13ix kTQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L7LosHk5; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 14b7a2b..862134e 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -80,9 +80,27 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +/** + * stm32_timer_width - Sort out the timer width (32/16) + * @to: a pointer to a timer-of structure + * + * Write the 32bits max value and read/return the result. If the timer + * is a 32bits width, the result will be UINT_MAX, otherwise it will + * be truncated by the 16bits register to USHRT_MAX. + * + * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a + * 16bits width. + */ +static u32 __init stm32_timer_width(struct timer_of *to) +{ + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); + + return readl_relaxed(timer_of_base(to) + TIM_ARR); +} + static void __init stm32_clockevent_init(struct timer_of *to) { - unsigned long max_delta; + u32 width = 0; int prescaler; to->clkevt.name = to->np->full_name; @@ -93,10 +111,8 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; - /* Detect whether the timer is 16 or 32 bits */ - writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { + width = stm32_timer_width(to); + if (width == UINT_MAX) { prescaler = 1; to->clkevt.rating = 250; } else { @@ -115,10 +131,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, max_delta); + timer_of_rate(to), 0x1, width); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, max_delta == UINT_MAX ? 32 : 16); + to->np, width == UINT_MAX ? 32 : 16); } static int __init stm32_timer_init(struct device_node *node) From patchwork Mon Jan 8 13:28:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123718 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2729059qgn; Mon, 8 Jan 2018 05:31:35 -0800 (PST) X-Google-Smtp-Source: ACJfBosaNqSGo0Vq4E5kHVSuCCZC0s5zuRm4cudqCPIV/MpSXdnmzRhNvqTk+ESOwiP1KWl/kB01 X-Received: by 10.99.151.81 with SMTP id d17mr9563167pgo.219.1515418295542; Mon, 08 Jan 2018 05:31:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418295; cv=none; d=google.com; s=arc-20160816; b=EuqV3ujtn5i90ITZid4jUYdjbVM5RgrgdZO80nuAT8Zk86TtOvOuXYHlzrD8ektBM4 Hx+m9dKPRjlRud2NxhWmZ2z7Vn6PR6B2KT30McoM2vgu5g7buWulE7ojriSRBk9z/his IsiFh/flLkxblO0nj2ACb/PXgKBplVjh+d1Zb1ZR6pVe0dqsIdPFSa1vhA4O7O/0fu39 z87kIqqTfDrmjBaPmKschhoVp2bUcJHHnhY227CinOHUyY6Yi26H5P7FMGKQ/NR+CKj3 LgXEX0jR43ONU9w0vrX/djUTW0LaMIgwaYdE/stvcLFmMUdXaGX4YzrAMGQo0LZ/r+0O tTig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=C2u3XKqf0LKFXaORJ7Yri2u/Iml2MgQlBrxLcnQJAR4=; b=dFzh31uk9IHrmX5bmIPjJypb3jthuuMP9M0nUcxG7hNbvLAADbdk9OxnT3e0Swr4Ni StfwXw/yixDNaCe0KYiHFokYdZrYPELoc4ZRbUFRwFlVSYnrS2Q6920cQkkdKI9du5ZD K8xeYejwX9NXyVkv/A3fVxAEHu1m/W6UWzklP9D5/MYQZtEP7EeX5ivcg94tNtkoJNvA oeqlYUOj8N7dPHfll3Ir2kAkKXcD2QMEim14PbtVEnLU14danovvpre1H1siq1qXVnjx YR+rEwLQQnqcoavrV1H6y0kxCFZN551iePeDy3WAXrXB5Pev9zSEq5J2prfJTBkAkD8r rwPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AqFnQKvx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d25si114322pfl.211.2018.01.08.05.31.35; Mon, 08 Jan 2018 05:31:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AqFnQKvx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933508AbeAHNbd (ORCPT + 28 others); Mon, 8 Jan 2018 08:31:33 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:44441 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932821AbeAHN3u (ORCPT ); Mon, 8 Jan 2018 08:29:50 -0500 Received: by mail-wm0-f68.google.com with SMTP id t8so14098588wmc.3 for ; Mon, 08 Jan 2018 05:29:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C2u3XKqf0LKFXaORJ7Yri2u/Iml2MgQlBrxLcnQJAR4=; b=AqFnQKvxKySnYo1Nz9ftr8QL6jkLvAYyPclbCKBkUZLUUmyMHogOD4RgnvB3u/zwXr crlz4qzn5y67hd6T5UY4cyec9Jt5Cp2ExD1ZXtNAKKCKWu1KixnkEMXg+SeNpWl5MGya 2GhWAqUUL+iK1zt4DDXMmlZVEaENYdrZgbwiU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C2u3XKqf0LKFXaORJ7Yri2u/Iml2MgQlBrxLcnQJAR4=; b=bh0on1iyRx/OVTz2umgq6Da/ebq8TND9p0Zx+H7p3wpdqH+Sbr4XM9Ij539sqPbw07 luuyogPe/wSPgq3fSCP84SdJKs+ge1vHMjHzhfig8OE+vNjMBnR2uAt019vhc2CKQLNp n+OvggLCuBaaCqe8OgMtRGnkQ8EjUQ3TUgsPdTAOpO8Pja+KLkj25uNQJH8qV/OhflDm 5igLYmfZbCAYBJAPQCLBrJ/6JpBHDmW6IXMf/IE/SM2pvrZ9bRQ7gTiZEz7VOnMqzUIX 182N+fi8WTGleEtX7reMTIRwie41awCx7mntgaAWqQ472vVH9u5u+TBId7b6pkmB26Nr TaDw== X-Gm-Message-State: AKGB3mK3+inciLCqLZXPCN2r1a7SpL+YGA1geP+uqM+Cs4C4KYEu0A1m UWXQK+itlRXffmzGhhfXDBCUQw== X-Received: by 10.28.149.131 with SMTP id x125mr8737221wmd.129.1515418189549; Mon, 08 Jan 2018 05:29:49 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:48 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 15/20] clocksource/drivers/stm32: Compute a prescaler value with a targeted rate Date: Mon, 8 Jan 2018 14:28:54 +0100 Message-Id: <1515418139-23276-15-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The prescaler value is arbitrarily set to 1024 without any regard to the timer frequency. For 32bits timers, there is no need to set a prescaler value as they wrap in an acceptable interval and give the opportunity to have precise timers on this platform. However, for 16bits timers a prescaler value is needed if we don't want to wrap too often per second which is unefficient and adds more and more error margin. With a targeted clock of 10MHz, the 16bits are precise enough whatever the timer frequency is as we will compute the prescaler. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 862134e..ac55896 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -37,6 +37,9 @@ #define TIM_EGR_UG BIT(0) +#define TIM_PSC_MAX USHRT_MAX +#define TIM_PSC_CLKRATE 10000 + static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); @@ -116,7 +119,14 @@ static void __init stm32_clockevent_init(struct timer_of *to) prescaler = 1; to->clkevt.rating = 250; } else { - prescaler = 1024; + prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to), + TIM_PSC_CLKRATE); + /* + * The prescaler register is an u16, the variable + * can't be greater than TIM_PSC_MAX, let's cap it in + * this case. + */ + prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; to->clkevt.rating = 100; } writel_relaxed(0, timer_of_base(to) + TIM_ARR); From patchwork Mon Jan 8 13:28:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123715 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727659qgn; Mon, 8 Jan 2018 05:30:25 -0800 (PST) X-Google-Smtp-Source: ACJfBotno/jykRexNrvzKKKPLxPLfLFybrk9aymacAqXqiXxvhwgBqoJqZEHNFWwutFE2xqDxJpg X-Received: by 10.99.97.209 with SMTP id v200mr1748232pgb.126.1515418225644; Mon, 08 Jan 2018 05:30:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418225; cv=none; d=google.com; s=arc-20160816; b=QVnhF05o7DQsVZKZENgyNFE2caoL9aCuzAvCejLSkiCGsg6AbVbX/DT+4rYoYeUndV aXr9nWYOwGfcFUWE3J+ZgyabOlfzPAWccjGC71iWJQSt6muvMKp8a4a/AClqZYZ2nYlp LDRKUdd00LkJ5oNQzWYU+Yw8U12qjvDF+oWfyFf//IGmac8Qjjlg+BM9hG1dcdQWJAnf 00KN3sD08VmeugVdLUoeQKYIupyYJm0BJAn3XTvSUJ54x1+ECP29KkHt/iayriLLE96y op3LL+nIJdvTMEgLqK5+jiCzURkFwnaN6SuXZMrGeHLkC/Cwt5s3chTIYRERuKHn/AG0 KbBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=WxW0wTXrQlL11cQloR5uFczaFJHJAFTucfu/a7Auct0=; b=jrY/ridEwqg8/w7syHU5LRXotR2y3R8PowvSIDDHSdjvO2ggwbhhJOesp8PA0dVa2h 09C6m7NoV5iGwJnxWcXOKA/cUIB0MF819lNILSmLCVot/t67BAdMErrDlK9/rZleT2r8 XO8k1ttyx84mwleYNkGF6DMiQ6WqTTzh4oSzVeZHpKGIE3aB+SPidvUTD8o225UMmGZ9 3GaqxQkqCYOZ8m914WvKmZZ1WJaGe1xzaY2BPtDyOG5oiy9DdqVbbWvvGS6tukDzBb+T acvrN0rxFC3O28ym79+JGWjPUQyHRdhN7/vNrFikO/cyRCNhsKTaf7rJki8AlFi5Zicg Rbmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UQ536CFx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w63si8403963pfd.289.2018.01.08.05.30.25; Mon, 08 Jan 2018 05:30:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UQ536CFx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933424AbeAHN36 (ORCPT + 28 others); Mon, 8 Jan 2018 08:29:58 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:38146 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933389AbeAHN3x (ORCPT ); Mon, 8 Jan 2018 08:29:53 -0500 Received: by mail-wm0-f67.google.com with SMTP id 64so14209652wme.3 for ; Mon, 08 Jan 2018 05:29:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WxW0wTXrQlL11cQloR5uFczaFJHJAFTucfu/a7Auct0=; b=UQ536CFx1KSNZwIcLAGAaAF8vgWhwaFTO7Zi/cFZoycBXhcJkugIZDnjAfh3byi9hP 75zsmzOrPInpXbWgHexOkgE02lRWFRBbbBOD9PhljG4D/vpQWwp4Nt2hyG1ZZY0tMYAu W9cPJN4jQLLgLb/QJ2rd/8CrccjvUoFsnVByM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WxW0wTXrQlL11cQloR5uFczaFJHJAFTucfu/a7Auct0=; b=bTtGL68QuGZwDfpyzfTzFR0pepNULVTEDysJ/eqi5p488K5qGkU5qyfrJ9BYKp6JrE ymnxxKjUwkintKjsJmoM/PsKI4AiDnnHyIALaW4l5ZsqRxYBjfeTbmIfEeMSa4XyGG7z wHK8fChHwyO249zY3EDOiHGyeohQRHvMJbJKVO7ZHk3+g3NOJW6JHt5B5r1+6E5kZy2c 1krj9CCODWWjSUcNAFhS04bztHFLyad9gBZj1Lj1AHCK34T5ZWp2srM7Y7JUajs7s1jA ZH7YdKCQHg6KkPQKJuYEvZKxE9sC4ZqaAhwORN6SpXu1l6vyWbvb2DFPTVzs45B/CUps m6oA== X-Gm-Message-State: AKGB3mLO98PeAOPkbS5iQpYw3SX3FUEppQyJW9Gle3WaxiS6bvmOUQU8 4tIby65PQgg+u8GCTy45mCBoAQ== X-Received: by 10.28.228.132 with SMTP id b126mr8402889wmh.18.1515418191532; Mon, 08 Jan 2018 05:29:51 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:50 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 16/20] clocksource/drivers/stm32: Add the oneshot mode Date: Mon, 8 Jan 2018 14:28:55 +0100 Message-Id: <1515418139-23276-16-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Benjamin Gaignard The stm32 timer block is able to have a counter and a comparator. Instead of using the auto-reload register for periodic event, we switch to the oneshot mode by using the comparator register. The timer is able to generate an interrupt when the counter overflows but we don't want that as this counter will be use as a clocksource in the next patches. So it is disabled by the UDIS bit of the control register. Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 56 ++++++++++++++++++++++++++++++--------- 1 file changed, 44 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index ac55896..baca42c 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -24,14 +24,18 @@ #define TIM_DIER 0x0c #define TIM_SR 0x10 #define TIM_EGR 0x14 +#define TIM_CNT 0x24 #define TIM_PSC 0x28 #define TIM_ARR 0x2c +#define TIM_CCR1 0x34 #define TIM_CR1_CEN BIT(0) +#define TIM_CR1_UDIS BIT(1) #define TIM_CR1_OPM BIT(3) #define TIM_CR1_ARPE BIT(7) #define TIM_DIER_UIE BIT(0) +#define TIM_DIER_CC1IE BIT(1) #define TIM_SR_UIF BIT(0) @@ -40,33 +44,57 @@ #define TIM_PSC_MAX USHRT_MAX #define TIM_PSC_CLKRATE 10000 +static void stm32_clock_event_disable(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + TIM_DIER); +} + +static void stm32_clock_event_enable(struct timer_of *to) +{ + writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); +} + static int stm32_clock_event_shutdown(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(0, timer_of_base(to) + TIM_CR1); + stm32_clock_event_disable(to); return 0; } -static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) +static int stm32_clock_event_set_next_event(unsigned long evt, + struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); + unsigned long now, next; + + next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt; + writel_relaxed(next, timer_of_base(to) + TIM_CCR1); + now = readl_relaxed(timer_of_base(to) + TIM_CNT); + + if ((next - now) > evt) + return -ETIME; - writel_relaxed(timer_of_period(to), timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); + writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER); return 0; } -static int stm32_clock_event_set_next_event(unsigned long evt, - struct clock_event_device *clkevt) +static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) +{ + struct timer_of *to = to_timer_of(clkevt); + + stm32_clock_event_enable(to); + + return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); +} + +static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - writel_relaxed(evt, timer_of_base(to) + TIM_ARR); - writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, - timer_of_base(to) + TIM_CR1); + stm32_clock_event_enable(to); return 0; } @@ -78,6 +106,11 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) writel_relaxed(0, timer_of_base(to) + TIM_SR); + if (clockevent_state_periodic(clkevt)) + stm32_clock_event_set_periodic(clkevt); + else + stm32_clock_event_shutdown(clkevt); + clkevt->event_handler(clkevt); return IRQ_HANDLED; @@ -108,9 +141,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) to->clkevt.name = to->np->full_name; to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_shutdown; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; to->clkevt.tick_resume = stm32_clock_event_shutdown; to->clkevt.set_next_event = stm32_clock_event_set_next_event; @@ -129,12 +163,10 @@ static void __init stm32_clockevent_init(struct timer_of *to) prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; to->clkevt.rating = 100; } - writel_relaxed(0, timer_of_base(to) + TIM_ARR); writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(0, timer_of_base(to) + TIM_SR); - writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); From patchwork Mon Jan 8 13:28:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123713 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727169qgn; Mon, 8 Jan 2018 05:30:02 -0800 (PST) X-Google-Smtp-Source: ACJfBovaxgorADg19gfyJVZPTi7bq1LKBCrwaQxMuFN8KjX9GMCqSDS+2hA3k3YE4wpmNeKgs5TI X-Received: by 10.99.106.138 with SMTP id f132mr9534746pgc.211.1515418202522; Mon, 08 Jan 2018 05:30:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418202; cv=none; d=google.com; s=arc-20160816; b=ltvKWfSI0M98lAqvkt1w6v+ItWbAwMdGtSHsudkwjVnMawEC0v9ERUAaIYd0B2iwwV 0vuWLxJdyrHTbXBXREAgKnmz98T+VIxZpqoxBMFExYLjBsFp+HmDAsRldLF31Flo6sfP rQgbBxfae6XUsSOUW6JRhE3HF3QjZdwZpRqKc4HHjt6voyxWWrRFlgDVl5LAhNC8vGel eMxfLnJdbYBtLd2MuROGi//oVWDtmOvRzmzNbKt/51326KPIV+k9jwhx+EnfZ2p2EDlz sRmsFNIEge/nfdaXNf1jW1uFxyeWyz/0XcYSF/YGQdcpSmhouz15ubrxhVmV89Xcdn4W wHKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=n3Zv50zCREws81YmzcKzEMLXghsn24WWNKl2Kh5AHH4=; b=k+lYH27dqlTeM8Hhx0gQiff0WzbKJwkSZrFwYMXY6A2kP2+hmLnHs1IgxbNZcB195U Zs3qmlawX47IgSJpm6zr4K3ZGzrV1e38Lhywm+B7NkYRa95Tfd0hRoj+HbhYqOasGfNZ cLIhs++w9i3eMNafPDqryIsbqyhJL50dHR4x5YkeARqkDp05OWctzJCLTncfmi0APgIY Xdn7+cumi5KiRpdSH+trsHYl4WS2sQ+GkjOD/iWpS35B+mp4BkjDR8leFQlEj6vozR1L Il77RuT8T1PbNEraOLEOO66MH5WGaQ6/9CPH5lhIkUB0Pus2+rp2pFa78stzGvZj8Peu XSGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HcfcEOiu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 107 +++++++++++++++++++++++++++++--------- 1 file changed, 82 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index baca42c..1891924 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -44,6 +44,42 @@ #define TIM_PSC_MAX USHRT_MAX #define TIM_PSC_CLKRATE 10000 +struct stm32_timer_private { + int bits; +}; + +/** + * stm32_timer_of_bits_set - set accessor helper + * @to: a timer_of structure pointer + * @bits: the number of bits (16 or 32) + * + * Accessor helper to set the number of bits in the timer-of private + * structure. + * + */ +static void stm32_timer_of_bits_set(struct timer_of *to, int bits) +{ + struct stm32_timer_private *pd = to->private_data; + + pd->bits = bits; +} + +/** + * stm32_timer_of_bits_get - get accessor helper + * @to: a timer_of structure pointer + * + * Accessor helper to get the number of bits in the timer-of private + * structure. + * + * Returns an integer corresponding to the number of bits. + */ +static int stm32_timer_of_bits_get(struct timer_of *to) +{ + struct stm32_timer_private *pd = to->private_data; + + return pd->bits; +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -124,35 +160,31 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) * is a 32bits width, the result will be UINT_MAX, otherwise it will * be truncated by the 16bits register to USHRT_MAX. * - * Returns UINT_MAX if the timer is 32bits width, USHRT_MAX if it is a - * 16bits width. */ -static u32 __init stm32_timer_width(struct timer_of *to) +static void __init stm32_timer_set_width(struct timer_of *to) { + u32 width; + writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR); - return readl_relaxed(timer_of_base(to) + TIM_ARR); + width = readl_relaxed(timer_of_base(to) + TIM_ARR); + + stm32_timer_of_bits_set(to, width == UINT_MAX ? 32 : 16); } -static void __init stm32_clockevent_init(struct timer_of *to) +/** + * stm32_timer_set_prescaler - Compute and set the prescaler register + * @to: a pointer to a timer-of structure + * + * Depending on the timer width, compute the prescaler to always + * target a 10MHz timer rate for the 16bits. 32bits timers are + * considered precise and long enough to not use the prescaler. + */ +static void __init stm32_timer_set_prescaler(struct timer_of *to) { - u32 width = 0; - int prescaler; + int prescaler = 1; - to->clkevt.name = to->np->full_name; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; - to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; - to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; - to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; - to->clkevt.tick_resume = stm32_clock_event_shutdown; - to->clkevt.set_next_event = stm32_clock_event_set_next_event; - - width = stm32_timer_width(to); - if (width == UINT_MAX) { - prescaler = 1; - to->clkevt.rating = 250; - } else { + if (stm32_timer_of_bits_get(to) != 32) { prescaler = DIV_ROUND_CLOSEST(timer_of_rate(to), TIM_PSC_CLKRATE); /* @@ -161,7 +193,6 @@ static void __init stm32_clockevent_init(struct timer_of *to) * this case. */ prescaler = prescaler < TIM_PSC_MAX ? prescaler : TIM_PSC_MAX; - to->clkevt.rating = 100; } writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); @@ -171,12 +202,26 @@ static void __init stm32_clockevent_init(struct timer_of *to) /* Adjust rate and period given the prescaler value */ to->of_clk.rate = DIV_ROUND_CLOSEST(to->of_clk.rate, prescaler); to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); +} + +static void __init stm32_clockevent_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); - clockevents_config_and_register(&to->clkevt, - timer_of_rate(to), 0x1, width); + to->clkevt.name = to->np->full_name; + to->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + to->clkevt.set_state_shutdown = stm32_clock_event_shutdown; + to->clkevt.set_state_periodic = stm32_clock_event_set_periodic; + to->clkevt.set_state_oneshot = stm32_clock_event_set_oneshot; + to->clkevt.tick_resume = stm32_clock_event_shutdown; + to->clkevt.set_next_event = stm32_clock_event_set_next_event; + to->clkevt.rating = bits == 32 ? 250 : 100; + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 0x1, + (1 << bits) - 1); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - to->np, width == UINT_MAX ? 32 : 16); + to->np, bits); } static int __init stm32_timer_init(struct device_node *node) @@ -196,14 +241,26 @@ static int __init stm32_timer_init(struct device_node *node) if (ret) goto err; + to->private_data = kzalloc(sizeof(struct stm32_timer_private), + GFP_KERNEL); + if (!to->private_data) + goto deinit; + rstc = of_reset_control_get(node, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); reset_control_deassert(rstc); } + stm32_timer_set_width(to); + + stm32_timer_set_prescaler(to); + stm32_clockevent_init(to); return 0; + +deinit: + timer_of_cleanup(to); err: kfree(to); return ret; From patchwork Mon Jan 8 13:28:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123717 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2728622qgn; Mon, 8 Jan 2018 05:31:13 -0800 (PST) X-Google-Smtp-Source: ACJfBos9vyGA3AHHTEXr7HsemHbw5bZRM0i3oPUvgMoOxRaJIvYCVlUcxrNX8bwVczWE2KEK53Qj X-Received: by 10.98.159.25 with SMTP id g25mr10549531pfe.39.1515418273451; Mon, 08 Jan 2018 05:31:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418273; cv=none; d=google.com; s=arc-20160816; b=LgQv73XvU46mYXGo6ZNVwe6qXspH8ZEr90nUPkKQvhUNtVGUy+CUPfxCgJYFv1gqUn IoV6L6kHMaEDjCZKmxu8Ywg6EdhfIt6/33mPTqFuOtn1HGBeAu+y3cDLTycRo56s4bqM bEsZ1A06wZVA6OVkWEhkakRS1dhCIs+XBmFdIpYRrjCp+wvH02eIDNZNCGRZVzsAPKNb 26sRi/HxKW/B7GquuxQcTZ2FYXIkdoWzJajuyLRKQRvd9ztDrk9E+FhBH5i76BC571L2 3YfP9htZtbkHg5Z7sV5scpRNuiGPdN0sybkoaW9pXF3DtbkdLVnJP4SH0TgE/+BX6JqN 16YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=zvaTTcfXtuzr1lD0vuoooMntsEE/356EFRYm5/iSR3U=; b=b/2rjszl+pptk11tabOZADJeAomJZzA0/GLEsbWV1LmAl2tviuhDRy5OnHq2NbIiMi JYO1rOvEQBrLHerAAOz61OChAl7XghSiykEw0xYMAE2S6Y87uSI3LHz+CTmTObT/CaWr PqDyrjh8zT9JCdlHnU+hA7ULrxQhmVfGFp6Q2PqumSnxD8Mj3FYhWIgEGhsik9oO53zt NFvjKA4aGEv8NAZEfqoWZg6LAZqGRpCYOH/1iuQ8JxLBXArCxQa1wKzftyp+VAwUUc69 ECM4L6KynMA3zGuamhUMqZ1klLlKBsWwkLkXRqy9qmnyCLtJ8IbT1rBpXdmCUakzYOXU A4vQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8W0dFPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Benjamin Gaignard Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 1891924..4634f4d 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "timer-of.h" @@ -80,6 +81,13 @@ static int stm32_timer_of_bits_get(struct timer_of *to) return pd->bits; } +static void __iomem *stm32_timer_cnt __read_mostly; + +static u64 notrace stm32_read_sched_clock(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -204,6 +212,31 @@ static void __init stm32_timer_set_prescaler(struct timer_of *to) to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ); } +static int __init stm32_clocksource_init(struct timer_of *to) +{ + u32 bits = stm32_timer_of_bits_get(to); + const char *name = to->np->full_name; + + /* + * This driver allows to register several timers and relies on + * the generic time framework to select the right one. + * However, nothing allows to do the same for the + * sched_clock. We are not interested in a sched_clock for the + * 16bits timers but only for the 32bits, so if no 32bits + * timer registered yet, we select this 32bits timer as a + * sched_clock. + */ + if (bits == 32 && !stm32_timer_cnt) { + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; + sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); + pr_info("%s: STM32 sched_clock registered\n", name); + } + + return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, + timer_of_rate(to), bits == 32 ? 250 : 100, + bits, clocksource_mmio_readl_up); +} + static void __init stm32_clockevent_init(struct timer_of *to) { u32 bits = stm32_timer_of_bits_get(to); @@ -256,6 +289,10 @@ static int __init stm32_timer_init(struct device_node *node) stm32_timer_set_prescaler(to); + ret = stm32_clocksource_init(to); + if (ret) + goto deinit; + stm32_clockevent_init(to); return 0; From patchwork Mon Jan 8 13:28:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123716 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727724qgn; Mon, 8 Jan 2018 05:30:28 -0800 (PST) X-Google-Smtp-Source: ACJfBoto1foT/rmqP5+9HCUJ2lg7OEww/b0SIyOavf8hrm3Cq3XETFXzhsPk+XjtFSnzNFNtwkp8 X-Received: by 10.159.205.129 with SMTP id v1mr11941091plo.31.1515418228738; Mon, 08 Jan 2018 05:30:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418228; cv=none; d=google.com; s=arc-20160816; b=raZq5ikvvUiak8v1rV7jHu/7ujwvpc/tCFukWW4rNLuKvH9gvjiVrITJDr5EEjD9GV oN5RxSIgVfr0HIU9+0FhdoLkZP0HPq+nwA11I0Dklv6JPzAvwcnMYiuH6Iq/+0M5LBFV vcy3qT6M8XLtjjWGdsDTIeDjzSYLdvSB1qIAoxAi0jxLnw0Y8LYVpWHygI+PDN4etycx rA+mFWbfbuLeiOJHJ4H0KXR3im1gQKrO90hIF/GYVKh7aUQVHwSrVj5jYXpKZafvYRUA rPABTKphE6qjtWCQvkY/v3iGopE7yZw2fGn0XRS3kCXF7X2wdBYApRFBNPhjs21FrQdi XZTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=li+kAXda59gUq6am3TC/ClLS6dgrh+RZG4z+TgzncBc=; b=lMy1Sq1LmnhpY1HID/LY2riWfdCOUGyarIheoK4YLTlyptyCVG43dorqLAF4phVw08 80QBVOWXOKOJDklekawTdDApDY3EAhr1I+ox9GDDwyg0nfh4k78u7a9n3S8yvP65YVnz 5yzuI2pTIswMUFGadZqm3nXzTcV7WEFZnr1mhRmfK2xmPp+JkzwXElgZfaGX5N88nAvz K8NiEbttMBCGdfWr/hWjCQRxch5WhgWP3RxnzqDgLLz/WUVIi/eK7ZUGkl7rkQC+TeZ9 RLjoijTsjOy7zvKNUBWXO5VwWh4mP8KadqqYRPURjRSoFJQVaNcMXNh8sgez8XqIfhHq Ao7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SjDyX058; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index 4634f4d..dcf8445 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -88,6 +89,13 @@ static u64 notrace stm32_read_sched_clock(void) return readl_relaxed(stm32_timer_cnt); } +static struct delay_timer stm32_timer_delay; + +static unsigned long stm32_read_delay(void) +{ + return readl_relaxed(stm32_timer_cnt); +} + static void stm32_clock_event_disable(struct timer_of *to) { writel_relaxed(0, timer_of_base(to) + TIM_DIER); @@ -230,6 +238,11 @@ static int __init stm32_clocksource_init(struct timer_of *to) stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name); + + stm32_timer_delay.read_current_timer = stm32_read_delay; + stm32_timer_delay.freq = timer_of_rate(to); + register_current_timer_delay(&stm32_timer_delay); + pr_info("%s: STM32 delay timer registered\n", name); } return clocksource_mmio_init(timer_of_base(to) + TIM_CNT, name, From patchwork Mon Jan 8 13:28:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 123714 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2727215qgn; Mon, 8 Jan 2018 05:30:04 -0800 (PST) X-Google-Smtp-Source: ACJfBosuFc//RrXy+0kpvv2y3MGaQmmD4eueZZ9OLMGWbPekHhXoKg4xJPc/QgWi3wIyznBMq1tM X-Received: by 10.84.217.30 with SMTP id o30mr1437103pli.155.1515418204539; Mon, 08 Jan 2018 05:30:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515418204; cv=none; d=google.com; s=arc-20160816; b=eC4cQo4xaMdAH+yOD3wlPZW42RKm1RfQffn+A64V43g+IcRnBPlT0P3B9pfNbDb4uc uAg8Ccvha5o03bKh9IAHwzT8MJ0CHIBbGxuFQY4DyRllZwygU0W0fisU7kbgMVp0Quhi 97sajTmesnTpbLtTkgNZYanuWd8v2ymDpl1KOltHhse7VFBaW73XJMQpKQ81EB/RNq3i RVEPab6NO36q0Tz5OH1NyxB2Hgp1zEHW0N3bbQUIljCSBsvEs4gBjM0z8fXKTXMGxyvh w7hZdwGzmmTSTBhHz+nEn8kr/ejN0AfHJ3LdTnaocHvTZxY8jRgxo6zNXZfPdVKT/Sf6 XQdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=m1H2f7beiH31JuAk86AoPNEnMD6CLJANQrwsbZWl3bk=; b=tJq/+wsndl5srSzMvZR6a+ou2r2UUbQNUEZSbV1ZqAwMgMtdWCLHlONAc0izQiVCOu HoAcgR4fH5EdJ8LOsoSgVJzWv2saxiPUvdDv2fcHrIqsCL07kgHKnLxKwmw71W8R5iEo jxp1KHkxh1Ii990G7kb0BACQcnjsLnSwYtQJ5ERbBKDA3TWxLs2yBVDZtdz5qvyLyw11 IS+8nntAPcQTCAAXkDIo09TJt3ythcsPs3VRSe03RK5v/QvB+QD1jW65CW23yD/n5Zwg IKMF2kqRlu5pOktOnPx/qP6OjDsK6awOhujFrEFmTHhV0SmTcRtqpnSoWOlI7jp15GVy 7Emw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GU9e0XDx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b31si8613527plb.613.2018.01.08.05.30.04; Mon, 08 Jan 2018 05:30:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GU9e0XDx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933453AbeAHNaC (ORCPT + 28 others); Mon, 8 Jan 2018 08:30:02 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:39151 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933434AbeAHNaA (ORCPT ); Mon, 8 Jan 2018 08:30:00 -0500 Received: by mail-wm0-f66.google.com with SMTP id i11so14201154wmf.4 for ; Mon, 08 Jan 2018 05:29:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m1H2f7beiH31JuAk86AoPNEnMD6CLJANQrwsbZWl3bk=; b=GU9e0XDxOWOMGnW9ZU5nWTspHyghUVoS4T2Rl1+IMVls8VGfL0sTmNtpKa5aiZ5mrL hHZRBvrIAgtFSdwJP95L3UGoK8S9iyk7I/E1lYu4epbNkWaqQvg5SDqPCe4VuiNTNbvF 5Eex1hk2DZdTj23PR6Seor1O8yjiSFq7cVGTw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m1H2f7beiH31JuAk86AoPNEnMD6CLJANQrwsbZWl3bk=; b=nrYGJiDtJ/tgqqG929IAfT7WA6155Gg8UVDgHddwSzGBNipF5wNeDSdV/GpApRVnnb 5c4ETpiJSvpx05R/pfxWnA04Sy/PbUjMnOkSBrHi+dk1nV305eqDlbYcGfxrKlf/maUj YcF4FfGZ7KB8ocP0H0VSOqxlpiukKx2K/rnexFeE34e9UtVBKWrsFN91+DnU6dU12tFz wK6bUYf+LBhsN50VYAW6CImpx5WiS9yT7EwxV4b/vZ9KspDx3Pnr99DWjMAM+1qzAreu szROypokKMmzBm+K5liTrs3q8Dq2jkUrQOSykw4Uyai662YrRo2AOQO6I8zQQKw9blUY hC9Q== X-Gm-Message-State: AKGB3mIIrfHtIwerl6wbAblwjhKDeGvV6tlumZuSrDKbQP+XVv0yiGPO JzAnFCjYV2E1w1C7GM9NLYKCXw== X-Received: by 10.28.128.83 with SMTP id b80mr10041445wmd.41.1515418199098; Mon, 08 Jan 2018 05:29:59 -0800 (PST) Received: from mai.lan ([2001:41d0:fe90:b800:312a:53a5:1bef:6622]) by smtp.gmail.com with ESMTPSA id q196sm14354222wmb.22.2018.01.08.05.29.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jan 2018 05:29:58 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Benjamin Gaignard , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org (moderated list:ARM/STM32 ARCHITECTURE) Subject: [PATCH 20/20] clocksource/drivers/stm32: Start the timer's counter sooner Date: Mon, 8 Jan 2018 14:28:59 +0100 Message-Id: <1515418139-23276-20-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> References: <1bbaef2e-4080-3f54-7db3-a8989acfd691@free.fr> <1515418139-23276-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As we have a lot of timers on this platform, we can have potentially all the timers enabled in the DT, so we don't want to start the timer for every probe otherwise they will be running for nothing as only one will be used. Start the timer only when setting the mode or when the clocksource is enabled. Signed-off-by: Daniel Lezcano Tested-by: Benjamin Gaignard Acked-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index dcf8445..4ce2345 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -101,7 +101,15 @@ static void stm32_clock_event_disable(struct timer_of *to) writel_relaxed(0, timer_of_base(to) + TIM_DIER); } -static void stm32_clock_event_enable(struct timer_of *to) +/** + * stm32_timer_start - Start the counter without event + * @to: a timer_of structure pointer + * + * Start the timer in order to have the counter reset and start + * incrementing but disable interrupt event when there is a counter + * overflow. By default, the counter direction is used as upcounter. + */ +static void stm32_timer_start(struct timer_of *to) { writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1); } @@ -137,7 +145,7 @@ static int stm32_clock_event_set_periodic(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return stm32_clock_event_set_next_event(timer_of_period(to), clkevt); } @@ -146,7 +154,7 @@ static int stm32_clock_event_set_oneshot(struct clock_event_device *clkevt) { struct timer_of *to = to_timer_of(clkevt); - stm32_clock_event_enable(to); + stm32_timer_start(to); return 0; } @@ -235,6 +243,13 @@ static int __init stm32_clocksource_init(struct timer_of *to) * sched_clock. */ if (bits == 32 && !stm32_timer_cnt) { + + /* + * Start immediately the counter as we will be using + * it right after. + */ + stm32_timer_start(to); + stm32_timer_cnt = timer_of_base(to) + TIM_CNT; sched_clock_register(stm32_read_sched_clock, bits, timer_of_rate(to)); pr_info("%s: STM32 sched_clock registered\n", name);