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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/15] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Date: Mon, 16 Nov 2020 16:08:17 +0000 Message-Id: <20201116160831.31000-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the Private Peripheral Bus range, which includes all of the memory mapped devices and registers that are part of the CPU itself, including the NVIC, systick timer, and debug and trace components like the Data Watchpoint and Trace unit (DWT). Within this large region, the range 0xe000e000 to 0xe000efff is the System Control Space (NVIC, system registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure alias. The architecture is clear that within the SCS unimplemented registers should be RES0 for privileged accesses and generate BusFault for unprivileged accesses, and we currently implement this. It is less clear about how to handle accesses to unimplemented regions of the wider PPB. Unprivileged accesses should definitely cause BusFaults (R_DQQS), but the behaviour of privileged accesses is not given as a general rule. However, the register definitions of individual registers for components like the DWT all state that they are RES0 if the relevant component is not implemented, so the simplest way to provide that is to provide RAZ/WI for the whole range for privileged accesses. (The v7M Arm ARM does say that reserved registers should be UNK/SBZP.) Expand the container MemoryRegion that the NVIC exposes so that it covers the whole PPB space. This means: * moving the address that the ARMV7M device maps it to down by 0xe000 bytes * moving the off and the offsets within the container of all the subregions forward by 0xe000 bytes * adding a new default MemoryRegion that covers the whole container at a lower priority than anything else and which provides the RAZWI/BusFault behaviour Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 1 + hw/arm/armv7m.c | 2 +- hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 12 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index bb087b23c35..33b6d8810c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -84,6 +84,7 @@ struct NVICState { MemoryRegion systickmem; MemoryRegion systick_ns_mem; MemoryRegion container; + MemoryRegion defaultmem; uint32_t num_irq; qemu_irq excpout; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8113b29f1fd..944f261dd05 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -225,7 +225,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); - memory_region_add_subregion(&s->container, 0xe000e000, + memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); for (i = 0; i < ARRAY_SIZE(s->bitband); i++) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 42b1ad59e65..9628ce876e0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2479,6 +2479,43 @@ static const MemoryRegionOps nvic_systick_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +/* + * Unassigned portions of the PPB space are RAZ/WI for privileged + * accesses, and fault for non-privileged accesses. + */ +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + *data = 0; + return MEMTX_OK; +} + +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ppb_default_ops = { + .read_with_attrs = ppb_default_read, + .write_with_attrs = ppb_default_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 1, + .valid.max_access_size = 8, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s = opaque; @@ -2675,7 +2712,6 @@ static void nvic_systick_trigger(void *opaque, int n, int level) static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s = NVIC(dev); - int regionlen; /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { @@ -2718,7 +2754,20 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) M_REG_S)); } - /* The NVIC and System Control Space (SCS) starts at 0xe000e000 + /* + * This device provides a single sysbus memory region which + * represents the whole of the "System PPB" space. This is the + * range from 0xe0000000 to 0xe00fffff and includes the NVIC, + * the System Control Space (system registers), the systick timer, + * and for CPUs with the Security extension an NS banked version + * of all of these. + * + * The default behaviour for unimplemented registers/ranges + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) + * is to RAZ/WI for privileged access and BusFault for non-privileged + * access. + * + * The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: * 0x004 - ICTR * 0x010 - 0xff - systick @@ -2741,32 +2790,39 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp) * generally code determining which banked register to use should * use attrs.secure; code determining actual behaviour of the system * should use env->v7m.secure. + * + * The container covers the whole PPB space. Within it the priority + * of overlapping regions is: + * - default region (for RAZ/WI and BusFault) : -1 + * - system register regions : 0 + * - systick : 1 + * This is because the systick device is a small block of registers + * in the middle of the other system control registers. */ - regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000; - memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); - /* The system register region goes at the bottom of the priority - * stack as it covers the whole page. - */ + memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, + "nvic-default", 0x100000); + memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1); memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); - memory_region_add_subregion(&s->container, 0, &s->sysregmem); + memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); memory_region_init_io(&s->systickmem, OBJECT(s), &nvic_systick_ops, s, "nvic_systick", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x10, + memory_region_add_subregion_overlap(&s->container, 0xe010, &s->systickmem, 1); if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); - memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem); + memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem); memory_region_init_io(&s->systick_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->systickmem, "nvic_systick_ns", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x20010, + memory_region_add_subregion_overlap(&s->container, 0x2e010, &s->systick_ns_mem, 1); } From patchwork Mon Nov 16 16:08:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324398 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3443617ils; Mon, 16 Nov 2020 08:17:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJwx5+91lRoc+9L0nNyqXIWdEF0xgHgxg2LQs/k4EA2c/lds/YYhCQYa1Tl1w7zlbwFG0oNg X-Received: by 2002:a25:3792:: with SMTP id e140mr22900248yba.277.1605543428699; Mon, 16 Nov 2020 08:17:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543428; cv=none; d=google.com; s=arc-20160816; b=Hbie60LH0a7wjQIIv3RbW1GOpsnZNdiAe4AougdR77JTW9X/9uX8As/TSa7yNBdjI6 7PzcYKNc/XQt+9sJglfHUsPnSY3Rehfgn2Nji+Zh1mwVJrRStNSZF8yLonlY8EHu62va f7MLBmbexivHFVzZVlXUdzAPJyficZZJxFK+61XjUTQZvJfmB4D5GzchVSyOhZUYyj2Q Arcb8r72aqGKyfRICbi7zTrH9hNslfmBbJVbibZVfsGOfvnfzieG9Ec3lZiLXH+EOFQi +7cHsWeaZg9yWeZoMWQedEHbbOgV3pik7o2P8sk2YR+qHZz2cr2jXAtJcV3iSD+a5Bkz 7ekA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HNHlpd9eKe0R86UXf9IfUiC/GomRktWtpFHvObtXEPY=; b=lrUjdn5wT4IdkwgleEtCFTvz1AIno/5p81AE1raj2Dya2AswZ9gNkBpaaKAvFXertQ t9VxvCQrq/FU+fu8ol5+sqCuBFBMG75x/WFxzeSiLJ+mI77ouAdG2XH9eChkv0YKP4+N T8q0+cjoATZM5uamEfXA7+IwBZ/2ZC+I/t1vaC/K/dpcYCM67ZT2f59bJd5KGYwkAOl4 Z80jngMpMO/g0pNdeEn+WOjk6MHydgSUKwJZ6BSCuxDPBPEKgQVSMhYx4IjMwkbheFdw QqX23FUsr4Iadm8Eo/+0z1mkRF0RrtfQwrLsgERxYwU9uoOhTUqAf3yTyvfPFK7Txl6D orjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=myxplUlx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/15] target/arm: Implement v8.1M PXN extension Date: Mon, 16 Nov 2020 16:08:18 +0000 Message-Id: <20201116160831.31000-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In v8.1M the PXN architecture extension adds a new PXN bit to the MPU_RLAR registers, which forbids execution of code in the region from a privileged mode. This is another feature which is just in the generic "in v8.1M" set and has no ID register field indicating its presence. Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 11b0803df72..abc470d9f17 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11754,6 +11754,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } else { uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); + bool pxn = false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } if (m_is_system_region(env, address)) { /* System space is always execute never */ @@ -11761,7 +11766,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn) { + if (*prot && !xn && !(pxn && !is_user)) { *prot |= PAGE_EXEC; } /* We don't need to look the attribute up in the MAIR0/MAIR1 From patchwork Mon Nov 16 16:08:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324397 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3442176ils; Mon, 16 Nov 2020 08:15:27 -0800 (PST) X-Google-Smtp-Source: ABdhPJx2c2b+Ci+7YKCfdW+CfH7bk6NejNYr5kodaw06ycmUhsjsKeYwfx7n672KE5D8evobf3nk X-Received: by 2002:a25:ac55:: with SMTP id r21mr18400850ybd.23.1605543327268; Mon, 16 Nov 2020 08:15:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543327; cv=none; d=google.com; s=arc-20160816; b=NK9DCMv2RXzOo54N2N3ZfhHrstM4cc34oe5UKwHoI5VTCtr5qbLi/9P7Mx5X3erKzy oGlfyFAVviyGln1X2aF0y+Cn4WgK76ofR3CMKlSW4Fymz9r1RcvqJwmGxLmJCH9eJmFE aiLbA9ujIWIGIvLXEMBv1ou2crgCq50YyLbpOGwOTv6VDOanMGA0Ad2CPTbBRNYDeru9 YXi4vCCwuc9EjeOhNmAaqYTMC/zAcqbk+vcMv3YS9GTLhG83hBoJwaTLwf/8lqYErUew ntISOa2fH6XI265VhSiDWzFd8ED6sF3YT2C+tJQkfsCDHkbF4gfJyWwtdbqt62/4VppC 3ltQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1E4/N3ngk9+sSJeoqjEEgug8EpMJh/6B7re7b8qvv04=; b=AkJXPIh7iiFFnivh0H5tc8AWyYRkkldDa6pw9SOL5Acxix0ZsIF1OJYALvU1QchJqc Ok5g/tu4YqRc5pSuALHkSAR/OpcQochiNtND5vQU2MxgfSSK2zpe/0vtnzkRF3A43rY7 /I5d4UO849oBLuQt4K5/GxmBYjBQvleDyWgS6gRWuRf+mWAOnJDI2yw2RmDIXdXarnnH QA5S9+2/HwhAyMPACPPJk6tEoizYE/HbFCLT3p+pY/nw2p1DiPx9XZAV2GH7qcOBQFnm SSm1IqkqH9iK7sVro/yWsGjq0nq9l9I21C1DIg7kcf6+YzWdEUqTAdvc1XCeZq+eAd/a aHvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Sb3nrN35; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/15] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Date: Mon, 16 Nov 2020 16:08:19 +0000 Message-Id: <20201116160831.31000-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In arm_cpu_realizefn() we check whether the board code disabled EL3 via the has_el3 CPU object property, which we create if the CPU starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in the ID_PFR1 and ID_AA64PFR0 registers. This codepath was incorrectly being taken for M-profile CPUs, which do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have the M-profile Security extension and so should have non-zero values in the ID_PFR1.Security field. Restrict the handling of the feature flag to A/R-profile cores. Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a4..40f3f798b2b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1674,7 +1674,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } } - if (!cpu->has_el3) { + if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { /* If the has_el3 CPU property is disabled then we need to disable the * feature. */ From patchwork Mon Nov 16 16:08:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324404 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4170397ejb; Mon, 16 Nov 2020 08:23:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJzN4BtPY+07ziEkvZkQAI5YFaP1706K5CubDcOlxqfP3Kvc170kBiAIjnZ6lAyIotjT80tP X-Received: by 2002:a25:32cb:: with SMTP id y194mr19185473yby.506.1605543839682; Mon, 16 Nov 2020 08:23:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543839; cv=none; d=google.com; s=arc-20160816; b=Sfyya9aF+JT+GruFeDUqgUX0Pg1MsLcOHjAv1+7b0Nxr4lrzRZA/kKJ149owsO4o6g TK7TMbfuQUeeJrZ8I1+oBF+CPnNuihuCL219WnzW9fPDbI9T7CoMqe4YHLOsmdXSra8z pjVqS75xFuchlryIKVJA/HrEcDVRFqALMTa5V47MaTnw2Pkw00CoODyTQmcee1seTuOE WWJWt6ofJwvgBFkpygWQo1Dj5Svy9gv6RoRKTUCTmg59UCWho7IaksTyXv1WRPw3cFEU urN3v3ATC3g9ZpWyXuWdssDK59A+Qh82QgEYdOGmxAqXnaOOwAS6qZfpgb0lpWCEn/aX WeRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=c5PknhEJpy0KAKZXEsCLw8GRPgWwprA9K/tNJNWAjsI=; b=oGoNWaeMGTSn58NHkhkzcfLISdp8w26rbz9aw0pig8z+hnV27qiuBrCCM9nLwuqgAN Yix/KfHR/NRKks/jCgOZ38stehnMbX8332z1pAUnRn/UYC7/0ykiqxzBBj8GkvXG7qo2 Vu1h6fC8KQAXRL+eEmnHfiw4aOLyQIKdd0QWxoZrItaMnGGhWsrUJ/sr7OxyOtYM5+Op MkjLsMYh+A3F6OQr1qek844B+mLWIP3SKvZIu3D8hZmxzjzvLXEnQArO87tUTU99P6kL 2SRsIZswfpJJWp2Dkn0B0Vu/DXugmT4xBPU+1TvP6bYQeKhkff15Ix5fkVZJ4bkumphg y4Xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=psp3789X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u106si1060183ybi.236.2020.11.16.08.23.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Nov 2020 08:23:59 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=psp3789X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kehIN-00056h-08 for patch@linaro.org; Mon, 16 Nov 2020 11:23:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1keh3c-0008QM-Qc for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:45 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:32950) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1keh3Y-0007oh-12 for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:44 -0500 Received: by mail-wr1-x42b.google.com with SMTP id u12so12052157wrt.0 for ; Mon, 16 Nov 2020 08:08:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=c5PknhEJpy0KAKZXEsCLw8GRPgWwprA9K/tNJNWAjsI=; b=psp3789X80MaTvpicYIfMY+DTGKETpjT6B19gLWo47Q3Y53NpPLCIvCa/abnN6hQHa 7fmaKpMbXljlETVfwZ4PTev9v0MEopuU1rmZROT3drUVh+5ma3EjiOIsEKnfPUvnH3Iv OQtdIuDYPQvrFmbpV2wkuhPPJEn2NBFAixFrKDZbra+uN/fmIsnLO+KcXV1iVi4OPl6M VbwsXXpQTzHMma2LK+c/cH0NkF8xVXOWKcOE3EoevRAnmFT8FT2xeEnZsGVbulYRTE4/ vfgqqrNqsPY+ukSVDZ2MHPzfXsI9900jZ57q+E0SHFkj7U3DAnZI036lNKBZQhg4Cm8/ 929Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c5PknhEJpy0KAKZXEsCLw8GRPgWwprA9K/tNJNWAjsI=; b=YMHpgx4fIM/InDxTTMaezosbku+iL81MLCcGVWC39ITeLlAX0TAi9y8hFZMqlOoF8L tl8Ps2fQ/hCKtUH6m3UI2b/1tqruEqtUpYWDJzx6BC2W9IHtUE6XbOuH0wR6Pd9ujElx /LPqDCYWRGsVdgcY4P2FErNx6mU5w/rtlLYJPwlVzmzKoTsZo/WT4zCPvjOPAEfX1+4l CMmYKV3FOH9CYkCVQxjr+po0G1w8IUl3XroSGw3H8vC/I344v3SakNcrKhogTcjPcP35 nffc+V6L4Ey2FJnHZLloGiuD0kWn06DEsVASPhDH2/FGAx1O/ZOyrvyOKwNmYRbWrvij vEjA== X-Gm-Message-State: AOAM532kJuaSJyzZ+whhqDl4M/9rlSh0ic4PJ/1XZFRW2shetB0l7RKT rEoC+CiiPkcmKerVsH5WZ+tnURxNc6cSBg== X-Received: by 2002:a05:6000:1006:: with SMTP id a6mr19788566wrx.367.1605542918422; Mon, 16 Nov 2020 08:08:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/15] target/arm: Implement VSCCLRM insn Date: Mon, 16 Nov 2020 16:08:20 +0000 Message-Id: <20201116160831.31000-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up in translate.c so it is before the #include of translate-vfp.c.inc. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 ++++ target/arm/m-nocp.decode | 8 +++- target/arm/translate.c | 18 +++---- target/arm/translate-vfp.c.inc | 86 ++++++++++++++++++++++++++++++++++ 4 files changed, 110 insertions(+), 11 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c18a9167665..806c18a499f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3555,6 +3555,15 @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0; } +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) +{ + /* + * Return true if M-profile state handling insns + * (VSCCLRM, CLRM, FPCTX access insns) are implemented + */ + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* Sadly this is encoded differently for A-profile and M-profile */ diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index 28c8ac6b94c..ccd62e8739a 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -29,13 +29,17 @@ # If the coprocessor is not present or disabled then we will generate # the NOCP exception; otherwise we let the insn through to the main decode. +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + &nocp cp { # Special cases which do not take an early NOCP: VLLDM and VLSTM VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 - # TODO: VSCCLRM (new in v8.1M) is similar: - #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + # VSCCLRM (new in v8.1M) is similar: + VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3 + VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2 NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp diff --git a/target/arm/translate.c b/target/arm/translate.c index f7d4ee393b7..4b17b2e0d46 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -100,6 +100,15 @@ void arm_translate_init(void) a64_translate_init(); } +/* Generate a label used for skipping this instruction */ +static void arm_gen_condlabel(DisasContext *s) +{ + if (!s->condjmp) { + s->condlabel = gen_new_label(); + s->condjmp = 1; + } +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -5156,15 +5165,6 @@ static void gen_srs(DisasContext *s, s->base.is_jmp = DISAS_UPDATE_EXIT; } -/* Generate a label used for skipping this instruction */ -static void arm_gen_condlabel(DisasContext *s) -{ - if (!s->condjmp) { - s->condlabel = gen_new_label(); - s->condjmp = 1; - } -} - /* Skip this instruction if the ARM condition is false */ static void arm_skip_unless(DisasContext *s, uint32_t cond) { diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index f966de5b1f8..daf39306d04 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3406,6 +3406,92 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) return true; } +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) +{ + int btmreg, topreg; + TCGv_i64 zero64; + TCGv_i32 zero32; + TCGv_i32 aspen, sfpa; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + /* Before v8.1M, fall through in decode to NOCP check */ + return false; + } + + /* Explicitly UNDEF because this takes precedence over NOCP */ + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { + unallocated_encoding(s); + return true; + } + + if (!dc_isar_feature(aa32_vfp_simd, s)) { + /* NOP if we have neither FP nor MVE */ + return true; + } + + /* + * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no + * active floating point context so we must NOP (without doing + * any lazy state preservation or the NOCP check). + */ + aspen = load_cpu_field(v7m.fpccr[M_REG_S]); + sfpa = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_subi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_or_i32(sfpa, sfpa, aspen); + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); + + if (s->fp_excp_el != 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + topreg = a->vd + a->imm - 1; + btmreg = a->vd; + + /* Convert to Sreg numbers if the insn specified in Dregs */ + if (a->size == 3) { + topreg = topreg * 2 + 1; + btmreg *= 2; + } + + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { + /* UNPREDICTABLE: we choose to undef */ + unallocated_encoding(s); + return true; + } + + /* Silently ignore requests to clear D16-D31 if they don't exist */ + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { + topreg = 31; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Zero the Sregs from btmreg to topreg inclusive. */ + zero64 = tcg_const_i64(0); + zero32 = tcg_const_i32(0); + if (btmreg & 1) { + write_neon_element32(zero32, btmreg >> 1, 1, MO_32); + btmreg++; + } + for (; btmreg + 1 <= topreg; btmreg += 2) { + write_neon_element64(zero64, btmreg >> 1, 0, MO_64); + } + if (btmreg == topreg) { + write_neon_element32(zero32, btmreg >> 1, 0, MO_32); + btmreg++; + } + assert(btmreg == topreg + 1); + /* TODO: when MVE is implemented, zero VPR here */ + return true; +} + static bool trans_NOCP(DisasContext *s, arg_nocp *a) { /* From patchwork Mon Nov 16 16:08:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324400 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3445441ils; Mon, 16 Nov 2020 08:19:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJyp6BW3wXRWy59H6FuAdlhqIsjeNA6vLiLY/Fkp8ysybkPCjsHI/2vGF4Vi4BlpT4sh8KYJ X-Received: by 2002:a25:ae14:: with SMTP id a20mr24959743ybj.43.1605543571017; Mon, 16 Nov 2020 08:19:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543571; cv=none; d=google.com; s=arc-20160816; b=lfoLzTVIrycWRNmU1Mc0dy0wCMg/8Zgs4gVY7SpULxzHR5u9Pow44rpefMUhTVQydv h/q+sCu+Cwed7kMhleImwTxZqe93p3CgrW9pfCDzByqo3QNDQLw0rBsJTrRiF3CkAm5J eyIBoecUDKquFpBSs3wqbns01TiVpN9w3sT0KVql5IY1dkwEWgy4B2RiUi9i5gVqMX8W XxQgOL4GBNRbXOx3EcX52d4BF/IF5UTUC47a34JhLzGCvvsVf3bqbG7fDBbe/y8H8RFF OxYWeU9v9UTZBNyosDEbw5QPgkQ+6/9WirUlA1zlP1UnH5JXcxXQ2byX+qtnQKHeeKu7 RrVw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id x9si18433949ybf.319.2020.11.16.08.19.30 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Nov 2020 08:19:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gzvYgcnk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kehDz-0001KP-A3 for patch@linaro.org; Mon, 16 Nov 2020 11:19:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1keh3c-0008Pm-F8 for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:44 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46211) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1keh3Z-0007pk-9U for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:44 -0500 Received: by mail-wr1-x42f.google.com with SMTP id d12so19230101wrr.13 for ; Mon, 16 Nov 2020 08:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ojq6mFjue/Cb7cv+9VNy9lJWWzr++JeLPodwO0KuPSM=; b=gzvYgcnkPF5RIQxhNjtVd3CwkJEuMoO7e2kEvyBAWvOoNA0O4Vza0DGAmcpQNIs3qS iKwcuFMeQ1iQIsVIZiidJSmFTFwRVAoj+Kl/SghcwE/epC3ADd+6QHPfAOduvUNv7wGH M3RezU5SsoOknlryQ+FPALBoInSgty1YBiHteyoFqV2aVyv7xheljWUewEsUMHuf0DZH LLnSkcO+aOI1lK40OkeRkb4l3ooyMjj2BDgggAB83BPUns5Rh3XRlUxcSRxSKmRcTuML HXzJZkkS8t448ppjADlB5h9snP/w6izVdyYE4UvT4vZHdIXjzU0YS0MqjHDMGQjhP8LT odNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ojq6mFjue/Cb7cv+9VNy9lJWWzr++JeLPodwO0KuPSM=; b=PfBJIwxVZm8k6dK9jxNCGFiYzlbSfpt6SNqGtlxs8TiFUvS2+aHFmKZ+tj3L/VwqFc 0N9tUCXjUG2jCdoibdzOBG/wXTTEiuY223pooe/ZCdzdYw1S+S9+bjc6WzD5lZlXh1Px lt4n73TDbBwfptq+6UavAMqTtn/qbXSH72jP0lypYc5OjJc5nUAI/R5Qcb5ooerrARj5 RPjoHUma9EAfjwE6P/za9BQ3c+p50ID/3/BXLpveksi5UibicF7gdx88KkIHE2hJvjHI Wn7aBKi9j9yIAv5MV9ODZJlLCe+J9DRtzVzyhXeCQMUId8LfDPSGWdm0qzS+/TLA2I6x K82Q== X-Gm-Message-State: AOAM532pNaA0OwMJdBG7yFYyrpwm0eraOFItvz/yK92qYQU94SZHQRxD 49bqp+RN8btG0vyiZFByrVmZ5fbYvEb1gQ== X-Received: by 2002:a5d:438f:: with SMTP id i15mr20325739wrq.121.1605542919794; Mon, 16 Nov 2020 08:08:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/15] target/arm: Implement CLRM instruction Date: Mon, 16 Nov 2020 16:08:21 +0000 Message-Id: <20201116160831.31000-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In v8.1M the new CLRM instruction allows zeroing an arbitrary set of the general-purpose registers and APSR. Implement this. The encoding is a subset of the LDMIA T2 encoding, using what would be Rn=0b1111 (which UNDEFs for LDMIA). Signed-off-by: Peter Maydell --- target/arm/t32.decode | 6 +++++- target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8152739b52b..59ab974c661 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +{ + # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding + CLRM 1110 1000 1001 1111 list:16 + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +} LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 &rfe !extern rn w pu diff --git a/target/arm/translate.c b/target/arm/translate.c index 4b17b2e0d46..ac8c118427f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7965,6 +7965,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 1); } +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) +{ + int i; + TCGv_i32 zero; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + return false; + } + + if (extract32(a->list, 13, 1)) { + return false; + } + + if (!a->list) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + zero = tcg_const_i32(0); + for (i = 0; i < 15; i++) { + if (extract32(a->list, i, 1)) { + /* Clear R[i] */ + tcg_gen_mov_i32(cpu_R[i], zero); + } + } + if (extract32(a->list, 15, 1)) { + /* + * Clear APSR (by calling the MSR helper with the same argument + * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) + */ + TCGv_i32 maskreg = tcg_const_i32(0xc << 8); + gen_helper_v7m_msr(cpu_env, maskreg, zero); + tcg_temp_free_i32(maskreg); + } + tcg_temp_free_i32(zero); + return true; +} + /* * Branch, branch with link */ From patchwork Mon Nov 16 16:08:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324402 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3445727ils; Mon, 16 Nov 2020 08:19:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJxFU0qKxddWd5CcfBsKjMrT3SD94V+jU3oy0B+RaHJRg2lhWByWi2x2/3VH1r28qo5UTI5q X-Received: by 2002:a25:20c3:: with SMTP id g186mr10235841ybg.475.1605543594068; Mon, 16 Nov 2020 08:19:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543594; cv=none; d=google.com; s=arc-20160816; b=nD8I3ft+9Vfdjw1OEpt5XohBNLicWgwxzPxp+JT4c0YSjQv9P5TTPeXGzF2mfx0GFQ ZqHkz7A1x2eMeZahEHF3fHwd0wiDZN/a3yUh+1tWfpttgWhmna8oxR/mO/PKk+W03zg8 IYoP06mOBay+RCvBa4kFwD94Qzh/Slb43/VTHqAwxhACQT1hPH8rVwxmqomzibh4A3jd tZQZiBw1VL92ILKPXO30PN3PKb1LaH4ZeRFWwXQ0QIRnpV8iG9mWsB5V7dY0aUm9xcuT gIQpHElWneCwbUQpRVYdK/k/cVRdzIAerhsnna+lfjuPflBnJ7S5DmjfRGP07Tv3K2Ph yHkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ndVG3Ur/YVssArwv222lKAY0FdZzdrlIXHioNrSqs3Q=; b=XDqRrK2AD/2OQ4mziJKrBu0WDA0BKb+wZkU+cV2UH7iA4GOCS8xoLFe+YbXPi2Iglm 4e6NyvHOSexZTb8BpNW6QmpTu5cXstU/X7sbD5Q6q3xTE5/yxPB8aaHfI1l6DR9/lXBV Vn5A1Yo4p0lnfQv89BlRczFNk7S204u4irhdhistF/fARNEUC5yraAl46Eih4Wz8QkJh Mpe1NnAqoac7IazqF/7au6vSi2QpfDGn15hG2FdEJWzDyEU1hnrejlBefNdeZRtWMyxy Evlr3zdz+vYwenbqoz2D4CXkE4fAvxUtlfQFSiqp58x3p6b1UjylsYH6HrmDEzZa2OCE LP7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iJB9gGn2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/15] target/arm: Enforce M-profile VMRS/VMSR register restrictions Date: Mon, 16 Nov 2020 16:08:22 +0000 Message-Id: <20201116160831.31000-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For M-profile before v8.1M, the only valid register for VMSR/VMRS is the FPSCR. We have a comment that states this, but the actual logic to forbid accesses for any other register value is missing, so we would end up with A-profile style behaviour. Add the missing check. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index daf39306d04..aee60ff98b3 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -622,7 +622,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) * Accesses to R15 are UNPREDICTABLE; we choose to undef. * (FPSCR -> r15 is a special case which writes to the PSR flags.) */ - if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) { + if (a->reg != ARM_VFP_FPSCR) { + return false; + } + if (a->rt == 15 && !a->l) { return false; } } From patchwork Mon Nov 16 16:08:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324403 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4170247ejb; Mon, 16 Nov 2020 08:23:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJx+6a9uadKlf+prX4kIkwoZRIOvLo7f5fw2TKDADuG+7XSc2frDDnGFSqHvyVqKlMeIJkXQ X-Received: by 2002:a25:9746:: with SMTP id h6mr18151435ybo.222.1605543828111; Mon, 16 Nov 2020 08:23:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543828; cv=none; d=google.com; s=arc-20160816; b=XhT3c8nDaCd1F/Iyb6ddx5yj2npQNcGaPOVn67r6Eu0sXbzNeAhpFJsGFf6Y7yiC/n qLTOACuYUtRKxg3qczk9n4N1FWbqPyO3ByCZHRkov23y4SYuuVc9kZRopXIcR3yOptro v55JaL8+NHXjvn1CyPGMJUnfF9PpFUd0oKzNdToftl3Hv4IYxhNzazNIFtC2KKRy2vk4 kvqVFILdSSZ/bPx2rQC7UxlVf5fhhr60djz6rGUffVCUD2wMSTjV3KtRN3f/0jy8zqZe QEcqLryvMW6umI+dht7419unJvdpwyQPFt8e1WD6TM9w926Jprd9Nmnq1MZjm/ZlF9p+ SeAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=nnPwlADakN+vC7KEmeazFxm2/dI86B7xYLVrWaaPTLY=; b=ne5aP35yax2qYlRgH5NLV7uQ5CXScazZ8TpQgxQD7q9zLMPKhAO222YtwpaqkRAOpL abTNtaWCMg0+cNzRZANgmEBJiNkITO7qxKkmR90pgILAXITkY8KTLqVpmdEgoSh/Ut+T tCfydxu3Fu5EgdTJpdjKNSnqkEubMCELyQBD0B4YHv7ucoR7otiE1FbD6gSzgianslHM X0AnnZtwdIiwiN+VIVMADBqX2os6wxFpMh9FCAMhusUfGMLPfHOxsuj9zExrcCh3GUSE STAtt1K0ofbiST3W2g8gek53PfKXPkbGS0qcOZVEO7tA+fWSj4a4GHQmESgbBahjrKsn 1vYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DWXIAOo6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d35si19299796ybi.158.2020.11.16.08.23.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 16 Nov 2020 08:23:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DWXIAOo6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kehIB-0005tJ-ES for patch@linaro.org; Mon, 16 Nov 2020 11:23:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58242) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1keh3e-0008VU-RS for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:46 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:51364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1keh3b-0007qU-OW for qemu-devel@nongnu.org; Mon, 16 Nov 2020 11:08:46 -0500 Received: by mail-wm1-x336.google.com with SMTP id 19so24228634wmf.1 for ; Mon, 16 Nov 2020 08:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nnPwlADakN+vC7KEmeazFxm2/dI86B7xYLVrWaaPTLY=; b=DWXIAOo6ygWWa4TVTErfiMF1QJB1Na0Xk0tq9Xk+59/KY3FQ2HOJJyLKf1NbqRtqAa VC6PcA23NppDqJRgq6LEaJo/XI78BumArxC3pwaoNVJyb7WOt1XP4nVzOtEvi2IDEF9h 19MDQ04qCNoam28Rqs9Fl4xHwqaaXioJUsmQAZ1G2N6TFQgrv8/ub5wfMrTAwhcmuung 1OPtPv1srCe9XAhQiB4y7sF7rZYIfiNDl2U+VFd3F79gdWBv2+S2TyKxvj2vq3GIVImr KHdO6+9o7Y5BoKaKfKlqF1blMvaOsI2IJAJEe6mvfb+w2BRhPkwgaboX2EcuA313LeOC yiQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nnPwlADakN+vC7KEmeazFxm2/dI86B7xYLVrWaaPTLY=; b=X8PStCcj7NgfLgBnB9xSzVoBUm2h4exCeJTXYK8HXPjga6nkwhCT99Bt2iOK1TLQSi a3oavqZYn7GqLSun1VH0LtGVychjItMqyuLItXY4BgUFQEo4AQE0zJc6hGzdSb1vih+S L9uThOMnAZafnYcPDznAr95Ic+25SjTUDb+dXa0K4f9sZpAu7/hSNA65rWDgeEGDY1D7 8ETi6UDQLNs0MsvYauAXK1k/JyGJAWoOTH2TyxdO57qmMRpUxrEIAj01SIyfqkzdrUL6 z43jnKX6ILAOJlnjxhZ0SBi93/355lUyyxo3U7qyJiTZj+q3NM8fSklm7JNsuyUY00AU e6Lw== X-Gm-Message-State: AOAM532d2bRjsyiyf1L6jUPajlOoLQz4KewPi3QUngwbA5yla/H2kuG+ ZWzdKXagNpokhNrSo4wDamQuaw== X-Received: by 2002:a1c:b18a:: with SMTP id a132mr16399651wmf.95.1605542922217; Mon, 16 Nov 2020 08:08:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/15] target/arm: Refactor M-profile VMSR/VMRS handling Date: Mon, 16 Nov 2020 16:08:23 +0000 Message-Id: <20201116160831.31000-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently M-profile borrows the A-profile code for VMSR and VMRS (access to the FP system registers), because all it needs to support is the FPSCR. In v8.1M things become significantly more complicated in two ways: * there are several new FP system registers; some have side effects on read, and one (FPCXT_NS) needs to avoid the usual vfp_access_check() and the "only if FPU implemented" check * all sysregs are now accessible both by VMRS/VMSR (which reads/writes a general purpose register) and also by VLDR/VSTR (which reads/writes them directly to memory) Refactor the structure of how we handle VMSR/VMRS to cope with this: * keep the M-profile code entirely separate from the A-profile code * abstract out the "read or write the general purpose register" part of the code into a loadfn or storefn function pointer, so we can reuse it for VLDR/VSTR. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 + target/arm/translate-vfp.c.inc | 181 ++++++++++++++++++++++++++++++--- 2 files changed, 170 insertions(+), 14 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 806c18a499f..3b20f935174 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1569,6 +1569,9 @@ enum arm_cpu_mode { #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 +/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ +#define QEMU_VFP_FPSCR_NZCV 0xffff + /* iwMMXt coprocessor control registers. */ #define ARM_IWMMXT_wCID 0 #define ARM_IWMMXT_wCon 1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index aee60ff98b3..5d880d12116 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -607,27 +607,180 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } +/* + * M-profile provides two different sets of instructions that can + * access floating point system registers: VMSR/VMRS (which move + * to/from a general purpose register) and VLDR/VSTR sysreg (which + * move directly to/from memory). In some cases there are also side + * effects which must happen after any write to memory (which could + * cause an exception). So we implement the common logic for the + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), + * which take pointers to callback functions which will perform the + * actual "read/write general purpose register" and "read/write + * memory" operations. + */ + +/* + * Emit code to store the sysreg to its final destination; frees the + * TCG temp 'value' it is passed. + */ +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value); +/* + * Emit code to load the value to be copied to the sysreg; returns + * a new TCG temporary + */ +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); + +/* Common decode/access checks for fp sysreg read/write */ +typedef enum fp_sysreg_check_result { + fp_sysreg_check_failed, /* caller should return false */ + fp_sysreg_check_done, /* caller should return true */ + fp_sysreg_check_continue, /* caller should continue generating code */ +} fp_sysreg_check_result; + +static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) +{ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return fp_sysreg_check_failed; + } + + switch (regno) { + case ARM_VFP_FPSCR: + case QEMU_VFP_FPSCR_NZCV: + break; + default: + return fp_sysreg_check_failed; + } + + if (!vfp_access_check(s)) { + return fp_sysreg_check_done; + } + + return fp_sysreg_check_continue; +} + +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, + fp_sysreg_loadfn *loadfn, + void *opaque) +{ + /* Do a write to an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case fp_sysreg_check_failed: + return false; + case fp_sysreg_check_done: + return true; + case fp_sysreg_check_continue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp = loadfn(s, opaque); + gen_helper_vfp_set_fpscr(cpu_env, tmp); + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, + fp_sysreg_storefn *storefn, + void *opaque) +{ + /* Do a read from an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case fp_sysreg_check_failed: + return false; + case fp_sysreg_check_done: + return true; + case fp_sysreg_check_continue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp = tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + storefn(s, opaque, tmp); + break; + case QEMU_VFP_FPSCR_NZCV: + /* + * Read just NZCV; this is a special case to avoid the + * helper call for the "VMRS to CPSR.NZCV" insn. + */ + tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + storefn(s, opaque, tmp); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) +{ + arg_VMSR_VMRS *a = opaque; + + if (a->rt == 15) { + /* Set the 4 flag bits in the CPSR */ + gen_set_nzcv(value); + tcg_temp_free_i32(value); + } else { + store_reg(s, a->rt, value); + } +} + +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_VMSR_VMRS *a = opaque; + + return load_reg(s, a->rt); +} + +static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) +{ + /* + * Accesses to R15 are UNPREDICTABLE; we choose to undef. + * FPSCR -> r15 is a special case which writes to the PSR flags; + * set a->reg to a special value to tell gen_M_fp_sysreg_read() + * we only care about the top 4 bits of FPSCR there. + */ + if (a->rt == 15) { + if (a->l && a->reg == ARM_VFP_FPSCR) { + a->reg = QEMU_VFP_FPSCR_NZCV; + } else { + return false; + } + } + + if (a->l) { + /* VMRS, move FP system register to gp register */ + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); + } else { + /* VMSR, move gp register to FP system register */ + return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); + } +} + static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) { TCGv_i32 tmp; bool ignore_vfp_enabled = false; - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return gen_M_VMSR_VMRS(s, a); } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. - * Accesses to R15 are UNPREDICTABLE; we choose to undef. - * (FPSCR -> r15 is a special case which writes to the PSR flags.) - */ - if (a->reg != ARM_VFP_FPSCR) { - return false; - } - if (a->rt == 15 && !a->l) { - return false; - } + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; } switch (a->reg) { From patchwork Mon Nov 16 16:08:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324406 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4173196ejb; Mon, 16 Nov 2020 08:28:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJy4p+mN498g8D0VVBjljDDp+rsPfc4CcdaA47fy4e+hJ7qAE26in9YIH+2L7KXXJGPBuEgS X-Received: by 2002:a25:a468:: with SMTP id f95mr18682419ybi.327.1605544082852; Mon, 16 Nov 2020 08:28:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605544082; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:42 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/15] target/arm: Move general-use constant expanders up in translate.c Date: Mon, 16 Nov 2020 16:08:24 +0000 Message-Id: <20201116160831.31000-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The constant-expander functions like negate, plus_2, etc, are generally useful; move them up in translate.c so we can use them in the VFP/Neon decoders as well as in the A32/T32/T16 decoders. Signed-off-by: Peter Maydell --- target/arm/translate.c | 46 +++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 21 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate.c b/target/arm/translate.c index ac8c118427f..3e5bcab0a62 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -109,6 +109,30 @@ static void arm_gen_condlabel(DisasContext *s) } } +/* + * Constant expanders for the decoders. + */ + +static int negate(DisasContext *s, int x) +{ + return -x; +} + +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -5174,29 +5198,9 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) /* - * Constant expanders for the decoders. + * Constant expanders used by T16/T32 decode */ -static int negate(DisasContext *s, int x) -{ - return -x; -} - -static int plus_2(DisasContext *s, int x) -{ - return x + 2; -} - -static int times_2(DisasContext *s, int x) -{ - return x * 2; -} - -static int times_4(DisasContext *s, int x) -{ - return x * 4; -} - /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { From patchwork Mon Nov 16 16:08:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324405 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4172847ejb; Mon, 16 Nov 2020 08:27:30 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMR/YfRY87W4uNqXTVyop9NZnzCMHOTf6w/hh3GEDg3uzTwIhHm6MBHOiqfhggDzwyrbQ7 X-Received: by 2002:a25:c946:: with SMTP id z67mr10876992ybf.56.1605544050666; Mon, 16 Nov 2020 08:27:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605544050; cv=none; d=google.com; s=arc-20160816; b=FW8iIVLMxkeU0HGFJBV7sqQxGwPbP4ClPCpCvrKF6VS8XX9+MaEC3b1oqqXo8vNBOt I21BZwljQo1D6tkRqUhM3O9L3t4edQBHK2i6sd8i7X3fP4V5z+Lg54mif0H9K0ZXInF+ rTA8hhWXi3QdxApYdQEKxRSMma/ImT9tX5vBpS0I7X3dgAF+YcZdSkeU2GKFDWeYfqYl 19XX3+ghRyR3LTiNR8xKgsyBOTs4oq0Ls5L7OhPbs7T9aNATqH5XVvcPatZz0GR0sfHm k00XGiizyl9s7O3IpUp3jKFF+klot9S4KUSi6VQt3ACp/zHpNQX640JFGt8n3eS4rZEo WRlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aHtpQRU3H8qXd2uvyEa+TFGGzXeXygeYRFKCnGAFOiY=; b=e5FXJfdQvxHGggT2CDzidwE03ddEwks2sPWaIe63k0c7TAovC00tixMDYAcNrBov8o Pv7Iqd10QYq1frda65LmEO25cVXhZ/Gd+sfvqWQ5GEdpXkMOrGJAsmyy6t5IAg22bR+U /op9LcdmtXw7SlTGLDOeVy7bucHG88EVUCclvMxwbWp8fdBxknB84qiDFdI3FqSMiwDP 2b52qRPAKLxu77watHG7FWehHtzt0Hi9C+dWE5A5F/3LUaSN5beaoPr/hCm8pKg8Grss OSC7PRBBnPFR2eu3m4ESRq+sHXWDsD83UsyDgjFBQwDUhtFtDgIGXu6bGfnwloFc6QTc c26Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Thn+dm+Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/15] target/arm: Implement VLDR/VSTR system register Date: Mon, 16 Nov 2020 16:08:25 +0000 Message-Id: <20201116160831.31000-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the new-in-v8.1M VLDR/VSTR variants which directly read or write FP system registers to memory. Signed-off-by: Peter Maydell --- target/arm/vfp.decode | 14 ++++++ target/arm/translate-vfp.c.inc | 89 ++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) -- 2.20.1 diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 51f143b4a51..45e3023840b 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -84,6 +84,20 @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp +# M-profile VLDR/VSTR to sysreg +%vldr_sysreg 22:1 13:3 +%imm7_0x4 0:7 !function=times_4 + +&vldr_sysreg rn reg imm a w p +@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ + reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg + +# P=0 W=0 is SEE "Related encodings", so split into two patterns +VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1 +VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 +VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1 +VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 + # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit move" # grouping: diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 5d880d12116..cc115f1d35d 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -912,6 +912,95 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) return true; } +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) +{ + arg_vldr_sysreg *a = opaque; + uint32_t offset = a->imm; + TCGv_i32 addr; + + if (!a->a) { + offset = - offset; + } + + addr = load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_st32(s, value, addr, get_mem_index(s)); + tcg_temp_free_i32(value); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_vldr_sysreg *a = opaque; + uint32_t offset = a->imm; + TCGv_i32 addr; + TCGv_i32 value = tcg_temp_new_i32(); + + if (!a->a) { + offset = - offset; + } + + addr = load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_ld32u(s, value, addr, get_mem_index(s)); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + return value; +} + +static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn == 15) { + return false; + } + return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); +} + +static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn == 15) { + return false; + } + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); +} + static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) { TCGv_i32 tmp; From patchwork Mon Nov 16 16:08:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324407 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4175037ejb; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/15] target/arm: Implement M-profile FPSCR_nzcvqc Date: Mon, 16 Nov 2020 16:08:26 +0000 Message-Id: <20201116160831.31000-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves like the existing FPSCR, except that it reads and writes only bits [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not permitted.) Implement the register. Since we don't yet implement MVE, we handle the QC bit as RES0, with todo comments for where we will need to add support later. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 13 +++++++++++++ target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3b20f935174..34f8f4afe18 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1524,6 +1524,13 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ +#define FPCR_V (1 << 28) /* FP overflow flag */ +#define FPCR_C (1 << 29) /* FP carry flag */ +#define FPCR_Z (1 << 30) /* FP zero flag */ +#define FPCR_N (1 << 31) /* FP negative flag */ + +#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) +#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) static inline uint32_t vfp_get_fpsr(CPUARMState *env) { @@ -1568,6 +1575,12 @@ enum arm_cpu_mode { #define ARM_VFP_FPEXC 8 #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 +/* These ones are M-profile only */ +#define ARM_VFP_FPSCR_NZCVQC 2 +#define ARM_VFP_VPR 12 +#define ARM_VFP_P0 13 +#define ARM_VFP_FPCXT_NS 14 +#define ARM_VFP_FPCXT_S 15 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ #define QEMU_VFP_FPSCR_NZCV 0xffff diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index cc115f1d35d..84e806004e4 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -648,6 +648,11 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) case ARM_VFP_FPSCR: case QEMU_VFP_FPSCR_NZCV: break; + case ARM_VFP_FPSCR_NZCVQC: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + break; default: return fp_sysreg_check_failed; } @@ -682,6 +687,22 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; + case ARM_VFP_FPSCR_NZCVQC: + { + TCGv_i32 fpscr; + tmp = loadfn(s, opaque); + /* + * TODO: when we implement MVE, write the QC bit. + * For non-MVE, QC is RES0. + */ + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + break; + } default: g_assert_not_reached(); } @@ -710,6 +731,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, gen_helper_vfp_get_fpscr(tmp, cpu_env); storefn(s, opaque, tmp); break; + case ARM_VFP_FPSCR_NZCVQC: + /* + * TODO: MVE has a QC bit, which we probably won't store + * in the xregs[] field. For non-MVE, where QC is RES0, + * we can just fall through to the FPSCR_NZCV case. + */ case QEMU_VFP_FPSCR_NZCV: /* * Read just NZCV; this is a special case to avoid the From patchwork Mon Nov 16 16:08:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324409 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4177905ejb; Mon, 16 Nov 2020 08:34:09 -0800 (PST) X-Google-Smtp-Source: ABdhPJzXhVqtoa9HWplhh9VHxFHmwLJga9gT5/5N826RwqOkhk1BGBIFFAvlQxgYcVHtvg6oB+tI X-Received: by 2002:a25:8448:: with SMTP id r8mr22130339ybm.253.1605544448648; Mon, 16 Nov 2020 08:34:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605544448; cv=none; d=google.com; s=arc-20160816; b=f7FIxrUYwEk7V1ftPvsYXJeBRaKynIx4h5cGWoU19DtFVPNXM8pQHMvJ2rHUknlwOJ 792rmtgYIQgzZqO7vi7FxnQ7XiGlTrar/IP92ynuAlH2ZOSTq7wYDQn0N2HjabLHd5oe Bz4cs/KmeWhuxADUUSXKwcv7pvcgp6qm7NXzpGHOk7NH/RqDWVtei0vSRL9khcxnuyQs iNtYGYvQ6TubOb8tP4UurNOPvT0hVZt+kUwDqRlaCHsCFm8yrw3hSG+P49jQGQmdh9kk 8vnL2LhfFPjvANHr0jAejArKqmziBEdDGWrlVj4iYbzSywFwGn+cXKoTV8ep0gq8DOVt 8ToA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=75Zceu/K9be36pIFImAJ+/cw2g18SD9setpoR1l2WBI=; b=Da+axCRU0dQCjWHKJ1IVV1daK8vddovaSZ+nuGOof5LE5tfQjuBqcZk770sjgDiPIC SfpusQXiH0r3i0N5das9nA4vTtkgJhSm7Vk1o5qdf/NlysMqSMbfjSpkUlJ5V2aHPxr/ C30u2KG/4JHv0lTcUDdukXE9hmf49AWyfm7pgS7fwOvA0/3QL5SPHbztfwKsfAN1G8pC pjE4wG2EECsh6Rd8qO9ihKx3PQ0xsJyGjuj0tznsPrQHvDopvnVst6Vc1StHaatl4kQ7 A2dMPBsQNXiUbRf9FMtJbMMO2MZFS3tqY9mgWMpzsvWwRTZj9yBPksgriTc74cHRuBMH xOQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vfzEj6yr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/15] target/arm: Use new FPCR_NZCV_MASK constant Date: Mon, 16 Nov 2020 16:08:27 +0000 Message-Id: <20201116160831.31000-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR in the previous commit; use it in a couple of places in existing code, where we're masking out everything except NZCV for the "load to Rt=15 sets CPSR.NZCV" special case. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 84e806004e4..1ccaccbc834 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -743,7 +743,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; default: @@ -884,7 +884,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) case ARM_VFP_FPSCR: if (a->rt == 15) { tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp = tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, cpu_env); From patchwork Mon Nov 16 16:08:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324396 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3442020ils; Mon, 16 Nov 2020 08:15:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMjn3ZJqm1hnIN/VgoE9NyEp3qgL1lzJkOyiFt3mt1bUQdscxsLFomSJUcEuZe9WbF2XRG X-Received: by 2002:a25:588b:: with SMTP id m133mr16658788ybb.522.1605543316861; Mon, 16 Nov 2020 08:15:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543316; cv=none; d=google.com; s=arc-20160816; b=0NAJNqhgu/AvLBAVQ5m7ExKsbRraztzDSVZZFG+2a4jrHgeL0Yq2nN0WMNYqw+dqAZ rd3FZt2stosl+NOfSLztBfiz8KmFD2v7a4JUcRjnK9HYFYPMRMUN+1CiHYZh+YMA3ssj exyRNyvrAAx0Pts+4w811A8SS2cM+/CEa0SisFGg2ZpLebe7F0N6xnkyDcCB2dDM5Xs+ zEUDmqrNID/taOFejMV9uduqMd81EXRyguwEgVE5az9wr59nRUwN0ONWjoQsgJQioA/0 rfLq9qR3AgzsUAwodXJzpFTOtvycUwd7Ampo3LMv7+m9mAICnu2vMn28xfdml7rDZPjJ Z9QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5URRqI2Uq5Oefocw0RaK3NP6xNImZJ6yO5PhF2xMruc=; b=JmfiTHAJzaQLwf564b8+fi3QtFB7GWu+UlYpDYb3cl1G6c+J8KU1FsNL3FKyvye20G UfvDkvh5B69DIyPCChKDJ+Fsj5BsKlAT2UbobtXYRB3y4X9QhlBN5z8BBg3Q5ACR+5Iy NINMFTEhudrkPO7Oa16Qsx0Q98Jwf9Z0apoSjy6i/yJ7BvVSe1OoR8EMXaYbREHBuFro /j0E+oAeBtpk0qljZtnVm8I/D8COMgoh0KFX6it6J6rI/0A0IwYfmXV9Yvjr47J48ytx iqqzYb8v+9r2KEVMh4+0UlbIrqax615RVlZ1LK2eoLZGzMn/37E4p32ltbmdDeFLvH8z s73g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JxEeSDAY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/15] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Date: Mon, 16 Nov 2020 16:08:28 +0000 Message-Id: <20201116160831.31000-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Factor out the code which handles M-profile lazy FP state preservation from full_vfp_access_check(); accesses to the FPCXT_NS register are a special case which need to do just this part (corresponding in the pseudocode to the PreserveFPState() function), and not the full set of actions matching the pseudocode ExecuteFPCheck() which normal FP instructions need to do. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 18 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 1ccaccbc834..6bc07992eb4 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -83,6 +83,32 @@ static inline long vfp_f16_offset(unsigned reg, bool top) return offs; } +/* + * Generate code for M-profile lazy FP state preservation if needed; + * this corresponds to the pseudocode PreserveFPState() function. + */ +static void gen_preserve_fp_state(DisasContext *s) +{ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount (and cause + * this to be the last insn in the TB). + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + s->base.is_jmp = DISAS_UPDATE_EXIT; + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact = false; + } +} + /* * Check that VFP access is enabled. If it is, do the necessary * M-profile lazy-FP handling and then return true. @@ -113,24 +139,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) /* Handle M-profile lazy FP state mechanics */ /* Trigger lazy-state preservation if necessary */ - if (s->v7m_lspact) { - /* - * Lazy state saving affects external memory and also the NVIC, - * so we must mark it as an IO operation for icount (and cause - * this to be the last insn in the TB). - */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - s->base.is_jmp = DISAS_UPDATE_EXIT; - gen_io_start(); - } - gen_helper_v7m_preserve_fp_state(cpu_env); - /* - * If the preserve_fp_state helper doesn't throw an exception - * then it will clear LSPACT; we don't need to repeat this for - * any further FP insns in this TB. - */ - s->v7m_lspact = false; - } + gen_preserve_fp_state(s); /* Update ownership of FP context: set FPCCR.S to match current state */ if (s->v8m_fpccr_s_wrong) { From patchwork Mon Nov 16 16:08:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324410 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4181120ejb; Mon, 16 Nov 2020 08:38:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJx2CG2L2tMddJOw40bJAJXR+uS8qkI17Y1k83B3bMN8mMG3h/Cm7Zmu+4eEFJiAeEOT6QLe X-Received: by 2002:a25:3b8c:: with SMTP id i134mr23551807yba.372.1605544685829; Mon, 16 Nov 2020 08:38:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605544685; cv=none; d=google.com; s=arc-20160816; b=mHwvKgEENEtbiFii+tiKLHz/s86e9TrbZOU5J/v2GrgXbeWaduD7ChI2tjjdyGU8Am fHdZNqv53VZ/iXXG+Pi0U8d/6qEbo/4AOKIOQty3EVgNaC0RnMU0RMJIR3QP3DtJBeCw ZyTThYchYfC8Nw5b+NlRI80yRApKgv1VPyOmyBImLHtuNvPahaa3BVzw9PQGIA6WKyiq Zb8e6+O1c10+PthjstXfp2luANhwl4zOnwiPXG9ESxTUIXLiruE5qiYHGDgEiGCxYBDv 85wmBEB+9H62IGwsM+XffS43N3nTiG0qsp0cEgOGRqrVUjq4woHI2x7bIWzrgHXQHmwC WRLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dp5OeL6zHEFo/uQpmEKWaIqQytKKS/VgbFkbBy3hcaw=; b=eODWfSzFBOTyfYUYb5f6z7ygj0KOi1t3a0P3nOAlIsUrHfn8ZWC/h1NRAdXFwBEFGN o0q2NOrfYXutaEFu4lfMWGMy5byuxD5CsUx87Rjc+stbj7YN/wIFjRPOSg8QnHKF9aZP kQcDjeLKD1rURfizR8EwxB8bZGpQKNqUdMHiVW3v9/inQsHFlN7zOruAQN8AFXQ6xH0R gwZRppkBCMbABLonFbA7wvSyNEkXOWVwJTXGsoeMEOrXfIFrVVDJz5mG2ujJxDLGo4H0 2z+uiu6yzt1PFWXxSXw59oH6CLKTUJvulaHPTzCzp8cZot6NfX+fZqWbqCTPavqg5Awc cleg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IdU4QEqq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/15] target/arm: Implement FPCXT_S fp system register Date: Mon, 16 Nov 2020 16:08:29 +0000 Message-Id: <20201116160831.31000-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the new-in-v8.1M FPCXT_S floating point system register. This is for saving and restoring the secure floating point context, and it reads and writes bits [27:0] from the FPSCR and the CONTROL.SFPA bit in bit [31]. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) -- 2.20.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 6bc07992eb4..c7ae306f12f 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -662,6 +662,14 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) return false; } break; + case ARM_VFP_FPCXT_S: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (!s->v8m_secure) { + return false; + } + break; default: return fp_sysreg_check_failed; } @@ -712,6 +720,26 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, tcg_temp_free_i32(tmp); break; } + case ARM_VFP_FPCXT_S: + { + TCGv_i32 sfpa, control, fpscr; + /* Set FPSCR[27:0] and CONTROL.SFPA from value */ + tmp = loadfn(s, opaque); + sfpa = tcg_temp_new_i32(); + tcg_gen_shri_i32(sfpa, tmp, 31); + control = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_deposit_i32(control, control, sfpa, + R_V7M_CONTROL_SFPA_SHIFT, 1); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(sfpa); + break; + } default: g_assert_not_reached(); } @@ -755,6 +783,36 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; + case ARM_VFP_FPCXT_S: + { + TCGv_i32 control, sfpa, fpscr; + /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ + tmp = tcg_temp_new_i32(); + sfpa = tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + control = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(sfpa); + /* + * Store result before updating FPSCR etc, in case + * it is a memory write which causes an exception. + */ + storefn(s, opaque, tmp); + /* + * Now we must reset FPSCR from FPDSCR_NS, and clear + * CONTROL.SFPA; so we'll end the TB here. + */ + tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + gen_lookup_tb(s); + break; + } default: g_assert_not_reached(); } From patchwork Mon Nov 16 16:08:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324399 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp3445184ils; Mon, 16 Nov 2020 08:19:10 -0800 (PST) X-Google-Smtp-Source: ABdhPJycaJvwMSqRCO+xVMsQ+JTxwrIdkZfcQk/pGfw2V+MHnOkhB0o3c8U12TOAzzloBlMwTBXv X-Received: by 2002:a25:3b8c:: with SMTP id i134mr23418646yba.372.1605543550490; Mon, 16 Nov 2020 08:19:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605543550; cv=none; d=google.com; s=arc-20160816; b=edxj+R+yYtLSKl39G54a3NL5GZbk6ToNuOVCAGe3/Bt6FVOINp0ECHd+XjGbiYCzmh ySxNFwCgYnaFQOifae4XOevLfCzBDaVHCHwf75nYhPvIx8gUbCdauqL++t+1EXPFViGJ tiwZFV8v/vcVN86rBQNAhrmZT9GrISgvGpaYbzo6rhBfBdXeKPoSmpLIHE7S2MosfODv qLK9ovkw41XPmciHpvkzHTIodC6tPd1T14gTM2mr1N6rzflvKGnB7H8caag4/6NZiBZV 1SeV6cLQG0RS1U6J8muRKyYh0yI7568tfknwbVwy+k89RarpjZMdR0lsMkN3SK4l6w/z YdPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HpGcUz/nkakqTXZdKeGHB+GL0ZV/75Y796jJ21zpvSI=; b=hgWf0SvnGWwLpXUjCugKY3ZaQejNgCDAarEz0WTQScw2zVMnsFTWYH2phDa3U5cGQh CG2DklNyrA2zuISFk6qPHP/8Or7hvZUd26Hfmb2gdbUrJyppgcBIgkVrYp2hw1dfR/6c RtDmcSfHiRC+PonCYfNj63W5O4gd5obqZkfKHBey9T+JbWMXx0qQ6YGFyvSxPdK4BxOH E59saiXpZlAXN8WvGoHVobWLowOOoFxGZPIWcaFkYcYwLG1JIPg76Q8WoitQgv5CHjiH qtjnHST9QuH+WCITMZjxR6Ku4IAo54hysKVVHszYPDbV6PN6OjtaeqajLYF5IX7KsGix DAlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dWKWu7Vz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:50 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/15] target/arm: Implement FPCXT_NS fp system register Date: Mon, 16 Nov 2020 16:08:30 +0000 Message-Id: <20201116160831.31000-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implement the v8.1M FPCXT_NS floating-point system register. This is a little more complicated than FPCXT_S, because it has specific handling for "current FP state is inactive", and it only wants to do PreserveFPState(), not the full set of actions done by ExecuteFPCheck() which vfp_access_check() implements. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 110 ++++++++++++++++++++++++++++++--- 1 file changed, 103 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index c7ae306f12f..d0c3a464a21 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -647,8 +647,20 @@ typedef enum fp_sysreg_check_result { fp_sysreg_check_continue, /* caller should continue generating code */ } fp_sysreg_check_result; -static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) +/* + * Emit code to check common UNDEF cases and handle lazy state preservation + * including the special casing for FPCXT_NS. For reads of sysregs, caller + * should provide storefn and opaque; for writes to sysregs these can be NULL. + * On return, if *insn_end_label is not NULL the caller needs to gen_set_label() + * it at the end of the other code generated for the insn. + */ +static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno, + fp_sysreg_storefn *storefn, + void *opaque, + TCGLabel **insn_end_label) { + *insn_end_label = NULL; + if (!dc_isar_feature(aa32_fpsp_v2, s)) { return fp_sysreg_check_failed; } @@ -663,6 +675,7 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) } break; case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { return false; } @@ -674,8 +687,46 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) return fp_sysreg_check_failed; } - if (!vfp_access_check(s)) { - return fp_sysreg_check_done; + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * We don't have a TB flag that matches the fpInactive check, so we + * do it at runtime as we don't expect FPCXT_NS accesses to be frequent. + * The code emitted here handles the fpInactive special case; + * the caller just has to do the codegen for the normal (!fpInactive) + * special case, and then set the label at the end. + */ + if (regno == ARM_VFP_FPCXT_NS) { + /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ + TCGLabel *fp_active_label = gen_new_label(); + TCGv_i32 aspen, fpca; + aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); + fpca = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_subi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); + tcg_gen_or_i32(fpca, fpca, aspen); + tcg_gen_brcondi_i32(TCG_COND_NE, fpca, 0, fp_active_label); + tcg_temp_free_i32(aspen); + tcg_temp_free_i32(fpca); + + /* fpInactive case: FPCXT_NS reads as FPDSCR_NS, write is NOP */ + if (storefn) { + TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); + storefn(s, opaque, tmp); + } + /* jump to end of insn */ + *insn_end_label = gen_new_label(); + tcg_gen_br(*insn_end_label); + + gen_set_label(fp_active_label); + /* !fpInactive: PreserveFPState() and handle register as normal */ + gen_preserve_fp_state(s); + } else { + if (!vfp_access_check(s)) { + return fp_sysreg_check_done; + } } return fp_sysreg_check_continue; @@ -687,8 +738,10 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, { /* Do a write to an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *insn_end_label; + bool lookup_tb = false; - switch (fp_sysreg_checks(s, regno)) { + switch (fp_sysreg_checks(s, regno, NULL, NULL, &insn_end_label)) { case fp_sysreg_check_failed: return false; case fp_sysreg_check_done: @@ -702,7 +755,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, tmp = loadfn(s, opaque); gen_helper_vfp_set_fpscr(cpu_env, tmp); tcg_temp_free_i32(tmp); - gen_lookup_tb(s); + lookup_tb = true; break; case ARM_VFP_FPSCR_NZCVQC: { @@ -721,6 +774,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, break; } case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: { TCGv_i32 sfpa, control, fpscr; /* Set FPSCR[27:0] and CONTROL.SFPA from value */ @@ -743,6 +797,12 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, default: g_assert_not_reached(); } + if (insn_end_label) { + gen_set_label(insn_end_label); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } @@ -752,8 +812,10 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, { /* Do a read from an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *insn_end_label; + bool lookup_tb = false; - switch (fp_sysreg_checks(s, regno)) { + switch (fp_sysreg_checks(s, regno, storefn, opaque, &insn_end_label)) { case fp_sysreg_check_failed: return false; case fp_sysreg_check_done: @@ -810,12 +872,46 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); - gen_lookup_tb(s); + lookup_tb = true; + break; + } + case ARM_VFP_FPCXT_NS: + { + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + /* Reads the same as FPCXT_S, but side effects differ */ + tmp = tcg_temp_new_i32(); + sfpa = tcg_temp_new_i32(); + fpscr = tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(fpscr, cpu_env); + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); + control = load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(control); + /* Store result before updating FPSCR, in case it faults */ + storefn(s, opaque, tmp); + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ + fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); + zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(sfpa); + tcg_temp_free_i32(fpdscr); + tcg_temp_free_i32(fpscr); + lookup_tb = true; break; } default: g_assert_not_reached(); } + if (insn_end_label) { + gen_set_label(insn_end_label); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } From patchwork Mon Nov 16 16:08:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 324408 Delivered-To: patch@linaro.org Received: by 2002:a17:906:d156:0:0:0:0 with SMTP id br22csp4176034ejb; Mon, 16 Nov 2020 08:31:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJyx8Ks+hxXnR2nT19xAIvGcBWWxeUx6yrYCbmw3GGL0vMi52IaTSKOaSXimRgcvMyCeOMO7 X-Received: by 2002:a25:bb10:: with SMTP id z16mr4575843ybg.281.1605544305544; Mon, 16 Nov 2020 08:31:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605544305; cv=none; d=google.com; s=arc-20160816; b=fieYaJ1WnxzHacsIpPp+hh5q/wVszwjGPkCsKoExzZ3ua42zrUWqwsfqK/nY2MOgui x8PwXnGSzDP8nM8LXheAyqQuZ3w3/mm7tK2c50sVB4PFiX3IPKJ6Sv0zoNuUd6xxooKr OczKoNPfViwmnicqSKrqhHdDdyN6j52/5gbtKuuzxtbzpbYp5WcIwdCGkDR37Plzv8vX 89xVlpW+EQHvxM+ud90yQGqtwCify7y961O1nNie+u5ofBKpKEGsiimqG8WpSz6Ft75q FHAC+xnezoB/y1aVQRIlzIdur+jwJTjay0c+BfswhK/0SnAgEPLxAVwufkqlpxq1SU2i 3hgw== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g20sm20116975wmh.20.2020.11.16.08.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Nov 2020 08:08:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/15] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Date: Mon, 16 Nov 2020 16:08:31 +0000 Message-Id: <20201116160831.31000-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201116160831.31000-1-peter.maydell@linaro.org> References: <20201116160831.31000-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ hw/intc/armv7m_nvic.c | 9 ++++++++- target/arm/cpu.c | 3 +++ 3 files changed, 16 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 34f8f4afe18..2bc25b65ab0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1521,14 +1521,19 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_AHP (1 << 26) /* Alternative half-precision */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ #define FPCR_V (1 << 28) /* FP overflow flag */ #define FPCR_C (1 << 29) /* FP carry flag */ #define FPCR_Z (1 << 30) /* FP zero flag */ #define FPCR_N (1 << 31) /* FP negative flag */ +#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ +#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) + #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9628ce876e0..be3bc1f1f45 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2068,7 +2068,14 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; case 0xf3c: /* FPDSCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - value &= 0x07c00000; + uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; + if (cpu_isar_feature(any_fp16, cpu)) { + mask |= FPCR_FZ16; + } + value &= mask; + if (cpu_isar_feature(aa32_lob, cpu)) { + value |= 4 << FPCR_LTPSIZE_SHIFT; + } cpu->env.v7m.fpdscr[attrs.secure] = value; } break; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40f3f798b2b..d6188f6566a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -262,6 +262,9 @@ static void arm_cpu_reset(DeviceState *dev) * always reset to 4. */ env->v7m.ltpsize = 4; + /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ + env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT; + env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT; } if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {