From patchwork Tue Nov 17 16:19:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 326320 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B3E9C63798 for ; Tue, 17 Nov 2020 16:20:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 19F24208CA for ; Tue, 17 Nov 2020 16:20:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VlBA8xDU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727288AbgKQQUD (ORCPT ); Tue, 17 Nov 2020 11:20:03 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46902 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726424AbgKQQUB (ORCPT ); Tue, 17 Nov 2020 11:20:01 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AHGJort008011; Tue, 17 Nov 2020 10:19:50 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605629990; bh=fOcGPq25kCNFtsMe/61ChnGUekQJo9px2A8HMNw0tXs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VlBA8xDU38k1OmY54F+lhoUf4oYPVObnEE3g08c4aoXKdIOjSzupdLN3XwCNsMKAh iYq9IgZLB02ey+C9mxHv3EfBtS7Y7M4tkl4KFWQH8GXrNtZbtXdDiHdR2bBXtu4Ag+ 3m/l9GfrgPgBqNora/OQNNEaiQ/5+k9cDwW/7IRI= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AHGJoZU099417 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 17 Nov 2020 10:19:50 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 17 Nov 2020 10:19:50 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 17 Nov 2020 10:19:50 -0600 Received: from pxplinux063.india.englab.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AHGJhwH032251; Tue, 17 Nov 2020 10:19:47 -0600 From: Sekhar Nori To: Nishanth Menon , Tero Kristo CC: Linux ARM Mailing List , Device Tree Mailing List , , Rob Herring , Faiz Abbas , Grygorii Strashko , Lokesh Vutla , Andre Przywara Subject: [PATCH v2 1/4] arm64: dts: ti: k3: squelch warning about lack of #interrupt-cells Date: Tue, 17 Nov 2020 21:49:39 +0530 Message-ID: <20201117161942.38754-2-nsekhar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201117161942.38754-1-nsekhar@ti.com> References: <20201117161942.38754-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are couple of places where INTA interrupt controller lacks #interrupt-cells property. This leads to warnings of the type: arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider When building TI device-tree files with W=2 warning level. Fix these. Signed-off-by: Sekhar Nori --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3eeb6e9876db..aa8725db0187 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -473,6 +473,7 @@ interrupt-controller; interrupt-parent = <&intr_main_navss>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <179>; ti,interrupt-ranges = <0 0 256>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e2a96b2c423c..ffedd9531362 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -148,6 +148,7 @@ interrupt-controller; interrupt-parent = <&main_navss_intr>; msi-controller; + #interrupt-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; From patchwork Tue Nov 17 16:19:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 327322 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5035C56202 for ; Tue, 17 Nov 2020 16:20:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8616F20897 for ; Tue, 17 Nov 2020 16:20:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GASktGpL" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727698AbgKQQUH (ORCPT ); Tue, 17 Nov 2020 11:20:07 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50636 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727287AbgKQQUD (ORCPT ); Tue, 17 Nov 2020 11:20:03 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0AHGJsSE106065; Tue, 17 Nov 2020 10:19:54 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1605629994; bh=XVvA09sBrLg0rV2ApBpdwuOCVUoDHc1YDJGQuDiMfRs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GASktGpLxSNFWTDzmliqFsh57RmB3oTJIRneHeaQeRC5oMEOs932ARwvULxv3hM91 nSBT/48rO2yHWsfAOgjSRzuvcpsqrDeAx618AXENpzISU0O30U0K1osq8dkYqJyfqg jAvJiCvKBvu+vUw7g8eTr8gQz/a2TBUmvYeLOybw= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0AHGJsMO049926 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 17 Nov 2020 10:19:54 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 17 Nov 2020 10:19:53 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 17 Nov 2020 10:19:53 -0600 Received: from pxplinux063.india.englab.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0AHGJhwI032251; Tue, 17 Nov 2020 10:19:50 -0600 From: Sekhar Nori To: Nishanth Menon , Tero Kristo CC: Linux ARM Mailing List , Device Tree Mailing List , , Rob Herring , Faiz Abbas , Grygorii Strashko , Lokesh Vutla , Andre Przywara Subject: [PATCH v2 2/4] arm64: dts: ti: k3: squelch warnings regarding no #address-cells for interrupt-controller Date: Tue, 17 Nov 2020 21:49:40 +0530 Message-ID: <20201117161942.38754-3-nsekhar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201117161942.38754-1-nsekhar@ti.com> References: <20201117161942.38754-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org With dtc 1.6.0, building TI device-tree files with W=2 results in warnings like below for all interrupt controllers. /bus@100000/bus@30000000/interrupt-controller1: Missing #address-cells in interrupt provider Fix these by adding #address-cells = <0>; for all interrupt controllers in TI device-tree files. Any other #address-cells value is really only needed if interrupt-map property is being used (which is not the case for existing TI device-tree files) Signed-off-by: Sekhar Nori --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 11 +++++++++++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 3 +++ 8 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index aa8725db0187..55aaa1404d7d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -440,6 +440,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <100>; ti,interrupt-ranges = <0 392 32>; @@ -461,6 +462,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <182>; ti,interrupt-ranges = <0 64 64>, @@ -474,6 +476,7 @@ interrupt-parent = <&intr_main_navss>; msi-controller; #interrupt-cells = <0>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <179>; ti,interrupt-ranges = <0 0 256>; @@ -670,6 +673,7 @@ interrupts = <192>, <193>, <194>, <195>, <196>, <197>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <96>; ti,davinci-gpio-unbanked = <0>; clocks = <&k3_clks 57 0>; @@ -685,6 +689,7 @@ interrupts = <200>, <201>, <202>, <203>, <204>, <205>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <90>; ti,davinci-gpio-unbanked = <0>; clocks = <&k3_clks 58 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi index ed42f13e7663..7fe5782a1f79 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi @@ -75,6 +75,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <156>; ti,interrupt-ranges = <0 712 16>; @@ -89,6 +90,7 @@ interrupts = <60>, <61>, <62>, <63>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <56>; ti,davinci-gpio-unbanked = <0>; clocks = <&k3_clks 59 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index d12dd89f3405..376de272cb4e 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -236,6 +236,7 @@ interrupts = <25 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 72d6496e88dd..d07081b20aee 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -67,6 +67,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <131>; ti,interrupt-ranges = <8 392 56>; @@ -85,6 +86,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <213>; ti,interrupt-ranges = <0 64 64>, @@ -97,6 +99,7 @@ reg = <0x00 0x33d00000 0x00 0x100000>; interrupt-controller; #interrupt-cells = <0>; + #address-cells = <0>; interrupt-parent = <&main_navss_intr>; msi-controller; ti,sci = <&dmsc>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index eb2a78a53512..4801876bd107 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -102,6 +102,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <137>; ti,interrupt-ranges = <16 960 16>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 52e121155563..0490cb15f0c9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -442,6 +442,7 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index ffedd9531362..7f44692e15ec 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -114,6 +114,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <131>; ti,interrupt-ranges = <8 392 56>; @@ -135,6 +136,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <213>; ti,interrupt-ranges = <0 64 64>, @@ -149,6 +151,7 @@ interrupt-parent = <&main_navss_intr>; msi-controller; #interrupt-cells = <0>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <209>; ti,interrupt-ranges = <0 0 256>; @@ -948,6 +951,7 @@ <260>, <261>, <262>, <263>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; @@ -964,6 +968,7 @@ interrupts = <288>, <289>, <290>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; @@ -981,6 +986,7 @@ <268>, <269>, <270>, <271>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; @@ -997,6 +1003,7 @@ interrupts = <292>, <293>, <294>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; @@ -1014,6 +1021,7 @@ <276>, <277>, <278>, <279>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; @@ -1030,6 +1038,7 @@ interrupts = <296>, <297>, <298>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; @@ -1047,6 +1056,7 @@ <284>, <285>, <286>, <287>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <128>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; @@ -1063,6 +1073,7 @@ interrupts = <300>, <301>, <302>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <36>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index e581cb1d87ee..ed3098ed7b56 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -102,6 +102,7 @@ interrupt-controller; interrupt-parent = <&gic500>; #interrupt-cells = <1>; + #address-cells = <0>; ti,sci = <&dmsc>; ti,sci-dev-id = <137>; ti,interrupt-ranges = <16 960 16>; @@ -116,6 +117,7 @@ interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <84>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; @@ -132,6 +134,7 @@ interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <0>; ti,ngpio = <84>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; From patchwork Tue Nov 17 16:19:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 327325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 710CEC2D0E4 for ; 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Tue, 17 Nov 2020 10:19:54 -0600 From: Sekhar Nori To: Nishanth Menon , Tero Kristo CC: Linux ARM Mailing List , Device Tree Mailing List , , Rob Herring , Faiz Abbas , Grygorii Strashko , Lokesh Vutla , Andre Przywara Subject: [PATCH v2 3/4] arm64: dts: ti: k3-j7200: Add gpio nodes Date: Tue, 17 Nov 2020 21:49:41 +0530 Message-ID: <20201117161942.38754-4-nsekhar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201117161942.38754-1-nsekhar@ti.com> References: <20201117161942.38754-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Faiz Abbas There are 4 instances of gpio modules in main domain: gpio0, gpio2, gpio4 and gpio6 Groups are created to provide protection between different processor virtual worlds. Each of these modules I/O pins are muxed within the group. Exactly one module can be selected to control the corresponding pin by selecting it in the pad mux configuration registers. This group pins out 69 lines (5 banks). Add DT modes for each module instance in the main domain. Similar to the gpio groups in main domain, there is one gpio group in wakeup domain with 2 mdoules instances in it. The gpio group pins out 73 pins (5 banks). Add DT nodes for each module instance in the wakeup domain. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 72 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 34 +++++++++ 2 files changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index d07081b20aee..b313b895fd31 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -449,4 +449,76 @@ dr_mode = "otg"; }; }; + + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, + <149>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 0>; + clock-names = "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, + <158>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 0>; + clock-names = "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, + <167>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 109 0>; + clock-names = "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, + <176>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 111 0>; + clock-names = "gpio"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 4801876bd107..a09e2157d80f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -108,6 +108,40 @@ ti,interrupt-ranges = <16 960 16>; }; + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <73>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <73>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "gpio"; + }; + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; From patchwork Tue Nov 17 16:19:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 326319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49AD3C6379F for ; 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Tue, 17 Nov 2020 10:19:57 -0600 From: Sekhar Nori To: Nishanth Menon , Tero Kristo CC: Linux ARM Mailing List , Device Tree Mailing List , , Rob Herring , Faiz Abbas , Grygorii Strashko , Lokesh Vutla , Andre Przywara Subject: [PATCH v2 4/4] arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules Date: Tue, 17 Nov 2020 21:49:42 +0530 Message-ID: <20201117161942.38754-5-nsekhar@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201117161942.38754-1-nsekhar@ti.com> References: <20201117161942.38754-1-nsekhar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Faiz Abbas There are 6 gpio instances inside SoC with 2 groups as show below: Group one: wkup_gpio0, wkup_gpio1 Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6 Only one instance from each group can be used at a time. So use main_gpio0 and wkup_gpio0 in current linux context and disable the rest of the nodes. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ef03e7636b66..0bc4170225d5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -127,6 +127,22 @@ status = "disabled"; }; +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;