From patchwork Mon Mar 20 13:11:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95529 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936047qgd; Mon, 20 Mar 2017 06:15:22 -0700 (PDT) X-Received: by 10.107.12.80 with SMTP id w77mr27218686ioi.124.1490015722329; Mon, 20 Mar 2017 06:15:22 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id b17si17737842ioa.40.2017.03.20.06.15.22; Mon, 20 Mar 2017 06:15:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D423B63E92; Mon, 20 Mar 2017 13:15:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A793F63E80; Mon, 20 Mar 2017 13:15:03 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E8C4A63E7E; Mon, 20 Mar 2017 13:14:56 +0000 (UTC) Received: from mail-pg0-f53.google.com (mail-pg0-f53.google.com [74.125.83.53]) by lists.linaro.org (Postfix) with ESMTPS id CD98C63E77 for ; Mon, 20 Mar 2017 13:14:52 +0000 (UTC) Received: by mail-pg0-f53.google.com with SMTP id t143so11444126pgb.2 for ; Mon, 20 Mar 2017 06:14:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kCclAYqx5Ggai0x5NpgA2FsrVyudX4CxRRu/ikW8818=; b=Y55j1f0s45zRvhQwoDO/fFARlNYv1sIKPHfwAcCB/MJPN9Y6xrXhuPIxXqSKDZ50IN srBaMK8hsNAR4wIFUu9Mec++C/I0Mh+8RZO/wl8IcOv7W+z/VsD7vXl6XULJ2X+H5fOP ipvJfwDS1N/MdtSrWSXZ1lCKzVsg8iglYbfudBR7lkqBd5RNWW0faYRqlwXsEvtu5goZ G9/S5fcXZrHw0Nmg+YR1I42aK3X+FTWBBWjlLjrpGCjJq8GRB5aAystMh8QRc6kBbalg MfHeuqlnDjA9QlpUXYRPYmJuNHJoeCkOon8RRSB0af23k8iyQDveh/VVjE15lRhhDI9Z 1OkQ== X-Gm-Message-State: AFeK/H00sJ5YuyntVXqLJNgG8JcvC/gGTXOZ09VgAyrxcPBlwQ0XISg1Y25Vz3y8gE53XC93Htk= X-Received: by 10.99.117.85 with SMTP id f21mr21800714pgn.143.1490015692066; Mon, 20 Mar 2017 06:14:52 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:51 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:05 +0800 Message-Id: <1490015485-53685-2-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 01/21] Hisilicon/UpdateFdtDxe: fix memory overflow issue X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The size of the updated DTB file may be increased, so we need to allocate more memory than the original DTB size,or memory overflow may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li Reviewed-by: Leif Lindholm --- Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c index 8586e33..699a820 100644 --- a/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c +++ b/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.c @@ -112,7 +112,7 @@ EFIAPI UpdateFdt ( Size = (UINTN)fdt_totalsize ((VOID*)(PcdGet64(FdtFileAddress))); NewFdtBlobSize = Size + ADD_FILE_LENGTH; - Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(Size), &NewFdtBlobBase); + Status = gBS->AllocatePages (AllocateAnyPages, EfiRuntimeServicesData, EFI_SIZE_TO_PAGES(NewFdtBlobSize), &NewFdtBlobBase); if (EFI_ERROR (Status)) { return EFI_OUT_OF_RESOURCES; From patchwork Mon Mar 20 13:11:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95530 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936192qgd; Mon, 20 Mar 2017 06:15:40 -0700 (PDT) X-Received: by 10.107.1.16 with SMTP id 16mr29476558iob.44.1490015740103; Mon, 20 Mar 2017 06:15:40 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id t28si17762871ioe.54.2017.03.20.06.15.39; Mon, 20 Mar 2017 06:15:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9506963E83; Mon, 20 Mar 2017 13:15:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 00C8263E88; Mon, 20 Mar 2017 13:15:12 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id F40BC63E7D; Mon, 20 Mar 2017 13:14:56 +0000 (UTC) Received: from mail-pg0-f49.google.com (mail-pg0-f49.google.com [74.125.83.49]) by lists.linaro.org (Postfix) with ESMTPS id 310BE63E74 for ; Mon, 20 Mar 2017 13:14:55 +0000 (UTC) Received: by mail-pg0-f49.google.com with SMTP id n190so77326894pga.0 for ; Mon, 20 Mar 2017 06:14:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pejj/z7kbi999QrOEihdGxqYHgivx28RjY4P4I2MW1g=; b=Joa+/JRgIpbxNweIi1Zk9ZsNXi3+fBXJHAni913uVdheTe+H+O05Grajt8yGYc+uYz aoIJc/UOdKVrFdw+WXu3UqqIdSOQbTNt6gVPdRGC3W7DIg2Eh/rPAGQyRuBECJG5zNj0 elcaqJoRqge3qALesrKMR0DYMN+oYyhsUV6VBXmqeOcVWIKXq5T/9dyLURzfSujgh21r NFdhtMCH04A53dYkGWHAtjs3V320BvPCNl9ZTM/OigJepfxz9BItL6mS471XuvRVlIDz 07xQ37V8//Z73Dcy4NHOwY9wUh6O/oFrLde+zZXsZhvMtEEEym/uIV58uNhjSOxKro2w PlkA== X-Gm-Message-State: AFeK/H2O3SlzgcEi2LKMSG7kdJXHt1ROIRXpHjzRsmo1z77Uu+p6IezVCoLuktpPvxOadueiF3iwag== X-Received: by 10.84.253.15 with SMTP id z15mr40573542pll.142.1490015694473; Mon, 20 Mar 2017 06:14:54 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:54 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:06 +0800 Message-Id: <1490015485-53685-3-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , shaochangliang , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 02/21] Hisilicon/PCIe: Fix the probability of I350 enumeration fail issue. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The I350 Hilink state is not stable, so we need to modify the rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: shaochangliang Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..3bad240 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -23,6 +23,9 @@ #include #define PCIE_SYS_REG_OFFSET 0x1000 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; @@ -470,6 +473,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i*0x4, \ + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); From patchwork Mon Mar 20 13:11:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95531 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936331qgd; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) X-Received: by 10.36.36.142 with SMTP id f136mr10560351ita.0.1490015758209; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id x195si1935763itx.90.2017.03.20.06.15.57; Mon, 20 Mar 2017 06:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id EDB6863E7F; Mon, 20 Mar 2017 13:15:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 55DA963E77; Mon, 20 Mar 2017 13:15:19 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9FA0A63E8B; Mon, 20 Mar 2017 13:15:16 +0000 (UTC) Received: from mail-pg0-f50.google.com (mail-pg0-f50.google.com [74.125.83.50]) by lists.linaro.org (Postfix) with ESMTPS id 76EDE63E74 for ; Mon, 20 Mar 2017 13:14:57 +0000 (UTC) Received: by mail-pg0-f50.google.com with SMTP id t143so11445116pgb.2 for ; Mon, 20 Mar 2017 06:14:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dZ+qAxsV8lgrVL8JOfxS0tv/oNfk9RG76x5ti1rk3o4=; b=sXLMKWYwrr7rCcq7Wlja5+Ppzp7osSUzH1OXkZ60t9GG7FoYsLKVvkBOL9d1u+Bl7P k3QnvwHylmDtAEiQEcAsVmz/J6cbpVbQnaOXWX6SzMYYTDiP8+J7sAf5hYe5ScKbPByx puHy0ZKgQMZWo1aNb0/4EciMvHPACC770C4D0U1Ft3J6ZLF/O5OHgJTVXEkUwfkAU4wF Sqnz7Wlz4ZZqld6000NX1W0fMmxu5tjGRvsO1DAEKCT2THD7O+9hf8qADfXS4snGbEe7 W2Rv98/D7um41Tu5JyuVknEl6NCU0/y9K2M2dANTI6yRn8sxmmXPNDu3aCXJaSYV1QfE tNGw== X-Gm-Message-State: AFeK/H0qC5DvJmH/y1VANOkZwjZ0wB5YugtNMDo8GhL+vACGxLfsFigR143NC4UFl8olAK0gqUXzYA== X-Received: by 10.84.128.75 with SMTP id 69mr5233316pla.111.1490015696720; Mon, 20 Mar 2017 06:14:56 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:56 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:07 +0800 Message-Id: <1490015485-53685-4-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 03/21] Hisilicon: disable RC Option Rom X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The M3(the corprocessor)PCIe driver will read Option Rom header durning enumeration, this opration will cause a completion error when there is no device inserted to the RC port, and the Option rom is uesless now. So we need to disable the RC Option Rom. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 3bad240..57699e0 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -904,6 +904,44 @@ void PcieConfigContextHi1610(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) return; } +UINT32 SysRegRead(UINT32 SocType, UINT32 HostBridgeNum, UINT32 Port, UINTN Reg) +{ + UINT32 Value; + if (SocType == 0x1610) { + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + Reg, Value); + } else { + //PCIE_APB_SLVAE_BASE is for 660,and each PCIe Ccontroller has the same APB_SLVAE_BASE + //in the same hostbridge. + RegRead(PCIE_APB_SLVAE_BASE[HostBridgeNum] + Reg, Value); + } + return Value; +} + +VOID +DisableRcOptionRom ( + UINT32 soctype, + UINT32 HostBridgeNum, + UINT32 Port, + PCIE_PORT_TYPE PcieType +) +{ + UINT32 Value = 0; + if (PcieType == PCIE_ROOT_COMPLEX) { + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value |= BIT2; //cs2 enable + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG); + Value &= ~BIT0; //disable option rom + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_EP_PCI_CFG_HDR12_REG, Value); + + Value = SysRegRead(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG); + Value &= ~BIT2; //cs2 disable + SysRegWrite(soctype, HostBridgeNum, Port, PCIE_SYS_REG_OFFSET + PCIE_SYS_CTRL21_REG, Value); + } + return; +} + EFI_STATUS EFIAPI PciePortInit ( @@ -964,6 +1002,8 @@ PciePortInit ( /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); + /* Disable RC Option Rom */ + DisableRcOptionRom(soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { From patchwork Mon Mar 20 13:11:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95532 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936496qgd; Mon, 20 Mar 2017 06:16:18 -0700 (PDT) X-Received: by 10.55.103.10 with SMTP id b10mr23981813qkc.207.1490015778612; Mon, 20 Mar 2017 06:16:18 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id z21si5376352qkb.50.2017.03.20.06.16.18; Mon, 20 Mar 2017 06:16:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 410BD63E8B; Mon, 20 Mar 2017 13:16:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A6E9363E80; Mon, 20 Mar 2017 13:15:23 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6544B63E8C; Mon, 20 Mar 2017 13:15:18 +0000 (UTC) Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by lists.linaro.org (Postfix) with ESMTPS id E4DC063E77 for ; Mon, 20 Mar 2017 13:14:59 +0000 (UTC) Received: by mail-pf0-f181.google.com with SMTP id e129so27016308pfh.0 for ; Mon, 20 Mar 2017 06:14:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3eI1vrJ+w4Be8sQaNEn623uVD7hXpSN9IdD1G1n/VIo=; b=U4B7k7qp/lZJOI5myFwB614XZS4CXiRZtb1FpLjgj56NiRZR2vRsi20HZcvIQEJIWL bqbiq4mvxSMXIE5TT9ooZ4uQnrlY9UQR1bK5YK4u2u6Xc6T4GbyXmTpW2WproCOoHUsf p/Gsf6GBJ0O4CqHutENduFh2m7vyVEjhD1sVZagtQZ/VQ6x/q/cD7yy+b3Na/ouc3VN9 P+iHOsNCKr2qcjHu5WiCtEckfqyR2C/8FNBHSC/t4Rel59TPlk3vk0kQVd6UWFkPjcVt iNm1wsjmpNig1rTO8zoDusz/1+zqsJdPlm6ZZJNfyYePs+9jMh/ZAmg5x9ShmOyEnusA tamA== X-Gm-Message-State: AFeK/H3d+u0BzMOK7R3s3Z43LLc0Gi2oj5A0m3RTS9jn3nj2k1izIgjtIR772uyPmr+6LZAy4Rc= X-Received: by 10.98.160.193 with SMTP id p62mr33095385pfl.67.1490015699124; Mon, 20 Mar 2017 06:14:59 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:14:58 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:08 +0800 Message-Id: <1490015485-53685-5-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 04/21] Hisilicon: Add reconfig lane number feature X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" In some cases, the PCIe device may close part of lanes in config state of LTSSM, the hip06 RC should reconfig lane number and try to linkup again. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 121 ++++++++++++++++++++- Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 3 + 2 files changed, 122 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 57699e0..b45d54f 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -42,6 +42,7 @@ extern PCIE_DRIVER_CFG gastr_pcie_driver_cfg; extern PCIE_IATU gastr_pcie_iatu_cfg; extern PCIE_IATU_VA mPcieIatuTable; +EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg); VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value) { RegWrite((UINT64)mPcieIntCfg.RegResource[Port] + Offset, Value); @@ -152,8 +153,123 @@ VOID PcieRxValidCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, BOOLEAN } } } +/* + * The ltssm register is assigned in an asynchronous way, the value + * of register may not right in metastable state. + * Read the register twice to get stable value. + */ +VOID PcieGetLtssmValue ( + UINT32 HostBridgeNum, + UINT32 Port, + UINT32* Value +) +{ + UINT32 ValueA; + UINT32 ValueB = 0; + UINT32 Count; + + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueA); + ValueA = ValueA & PCIE_LTSSM_STATE_MASK; + + Count = 0; + while (Count < 2) { + + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SYS_REG_OFFSET + PCIE_SYS_STATE4_REG, ValueB); + ValueB = ValueB & PCIE_LTSSM_STATE_MASK; + + /* Get the same state in continuous two times*/ + if (ValueA == ValueB) { + break; + } + + /* If the second value not equel to the first, + * we return the second one as the stable + */ + ValueA = ValueB; + Count++; + } + + *Value = ValueB; + + return; + +} + +/* + * In some cases, the PCIe device may close part of lanes in + * config state of LTSSM, the hip06 RC should reconfig lane num + * and try to linkup again. + */ +VOID PcieReconfigLaneNum ( + UINT32 soctype, + UINT32 HostBridgeNum, + UINT32 Port, + PCIE_DRIVER_CFG *PcieCfg +) +{ + EFI_STATUS Status; + UINT32 LtssmStatus; + UINT32 RegVal; + UINT32 LoopCnt = 0; + UINT32 LaneNumCnt = 0; + PCIE_PORT_WIDTH PortWidth = PcieCfg->PortInfo.PortWidth; + + // 500 * 200us = 100ms, so it takes 100 ms must to reconfig lane numbers + while (LoopCnt < 500) { + + /* + * The minimum lanenum is 1, no need to try any more. + */ + if (PortWidth <= 1) { + DEBUG((DEBUG_ERROR, "PcieReconfigLanenum PortWidth <= 1 !\n")); + return; + } + + /* + * Check the lane num config state is normal or not. + */ + PcieGetLtssmValue(HostBridgeNum, Port, &LtssmStatus); + if ((LtssmStatus == PCIE_LTSSM_CFG_LANENUM_ACPT) || (LtssmStatus == PCIE_LTSSM_CFG_COMPLETE)) { + LaneNumCnt++; + } else if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + PcieGetLtssmValue(HostBridgeNum, Port, &LtssmStatus); + if (LtssmStatus == PCIE_LTSSM_LINKUP_STATE) { + break; + } + } else { + LaneNumCnt = 0; + } + + /* + * The lane num config state is abnormal, need to reconfig + * the lane num and try to establish link again. + */ + if (LaneNumCnt > 5) { + /* Disable LTSSM */ + RegRead(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + RegVal &= ~(BIT11); + RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_CTRL_7_REG, RegVal); + PcieCfg->PortInfo.PortWidth = (PCIE_PORT_WIDTH)((UINT8)PcieCfg->PortInfo.PortWidth >> 1); + + Status = PciePortInit(soctype, HostBridgeNum, PcieCfg); + if(EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "PcieReconfigLanenum HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); + } + return; + } + + LoopCnt++; + /* Pcie 3.0 Spec,part 4.2.6.3.4.1: the Upstream Lanes are permitted + * delay up to 1 ms before transitioning to Configuration.Lanenum.Accept. + * So the delay time 200 us * 5(LanNumCnt) = 1ms, not beyond the reasonable range. + */ + MicroSecondDelay(200); + } + + return ; +} -EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) +EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, PCIE_DRIVER_CFG *PcieCfg) { PCIE_CTRL_7_U pcie_ctrl7; UINT32 Value = 0; @@ -168,6 +284,7 @@ EFI_STATUS PcieEnableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) Value |= BIT11|BIT30|BIT31; RegWrite(PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + 0x1114, Value); (VOID)PcieRxValidCtrl(soctype, HostBridgeNum, Port, 1); + PcieReconfigLaneNum(soctype, HostBridgeNum, Port, PcieCfg); return EFI_SUCCESS; } else @@ -1005,7 +1122,7 @@ PciePortInit ( /* Disable RC Option Rom */ DisableRcOptionRom(soctype, HostBridgeNum, PortIndex, PcieCfg->PortInfo.PortType); /* assert LTSSM enable */ - (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex); + (VOID)PcieEnableItssm(soctype, HostBridgeNum, PortIndex, PcieCfg); if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { //PCIe will still work even if performance tuning fails, //and there is warning message inside the function to print diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index 539d567..b750910 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -8982,6 +8982,7 @@ typedef union tagIepMsiCtrlIntStatus #define PCIE_SYS_CTRL28_REG (PCI_SYS_BASE + 0x1c4) #define PCIE_SYS_CTRL29_REG (PCI_SYS_BASE + 0x1c8) #define PCIE_SYS_CTRL54_REG (PCI_SYS_BASE + 0x274) +#define PCIE_SYS_STATE4_REG (PCI_SYS_BASE + 0x31C) #define PCIE_SYS_STATE5_REG (PCI_SYS_BASE + 0x30) #define PCIE_SYS_STATE6_REG (PCI_SYS_BASE + 0x34) #define PCIE_SYS_STATE7_REG (PCI_SYS_BASE + 0x38) @@ -12694,6 +12695,8 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE3_REG (PCIE_SUBCTRL_BASE + 0x6814) #define PCIE_SUBCTRL_SC_PCIE0_SYS_STATE4_REG (PCIE_SUBCTRL_BASE + 0x6818) #define PCIE_LTSSM_STATE_MASK (0x3f) +#define PCIE_LTSSM_CFG_LANENUM_ACPT 0x0a +#define PCIE_LTSSM_CFG_COMPLETE 0x0b #define PCIE_LTSSM_LINKUP_STATE (0x11) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS0_REG (PCIE_SUBCTRL_BASE + 0x6880) #define PCIE_SUBCTRL_SC_PCIE0_AXI_MSTR_OOO_WR_STS1_REG (PCIE_SUBCTRL_BASE + 0x6884) From patchwork Mon Mar 20 13:11:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95533 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp936954qgd; Mon, 20 Mar 2017 06:17:19 -0700 (PDT) X-Received: by 10.55.162.204 with SMTP id l195mr23853559qke.272.1490015838952; Mon, 20 Mar 2017 06:17:18 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Mon, 20 Mar 2017 06:15:01 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.14.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:01 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:09 +0800 Message-Id: <1490015485-53685-6-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 05/21] Hisilicon D02/D03/D05: update uefi version to rock1.6 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D05/D05.dsc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index b611579..3f2ea31 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -145,7 +145,7 @@ gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000 gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000 gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI 16.08 RC1" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D02 UEFI ROCK1.6" gHisiTokenSpaceGuid.PcdSystemProductName|L"D02" gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary" diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 9c73494..b44a5a3 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -170,7 +170,7 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI 16.12 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 UEFI ROCK1.6" gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 2877da0..b17903c 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -188,7 +188,7 @@ gHisiTokenSpaceGuid.PcdIsMPBoot|1 gHisiTokenSpaceGuid.PcdSocketMask|0x3 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.12 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI ROCK1.6" gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" From patchwork Mon Mar 20 13:11:10 2017 Content-Type: text/plain; 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Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li Reviewed-by: Graeme Gregory --- Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c index 41f5692..98be4dc 100644 --- a/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c +++ b/Chips/Hisilicon/Drivers/AcpiPlatformDxe/EthMac.c @@ -442,6 +442,27 @@ static EFI_STATUS ProcessDSDT( return EFI_SUCCESS; } +VOID +AcpiPlatformChecksum ( + IN UINT8 *Buffer, + IN UINTN Size + ) +{ + UINTN ChecksumOffset; + + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); + + // + // set checksum to 0 first + // + Buffer[ChecksumOffset] = 0; + + // + // Update checksum value + // + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); +} + EFI_STATUS EthMacInit(void) { EFI_STATUS Status; @@ -478,6 +499,7 @@ EFI_STATUS EthMacInit(void) ProcessDSDT(AcpiTableProtocol, TableHandle); AcpiTableProtocol->Close(TableHandle); + AcpiPlatformChecksum ((UINT8*)Table, Table->Length); } return EFI_SUCCESS; From patchwork Mon Mar 20 13:11:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95535 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937280qgd; Mon, 20 Mar 2017 06:18:01 -0700 (PDT) X-Received: by 10.107.182.134 with SMTP id g128mr27103363iof.141.1490015881867; Mon, 20 Mar 2017 06:18:01 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl index bcd31d6..8f38359 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Iort.asl @@ -205,8 +205,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -234,8 +234,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 From patchwork Mon Mar 20 13:11:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95538 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937662qgd; Mon, 20 Mar 2017 06:18:54 -0700 (PDT) X-Received: by 10.200.45.59 with SMTP id n56mr26202115qta.137.1490015934180; Mon, 20 Mar 2017 06:18:54 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id h20si12869096qte.87.2017.03.20.06.18.53; Mon, 20 Mar 2017 06:18:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C86C86071D; Mon, 20 Mar 2017 13:18:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 1F9BF63EA4; Mon, 20 Mar 2017 13:16:05 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D50F463EA4; Mon, 20 Mar 2017 13:15:59 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id CD32F63E86 for ; Mon, 20 Mar 2017 13:15:11 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id p189so42673890pfp.1 for ; Mon, 20 Mar 2017 06:15:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QOtvb2kz4xdpHUayQvUf5LyHnTxuI7R0B4iIG8jG6RY=; b=fV+jYE/Gvyp8o/6XRCH1nVD+enD04cQNoZ/gHGRzL3pwgFiLCckoSKGxNAI6WZ3OWi e7me3rF2iutjz6JjGBSlByRX4EbCRlRKX2wdiceErqwUvVUxDzRXLvnMtK1ELUH0a8bh qmREFiylBcE1+su9xblDQZ6apE43uThPVHsUPg71A/lSRhWEh5177I8M4G+CKmCSe2dC weTIDPu/ZkakQ9AmG9qxRq6wMaTUQ8KIrMcspBV4G9yl50QIGZd3TgbnUXFzMwAX4I15 XSrS9KFTPfsBZHLVhKpTm5qVyGZRNGGDC7OJpD2bjyBrhsKTlUI5BuL6A+qYkSKWb8IO SwyA== X-Gm-Message-State: AFeK/H0kLo73YRoDSmezq5n32zC+RhUFwbsc6i3gzkrZ38JkHqYGVbeASZ/pfwQdytAM1UIsdaQ= X-Received: by 10.99.149.66 with SMTP id t2mr31696274pgn.152.1490015711167; Mon, 20 Mar 2017 06:15:11 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:10 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:12 +0800 Message-Id: <1490015485-53685-9-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , wanglijun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 08/21] Hisilicon/D03: Fix IORT test in luvOS test fail X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" CPM should also be 1 when CCA is 1. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index 9a045b7..9295485 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -296,8 +296,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000000 @@ -325,8 +325,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000001 @@ -354,8 +354,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 From patchwork Mon Mar 20 13:11:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95537 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937520qgd; Mon, 20 Mar 2017 06:18:35 -0700 (PDT) X-Received: by 10.55.148.71 with SMTP id w68mr26141665qkd.268.1490015915486; Mon, 20 Mar 2017 06:18:35 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl index 61a3c33..50ccac1 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl @@ -406,8 +406,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000002 @@ -434,8 +434,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000004 @@ -463,8 +463,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000005 @@ -492,8 +492,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000006 @@ -520,8 +520,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 00000007 @@ -548,8 +548,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000a @@ -577,8 +577,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000c @@ -606,8 +606,8 @@ Read Allocate : 0 Override : 0 [0002] Reserved : 0000 -[0001] Memory Flags (decoded below) : 00 - Coherency : 0 +[0001] Memory Flags (decoded below) : 01 + Coherency : 1 Device Attribute : 0 [0004] ATS Attribute : 00000000 [0004] PCI Segment Number : 0000000d From patchwork Mon Mar 20 13:11:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95536 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937409qgd; Mon, 20 Mar 2017 06:18:19 -0700 (PDT) X-Received: by 10.107.62.68 with SMTP id l65mr31935046ioa.213.1490015899776; Mon, 20 Mar 2017 06:18:19 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id y126si10625587itf.109.2017.03.20.06.18.19; Mon, 20 Mar 2017 06:18:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2EEFA63E7B; Mon, 20 Mar 2017 13:18:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id BC4D463E9E; Mon, 20 Mar 2017 13:15:59 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C6E0563E89; Mon, 20 Mar 2017 13:15:55 +0000 (UTC) Received: from mail-pg0-f42.google.com (mail-pg0-f42.google.com [74.125.83.42]) by lists.linaro.org (Postfix) with ESMTPS id 57E4D63E74 for ; Mon, 20 Mar 2017 13:15:17 +0000 (UTC) Received: by mail-pg0-f42.google.com with SMTP id 21so44055320pgg.1 for ; Mon, 20 Mar 2017 06:15:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v4Q1H8d/RZ8d17xhiIPREIT3XnNFue0bBgxUXS0nqr8=; b=rgTDvLgd+HsN/rz7MknI6Ke8nwYnGogiwVN2bjJCh7ElJaCnQmW138wSTsmmIUw2Dt mJ/Q9AKPI2g6lQ3iX+D+NETUO2N3F+kDTE5EzJt3goDNqPP5UWUFULxMCqHdlAFyIAjs s0I32fk7y9UkjMTlw32BQveQavG8q5kHL6yoz+o3IcNOtQJ51HY4tXrBahR94kOED5bX 1YeCW0Cx/8hZKrk9tu8OLrUEiEKHSE7MiVzcq2Tpu+pUVKTiA1AtVK7wcIrdvrTLBF/C o4QA4ojZpW1MeTfSdJRLFXWGmCNML2h0s+H9VCELgl81CjqkoTEE+rfmNIuGuAKF5HzU Ylcw== X-Gm-Message-State: AFeK/H2NuerB1oiE6d12nXfbhuKkU+9a1SLqLFMS+q8sOBhB77GGfqrWZsRDpweTBsZdmjQu5nw= X-Received: by 10.98.54.196 with SMTP id d187mr33335539pfa.33.1490015716615; Mon, 20 Mar 2017 06:15:16 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:16 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:14 +0800 Message-Id: <1490015485-53685-11-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , wanglijun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 10/21] Hisilicon: Add Reset interface for block IO protocol X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Reset interface for block IO protocol to make it compliant with UEFI specification, or it will cause exception when the interface is called. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 12 ++++++++++++ Drivers/Block/ramdisk/ramdisk.c | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c index 544228a..d118a90 100644 --- a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -444,6 +444,17 @@ FvbGetBlockSize ( return Status; } +EFI_STATUS +EFIAPI +FvbReset( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +) +{ + return EFI_SUCCESS; +} + + /** Reads the specified number of bytes into a buffer from the specified block. @@ -921,6 +932,7 @@ FlashCreateInstance ( Instance->Size = FlashSize; Instance->BlockIoProtocol.Media = &Instance->Media; + Instance->BlockIoProtocol.Reset = FvbReset; Instance->Media.MediaId = MediaId; Instance->Media.BlockSize = BlockSize; Instance->Media.LastBlock = (FlashSize / BlockSize) - 1; diff --git a/Drivers/Block/ramdisk/ramdisk.c b/Drivers/Block/ramdisk/ramdisk.c index 21e090b..bd2607d 100644 --- a/Drivers/Block/ramdisk/ramdisk.c +++ b/Drivers/Block/ramdisk/ramdisk.c @@ -200,6 +200,17 @@ UINT8 TestSize(UINT32 ts) EFI_SYSTEM_TABLE BackupSystemTable; +EFI_STATUS +EFIAPI +RamDiskReset( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification +) +{ + return EFI_SUCCESS; +} + + /* * Entry point for RamDisk driver. */ @@ -274,6 +285,7 @@ EFI_STATUS InitializeRamDiskDriver( RamDiskDev->BlkIo.ReadBlocks = RamDiskReadBlocks; RamDiskDev->BlkIo.WriteBlocks = RamDiskWriteBlocks; RamDiskDev->BlkIo.FlushBlocks = RamDiskFlushBlocks; + RamDiskDev->BlkIo.Reset = RamDiskReset; RamDiskDev->DevicePath = DuplicateDevicePath((EFI_DEVICE_PATH*)&RamDiskDevicePath); From patchwork Mon Mar 20 13:11:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95539 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937824qgd; Mon, 20 Mar 2017 06:19:16 -0700 (PDT) X-Received: by 10.200.54.13 with SMTP id m13mr25080665qtb.214.1490015956343; Mon, 20 Mar 2017 06:19:16 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id z53si12859845qta.146.2017.03.20.06.19.15; Mon, 20 Mar 2017 06:19:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id D153663E86; Mon, 20 Mar 2017 13:19:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id EE4C0607F6; Mon, 20 Mar 2017 13:16:55 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E61DA607B8; Mon, 20 Mar 2017 13:16:34 +0000 (UTC) Received: from mail-pf0-f177.google.com (mail-pf0-f177.google.com [209.85.192.177]) by lists.linaro.org (Postfix) with ESMTPS id C22B363E8F for ; Mon, 20 Mar 2017 13:15:19 +0000 (UTC) Received: by mail-pf0-f177.google.com with SMTP id p189so42675486pfp.1 for ; Mon, 20 Mar 2017 06:15:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ndZojj+hI3dYtdjExew4/paU2pwYirB6AWbzHfXCeas=; b=HGAb8PMPnfBPWNNUHsB3om2haSv7s0wg9OJoBYGF/YpAXtYT2kniZB2HjI8mVSfXwK /fE21BUzxuEN1AtWuVZL/dCeCL/CBy8udwfXFrWgGL/hwb3N3fAz8eraoEIF8zdWlNg1 FFlR6j4MFevZMxFPt52jJXi4mC8r0rvcZmz+PjjdJd0+77v6aaa8UDlCZV4nahld/Nco /oMTT6McOrp8NIBMFV2GYv8CzMYR8e2UeGQakkDJfoW7irM4V6DYP01nfZqyIfWWUz6e /ho6JMq6RhY+1oV1B6tJN/8LUZfpbw70b+O/o36m1xgBymxy0XP/HOo/vKjVB8sTUVn9 2Ngg== X-Gm-Message-State: AFeK/H17jF45+jqpmMS1Ax4ERY0calizwLBBDObSbhiC8NGT7mt+0G+ypxn+P399DEzMexkUodo= X-Received: by 10.84.217.2 with SMTP id o2mr39952319pli.51.1490015718991; Mon, 20 Mar 2017 06:15:18 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:18 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:15 +0800 Message-Id: <1490015485-53685-12-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , wanglijun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 11/21] Hisilicon: Fix SCT PCIBusSupportTest error X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL/EFI_PCI_IO_PROTOCOL must returns EFI_INVALID_PARAMETER, change return value. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..30619f5 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -824,8 +824,8 @@ RootBridgeConstructor ( PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ - EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | \ - EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER; + EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + PrivateData->Attributes = PrivateData->Supports; Protocol->ParentHandle = HostBridgeHandle; @@ -1275,6 +1275,9 @@ RootBridgeIoPollMem ( return EFI_INVALID_PARAMETER; } + if (Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } // // No matter what, always do a single poll. // @@ -2010,7 +2013,10 @@ RootBridgeIoMap ( ) { DMA_MAP_OPERATION DmaOperation; - + if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || + Mapping == NULL) { + return EFI_INVALID_PARAMETER; + } if (Operation == EfiPciOperationBusMasterRead) { DmaOperation = MapOperationBusMasterRead; } else if (Operation == EfiPciOperationBusMasterWrite) { @@ -2245,6 +2251,11 @@ RootBridgeIoSetAttributes ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); + if((Attributes & (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED)) && + (ResourceBase == NULL || ResourceLength == NULL)) { + return EFI_INVALID_PARAMETER; + } + if (Attributes != 0) { if ((Attributes & (~(PrivateData->Supports))) != 0) { return EFI_UNSUPPORTED; From patchwork Mon Mar 20 13:11:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95540 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp937968qgd; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) X-Received: by 10.36.94.206 with SMTP id h197mr9224161itb.27.1490015975506; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 62si17668939ioz.249.2017.03.20.06.19.35; Mon, 20 Mar 2017 06:19:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id CF68B6086C; Mon, 20 Mar 2017 13:19:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 2900863EA2; Mon, 20 Mar 2017 13:16:59 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 6C01D60747; Mon, 20 Mar 2017 13:16:39 +0000 (UTC) Received: from mail-pg0-f47.google.com (mail-pg0-f47.google.com [74.125.83.47]) by lists.linaro.org (Postfix) with ESMTPS id 4CC9863E7A for ; Mon, 20 Mar 2017 13:15:22 +0000 (UTC) Received: by mail-pg0-f47.google.com with SMTP id n190so77332832pga.0 for ; Mon, 20 Mar 2017 06:15:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qoTwTcPYiWS7ZYKwwq9oNhp0Pk/wBtt8O7//z8hNlZ4=; b=lu67deqwC80HSz1G4sMOFtAkCHbS+CJYwxTVPbbgan6d7pmXYAj6DTVwMpfvaBsdcr 7Q1nAYp8HVUwM6TsNtjjK2LtV6fu1gC/NkVntnxnYzuJZV9K++67ottUOFGZfekp0xrx rrBH6R3OacdTeP6yjRuQhzPw617sglWmG7gdxknby7jQGH5GEBXvCWsOGEpZoPvRj8/O 2/fjUMdgDzbQzbHJj8/QW6UwqVcnP3IC5j02BjuO/uXnDtnCQ4KbACs2O3LR7nYVmG/f zmwUCppkC0FiSEnS/67G4wzJzpMC1xqGG+S7mxUBLsG7FUE4XTwf+BY7YVU1ogCdOQNC t1jA== X-Gm-Message-State: AFeK/H15f/V25qoEMFbYkPT0rAGG9bpcz2GW6pHzScawOYFWVUGOtSIdsmPz+d48RnY49bj7zOM= X-Received: by 10.84.233.205 with SMTP id m13mr13770035pln.49.1490015721361; Mon, 20 Mar 2017 06:15:21 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:20 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:16 +0800 Message-Id: <1490015485-53685-13-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 12/21] Hisilicon/D05: support the compatibility of kernel PCIe driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx). 1. add _OSC support 2. put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- .../Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 641 ++++++++++++++++----- 1 file changed, 508 insertions(+), 133 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index f9b4722..deca155 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -40,6 +40,49 @@ Scope(_SB) } } +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + // 1P NA PCIe2 Device (PCI2) { @@ -89,17 +132,43 @@ Scope(_SB) Device (RES2) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (0xf) } - } // Device(PCI2) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x2) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000 , 0x10000) //host bridge register space + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + + Device (R1NA) // reserve 1p NA ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87] + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + // 1p NB PCIe0 Device (PCI4) { @@ -149,30 +218,55 @@ Scope(_SB) Device (RES4) { Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0090000, // Min Base Address - 0x8a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) }) } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI4) + Device (RES4) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x4) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0090000, // Min Base Address + 0x8a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + // 1P NB PCI1 Device (PCI5) { @@ -219,31 +313,57 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES5) + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a0200000, // Min Base Address - 0x8a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI5) + + Device (RES5) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x5) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a0200000, // Min Base Address + 0x8a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI5) + } // 1P NB PCIe2 Device (PCI6) @@ -291,31 +411,58 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES6) + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00a0000, // Min Base Address - 0x8a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI6) + + Device (RES6) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x6) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00a0000, // Min Base Address + 0x8a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI6) + } + // 1P NB PCIe3 Device (PCI7) { @@ -362,31 +509,120 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RES7) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x8a00b0000, // Min Base Address - 0x8a00bffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) } + } // Device(PCI7) + Device (RES7) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x7) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a00b0000, // Min Base Address + 0x8a00bffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCI7) + } + + Device (R1NB) // reserve 1p NB ECAM resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 88-8f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8a8800000, // Min Base Address + 0x8a8ffffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 0-7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b0000000, // Min Base Address + 0x8b07fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus c0-c7] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8ac000000, // Min Base Address + 0x8ac7fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + QwordMemory ( //ECAM space for [bus 90-97] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x8b9000000, // Min Base Address + 0x8b97fffff, // Max Base Address + 0x0, // Translate + 0x800000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } + // 2P NA PCIe2 Device (PCIa) { @@ -433,31 +669,82 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESa) + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x600a00a0000, // Min Base Address - 0x600a00affff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (0xf) } + } // Device(PCIa) + + Device (RESa) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xa) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x600a00a0000, // Min Base Address + 0x600a00affff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (0xf) } - } // Device(PCIa) + } + + Device (R2NA) //reserve for 2p NA ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 10-1f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x64001000000, // Min Base Address + 0x64001ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (0xf) + } + } + // 2P NB PCIe0 Device (PCIc) { @@ -504,32 +791,57 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESc) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0090000, // Min Base Address - 0x700a009ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) - } + Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } } // Device(PCIc) + Device (RESc) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xc) // Unique ID + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //host bridge register space + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0090000, // Min Base Address + 0x700a009ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) + } + } //2P NB PCIe1 Device (PCId) { @@ -576,30 +888,93 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - Device (RESd) + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CRS, ResourceTemplate (){ //host bridge register space + QwordMemory ( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + } + PCI_OSC_SUPPORT() + Method (_STA, 0x0, NotSerialized) { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CID, "PNP0C02") // Motherboard reserved resource - Name (_CRS, ResourceTemplate (){ - QwordMemory ( - ResourceProducer, - PosDecode, - MinFixed, - MaxFixed, - NonCacheable, - ReadWrite, - 0x0, // Granularity - 0x700a0200000, // Min Base Address - 0x700a020ffff, // Max Base Address - 0x0, // Translate - 0x10000 // Length - ) - }) + Return (RBYV()) + } + } // Device(PCId) + + Device (RESd) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0xd) // Unique ID + Name (_CRS, ResourceTemplate (){ //host bridge register space + QwordMemory ( + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x700a0200000, // Min Base Address + 0x700a020ffff, // Max Base Address + 0x0, // Translate + 0x10000 // Length + ) + }) + Method (_STA, 0x0, NotSerialized) + { + Return (RBYV()) } + } + + Device (R2NB) //reserve for 2p NB ecam resource + { + Name (_HID, "PNP0C02") // Motherboard reserved resource + Name (_CRS, ResourceTemplate (){ + QwordMemory ( //ECAM space for [bus 20-2f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x74002000000, // Min Base Address + 0x74002ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + QwordMemory ( //ECAM space for [bus 30-3f] + ResourceConsumer, + PosDecode, + MinFixed, + MaxFixed, + NonCacheable, + ReadWrite, + 0x0, // Granularity + 0x78003000000, // Min Base Address + 0x78003ffffff, // Max Base Address + 0x0, // Translate + 0x1000000 // Length + ) + }) Method (_STA, 0x0, NotSerialized) { Return (RBYV()) } - } // Device(PCId) + } } From patchwork Mon Mar 20 13:11:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95541 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp938212qgd; Mon, 20 Mar 2017 06:20:15 -0700 (PDT) X-Received: by 10.107.132.196 with SMTP id o65mr27170790ioi.4.1490016015011; Mon, 20 Mar 2017 06:20:15 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id j196si10638451itc.57.2017.03.20.06.20.14; Mon, 20 Mar 2017 06:20:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8DF2063E74; Mon, 20 Mar 2017 13:20:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 6251660975; Mon, 20 Mar 2017 13:17:09 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E5F3360975; Mon, 20 Mar 2017 13:17:04 +0000 (UTC) Received: from mail-pg0-f43.google.com (mail-pg0-f43.google.com [74.125.83.43]) by lists.linaro.org (Postfix) with ESMTPS id 6080363E87 for ; Mon, 20 Mar 2017 13:15:24 +0000 (UTC) Received: by mail-pg0-f43.google.com with SMTP id 21so44056938pgg.1 for ; Mon, 20 Mar 2017 06:15:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LEz/R0qzkgPtVGaigwQWovTv8x5pSWUlSvm6uoOW4KM=; b=aGx9/GPFxhaRNaSFNp3kEM0OaMfmtWQk0Cmug+k0GUmsjQcrsqNoJCKD+N6ELa8Q0w 37v7aPoiMNrPZsSmfJTGTXroxmklb+BcmoGdwFxtpOD+CoNfagXWnM4pGDTam1CtKsuF lAWzUzwaChVgocanKkx2tgWx2T4n2uif+IZGg2Ypsvx16taRz6UpEb8Jb2azS3MprZQr N1jD8xOhAwtmK5f3CWQ3WvZKu2568euP8cVb+OyiGuiTKaEyjWa/DeMZB/IbEmI/E3uB 8zsxvEf+FfXbBx2UvD+3cDIusmy3B4HHJeecpyyEGb/MSgYZ31RQ0h4uI4GzQ/GWoiBG qRCA== X-Gm-Message-State: AFeK/H0uWHWo/S0KLYSyUo8ygA0m1VKNykEIeU5PLxsujg+usrApqVcKIMt56RwLrtA4ppu2idA= X-Received: by 10.98.16.137 with SMTP id 9mr32945049pfq.104.1490015723602; Mon, 20 Mar 2017 06:15:23 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:23 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:17 +0800 Message-Id: <1490015485-53685-14-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 13/21] Hisilicon/D03: support the compatibility of kernel PCIe driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" As the PCIe driver is updated in kernel 4.10, and it will read the PCIe resource in the PCIe device, so the resource description should also be put into the Device(PCIx). 1. add _OSC support 2. put the pcie resource description into the Device(PCIx), in order to compatible with kernel 4.10 PCIe driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: hensonwang Signed-off-by: Heyi Guo Signed-off-by: Yi Li Signed-off-by: Chenhui Sun --- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl | 182 ++++++++++----------- 1 file changed, 85 insertions(+), 97 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl index 573c0a3..8c768a7 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Pci.asl @@ -17,12 +17,55 @@ **/ //#include "ArmPlatform.h" +/* + See ACPI 6.1 Spec, 6.2.11, PCI Firmware Spec 3.0, 4.5 +*/ +#define PCI_OSC_SUPPORT() \ + Name(SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name(CTRL, Zero) /* PCI _OSC Control Field value */ \ + Method(_OSC,4) { \ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField(Arg3,0,CDW1) \ + CreateDWordField(Arg3,4,CDW2) \ + CreateDWordField(Arg3,8,CDW3) \ + /* Save Capabilities DWord2 & 3 */ \ + Store(CDW2,SUPP) \ + Store(CDW3,CTRL) \ + /* Only allow native hot plug control if OS supports: */ \ + /* ASPM */ \ + /* Clock PM */ \ + /* MSI/MSI-X */ \ + If(LNotEqual(And(SUPP, 0x16), 0x16)) { \ + And(CTRL,0x1E,CTRL) \ + }\ + \ + /* Do not allow native PME, AER */ \ + /* Never allow SHPC (no SHPC controller in this system)*/ \ + And(CTRL,0x10,CTRL) \ + If(LNotEqual(Arg1,One)) { /* Unknown revision */ \ + Or(CDW1,0x08,CDW1) \ + } \ + \ + If(LNotEqual(CDW3,CTRL)) { /* Capabilities bits were masked */ \ + Or(CDW1,0x10,CDW1) \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + Store(CTRL,CDW3) \ + Return(Arg3) \ + } Else { \ + Or(CDW1,4,CDW1) /* Unrecognized UUID */ \ + Return(Arg3) \ + } \ + } // End _OSC + Scope(_SB) { // PCIe Root bus Device (PCI0) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 0) // Segment of this Root complex Name(_BBN, 0) // Base Bus Number @@ -65,43 +108,22 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) + PCI_OSC_SUPPORT() + } // Device(PCI0) - Device (RES0) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Device (RES0) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x0) // Unique ID Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0090000 , 0x10000) + Memory32Fixed (ReadWrite, 0xa0090000, 0x10000) //host bridge register space }) - } - - OperationRegion(SCTR, SystemMemory, 0xa009131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } - } // Device(PCI0) - + } // PCIe Root bus Device (PCI1) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 1) // Segment of this Root complex Name(_BBN, 0xe0) // Base Bus Number @@ -144,44 +166,22 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - - Device (RES1) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa0200000 , 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa020131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) { - - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } + PCI_OSC_SUPPORT() } // Device(PCI1) + Device (RES1) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x1) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa0200000, 0x10000) //host bridge register space + }) + } // PCIe Root bus Device (PCI2) { - Name (_HID, "HISI0080") // PCI Express Root Bridge + Name (_HID, "PNP0A08") // PCI Express Root Bridge Name (_CID, "PNP0A03") // Compatible PCI Root Bridge Name(_SEG, 2) // Segment of this Root complex Name(_BBN, 0x80) // Base Bus Number @@ -224,38 +224,26 @@ Scope(_SB) }) // Name(RBUF) Return (RBUF) } // Method(_CRS) - - Device (RES2) - { - Name (_HID, "HISI0081") // HiSi PCIe RC config base address - Name (_CRS, ResourceTemplate (){ - Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) - }) - } - - OperationRegion(SCTR, SystemMemory, 0xa00a131c, 4) - Field(SCTR, AnyAcc, NoLock, Preserve) { - LSTA, 32, - } - Method(_DSM, 0x4, Serialized) { - If(LEqual(Arg0,ToUUID("6d30f553-836c-408e-b6ad-45bccc957949"))) - { - switch(ToInteger(Arg2)) - { - // Function 0: Return LinkStatus - case(0) { - Store (0, Local0) - Store (LSTA, Local0) - Return (Local0) - } - default { - } - } - } - // If not one of the function identifiers we recognize, then return a buffer - // with bit 0 set to 0 indicating no functions supported. - return(Buffer(){0}) - } + PCI_OSC_SUPPORT() } // Device(PCI2) + + Device (RES2) + { + Name (_HID, "HISI0081") // HiSi PCIe RC config base address + Name (_CID, "PNP0C02") // Motherboard reserved resource + Name (_UID, 0x2) // Unique ID + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xa00a0000, 0x10000) //host bridge register space + }) + } + Device (RESP) //reserve for ecam resource + { + Name (_HID, "PNP0C02") + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xb0000000, 0x2000000) //ECAM space for PCI0 [bus 00-1f] + Memory32Fixed (ReadWrite, 0xbe000000, 0x2000000) //ECAM space for PCI1 [bus e0-ff] + Memory32Fixed (ReadWrite, 0xa8000000, 0x2000000) //ECAM space for PCI2 [bus 80-9f] + }) + } } From patchwork Mon Mar 20 13:11:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95542 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp938485qgd; Mon, 20 Mar 2017 06:20:55 -0700 (PDT) X-Received: by 10.36.170.68 with SMTP id y4mr9221236iti.7.1490016055018; Mon, 20 Mar 2017 06:20:55 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i143si17768832ioa.204.2017.03.20.06.20.54; Mon, 20 Mar 2017 06:20:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 675C76086C; Mon, 20 Mar 2017 13:20:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 988E063EB2; Mon, 20 Mar 2017 13:17:14 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 9958F63EAF; Mon, 20 Mar 2017 13:17:09 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id 1855B63E95 for ; Mon, 20 Mar 2017 13:15:27 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id 20so17971507pfk.2 for ; Mon, 20 Mar 2017 06:15:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8tohqtvpirly/d1nH41SpwD7BhMSGg2hRl0ieBgKkAI=; b=qklxdAisbjyCU5BqVPPWcfUohJTn3ay+5MubR2UjnQkFDn6Kw/TaR5r7rMP5654zg9 b87LcweU1gRSxflIZzi9P21oIJibEwa/x2lC9WRkDsPN5bw8ZsMOX/S1wVA4COzvm0DI PK5GV1zCa/kF911LphvVSGtHBhW8PRO3UqDQCcWtZF2kippd5l2bX1pLL5YpwUF/ysT5 qEOcMnc0k8fJ0RQ7eBhFnjIQILXBEM60Upwj9dm8hSznKZWKaNBUilDTAbh1uSybr8lS q8c64F5Z68UI1xUN7HYWZ/afgUpumtXNVdDxnQH+V1v8DnHNJ85anRjFamXWalUux7kF Mspg== X-Gm-Message-State: AFeK/H0/VMItZYZnB5KNuMsgw7RHBBbRl8bM7g7DYPccpNwHpL2bvqau97F8llVle84XX1BT97s= X-Received: by 10.99.150.1 with SMTP id c1mr31458221pge.160.1490015726394; Mon, 20 Mar 2017 06:15:26 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:25 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:18 +0800 Message-Id: <1490015485-53685-15-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , Heyi Guo , wanghuiqiang@huawei.com, sunchenhui@huawei.com, Chenhui Sun Subject: [Linaro-uefi] [Linaro-uefi v1 14/21] Hisilicon/D03/D05: Change Monotonic Driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Fix SCT BootServicesTest\MiscBootServicesTest error, GetNextMonotonicCount() gets the high 32-bit after reset at EFI_TPL_APPLICATION,EFI_TPL_CALLBACK,EFI_TPL_NOTIFY. Monotonic Driver is switched from EmbeddedPkg to MdeModulePkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 1 - Platforms/Hisilicon/D05/D05.fdf | 2 +- 4 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index b44a5a3..81b8271 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -372,7 +372,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3302ec9..3102f94 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -167,7 +167,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index b17903c..78c7913 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -492,7 +492,6 @@ } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf index bdfb211..5a646f3 100644 --- a/Platforms/Hisilicon/D05/D05.fdf +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -171,7 +171,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf - INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf From patchwork Mon Mar 20 13:11:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95543 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp938673qgd; Mon, 20 Mar 2017 06:21:22 -0700 (PDT) X-Received: by 10.107.183.66 with SMTP id h63mr26933708iof.60.1490016082168; Mon, 20 Mar 2017 06:21:22 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 89si17767538iot.153.2017.03.20.06.21.21; Mon, 20 Mar 2017 06:21:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A5A2F60975; Mon, 20 Mar 2017 13:21:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id CACC263E94; Mon, 20 Mar 2017 13:17:19 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C1D5963E96; Mon, 20 Mar 2017 13:17:14 +0000 (UTC) Received: from mail-pg0-f54.google.com (mail-pg0-f54.google.com [74.125.83.54]) by lists.linaro.org (Postfix) with ESMTPS id C87AD63E96 for ; Mon, 20 Mar 2017 13:15:29 +0000 (UTC) Received: by mail-pg0-f54.google.com with SMTP id 21so44058132pgg.1 for ; Mon, 20 Mar 2017 06:15:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Bcy5WZpusIuAHD0OakjOnOy6FTxssAjeRANhi1VzL4=; b=fnRu3Q22bgCTn115ZD0Qxd763EFhejOprStvqtEQBnWt0nsevzk7noZEFZ0DmP2lMc 1rTKttCHkAX70cTuPN3XA6qevXiWAEqTYf8IKnKgpjODuHgcBA1n3pw+NgHBzubto+G/ x6rjsLThJbuIZaDUTbU2LRxaWLUkhxR3ivEf66WrR32CSitZfC362L7htCLRk/ZrZci0 Y5xpYQAZJFdlgHhIa5yIjgp7+h+Oc0L5DTf5kMtSiqCdrQQ0Wy7HNQjowF++vVGD61Yr o32khgpfvzXXZTZdtb0aaCqA6jFW1x65E+N4nAqJyIjFiGeJMTwA+D7csgcuZtzmznns vK+Q== X-Gm-Message-State: AFeK/H2XoDVV8gh/nbQiw5DuY3yYk/QNLIN7cgiyo3gOpBoLemks0zThFu/G2EYH67D6zW5Xr5s= X-Received: by 10.99.238.69 with SMTP id n5mr31067255pgk.38.1490015729045; Mon, 20 Mar 2017 06:15:29 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:28 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:19 +0800 Message-Id: <1490015485-53685-16-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , wanglijun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 15/21] Hisilicon: switch to generic watchdog driver X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" SP805 watchdog driver does not really take effect the platforms, so we switch to generic watchdog driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wanglijun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Platforms/Hisilicon/D02/Pv660D02.dsc | 2 +- Platforms/Hisilicon/D02/Pv660D02.fdf | 2 +- Platforms/Hisilicon/D03/D03.dsc | 2 +- Platforms/Hisilicon/D03/D03.fdf | 2 +- Platforms/Hisilicon/D05/D05.dsc | 2 +- Platforms/Hisilicon/D05/D05.fdf | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Platforms/Hisilicon/D02/Pv660D02.dsc b/Platforms/Hisilicon/D02/Pv660D02.dsc index 3f2ea31..2a70974 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.dsc +++ b/Platforms/Hisilicon/D02/Pv660D02.dsc @@ -339,7 +339,7 @@ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf ArmPkg/Drivers/TimerDxe/TimerDxe.inf - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf # diff --git a/Platforms/Hisilicon/D02/Pv660D02.fdf b/Platforms/Hisilicon/D02/Pv660D02.fdf index 406b501..b430712 100644 --- a/Platforms/Hisilicon/D02/Pv660D02.fdf +++ b/Platforms/Hisilicon/D02/Pv660D02.fdf @@ -196,7 +196,7 @@ READ_LOCK_STATUS = TRUE INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf # # FAT filesystem + GPT/MBR partitioning diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 81b8271..24c88a3 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -396,7 +396,7 @@ ArmPkg/Drivers/TimerDxe/TimerDxe.inf - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf # #ACPI diff --git a/Platforms/Hisilicon/D03/D03.fdf b/Platforms/Hisilicon/D03/D03.fdf index 3102f94..b254667 100644 --- a/Platforms/Hisilicon/D03/D03.fdf +++ b/Platforms/Hisilicon/D03/D03.fdf @@ -189,7 +189,7 @@ READ_LOCK_STATUS = TRUE INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf # # FAT filesystem + GPT/MBR partitioning diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 78c7913..9de1be6 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -516,7 +516,7 @@ ArmPkg/Drivers/TimerDxe/TimerDxe.inf - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf # #ACPI diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf index 5a646f3..987427c 100644 --- a/Platforms/Hisilicon/D05/D05.fdf +++ b/Platforms/Hisilicon/D05/D05.fdf @@ -193,7 +193,7 @@ READ_LOCK_STATUS = TRUE INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf # # FAT filesystem + GPT/MBR partitioning From patchwork Mon Mar 20 13:11:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95544 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp938891qgd; Mon, 20 Mar 2017 06:21:55 -0700 (PDT) X-Received: by 10.200.37.199 with SMTP id f7mr27755398qtf.147.1490016115765; Mon, 20 Mar 2017 06:21:55 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id l76si12871973qkh.86.2017.03.20.06.21.55; Mon, 20 Mar 2017 06:21:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7888160A25; Mon, 20 Mar 2017 13:21:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 04B0063E9A; Mon, 20 Mar 2017 13:17:26 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id B85FF63EB3; Mon, 20 Mar 2017 13:17:19 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 44A2F63E99 for ; Mon, 20 Mar 2017 13:15:32 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id p189so42677870pfp.1 for ; Mon, 20 Mar 2017 06:15:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aFOgIMtLHOMPhFjZROwz/y3tJ0VcK+fTnddyJ8RyNiQ=; b=FNYQoDaQkN+bXJFYdDUzyJvS0tWMhbIR3EQJ72iHrlr3phfVAwQZn7NUdNHX4NktrA dtGsLAre5Rt+q6V7S2G5HVCEnJq6+Bhy5bLBwcY14FrXDq4yJRLA3z4mUs6C6kZFT8H0 DNHe0R+qTm6ifUrG94iiaiq9nv3OrlSc3a93GaDOEbRYbCaMm4t6nI4w4yp7dlL/IjIZ KTjFPNC7XRe+ZuCett710wYeNvbf2MkWmwdTICBzXXOjgckNMPRKZTatKHKr7cX5juAt kPTEIlkDNNK8qeKcP54cV41WqJjphH78nmOqhPw4mrRZ+VCxj0tJjaLL5oLiAdnq3SkV VJFQ== X-Gm-Message-State: AFeK/H0rwlyUBnCsrytnHpDl7QjaDalvedyTMuDQsCQJowibb7RDXHPxNrHEcxePuYtuA+Yo1tM= X-Received: by 10.99.253.5 with SMTP id d5mr30866433pgh.47.1490015731473; Mon, 20 Mar 2017 06:15:31 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:31 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:20 +0800 Message-Id: <1490015485-53685-17-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Ming Huang , Chenhui Sun , Yi Li , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 16/21] Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 29 ++++++++++++++-------- .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 +++++++++-- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..2289d4b 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType = 1; Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ - Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin = RootBridgeInstance->IoBase; Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 32; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > 0xFFFFFFFF) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 0; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag = 0; Ptr->SpecificFlag = 6; Ptr->AddrSpaceGranularity = 64; - /* This is PCIE Device Bus which start address is the low 32bit of mem base*/ + /* PCIE device Bar should be based on PciRegionBase */ Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF); + (RootBridgeInstance->PciRegionBase & 0xFFFFFFFFFFFFFFFF); Ptr->AddrRangeMax = 0; Ptr->AddrTranslationOffset = \ (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; diff --git a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 30619f5..7902831 100644 --- a/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2312,8 +2312,19 @@ RootBridgeIoConfiguration ( PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index = 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->IoBase; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin = (PrivateData->ResAllocNode[Index].Base - PrivateData->MemBase) + + (PrivateData->PciRegionBase & 0xFFFFFFFFFFFFFFFF); + } + Configuration.SpaceDesp[Index].AddrRangeMax = Configuration.SpaceDesp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; } } From patchwork Mon Mar 20 13:11:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95545 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp938912qgd; Mon, 20 Mar 2017 06:22:00 -0700 (PDT) X-Received: by 10.200.39.194 with SMTP id x2mr25312394qtx.139.1490016120290; Mon, 20 Mar 2017 06:22:00 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Mon, 20 Mar 2017 06:15:33 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:33 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:21 +0800 Message-Id: <1490015485-53685-18-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 17/21] D03: update acpi tables to ACPI6.1 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li Reviewed-by: Graeme Gregory --- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc | 20 ++-- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc | 39 +++---- Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc | 30 +++--- .../Hi1610/Hi1610AcpiTables/MadtHi1610.aslc | 120 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 2 +- 6 files changed, 110 insertions(+), 109 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc index ed47a44..7e5c8ef 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Mcfg.aslc @@ -11,7 +11,7 @@ #include #include "Hi1610Platform.h" -#define ACPI_5_0_MCFG_VERSION 0x1 +#define ACPI_6_1_MCFG_VERSION 0x1 #pragma pack(1) typedef struct @@ -21,28 +21,28 @@ typedef struct UINT8 ucStartBusNum; UINT8 ucEndBusNum; UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; typedef struct { EFI_ACPI_DESCRIPTION_HEADER Header; UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG; typedef struct { - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[3]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[3]; +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; #pragma pack() -EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc index 72cc66c..d5bc299 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Facs.aslc @@ -19,15 +19,15 @@ #include -EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc index 5307041..025b42c 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Fadt.aslc @@ -22,16 +22,16 @@ #include #include -EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -65,23 +65,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify }; // diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc index 922f5c3..4c1050a 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Gtdt.aslc @@ -23,9 +23,9 @@ #include #include -#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE #define GTDT_GLOBAL_FLAGS_LEVEL 0 // Note: We could have a build flag that switches between memory mapped/non-memory mapped timer @@ -36,9 +36,9 @@ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #endif -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0 #define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) @@ -46,18 +46,18 @@ #pragma pack (1) typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1610_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () -EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 0, // UINT32 Reserved @@ -72,14 +72,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc index 7bebe8f..f302dd6 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/MadtHi1610.aslc @@ -37,20 +37,20 @@ #pragma pack (1) typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[1]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; #pragma pack () -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -59,65 +59,65 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // ACPI v5.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet32 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0xC6000000), + EFI_ACPI_6_1_GIC_ITS_INIT(0,0xC6000000), } }; diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 5a810ec..0e65b1f 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -35,7 +35,7 @@ #define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ - 3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ } From patchwork Mon Mar 20 13:11:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95549 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp939826qgd; Mon, 20 Mar 2017 06:24:18 -0700 (PDT) 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wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 18/21] D05: update acpi tables to ACPI6.1 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc | 16 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc | 2 +- Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 152 ++++---- Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc | 39 +- Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc | 42 +- .../Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 424 ++++++++++----------- Chips/Hisilicon/Include/Library/AcpiNextLib.h | 26 +- 9 files changed, 358 insertions(+), 353 deletions(-) diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc index bdf42c0..b47cfec 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc @@ -40,7 +40,7 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), MCFG_VERSION, 0x00, // Checksum will be updated at runtime diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc index 89cc4a9..0845d66 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc @@ -19,25 +19,25 @@ #pragma pack(1) typedef struct { UINT8 Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; +} EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE; typedef struct { - EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; - EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; + EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER Header; + EFI_ACPI_6_1_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT]; -} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE; +} EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE; #pragma pack() // // System Locality Information Table // Please modify all values in Slit.h only. // -EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { +EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = { { { - EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE), - EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, + EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_SYSTEM_LOCALITY_INFORMATION_TABLE), + EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc index e1c26c9..0cda870 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Spcr.aslc @@ -25,7 +25,7 @@ #define SPCR_FLOW_CONTROL_NONE 0 STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { - ARM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), // UINT8 InterfaceType; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc index 00c2015..b448a29 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -24,9 +24,9 @@ // EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { { - {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, + {EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE), - EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, + EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, @@ -43,83 +43,83 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = { // Memory Affinity // { - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), + EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001), }, { - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000), //GICC Affinity Processor 0 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000), //GICC Affinity Processor 1 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000), //GICC Affinity Processor 2 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000), //GICC Affinity Processor 3 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000), //GICC Affinity Processor 4 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000), //GICC Affinity Processor 5 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000), //GICC Affinity Processor 6 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000), //GICC Affinity Processor 7 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000), //GICC Affinity Processor 8 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000), //GICC Affinity Processor 9 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000), //GICC Affinity Processor 10 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000), //GICC Affinity Processor 11 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000), //GICC Affinity Processor 12 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000), //GICC Affinity Processor 13 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000), //GICC Affinity Processor 14 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000), //GICC Affinity Processor 15 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000), //GICC Affinity Processor 16 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000), //GICC Affinity Processor 17 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000), //GICC Affinity Processor 18 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000), //GICC Affinity Processor 19 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000), //GICC Affinity Processor 20 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000), //GICC Affinity Processor 21 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000), //GICC Affinity Processor 22 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000), //GICC Affinity Processor 23 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000), //GICC Affinity Processor 24 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000), //GICC Affinity Processor 25 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000), //GICC Affinity Processor 26 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000), //GICC Affinity Processor 27 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000), //GICC Affinity Processor 28 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000), //GICC Affinity Processor 29 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000), //GICC Affinity Processor 30 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000), //GICC Affinity Processor 31 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000), //GICC Affinity Processor 32 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000), //GICC Affinity Processor 33 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000), //GICC Affinity Processor 34 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000), //GICC Affinity Processor 35 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000), //GICC Affinity Processor 36 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000), //GICC Affinity Processor 37 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000), //GICC Affinity Processor 38 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000), //GICC Affinity Processor 39 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000), //GICC Affinity Processor 40 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000), //GICC Affinity Processor 41 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000), //GICC Affinity Processor 42 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000), //GICC Affinity Processor 43 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000), //GICC Affinity Processor 44 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000), //GICC Affinity Processor 45 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000), //GICC Affinity Processor 46 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000), //GICC Affinity Processor 47 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000), //GICC Affinity Processor 48 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000), //GICC Affinity Processor 49 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000), //GICC Affinity Processor 50 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000), //GICC Affinity Processor 51 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000), //GICC Affinity Processor 52 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000), //GICC Affinity Processor 53 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000), //GICC Affinity Processor 54 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000), //GICC Affinity Processor 55 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000), //GICC Affinity Processor 56 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000), //GICC Affinity Processor 57 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000), //GICC Affinity Processor 58 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000), //GICC Affinity Processor 59 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000), //GICC Affinity Processor 60 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000), //GICC Affinity Processor 61 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000), //GICC Affinity Processor 62 + EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000) //GICC Affinity Processor 63 }, }; diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc index 2908b24..a5e2e7d 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc @@ -19,15 +19,15 @@ #include -EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc index 152410b..67fa4d6 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc @@ -22,16 +22,16 @@ #include #include -EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -65,23 +65,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0 // UINT64 Hypervisor Vendor Identify }; // diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc index b472828..16e2c6a 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc @@ -22,43 +22,31 @@ #include #include "Hi1616Platform.h" -#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT -#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE -#define GTDT_GLOBAL_FLAGS_LEVEL 0 - -// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer -#ifdef SYSTEM_TIMER_BASE_ADDRESS - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) -#else - #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) - #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF -#endif - -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0 +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY #define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) #pragma pack (1) typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[HI1616_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () -EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), - SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0xFFFFFFFFFFFFFFFF, // UINT64 CntControl Base PhysicalAddress 0, // UINT32 Reserved FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags @@ -71,14 +59,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc index b83c221..169ee72 100644 --- a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc +++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -40,20 +40,20 @@ #pragma pack (1) typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[64]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[8]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[64]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; #pragma pack () -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -62,216 +62,216 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of - // ACPI v5.1). + // ACPI v6.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), - FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID_TA(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID_TA(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID_TA(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID_TA(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID_TA(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID_TA(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID_TA(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID_TA(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID_TA(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID_TA(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID_TA(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID_TA(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID_TA(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID_TA(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 16, 16, PLATFORM_GET_MPID_TB(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 17, 17, PLATFORM_GET_MPID_TB(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 18, 18, PLATFORM_GET_MPID_TB(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 19, 19, PLATFORM_GET_MPID_TB(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 21, 21, PLATFORM_GET_MPID_TB(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 22, 22, PLATFORM_GET_MPID_TB(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 23, 23, PLATFORM_GET_MPID_TB(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 24, 24, PLATFORM_GET_MPID_TB(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 25, 25, PLATFORM_GET_MPID_TB(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 26, 26, PLATFORM_GET_MPID_TB(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 27, 27, PLATFORM_GET_MPID_TB(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 29, 29, PLATFORM_GET_MPID_TB(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 30, 30, PLATFORM_GET_MPID_TB(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 31, 31, PLATFORM_GET_MPID_TB(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 32, 32, PLATFORM_GET_MPID_TA_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 33, 33, PLATFORM_GET_MPID_TA_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 34, 34, PLATFORM_GET_MPID_TA_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 35, 35, PLATFORM_GET_MPID_TA_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 37, 37, PLATFORM_GET_MPID_TA_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 38, 38, PLATFORM_GET_MPID_TA_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 39, 39, PLATFORM_GET_MPID_TA_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 40, 40, PLATFORM_GET_MPID_TA_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 41, 41, PLATFORM_GET_MPID_TA_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 42, 42, PLATFORM_GET_MPID_TA_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 43, 43, PLATFORM_GET_MPID_TA_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 45, 45, PLATFORM_GET_MPID_TA_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 46, 46, PLATFORM_GET_MPID_TA_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 47, 47, PLATFORM_GET_MPID_TA_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 48, 48, PLATFORM_GET_MPID_TB_2(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 49, 49, PLATFORM_GET_MPID_TB_2(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 50, 50, PLATFORM_GET_MPID_TB_2(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 51, 51, PLATFORM_GET_MPID_TB_2(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 53, 53, PLATFORM_GET_MPID_TB_2(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 54, 54, PLATFORM_GET_MPID_TB_2(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 55, 55, PLATFORM_GET_MPID_TB_2(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x2C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 56, 56, PLATFORM_GET_MPID_TB_2(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x300000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 57, 57, PLATFORM_GET_MPID_TB_2(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 58, 58, PLATFORM_GET_MPID_TB_2(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x380000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 59, 59, PLATFORM_GET_MPID_TB_2(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x3C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x400000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 61, 61, PLATFORM_GET_MPID_TB_2(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x440000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 62, 62, PLATFORM_GET_MPID_TB_2(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x480000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 63, 63, PLATFORM_GET_MPID_TB_2(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase), + FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x4C0000 /* GicRBase */, 0), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a - EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b - EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a - EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b - EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a - EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b - EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a - EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b + EFI_ACPI_6_1_GIC_ITS_INIT(0,0x4C000000), //peri a + EFI_ACPI_6_1_GIC_ITS_INIT(1,0x6C000000), //peri b + EFI_ACPI_6_1_GIC_ITS_INIT(2,0xC6000000), //dsa a + EFI_ACPI_6_1_GIC_ITS_INIT(3,0x8C6000000), //dsa b + EFI_ACPI_6_1_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a + EFI_ACPI_6_1_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b + EFI_ACPI_6_1_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a + EFI_ACPI_6_1_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b } }; diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h index 0e65b1f..60f9925 100644 --- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h @@ -19,9 +19,9 @@ #ifndef __ACPI_NEXT_LIB_H__ #define __ACPI_NEXT_LIB_H__ -#define EFI_ACPI_6_0_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ { \ - EFI_ACPI_6_0_GIC_ITS, sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\ } @@ -32,21 +32,37 @@ GicRBase, GicRlength \ } -#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ { \ 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ ACPIProcessorUID, Flags, ClockDomain \ } -#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT( \ +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ { \ - 1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ EFI_ACPI_RESERVED_QWORD \ } +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ + { \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ + } + + #pragma pack(1) // // Define the number of each table type. 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Mon, 20 Mar 2017 06:15:38 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:38 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:23 +0800 Message-Id: <1490015485-53685-20-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 19/21] D02: update acpi tables to ACPI6.1 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc | 8 +- Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc | 39 ++++---- Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc | 30 +++--- Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc | 126 ++++++++++++------------ Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc | 20 ++-- Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc | 6 +- 7 files changed, 119 insertions(+), 118 deletions(-) diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc index 93b2c90..3a8313a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dbg2.aslc @@ -32,7 +32,7 @@ typedef struct { EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader; - EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS]; UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS]; CHAR8 NamespaceString[NAMESPACE_STRING_SIZE]; } EFI_ACPI_DBG2_DDI_STRUCT; @@ -47,7 +47,7 @@ typedef struct { EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_DEBUG_PORT_2_TABLE_SIGNATURE, + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE, EFI_ACPI_DEBUG_PORT_2_TABLE, EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION ), @@ -72,10 +72,10 @@ EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = { }, { { - EFI_ACPI_6_0_SYSTEM_MEMORY, + EFI_ACPI_6_1_SYSTEM_MEMORY, 32, 0, - EFI_ACPI_6_0_BYTE, + EFI_ACPI_6_1_BYTE, FixedPcdGet64(PcdSerialRegisterBase) } }, diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc index 72cc66c..d5bc299 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Facs.aslc @@ -19,15 +19,15 @@ #include -EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature - sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length +EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = { + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32 Signature + sizeof (EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE), // UINT32 Length 0xA152, // UINT32 HardwareSignature 0, // UINT32 FirmwareWakingVector 0, // UINT32 GlobalLock 0, // UINT32 Flags 0, // UINT64 XFirmwareWakingVector - EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; + EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION, // UINT8 Version; { EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[0] EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0[1] EFI_ACPI_RESERVED_BYTE }, // UINT8 Reserved0[2] diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc index 5907c65..76b281f 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Fadt.aslc @@ -23,16 +23,16 @@ #include #include -EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { ARM_ACPI_HEADER ( - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE, - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION ), 0, // UINT32 FirmwareCtrl 0, // UINT32 Dsdt EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 - EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile 0, // UINT16 SciInt 0, // UINT32 SmiCmd 0, // UINT8 AcpiEnable @@ -66,23 +66,24 @@ EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { 0, // UINT8 Century 0, // UINT16 IaPcBootArch 0, // UINT8 Reserved1 - EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE ResetReg 0, // UINT8 ResetValue - EFI_ACPI_5_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags - EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision 0, // UINT64 XFirmwareCtrl 0, // UINT64 XDsdt - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk - NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg - NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS, // EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE SleepStatusReg + 0, // UINT64 Hypervisor Vendor Identify }; // diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc index f677feb..054eb2c 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Gtdt.aslc @@ -23,9 +23,9 @@ #include #include -#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT #define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 -#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE #define GTDT_GLOBAL_FLAGS_LEVEL 0 // Note: We could have a build flag that switches between memory mapped/non-memory mapped timer @@ -36,9 +36,9 @@ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF #endif -#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE #define GTDT_TIMER_LEVEL_TRIGGERED 0 -#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY #define GTDT_TIMER_ACTIVE_HIGH 0 #define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) @@ -46,18 +46,18 @@ #pragma pack (1) typedef struct { - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; - EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT]; -} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES; + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[PV660_WATCHDOG_COUNT]; +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES; #pragma pack () -EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { { ARM_ACPI_HEADER( - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES, - EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES, + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION ), SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress 0, // UINT32 Reserved @@ -72,14 +72,14 @@ EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = { 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress #ifdef notyet PV660_WATCHDOG_COUNT, // UINT32 PlatformTimerCount - sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset }, { - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0), 0, 0, 0, 0), - EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( - //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) + EFI_ACPI_6_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( + //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER) 0, 0, 0, 0) } #else /* !notyet */ diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc index 4edb95d..d83584a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Madt.aslc @@ -36,20 +36,20 @@ #pragma pack (1) typedef struct { - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_5_1_GIC_STRUCTURE GicInterfaces[16]; - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicITS[4]; -} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[16]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[4]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; #pragma pack () -EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { { ARM_ACPI_HEADER ( - EFI_ACPI_1_0_APIC_SIGNATURE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE, - EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION ), // // MADT specific fields @@ -58,68 +58,68 @@ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { 0, // Flags }, { - // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, + // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase, // GsivId, GicRBase, Mpidr) // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of // ACPI v5.1). // The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses // the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table. - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */), - EFI_ACPI_5_1_GICC_STRUCTURE_INIT( - 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), - FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 0, 0, PLATFORM_GET_MPID(0, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x100000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 1, 1, PLATFORM_GET_MPID(0, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x130000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 2, 2, PLATFORM_GET_MPID(0, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x160000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 3, 3, PLATFORM_GET_MPID(0, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x190000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 4, 4, PLATFORM_GET_MPID(1, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1C0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 5, 5, PLATFORM_GET_MPID(1, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x1F0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 6, 6, PLATFORM_GET_MPID(1, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x220000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 7, 7, PLATFORM_GET_MPID(1, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x250000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 8, 8, PLATFORM_GET_MPID(2, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x280000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 9, 9, PLATFORM_GET_MPID(2, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2B0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 10, 10, PLATFORM_GET_MPID(2, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x2E0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 11, 11, PLATFORM_GET_MPID(2, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x310000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 12, 12, PLATFORM_GET_MPID(3, 0), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x340000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 13, 13, PLATFORM_GET_MPID(3, 1), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x370000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 14, 14, PLATFORM_GET_MPID(3, 2), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3A0000 /* GicRBase */, 0), + EFI_ACPI_6_1_GICC_STRUCTURE_INIT( + 15, 15, PLATFORM_GET_MPID(3, 3), EFI_ACPI_6_1_GIC_ENABLED, 23, FixedPcdGet64 (PcdGicInterruptInterfaceBase), + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicDistributorBase) + 0x3D0000 /* GicRBase */, 0), }, - EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 0x4), { - EFI_ACPI_6_0_GIC_ITS_INIT(0,0x8C000000), // pc - EFI_ACPI_6_0_GIC_ITS_INIT(1,0xC6000000), // dsa - EFI_ACPI_6_0_GIC_ITS_INIT(2,0xA3000000), // m3 - EFI_ACPI_6_0_GIC_ITS_INIT(3,0xB7000000) // pcie + EFI_ACPI_6_1_GIC_ITS_INIT(0,0x8C000000), // pc + EFI_ACPI_6_1_GIC_ITS_INIT(1,0xC6000000), // dsa + EFI_ACPI_6_1_GIC_ITS_INIT(2,0xA3000000), // m3 + EFI_ACPI_6_1_GIC_ITS_INIT(3,0xB7000000) // pcie } }; diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc index f783534..69b7b38 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Mcfg.aslc @@ -13,7 +13,7 @@ #include #include "Pv660Platform.h" -#define ACPI_5_0_MCFG_VERSION 0x1 +#define ACPI_6_1_MCFG_VERSION 0x1 #pragma pack(1) typedef struct @@ -23,28 +23,28 @@ typedef struct UINT8 ucStartBusNum; UINT8 ucEndBusNum; UINT32 Reserved2; -}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE; +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE; typedef struct { EFI_ACPI_DESCRIPTION_HEADER Header; UINT64 Reserved1; -}EFI_ACPI_5_0_MCFG_TABLE_CONFIG; +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG; typedef struct { - EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; - EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2]; -}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg; + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[2]; +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE; #pragma pack() -EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg= { { { - EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, - sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), - ACPI_5_0_MCFG_VERSION, + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE), + ACPI_6_1_MCFG_VERSION, 0x00, // Checksum will be updated at runtime {EFI_ACPI_ARM_OEM_ID}, EFI_ACPI_ARM_OEM_TABLE_ID, diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc index 7eef5f9..5a9ce4a 100644 --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Spcr.aslc @@ -24,7 +24,7 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { //Header; ARM_ACPI_HEADER( - EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION ), @@ -32,10 +32,10 @@ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, //Reserved1[3]; //BaseAddress; { - EFI_ACPI_6_0_SYSTEM_MEMORY, + EFI_ACPI_6_1_SYSTEM_MEMORY, 32, 0, - EFI_ACPI_6_0_BYTE, + EFI_ACPI_6_1_BYTE, FixedPcdGet64(PcdSerialRegisterBase) }, EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, //InterruptType; From patchwork Mon Mar 20 13:11:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95546 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp939184qgd; Mon, 20 Mar 2017 06:22:37 -0700 (PDT) X-Received: by 10.237.44.229 with SMTP id g92mr25653234qtd.204.1490016157303; Mon, 20 Mar 2017 06:22:37 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. 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Mon, 20 Mar 2017 06:15:41 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:41 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:24 +0800 Message-Id: <1490015485-53685-21-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: Yi Li , Chenhui Sun , wangljjun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 20/21] Hisilicon: Fixed SCT MediaAccessTest\BlockIOProtocolTest issue X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" EFI_BLOCK_IO_PROTOCOL.ReadBlocks - ReadBlocks() returns valid parameter Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: wangljjun Signed-off-by: Heyi Guo Signed-off-by: Yi Li --- Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c | 12 ++++++++++-- Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 2 +- Drivers/Block/ramdisk/ramdisk.c | 18 +++++++++++------- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c index 91c0733..5d5f3fa 100644 --- a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c +++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashBlockIoDxe.c @@ -29,10 +29,14 @@ FlashBlockIoReadBlocks ( OUT VOID* Buffer ) { - FLASH_INSTANCE* Instance; - EFI_STATUS Status; + FLASH_INSTANCE* Instance; + EFI_STATUS Status; + EFI_BLOCK_IO_MEDIA *Media; + UINTN IoAlign; Instance = INSTANCE_FROM_BLKIO_THIS(This); + Media = This->Media; + IoAlign = Media->IoAlign; DEBUG ((EFI_D_INFO, "FlashBlockIoReadBlocks(MediaId=0x%x, Lba=%ld, BufferSize=0x%x bytes (%d kB), BufferPtr @ 0x%08x)\n", MediaId, Lba, BufferSizeInBytes, Buffer)); @@ -44,6 +48,10 @@ FlashBlockIoReadBlocks ( { Status = EFI_MEDIA_CHANGED; } + else if (IoAlign > 0 && (((UINTN) Buffer & (IoAlign - 1)) != 0)) + { + Status = EFI_INVALID_PARAMETER; + } else { Status = FlashReadBlocks (Instance, Lba, BufferSizeInBytes, Buffer); diff --git a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c index d118a90..c719d53 100644 --- a/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -1125,7 +1125,7 @@ FlashReadBlocks ( // We must have some bytes to read if (BufferSizeInBytes == 0) { - return EFI_BAD_BUFFER_SIZE; + return EFI_SUCCESS; } // The size of the buffer must be a multiple of the block size diff --git a/Drivers/Block/ramdisk/ramdisk.c b/Drivers/Block/ramdisk/ramdisk.c index bd2607d..14c2f0e 100644 --- a/Drivers/Block/ramdisk/ramdisk.c +++ b/Drivers/Block/ramdisk/ramdisk.c @@ -481,14 +481,18 @@ STATIC EFI_STATUS RamDiskReadBlocks( Media = This->Media; - if(BufferSize % Media->BlockSize != 0) + if (Media->MediaId != MediaId) { + return EFI_MEDIA_CHANGED; + } + if (BufferSize % Media->BlockSize != 0) { return EFI_BAD_BUFFER_SIZE; - - if(LBA > Media->LastBlock) - return EFI_DEVICE_ERROR; - - if(LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock) - return EFI_DEVICE_ERROR; + } + if (BufferSize == 0) { + return EFI_SUCCESS; + } + if (LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock) { + return EFI_INVALID_PARAMETER; + } RamDiskDev = RAM_DISK_FROM_THIS(This); RamDiskLBA = RamDiskDev->Start + MultU64x32(LBA,Media->BlockSize); From patchwork Mon Mar 20 13:11:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chenhui Sun X-Patchwork-Id: 95548 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp939571qgd; Mon, 20 Mar 2017 06:23:37 -0700 (PDT) X-Received: by 10.36.43.194 with SMTP id h185mr10515043ita.121.1490016217790; Mon, 20 Mar 2017 06:23:37 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id v1si10673457itb.117.2017.03.20.06.23.37; Mon, 20 Mar 2017 06:23:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 4AFCA60A3C; Mon, 20 Mar 2017 13:23:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A6A2763EB1; Mon, 20 Mar 2017 13:17:52 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BAB0663E81; Mon, 20 Mar 2017 13:17:37 +0000 (UTC) Received: from mail-pg0-f51.google.com (mail-pg0-f51.google.com [74.125.83.51]) by lists.linaro.org (Postfix) with ESMTPS id 12D7463E83 for ; Mon, 20 Mar 2017 13:15:45 +0000 (UTC) Received: by mail-pg0-f51.google.com with SMTP id n190so77337503pga.0 for ; Mon, 20 Mar 2017 06:15:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uD2oHLcFBtP1vqWqJQs6S8juyOjlCkW7ZrAs//3++rU=; b=Ip0+C4WY/43v/Ms1+N0oHI3veQn9RFkf3k3DdhzCQAZUQstBMIisOQviLKnjcS30NT QHt3g/cANboNHwLZFH4VynqPftu8DPA3w4dZPsynBpNbuIG5Bd+m5ZSq/6t9jb79DHD5 nYQOehyaUrQr5WeQMnqdlwDoe3znHgEEhUzgPp3UyShtRjJguzz9zuWGcF9yCZ6c8rM+ tdA66RcKuMVgE7PikMjZ92NWxRRqkFCFSEUpbyCkEC2781u1UPqhC3Op6hAa1FHb0IyT Xn7tfzyR6rtxy9yHMYvgGdDeXCicewqyzFIZTcA/yxHa53EfxX5i5V9milhCn+8cIq3Z ekrg== X-Gm-Message-State: AFeK/H0B4/YZ0PyZaSo18Tez51F+m/v+672LFFwsp/lqKSfJY/55bixykX0cMPorJxedNyByJuM= X-Received: by 10.98.103.75 with SMTP id b72mr32625074pfc.105.1490015744254; Mon, 20 Mar 2017 06:15:44 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a62sm33573787pgc.60.2017.03.20.06.15.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 20 Mar 2017 06:15:43 -0700 (PDT) From: Chenhui Sun To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org Date: Mon, 20 Mar 2017 21:11:25 +0800 Message-Id: <1490015485-53685-22-git-send-email-chenhui.sun@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> References: <1490015485-53685-1-git-send-email-chenhui.sun@linaro.org> Cc: huangming , Chenhui Sun , sunchenhui@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [Linaro-uefi v1 21/21] Hisilicon D03/D05: get boot option from BMC X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Support the feature that BIOS get boot option from BMC and put it in the first boot order. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: huangming Signed-off-by: Chenhui Sun --- .../Library/PlatformIntelBdsLib/IntelBdsPlatform.c | 310 +++++++++++++++++++++ .../PlatformIntelBdsLib/PlatformIntelBdsLib.inf | 2 + Platforms/Hisilicon/D03/D03.dsc | 1 - Platforms/Hisilicon/D05/D05.dsc | 1 - 4 files changed, 312 insertions(+), 2 deletions(-) diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c index efefeb6..7bba2f4 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/IntelBdsPlatform.c @@ -19,18 +19,108 @@ **/ +#include #include #include +#include +#include #include #include +#include #include #include +#include #include #include #include #include "IntelBdsPlatform.h" +#define BOOT_OPTION_BOOT_FLAG_VALID 1 +#define BOOT_OPTION_BOOT_FLAG_INVALID 0 + +typedef enum { + NoOverride = 0x0, + ForcePxe, + ForceDefaultHardDisk, + ForceDefaultHardDiskSafeMode, + ForceDefaultDiagnosticPartition, + ForceDefaultCD, + ForceSetupUtility, + ForceRemoteRemovableMedia, + ForceRemoteCD, + ForcePrimaryRemoteMedia, + ForceRemoteHardDisk = 0xB, + ForcePrimaryRemovableMedia = 0xF +} BOOT_DEVICE_SELECTOR; + +// Get System Boot Option data structure +// +typedef struct { + UINT8 ParameterVersion :4; + UINT8 Reserved1 :4; + UINT8 ParameterSelector :7; + UINT8 ParameterValid :1; + // + // Boot Flags Data 1 + // + UINT8 Reserved2 :5; + UINT8 BiosBootType :1; + UINT8 Persistent :1; + UINT8 BootFlagsValid :1; + // + // Boot Flags Data 2 + // + UINT8 LockResetBtn :1; + UINT8 ScreenBlank :1; + UINT8 BootDeviceSelector :4; + UINT8 LockKeyboard :1; + UINT8 ClearCmos :1; + // + // Boot Flags Data 3 + // + UINT8 ConsoleRedirectionControl :2; + UINT8 LockSleepBtn :1; + UINT8 UserPasswordByPass :1; + UINT8 Reserved3 :1; + UINT8 FirmwareVerbosity :2; + UINT8 LockPowerBtn :1; + // + // Boot Flags Data 4 + // + UINT8 MuxControlOverride :3; + UINT8 ShareModeOverride :1; + UINT8 Reserved4 :4; + // + // Boot Flags Data 5 + // + UINT8 DeviceInstanceSelector :5; + UINT8 Reserved5 :3; +} IPMI_GET_BOOT_OPTION; + +#define EFI_ACPI_PCI_SAS_DEVICE_PATH_GUID \ + { \ + 0xA0441D0, 0x0, 0x0, {0x1, 0x1, 0x06, 0x0, 0x0, 0x0, 0x1, 0x1 } \ + } + +typedef struct{ + UINT8 NodeType; + UINT8 NodeSubType; + EFI_GUID *Guid; + UINTN DeviceType; +}OemDeviceType; + +OemDeviceType DeviceTypeArray[]={ + {MESSAGING_DEVICE_PATH, MSG_SATA_DP, NULL, BBS_TYPE_HARDDRIVE}, + {MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, &((EFI_GUID)EFI_ACPI_PCI_SAS_DEVICE_PATH_GUID), BBS_TYPE_HARDDRIVE}, + {MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, &((EFI_GUID)DEVICE_PATH_MESSAGING_SAS), BBS_TYPE_HARDDRIVE}, + {MESSAGING_DEVICE_PATH, MSG_USB_DP, NULL, BBS_TYPE_USB}, + {MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP, NULL, BBS_TYPE_EMBEDDED_NETWORK}, + {MEDIA_DEVICE_PATH, MEDIA_CDROM_DP, NULL, BBS_TYPE_CDROM} +}; + +EFI_STATUS IpmiCmdGetSysBootOptions(OUT IPMI_GET_BOOT_OPTION *BootOption ); +EFI_STATUS IpmiCmdSetSysBootOptions(IPMI_GET_BOOT_OPTION *BootOption ); //3CEF354A-3B7A-4519-AD70-72A134698311 GUID gEblFileGuid = {0x3CEF354A, 0x3B7A, 0x4519, {0xAD, 0x70, @@ -361,6 +451,223 @@ AddOutput ( ReportText)); } +UINT16 DeviceTypeFoundInFileSystemHandles (EFI_DEVICE_PATH_PROTOCOL *DevicePathIn) +{ + EFI_STATUS Status; + EFI_HANDLE *FileSystemHandles; + UINTN NumberFileSystemHandles; + UINTN Index; + EFI_DEVICE_PATH_PROTOCOL *DevicePathGot; + EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol; + CHAR16* DevicePathTxtIn = NULL; + CHAR16* DevicePathTxtGot = NULL; + EFI_DEVICE_PATH_PROTOCOL *DevicePathNode = NULL; + UINT16 Result = BBS_TYPE_UNKNOWN; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleFileSystemProtocolGuid, + NULL, + &NumberFileSystemHandles, + &FileSystemHandles + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(%d):error!\n", __FUNCTION__,__LINE__)); + return BBS_TYPE_UNKNOWN; + } + + Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a(%d):error!\n", __FUNCTION__,__LINE__)); + return BBS_TYPE_UNKNOWN; + } + DevicePathTxtIn = DevicePathToTextProtocol->ConvertDevicePathToText (DevicePathIn, TRUE, TRUE); + + for (Index = 0; Index < NumberFileSystemHandles; Index++) { + DevicePathGot = DevicePathFromHandle (FileSystemHandles[Index]); + DevicePathTxtGot = DevicePathToTextProtocol->ConvertDevicePathToText (DevicePathGot, TRUE, TRUE); + + if (StrnCmp(DevicePathTxtIn, DevicePathTxtGot, StrLen(DevicePathTxtIn)) == 0) { + DevicePathNode = DevicePathGot; + while (!IsDevicePathEnd (DevicePathNode)) { + if ((DevicePathNode->Type == MEDIA_DEVICE_PATH) && (DevicePathNode->SubType == MEDIA_CDROM_DP)) { + Result = BBS_TYPE_CDROM; + break; + } + DevicePathNode = NextDevicePathNode (DevicePathNode); + } + } + + if (Result != BBS_TYPE_UNKNOWN) { + break; + } + } + + if (NumberFileSystemHandles != 0) { + FreePool (FileSystemHandles); + } + if (DevicePathTxtGot != NULL) { + FreePool (DevicePathTxtGot); + } + if (DevicePathTxtIn != NULL) { + FreePool (DevicePathTxtIn); + } + + return Result; +} + +UINT16 UniGetEfiDeviceType( + IN BDS_COMMON_OPTION *BootOption +) +{ + EFI_DEVICE_PATH_PROTOCOL* DevicePathNode; + UINTN DeviceCnt; + UINTN Loop; + VENDOR_DEVICE_PATH *Vender; + UINT16 Result; + + DeviceCnt = sizeof (DeviceTypeArray) / sizeof (OemDeviceType); + DevicePathNode = BootOption->DevicePath; + while (!IsDevicePathEnd (DevicePathNode)) { + for (Loop = 0; Loop < DeviceCnt; Loop++) { + if ((DevicePathType (DevicePathNode) == DeviceTypeArray[Loop].NodeType) && + (DevicePathSubType (DevicePathNode) == MSG_VENDOR_DP)) { + Vender = (VENDOR_DEVICE_PATH*)(DevicePathNode); + if (CompareMem(&(Vender->Guid), DeviceTypeArray[Loop].Guid, sizeof(EFI_GUID)) == 0) { + return DeviceTypeArray[Loop].DeviceType; + } + } else if ((DevicePathType (DevicePathNode) == MESSAGING_DEVICE_PATH) && + (DevicePathSubType (DevicePathNode) == MSG_USB_DP)) { + Result = DeviceTypeFoundInFileSystemHandles (BootOption->DevicePath); + if (Result != BBS_TYPE_UNKNOWN) { + return Result; + } + } else if ((DevicePathType (DevicePathNode) == DeviceTypeArray[Loop].NodeType) && + (DevicePathSubType (DevicePathNode) == DeviceTypeArray[Loop].NodeSubType)) { + return DeviceTypeArray[Loop].DeviceType; + } + } + + DevicePathNode = NextDevicePathNode (DevicePathNode); + } + + return BBS_TYPE_UNKNOWN; +} + +EFI_STATUS GetBmcBootOptionsSetting (IPMI_GET_BOOT_OPTION *BmcBootOpt) +{ + EFI_STATUS Status = EFI_SUCCESS; + + Status = IpmiCmdGetSysBootOptions (BmcBootOpt); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a - %d Get iBMC BootOpts %r!\n", __FUNCTION__, __LINE__,Status)); + return Status; + } + + if (BmcBootOpt->BootFlagsValid != BOOT_OPTION_BOOT_FLAG_VALID) { + DEBUG ((DEBUG_ERROR, "%a - %d BootFlags is Invalid !\n", __FUNCTION__, __LINE__)); + return EFI_INVALID_PARAMETER; + } + + if (BmcBootOpt->Persistent) { + BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_VALID; + } else { + BmcBootOpt->BootFlagsValid = BOOT_OPTION_BOOT_FLAG_INVALID; + } + + Status = IpmiCmdSetSysBootOptions (BmcBootOpt); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a - %d Set iBMC BootOpts %r!\n", __FUNCTION__, __LINE__, Status)); + } + + return Status; +} + +VOID ProductBdsPolicyAfterSetup ( VOID ) +{ + EFI_STATUS Status = EFI_SUCCESS; + IPMI_GET_BOOT_OPTION BmcBootOpt; + UINT16 *OptionOrder; + UINTN OptionOrderSize; + UINTN DeviceType = BBS_TYPE_UNKNOWN; + UINTN Index; + BDS_COMMON_OPTION *Option; + CHAR16 OptionName[20]; + LIST_ENTRY BootOptionList; + UINT16 BootIdx; + UINT16 *BootNextBuf; + + InitializeListHead (&BootOptionList); + + Status = GetBmcBootOptionsSetting (&BmcBootOpt); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a - %d : %r!\n", __FUNCTION__, __LINE__,Status)); + return; + } + + if (BmcBootOpt.BootDeviceSelector == ForcePrimaryRemovableMedia) { + DeviceType = BBS_TYPE_USB; + } else if (BmcBootOpt.BootDeviceSelector == ForcePxe) { + DeviceType = BBS_TYPE_EMBEDDED_NETWORK; + } else if (BmcBootOpt.BootDeviceSelector == ForceDefaultHardDisk) { + DeviceType = BBS_TYPE_HARDDRIVE; + } else if (BmcBootOpt.BootDeviceSelector == ForceDefaultCD) { + DeviceType = BBS_TYPE_CDROM; + } else { + return; + } + + DEBUG ((DEBUG_ERROR, "BMC set BootType=%x\n", DeviceType)); + + OptionOrder = BdsLibGetVariableAndSize ( + L"BootOrder", + &gEfiGlobalVariableGuid, + &OptionOrderSize + ); + if (OptionOrder == NULL) { + DEBUG ((DEBUG_ERROR, "%a - %d error\n", __FUNCTION__, __LINE__)); + return; + } + + BootIdx = 0; + BootNextBuf = (UINT16*)AllocatePool(OptionOrderSize); + if (BootNextBuf == NULL) { + DEBUG ((DEBUG_ERROR, "Out of resources.\n")); + return; + } + + for (Index = 0; Index < OptionOrderSize / sizeof (UINT16); Index++) { + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", OptionOrder[Index]); + Option = BdsLibVariableToOption (&BootOptionList, OptionName); + if (Option == NULL) { + DEBUG((DEBUG_ERROR, "%a - %d Boot%04x is Null!\n", __FUNCTION__, __LINE__, OptionOrder[Index])); + continue; + } + + if (DeviceType == UniGetEfiDeviceType(Option)) { + BootNextBuf[BootIdx] = OptionOrder[Index]; + BootIdx++; + } + RemoveEntryList (&Option->Link); + FreePool (Option); + } + + if (BootIdx > 0) { + Status = gRT->SetVariable ( + L"BootNext", + &gEfiGlobalVariableGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + BootIdx*sizeof(UINT16), + BootNextBuf + ); + DEBUG ((DEBUG_ERROR, "Set BootNext %r, size=%x\n", Status, BootIdx*sizeof(UINT16))); + } + + FreePool (OptionOrder); + FreePool (BootNextBuf); + + return; +} /** The function will execute with as the platform policy, current policy @@ -469,6 +776,9 @@ PlatformBdsPolicyBehavior ( // BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder"); + //get boot option from BMC + ProductBdsPolicyAfterSetup(); + //PlatformBdsEnterFrontPage (GetFrontPageTimeoutFromQemu(), TRUE); Print (L"Press Enter to boot OS immediately.\n"); Print (L"Press any other key in %d seconds to stop automatical booting...\n", PcdGet16(PcdPlatformBootTimeOut)); diff --git a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf index baceb57..a09683d 100644 --- a/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf +++ b/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf @@ -49,6 +49,7 @@ DebugLib DevicePathLib GenericBdsLib + IpmiCmdLib MemoryAllocationLib PcdLib PrintLib @@ -78,3 +79,4 @@ gEfiLoadedImageProtocolGuid gEfiPciRootBridgeIoProtocolGuid gEfiSimpleFileSystemProtocolGuid + gEfiDevicePathToTextProtocolGuid diff --git a/Platforms/Hisilicon/D03/D03.dsc b/Platforms/Hisilicon/D03/D03.dsc index 24c88a3..05dd5d8 100644 --- a/Platforms/Hisilicon/D03/D03.dsc +++ b/Platforms/Hisilicon/D03/D03.dsc @@ -367,7 +367,6 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc index 9de1be6..efdedfd 100644 --- a/Platforms/Hisilicon/D05/D05.dsc +++ b/Platforms/Hisilicon/D05/D05.dsc @@ -487,7 +487,6 @@ OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf } MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf