From patchwork Tue Jan 16 16:45:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124742 Delivered-To: patch@linaro.org Received: by 10.46.64.148 with SMTP id r20csp1075527lje; Tue, 16 Jan 2018 08:46:37 -0800 (PST) X-Google-Smtp-Source: ACJfBosnZh+1iI1ZO9ChSurNC0Cq2j5dtqEW/IafREoSt5mSLHL9k1TmOtLn8uWscNKO9LuRecMK X-Received: by 10.129.212.72 with SMTP id g8mr21418924ywl.90.1516121197384; Tue, 16 Jan 2018 08:46:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516121197; cv=none; d=google.com; s=arc-20160816; b=SFpyWDBbR0jGmhLUEbvKFsWkYCc0Mey25WCp5OnHT/K4bRK5/7pcK0h4oFkaZGJN7C +9r58B5Lhoe9/1Wg1tA0o+RBCyx+On7o+A/VRsTtpNr9nJJaNk/iIiC803OCxBqPuCT9 OUNZ2704WQ/cfBRNTGg9kPMVabdRs/iQiHop5DGuGuWcOBgbR9ht+OlF5tOI2InXv897 B979mcxWReK6EVtfMQK5TVMJLoNbYbwRS66ih68377BiGZt+C2yEuJYtGNeA2yC0OYnq vbY0K/bc/xX4NaABBGScAN0TqnE6ZCo27ZRKkAiF0Q0qEsot1Bot5y7o1v91JZ4keABJ zrVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6NsXEr3flB7sBkwFuqOd8m3pcuQPwR79IBEPep8/0tE=; b=1Kt6X+YFsKacUYemjjkckUWj0FBgfjIYxWZQE2Ds9cyehJVUWMBvlNqou/9j4gPkVg j2pijo41Nir+OGPaR18qw5/rFZTE76bjMDGqtqjE8lyNi8Dl23QjQZGdQanAxktxRJpj mg+P+RNypTyt4QNqQdjwncqJZHwCY1uOL1Wswm0snuP/FIdHYb/ZhTk9NxIBekEDV+ya cMkm/i0gn4v+/SgXOufYVyv6jpK11woUrkRHpPQsWxgVzyZV3J/GjusMDGeqJmM0F1FZ NSMBJf/w1n07REM+TDi4EScJNkzPa4tD+XymaDqAtBECTGtwqVA2LmYGRLfUX9Mpb6np rQuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UT1akP8b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r18si580084ybj.635.2018.01.16.08.46.37 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Jan 2018 08:46:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UT1akP8b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNg-0000UZ-Ka for patch@linaro.org; Tue, 16 Jan 2018 11:46:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52071) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNG-0000U0-B4 for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebUNC-0008NO-MQ for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:10 -0500 Received: from mail-pf0-x242.google.com ([2607:f8b0:400e:c00::242]:39642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ebUNC-0008M2-Ef for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:06 -0500 Received: by mail-pf0-x242.google.com with SMTP id e11so9976601pff.6 for ; Tue, 16 Jan 2018 08:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6NsXEr3flB7sBkwFuqOd8m3pcuQPwR79IBEPep8/0tE=; b=UT1akP8bizUIqvSYHFEZz4m66sGKbgh7LxXoRkqzy9tPfxXOyslibJdlwh/PKpL0Lt iF98IGrg87bDOiZHBZfitmnzppPur3SCjMU36TksQn5LtSuKipNPgE5SzFnl4H/NY7mZ FR14aNnTMsQ4AeinjaCYpqUZUKTyZQ+BDZl1o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6NsXEr3flB7sBkwFuqOd8m3pcuQPwR79IBEPep8/0tE=; b=OKmqiV/uHxBazk+83o2+Igg+bMwbMjaivbgj76Z3G8EMdrsmprmgYvIuVKccVeBHXl GStya8m/ibbegPpfQFmlLKPwZP4kBxNUovg/PgvPUtNFYk5E37dj1FrZFg8+tjf/ab1d PskTu0u5FkInaHSbC/ZfRPO1Ew3JNgI8aY23vyeaGVb6oaCgq2jwts4eHF0S7SUphdqJ MNTEcB4bsq5OLMiQDXppfkGXt7uepB6xps0sBlEgoU1BwD5EfBx/iyc0oUT/up4YNUIL 8NMxhcNWjo+vTrh0lzTuFon9hWw93mdZW7O5MhGsRwogq2ZSc5A3/bcEWaUlvZ737zFo JHAw== X-Gm-Message-State: AKGB3mIXGnYGrtrDMRoDmuihUYwNIQiar59A+38vPYLKxamPT6xrp4Iz AtoZJ3ODFaCd7IwQsOUpCNiF98lPFrU= X-Received: by 10.99.97.69 with SMTP id v66mr28033366pgb.307.1516121165075; Tue, 16 Jan 2018 08:46:05 -0800 (PST) Received: from cloudburst.twiddle.net.com (24-181-135-57.dhcp.knwc.wa.charter.com. [24.181.135.57]) by smtp.gmail.com with ESMTPSA id y7sm3875780pfe.48.2018.01.16.08.46.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jan 2018 08:46:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 08:45:57 -0800 Message-Id: <20180116164600.7480-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116164600.7480-1-richard.henderson@linaro.org> References: <20180116164600.7480-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL v2 1/4] tcg/arm: Fix double-word comparisons X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The code sequence we were generating was only good for unsigned comparisons. For signed comparisions, use the sequence from gcc. Fixes booting of ppc64 firmware, with a patch changing the code sequence for ppc comparisons. Tested-by: Michael Roth Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 86 +++++++++++++++++++++++++++++++++--------------- 1 file changed, 60 insertions(+), 26 deletions(-) -- 2.14.3 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 98a12535a5..d7b09e8e0c 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1103,6 +1103,56 @@ static inline void tcg_out_mb(TCGContext *s, TCGArg a0) } } +static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args, + const int *const_args) +{ + TCGReg al = args[0]; + TCGReg ah = args[1]; + TCGArg bl = args[2]; + TCGArg bh = args[3]; + TCGCond cond = args[4]; + int const_bl = const_args[2]; + int const_bh = const_args[3]; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_NE: + case TCG_COND_LTU: + case TCG_COND_LEU: + case TCG_COND_GTU: + case TCG_COND_GEU: + /* We perform a conditional comparision. If the high half is + equal, then overwrite the flags with the comparison of the + low half. The resulting flags cover the whole. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, ah, bh, const_bh); + tcg_out_dat_rI(s, COND_EQ, ARITH_CMP, 0, al, bl, const_bl); + return cond; + + case TCG_COND_LT: + case TCG_COND_GE: + /* We perform a double-word subtraction and examine the result. + We do not actually need the result of the subtract, so the + low part "subtract" is a compare. For the high half we have + no choice but to compute into a temporary. */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_SBC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return cond; + + case TCG_COND_LE: + case TCG_COND_GT: + /* Similar, but with swapped arguments, via reversed subtract. */ + tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, + TCG_REG_TMP, al, bl, const_bl); + tcg_out_dat_rI(s, COND_AL, ARITH_RSC | TO_CPSR, + TCG_REG_TMP, ah, bh, const_bh); + return tcg_swap_cond(cond); + + default: + g_assert_not_reached(); + } +} + #ifdef CONFIG_SOFTMMU #include "tcg-ldst.inc.c" @@ -1964,22 +2014,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], arg_label(args[3])); break; - case INDEX_op_brcond2_i32: - /* The resulting conditions are: - * TCG_COND_EQ --> a0 == a2 && a1 == a3, - * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3, - * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3, - * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3), - * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3), - * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3, - */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[0], args[2], const_args[2]); - tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], - arg_label(args[5])); - break; case INDEX_op_setcond_i32: tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, args[1], args[2], const_args[2]); @@ -1988,15 +2022,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], ARITH_MOV, args[0], 0, 0); break; + + case INDEX_op_brcond2_i32: + c = tcg_out_cmp2(s, args, const_args); + tcg_out_goto_label(s, tcg_cond_to_arm_cond[c], arg_label(args[5])); + break; case INDEX_op_setcond2_i32: - /* See brcond2_i32 comment */ - tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, - args[2], args[4], const_args[4]); - tcg_out_dat_rIN(s, COND_EQ, ARITH_CMP, ARITH_CMN, 0, - args[1], args[3], const_args[3]); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[5]], - ARITH_MOV, args[0], 0, 1); - tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[5])], + c = tcg_out_cmp2(s, args + 1, const_args + 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[c], ARITH_MOV, args[0], 0, 1); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(c)], ARITH_MOV, args[0], 0, 0); break; @@ -2093,9 +2127,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef sub2 = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } }; static const TCGTargetOpDef br2 - = { .args_ct_str = { "r", "r", "rIN", "rIN" } }; + = { .args_ct_str = { "r", "r", "rI", "rI" } }; static const TCGTargetOpDef setc2 - = { .args_ct_str = { "r", "r", "r", "rIN", "rIN" } }; + = { .args_ct_str = { "r", "r", "r", "rI", "rI" } }; switch (op) { case INDEX_op_goto_ptr: From patchwork Tue Jan 16 16:45:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124743 Delivered-To: patch@linaro.org Received: by 10.46.64.148 with SMTP id r20csp1075551lje; Tue, 16 Jan 2018 08:46:42 -0800 (PST) X-Google-Smtp-Source: ACJfBosicyv0UCQgD/YXsymcjbxen+7/GbbyNexc9qL9/DCzM1zkcno5nvKNWD3Df0Spy1sjr1J7 X-Received: by 10.37.231.140 with SMTP id e134mr31159701ybh.329.1516121201959; Tue, 16 Jan 2018 08:46:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516121201; cv=none; d=google.com; s=arc-20160816; b=ww/s7+Gi+81VIs4g7jY4OkljYZIkp+fgC9rNWm0ra1K8XhMxU940yOA45rqKnbF7Qj oJz9h8Mnd5ltCxHRvnfzxOE6ANrUKhzURb5/oSmzKKH5LSYmuBvpmCf9ZZ45nSk4JSHX 117s2ZTs19OQrAAGMdaeT6ZxFywxiA/sTfuU2OFCWd10z4+1aq09Ql7QqTKr5elrD3r5 QIihhC0V0d8gBV9+7+Rd/QJ/TApjN5mdtJ1QpV0243padP73iu0NP1ZLRvMlRzNspK+L hSn52k0AoDaHK+yEOFw8m+HfqZc/DqfQq2c+TWP1jE5c75t3bZ6iq2XKuit4zBEuJ8+p jWSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NWl592gmcmqdqRRwvrPDTA263IuCumCkTRQeZKUCePU=; b=g2fexJqfhT+nmQNsc0Iycf2Qk6A0Ajjg6MA8rf6ZiYVrHOtaMNlG+cAQ/nD+8BhvmV syXOhq+iETAv4scLL44T03Xv4AbAzb7gRSRMBlmD8K6ptQunaQx7KG3rDP491lsrv/1f mTYsrp7xq7FjgSWCg2eRCWHDTnrhcujOKgQ2DH+zz27p6Gypo52LSVl9yTn5YULp1MAX 2x052IloI5kpb2Sr+ByJTLKXnUp8mKJVS+raLkMSAZwrfC4fjT7Bb9oAL3Qbmn4QEhEM YPquu6voPmY4Mr76pKnl2yl717OBHzccyFKVq9h99SPvc8GVFYDoi4ZUnCloTuNFq3v8 HVfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=M/iCaZLV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s188si573169ywd.531.2018.01.16.08.46.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Jan 2018 08:46:41 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=M/iCaZLV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48216 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNl-0000Vy-D2 for patch@linaro.org; Tue, 16 Jan 2018 11:46:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52085) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNI-0000UJ-B5 for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebUNE-0008Ox-31 for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:12 -0500 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:43808) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ebUND-0008Oa-Tc for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:08 -0500 Received: by mail-pg0-x242.google.com with SMTP id n17so2201133pgf.10 for ; Tue, 16 Jan 2018 08:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NWl592gmcmqdqRRwvrPDTA263IuCumCkTRQeZKUCePU=; b=M/iCaZLVBDMSb5j2yXv9Cqw0Aqmudgr/z2Z4GNogS/9wys9K1jq6dQTEzMkQjnkMrQ 6MC/rfTgu/2RyI7cSRwPP5zFBLStGYebE8vh8X581ElcB4I3cneb2wZyX+DzpiOfaBca VzJbw8qJIP74UEpRQJxToo7j4udn/HVh5BXUI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NWl592gmcmqdqRRwvrPDTA263IuCumCkTRQeZKUCePU=; b=ZCE9USZIjEaC7BqAMCiRHuFAqArQzMcFYYNTieLvSU8vqG1GqUZPr7Amr5I2k+qta0 mWS6aW/4VMNhgci6jQQwdlZvyCNd+KeBv9d6p5hN+1AHmFVCtC2S5xgnxRaborKsVQlO tR5QJYGnmoWTDAgomy8//gj5bzRLiYOjcF9IqfCmDsF0YtibnVDiE9o0xZbi9sd0oGBP rsLqjUO40s8yqJ2oSj6fwBt/d100llNgG0FYulGaP99NEqH9YxQd82oFfkGDyVburkUX BZUiUSDw0Qq2gkcAKOwXonTdXcNJnvubB1vt99rt8BgI7ygbuJ0FQSkoKZkwMX+DCkYU r3Ag== X-Gm-Message-State: AKwxytdj49WZyv9ffj2I6+/KqNRiNX9bOfDDVE6g3sGJKoJutlTYHwqW BIIzm7KIc/COCi8MsQhgMjRT5uDrARM= X-Received: by 10.101.75.81 with SMTP id k17mr208568pgt.335.1516121166510; Tue, 16 Jan 2018 08:46:06 -0800 (PST) Received: from cloudburst.twiddle.net.com (24-181-135-57.dhcp.knwc.wa.charter.com. [24.181.135.57]) by smtp.gmail.com with ESMTPSA id y7sm3875780pfe.48.2018.01.16.08.46.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jan 2018 08:46:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 08:45:58 -0800 Message-Id: <20180116164600.7480-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116164600.7480-1-richard.henderson@linaro.org> References: <20180116164600.7480-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PULL v2 2/4] tcg/arm: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) -- 2.14.3 diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index d7b09e8e0c..dc83f3e5be 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1247,12 +1247,6 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, /* We're expecting to use an 8-bit immediate and to mask. */ QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); -/* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset. - Using the offset of the second entry in the last tlb table ensures - that we can index all of the elements of the first entry. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) - > 0xffff); - /* Load and compare a TLB entry, leaving the flags set. Returns the register containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ @@ -1265,6 +1259,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend); + int mask_off; unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); @@ -1296,16 +1291,25 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); } - /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff - || (use_armv6_instructions && TARGET_LONG_BITS == 64 - && cmp_off > 0xff)) { + /* Add portions of the offset until the memory access is in range. + * If we plan on using ldrd, reduce to an 8-bit offset; otherwise + * we can use a 12-bit offset. */ + if (use_armv6_instructions && TARGET_LONG_BITS == 64) { + mask_off = 0xff; + } else { + mask_off = 0xfff; + } + while (cmp_off > mask_off) { + int shift = ctz32(cmp_off & ~mask_off) & ~1; + int rot = ((32 - shift) << 7) & 0xf00; + int addend = cmp_off & (0xff << shift); tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, - (24 << 7) | (cmp_off >> 8)); + rot | ((cmp_off >> shift) & 0xff)); base = TCG_REG_R2; - add_off -= cmp_off & 0xff00; - cmp_off &= 0xff; + add_off -= addend; + cmp_off -= addend; } + if (!use_armv7_instructions) { tcg_out_dat_imm(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1); From patchwork Tue Jan 16 16:45:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124745 Delivered-To: patch@linaro.org Received: by 10.46.64.148 with SMTP id r20csp1076344lje; Tue, 16 Jan 2018 08:49:34 -0800 (PST) X-Google-Smtp-Source: ACJfBovq0/t/BycYW9pVymnFavHiMpFVe+S0PEZTO1egRQCYm6uqTbAlY/f1wds69HMfgsosemZt X-Received: by 10.37.179.203 with SMTP id x11mr35264142ybf.20.1516121374198; Tue, 16 Jan 2018 08:49:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516121374; cv=none; d=google.com; s=arc-20160816; b=MquuwjeExi0fB+tFU+euUw809zXgL3uok1J7sXGWcVrbsxYIxygt2HEAG2lmaYBKW7 ZXe1CaYgr5DHcjrUWxl0+sRMNDb5BilRPZBcZ4qmt0YL1sfXubPMQXJqGAmnLAsnQLm8 noa9TxLSVAt28F2HFx6oVd1FLHmIQ2z5whDQhMv9ZMRtDIGytDrZ/p2oZ2ShYSAN4WNc d/i7ZHiulClSM0Z+JXQRmKkwG5eqmArvv60QcZnA78Kluds4hgE6JBma3V+I7T6+GBwx y+8N2Z0wn2TL/RAJiJ8M35jmr194gmoQG9KnxL+Fk+1Q/UwwwHU1uN5KS7+IzSJUVQGb mnOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=yLGxDDVt6/nof1zka14Eg9JuQebRrAcFmO7hmSnL9X4NOYB+uk1uLIQebzjb4hSAUE 6xHB1KFmaOG2bh7t3lUs44+iauE/aHCKH/oC1fsnzBwwgXwhZCBTAK8UHs9HP5BuXW9j uV3h30CKTTwKIqoTY9g9zw7fMDwFX2kt5WTrAJ2q6t75YNxkufabkt+7sntXGfh1sDR9 YFH1MO6p0kkBhWIBQWfVhFlSO+RUXuPv4+4PiyMYD9U7NsoCX9ASRpqaY+PFNHzkklol erPa8vWKfNOtXZ19+Q8i9jA5wffdmBE/J0v+e5lszS+FIsV265ET5ZTalvoCyoYqDOvn RunQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RLJIVa0W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n73si589928yba.311.2018.01.16.08.49.34 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Jan 2018 08:49:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RLJIVa0W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48220 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUQX-0001nc-Kr for patch@linaro.org; Tue, 16 Jan 2018 11:49:33 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNJ-0000Ur-5R for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebUNF-0008Q3-BE for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:13 -0500 Received: from mail-pg0-x243.google.com ([2607:f8b0:400e:c05::243]:46917) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ebUNF-0008PI-6O for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:09 -0500 Received: by mail-pg0-x243.google.com with SMTP id s9so7958782pgq.13 for ; Tue, 16 Jan 2018 08:46:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=RLJIVa0WSpIBt4SM+ANf6dOPk3+HoICkMDWXQ4mQo6vmIv0vgsL3FsaKq0aNbAC5Jo oWVgPHBWBaf1E4wh/Tas6+LsP3mPWbugpEipvSni/engOU+/o63tto4VTSu9/VVYSMvC Xo7+0+9HvnU6wiC2z7hXulEWpvVewc4kdweYY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RkJQxOnAGP0/1GM4j5AhPbVm0ZbUL4Gx9Je9FrSasnc=; b=ovH3BC5nBKchT8I6DmpPVaOOBItparsDY/+V1oNMfZ+lA9XTZpIIyELTOWcfskyFSz 6j4IsEedjgbHIT8/tVbA6RyR5mRAxH8RML5uj5JEYDHnXRh64a8x21j1/thnjrbO13RT WW8kIt/6flDKlfKo1huPFkbMr3aGEssrncclO11N9z2I7CKbJB9zyJiQeKcQXHJW2BIT BavhyWAi2bBSqWAhZvsr1Tw025EK8wPYsMI7MjijBX6c4D3jca4mlUYIhsDYK7RgzwsL jDpMc9d63l9xq0quQTCK7tDRuUqE6DDKNa+kpIWxBBZIoDTnajrJH1V80FeMEXqukGdZ cDRg== X-Gm-Message-State: AKwxytfTOaSsPUVKHuerd6nt6sBnmy1ptLoQ0wXACwLJXhty1utZLzyT ISmS+3CG6DKuoQ48lBBCFwv67QPqjto= X-Received: by 10.99.140.18 with SMTP id m18mr13221786pgd.59.1516121167879; Tue, 16 Jan 2018 08:46:07 -0800 (PST) Received: from cloudburst.twiddle.net.com (24-181-135-57.dhcp.knwc.wa.charter.com. [24.181.135.57]) by smtp.gmail.com with ESMTPSA id y7sm3875780pfe.48.2018.01.16.08.46.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jan 2018 08:46:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 08:45:59 -0800 Message-Id: <20180116164600.7480-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116164600.7480-1-richard.henderson@linaro.org> References: <20180116164600.7480-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PULL v2 3/4] tcg/ppc: Support tlb offsets larger than 64k X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" AArch64 with SVE has an offset of 80k to the 8th TLB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) -- 2.14.3 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 879885b68b..74f9b4aa34 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1524,16 +1524,15 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, /* Compensate for very large offsets. */ if (add_off >= 0x8000) { - /* Most target env are smaller than 32k; none are larger than 64k. - Simplify the logic here merely to offset by 0x7ff0, giving us a - range just shy of 64k. Check this assumption. */ - QEMU_BUILD_BUG_ON(offsetof(CPUArchState, - tlb_table[NB_MMU_MODES - 1][1]) - > 0x7ff0 + 0x7fff); - tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0)); + int low = (int16_t)cmp_off; + int high = cmp_off - low; + assert((high & 0xffff) == 0); + assert(cmp_off - high == (int16_t)(cmp_off - high)); + assert(add_off - high == (int16_t)(add_off - high)); + tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, base, high >> 16)); base = TCG_REG_TMP1; - cmp_off -= 0x7ff0; - add_off -= 0x7ff0; + cmp_off -= high; + add_off -= high; } /* Extraction and shifting, part 2. */ From patchwork Tue Jan 16 16:46:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 124746 Delivered-To: patch@linaro.org Received: by 10.46.64.148 with SMTP id r20csp1076354lje; Tue, 16 Jan 2018 08:49:36 -0800 (PST) X-Google-Smtp-Source: ACJfBosnyf9PAkhAXiA1itAVY9TeqKnsUa3o5LjsXLF9Kjb4DqiRWl0DHxprE/6yCF3OmAAf7BpS X-Received: by 10.13.241.68 with SMTP id a65mr35927755ywf.205.1516121376142; Tue, 16 Jan 2018 08:49:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516121376; cv=none; d=google.com; s=arc-20160816; b=wPkDXU3XqRPpipJufmeopGzjIN4XIl5OglSLV65ky0JqYvR/bae56wHNFXcNe/ZDti WoSpX0CT+4udIyPVmqqDg7e1Us6hKMsGS4i9WUJvK+TKiE6hh/VZisIIa6R2k8ohF7ef 5YcY61FIIJl9bmw6rLCQAhQinywogLyfTDBCnsW9sZPU5d9COWLnF4PfrzI6Jd6eVyGj wC6AEChTwhUSJWmYJoYkCpZIXus81Lv+4miYyTg6lWSJtn10y7Eq3VKX5cZHzcXnjmLY kWlJFqvgcikr5vQc9gQhBBK29cBVx7RHGVaCMkasNxx72nIqXuks9GFiQMTyxaslMlOO Nmbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=ejAxQWE2JqEWtHIQ0a5NmxOhMLmzF6ylqCWbWExnSLLYePn3ZZ6i09wcPUlWqMnyg/ FPtXZmQ01p1ru56Cs3XrcvzulRlBtgB0SvM7tQzhm+nMWUznreIV8zQXbe6iqZabmgM1 IBDihT30a51zR3s6fWa5x2BJiQ+xputWXEDHInZ+UyHvu1fo9qdW7gc37IfQhayC/7GJ c9SDmx7zeDRcHRSef4KGZwH0xu1SaypaUw6yW9J14hMiHLzhm4kGO/KbELwbdKMPv+DA GTWCELWxIeXCb+fBO2AGUdrPe7xdW8dlcpaBwy+2uAYe1sTlF3MFpXAwEYJJQVXY7NU1 edjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QG6ttO9J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id o6si600577ywm.109.2018.01.16.08.49.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 16 Jan 2018 08:49:36 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QG6ttO9J; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48221 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUQZ-0001oP-H0 for patch@linaro.org; Tue, 16 Jan 2018 11:49:35 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52087) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ebUNI-0000UL-D4 for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ebUNH-0008RK-8s for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:12 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:41196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ebUNH-0008Qp-2J for qemu-devel@nongnu.org; Tue, 16 Jan 2018 11:46:11 -0500 Received: by mail-pl0-x242.google.com with SMTP id q3so6573727plr.8 for ; Tue, 16 Jan 2018 08:46:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=QG6ttO9JU1DNfAmlIpgrCexIAQNBb/Su2KM4PYX6IAnN6/CrAHq5oXkAyhyO7AsxpG 3ef5so/sdcK84qVIwH2av0te20mZioWwzZqTWh3SDTolZ64U6dxVa0M5H5FeUfRq+l+o wMvlH7RFyiYciz41S7GHv/jNtJv1K4PevQuo4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FUUWRYtwa278VZrUKwI2J5+6Tu8CghM2hw9X/xV8zwA=; b=iBgdrQsj80NO4HKWKYtpIGC/6acLG+ml80GULOVy5OnZpNkJFc6Zfhy0hykeHkyg6Y yDDExm0pRDPIXOUjyW93j8SD5p2HtCwrcFLLfT54BOmJ3vETIFTNFB9VOB7J7v3KoWJJ inLS6aOsJNwsGIChCmLo7yutAOHs6XTEcBHjvzVrRJzu4BGCmiRKk4rKg+uHt+oWUdsa GxXTFtEdzaC7w/yMXhDXi8ymiTFD3BeOQV9ow2TkCCT3wjZkzkO5SgGOIn64iFS0EtXS 412m4xN5i1OuLhnAlqOhWUCbkYvs7BqGr8g+z6WS9VVcRWc/ov41u9iypC0pdNLoHKCo 4RUQ== X-Gm-Message-State: AKGB3mLC6JHNXW+un4liBeTavmxRBCQebukhKgT1jAD+patVmenj8DK1 ibsKDIY3K8BiQcmggmZDu+rJ10f3w6k= X-Received: by 10.84.151.70 with SMTP id i64mr40148525pli.337.1516121169671; Tue, 16 Jan 2018 08:46:09 -0800 (PST) Received: from cloudburst.twiddle.net.com (24-181-135-57.dhcp.knwc.wa.charter.com. [24.181.135.57]) by smtp.gmail.com with ESMTPSA id y7sm3875780pfe.48.2018.01.16.08.46.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 Jan 2018 08:46:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 16 Jan 2018 08:46:00 -0800 Message-Id: <20180116164600.7480-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180116164600.7480-1-richard.henderson@linaro.org> References: <20180116164600.7480-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PULL v2 4/4] tcg/ppc: Allow a 32-bit offset to the constant pool X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We recently relaxed the limit of the number of opcodes that can appear in a TranslationBlock. In certain cases this has resulted in relocation overflow. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.inc.c | 67 ++++++++++++++++++++++++++++-------------------- 1 file changed, 39 insertions(+), 28 deletions(-) -- 2.14.3 diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 74f9b4aa34..86f7de5f7e 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -222,33 +222,6 @@ static inline void tcg_out_bc_noaddr(TCGContext *s, int insn) tcg_out32(s, insn | retrans); } -static void patch_reloc(tcg_insn_unit *code_ptr, int type, - intptr_t value, intptr_t addend) -{ - tcg_insn_unit *target; - tcg_insn_unit old; - - value += addend; - target = (tcg_insn_unit *)value; - - switch (type) { - case R_PPC_REL14: - reloc_pc14(code_ptr, target); - break; - case R_PPC_REL24: - reloc_pc24(code_ptr, target); - break; - case R_PPC_ADDR16: - assert(value == (int16_t)value); - old = *code_ptr; - old = deposit32(old, 0, 16, value); - *code_ptr = old; - break; - default: - tcg_abort(); - } -} - /* parse target specific constraints */ static const char *target_parse_constraint(TCGArgConstraint *ct, const char *ct_str, TCGType type) @@ -552,6 +525,43 @@ static const uint32_t tcg_to_isel[] = { [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), }; +static void patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + tcg_insn_unit *target; + tcg_insn_unit old; + + value += addend; + target = (tcg_insn_unit *)value; + + switch (type) { + case R_PPC_REL14: + reloc_pc14(code_ptr, target); + break; + case R_PPC_REL24: + reloc_pc24(code_ptr, target); + break; + case R_PPC_ADDR16: + /* We are abusing this relocation type. This points to a pair + of insns, addis + load. If the displacement is small, we + can nop out the addis. */ + if (value == (int16_t)value) { + code_ptr[0] = NOP; + old = deposit32(code_ptr[1], 0, 16, value); + code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB); + } else { + int16_t lo = value; + int hi = value - lo; + assert(hi + lo == value); + code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); + code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); + } + break; + default: + g_assert_not_reached(); + } +} + static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); @@ -690,7 +700,8 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, -(intptr_t)s->code_gen_ptr); - tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0)); + tcg_out32(s, LD | TAI(ret, ret, 0)); return; }