From patchwork Fri Nov 20 01:03:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 329135 Delivered-To: patch@linaro.org Received: by 2002:a17:907:2110:0:0:0:0 with SMTP id qn16csp847362ejb; Thu, 19 Nov 2020 17:04:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJzML0MgziASYrKzvnwBboKfxxKU0CQrcpnfdNrW+Nqe4VyHvPTwboU3bvfeHqfyidyCUUjU X-Received: by 2002:aa7:c904:: with SMTP id b4mr1285474edt.161.1605834291042; Thu, 19 Nov 2020 17:04:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605834291; cv=none; d=google.com; s=arc-20160816; b=c5onVI6fl1gvk608Xqnm6vF69iMEeflGL1oPU0YxJUypPV5DkCV3AB/7OrBcKGo7Aj wX9V7++OI9e/8GqvT/41St/AhofUWzBrj7o6OiHmZuozs2sxanykU5yDHsz7HrxfHlEx WMcAnXvB7iDkYjSJoQ2iDx0i1rNunrFBj9Oj3M+/VH0ktmLqo1HCRsmiW3mQuDOwEnfd 6/LWR8IJDiBcD7+4Jl+UonwCY8Jv0aP44ic31iW9JYSwxt4W42GPBOhYv4AuODIUGe77 yewhzmzB1VVbSsahW9RGTgmXkRN2U8aLIpUisHNsiFVGLXhpceJlG103zC6Jqosmd7x4 siMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:sender :dkim-signature; bh=bPCMPJxJWTMvBrVkME/ryiL/OXocxj1MZvKWXxVItBY=; b=scPUdvousu10EJWWyQDPtC2Gu2346STEwqxlSxrmXWep6vWxPDkhzBrq2SHLDd8IxM bzni/c9+wbYv6oF4YqrJR4qbVlLoxq1BPB6DVfi0e1I8lUeiOpf4+HiZizmLQXP3jxbV 21HXoTiIpCDlzgE+m+BBx3riAN/aPJHKfE0kPXSu8xtHtlbMmG3Q84tFlFVMxxbov0yR CqDV+xD2YDWppG0bGSItyLqEbSv/6ccRrvWWpgOeZMoGkUQoFruppuQTTIc5c+drzVnX MGcukfmreYt5rYhtiKKWj363oGWRodV4iEHGd5arogd81AT0mbsKm7Qo+fBWCKjPKXH8 Lbug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=RdFSbcbx; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i7si1131094ejo.726.2020.11.19.17.04.50; Thu, 19 Nov 2020 17:04:51 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=RdFSbcbx; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726483AbgKTBDc (ORCPT + 6 others); Thu, 19 Nov 2020 20:03:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726479AbgKTBDb (ORCPT ); Thu, 19 Nov 2020 20:03:31 -0500 Received: from mail-pl1-x641.google.com (mail-pl1-x641.google.com [IPv6:2607:f8b0:4864:20::641]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E889FC0613CF; Thu, 19 Nov 2020 17:03:31 -0800 (PST) Received: by mail-pl1-x641.google.com with SMTP id 18so3934765pli.13; Thu, 19 Nov 2020 17:03:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bPCMPJxJWTMvBrVkME/ryiL/OXocxj1MZvKWXxVItBY=; b=RdFSbcbxkLQtLxjILInvToXaswIDLhPnbN+w0IuneXnRSeJNOgABy8GWbRNutWwOaN jl96fb5Lrwu6/u/jeqvCTZvJUFbvSsDPD3FnqeDushbW8G4IRpT5CzoBSI03fHdvaISL krnLtdFm+CoNyTOH7eFso8g3riJ0HWkJ6aPzrIxe3pjeg4wtPoy88IHQdlv2eQK8/Yu9 fkyR+A/2LILxQQw0vvItnQpWlpHiGdXQKE+tIAH7ib4tbl4YGOCIeJzOyzRKd0Nu3BD7 BmCtLxM8YduwEvD6ItrBpXL5V61ulAls5MTpJYD4fBHpoeBnAklize24HQrwrMxfuPRk HOiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=bPCMPJxJWTMvBrVkME/ryiL/OXocxj1MZvKWXxVItBY=; b=VjDSf4JeoDxhqzLPDaNZhB3W1CUC+Y8tCv2EouCKbmQ4HiDHBKkYVlEupBH/q35vxi 3GurVxqnYaNr3ciNwFEl9IDNLNiDiIgh2r/hsNbAt6ru7OSnE/TLl35SzFghdQxO3Dzo u9Rlbc/bpEAbscytG8mAnEEA20ZWA79DnpBwBqKMGUlQGF4byqF+kMlCPKRDrLtGrvCm d/DOONH+HdjFzVNBbzlwxct/sCnblUOT253VBVk0JI6n05t6H5ZkxyWY1c5Ldp7592eM 687b2MPuAMNvGOKQzSfRURo9ekXBjvepNBsuEt10j9s+RlAenjNwNiYHoUREuyFg7s1+ 0ahA== X-Gm-Message-State: AOAM530LIDLLjBYnlcvmJhi/n6WpFfkszkaHL2TRbM8l1JljYPRztZKr zTJ7uhJmwiHtHEqYR8uyNr0= X-Received: by 2002:a17:902:e9c4:b029:d6:d5d6:c288 with SMTP id 4-20020a170902e9c4b02900d6d5d6c288mr11446039plk.22.1605834211452; Thu, 19 Nov 2020 17:03:31 -0800 (PST) Received: from localhost.localdomain ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id q14sm1205273pfl.163.2020.11.19.17.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 17:03:30 -0800 (PST) Sender: "joel.stan@gmail.com" From: Joel Stanley To: Rob Herring , Eddie James , Guenter Roeck , Andrew Jeffery Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 1/3] dt-bindings: fsi: Add P10 OCC device documentation Date: Fri, 20 Nov 2020 11:33:13 +1030 Message-Id: <20201120010315.190737-2-joel@jms.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201120010315.190737-1-joel@jms.id.au> References: <20201120010315.190737-1-joel@jms.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Eddie James Add the P10 compatible string. Signed-off-by: Eddie James Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.29.2 Acked-by: Rob Herring diff --git a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt index 99ca9862a586..e73358075a90 100644 --- a/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt +++ b/Documentation/devicetree/bindings/fsi/ibm,p9-occ.txt @@ -1,13 +1,13 @@ -Device-tree bindings for FSI-attached POWER9 On-Chip Controller (OCC) ---------------------------------------------------------------------- +Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC) +----------------------------------------------------------------------------- -This is the binding for the P9 On-Chip Controller accessed over FSI from a -service processor. See fsi.txt for details on bindings for FSI slave and CFAM +This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from +a service processor. See fsi.txt for details on bindings for FSI slave and CFAM nodes. The OCC is not an FSI slave device itself, rather it is accessed -through the SBE fifo. +through the SBE FIFO. Required properties: - - compatible = "ibm,p9-occ" + - compatible = "ibm,p9-occ" or "ibm,p10-occ" Examples: From patchwork Fri Nov 20 01:03:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 329137 Delivered-To: patch@linaro.org Received: by 2002:a17:907:2110:0:0:0:0 with SMTP id qn16csp847372ejb; Thu, 19 Nov 2020 17:04:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJxYB6bEvcF3SeXivkh4ls7nElc3r6NO2Gf6SPsZspkCrzmc8Jayixco4mky2FvywI79pnne X-Received: by 2002:a17:906:3ad5:: with SMTP id z21mr4991942ejd.35.1605834291900; Thu, 19 Nov 2020 17:04:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605834291; cv=none; d=google.com; s=arc-20160816; b=fdpzlh8xTT6AZlj81k0bDHcikQYOpB6crMfe+fmaPuPjAeaUibhLCk/U0zVP8cxAdk 6sd9PO1GbyoqgcmWW0KUIz4PcCeQU/3pZkAncYbygjseb7uv2ZeKp5a+ZXubzJsD1HJJ wNHYTlFfxVgPHMl4w7qwVeKxj+3OiGPKCo844fjQHI7mdBDUjuMOrdGt1phIRQNTTyGr sZGXWZ+a7sPmb1hLwFttrgcWyFwtoOXCW6irXPHG4wL50Uiyba5bnmM+uz9RSkkMCAMI FMaVwBxHt90WKq6oA1Yg42k2dlYZiSq+FNu7O1agTpkY9SRqJ9BsjDvl8sudGuEXCMAY g37A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from:sender :dkim-signature; bh=EiK50gZFRvZf6hl7npXpnNvDrQlEKrxGEmTIg/yKDkI=; b=U3mIM/oB5jMUwqyFxF6LXl0G2Wn4fkM1L4GRugGHttLaZuo/ODX6MXBvgWr/GJhsim yxHlCSqJh3MV9Lc1a4KVgD0SpqtK+1uNrjrxFNW13zzxwJGirfpPv+juYOj0xj2C64Le 3/lhF1K7ZkPpLr1sMYxjTFvZILUlBRFRvx3qclMM9VSHE6uVNoL5iN73BbR9iBlfvPuz E/7+ru6Y3DSTD2/fDFMMZ14CsKYs/5AGPi/GAPDe2bs/YE8RUwvfzl8oJARdgChVZjLk TIc5L8s1rXoF4rPaCd5VGo3pymfAsitBnnG1KRoi3EVV16c8NT9IccSz7n9yHfXpVwYt WJ2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=TKLjMstg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i7si1131094ejo.726.2020.11.19.17.04.51; Thu, 19 Nov 2020 17:04:51 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=TKLjMstg; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726479AbgKTBDh (ORCPT + 6 others); Thu, 19 Nov 2020 20:03:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726189AbgKTBDh (ORCPT ); Thu, 19 Nov 2020 20:03:37 -0500 Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 794D1C0613CF; Thu, 19 Nov 2020 17:03:37 -0800 (PST) Received: by mail-pf1-x441.google.com with SMTP id q10so6249717pfn.0; Thu, 19 Nov 2020 17:03:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EiK50gZFRvZf6hl7npXpnNvDrQlEKrxGEmTIg/yKDkI=; b=TKLjMstgNn6hZHEN80pmev0XaV77aX7Ox9/KlCscuge+05zoLOfZhK+QbL/6jjXj68 /x6AQy3IrPgvtkg2D6KgfBgyUwi6fASU7DvPApatLyOgz2vy2NmE/u5h9ttOK/9hrrsx NPEXf4KMjEpjxgKgbTdeEh72h0g+BUNWJmxhOCJgQSrkxZfzkERJxh5WBAYWJ+2yPJNU +lfA4yP9uemk+Y9PcP6SFUT9c49+un8p28+Zxn4LQw9Z0dsNaiD/WRQByvURNVmwPGaW OSdS9zUjjJTGpKmEEA92QLV58POPo4PvqJAr9srlFr3IFve0cPbZsnXmYRxgUUgrtgVs gghA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EiK50gZFRvZf6hl7npXpnNvDrQlEKrxGEmTIg/yKDkI=; b=DyQb7rYKm3YQNAM2eOASWEJmP2FF8Jg0UqnqCEtWGa3olX+wLpjpBY1wlK1AUY/5ab H9+pPZzygyFP9DOrlu/haPb0krsAUlYcVSIGEzFjkFFs3P8xHF+PZHIuntOuA/JUbFBg L6DptDUbNE/tSJLdErk6eaQ4IybpgLADDYPw92s1AuveK+1oNUUDeImoP04MyBdrTQLL QUxwFfvGXi6gQ/wKJiXxO47XNjUqbVzBO7Y+kH9W1mL/9JTNDXhhy5ES3ePoLm1PmzTG ITNSLrc6XPTNVAdtQXw7HgfXqTh3M3SDN7RxpG/qvpbmi4ZJiJDCvPvPRBfcKDe03O6R 13ag== X-Gm-Message-State: AOAM530UnYmrELWSjsFJgaY8LMRLzECxm4QwAQIdw7+yVdzYirRfEqgK fbQ/85gDrwvFZOMvoLan270= X-Received: by 2002:a17:90a:bd0d:: with SMTP id y13mr7055267pjr.236.1605834217035; Thu, 19 Nov 2020 17:03:37 -0800 (PST) Received: from localhost.localdomain ([45.124.203.19]) by smtp.gmail.com with ESMTPSA id q14sm1205273pfl.163.2020.11.19.17.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 17:03:35 -0800 (PST) Sender: "joel.stan@gmail.com" From: Joel Stanley To: Rob Herring , Eddie James , Guenter Roeck , Andrew Jeffery Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-fsi@lists.ozlabs.org Subject: [PATCH v2 2/3] fsi: occ: Add support for P10 Date: Fri, 20 Nov 2020 11:33:14 +1030 Message-Id: <20201120010315.190737-3-joel@jms.id.au> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201120010315.190737-1-joel@jms.id.au> References: <20201120010315.190737-1-joel@jms.id.au> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Eddie James The P10 OCC has a different SRAM address for the command and response buffers. In addition, the SBE commands to access the SRAM have changed format. Add versioning to the driver to handle these differences. Signed-off-by: Eddie James Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- v2: Fix sparse warning with a cast as Guneter suggested --- drivers/fsi/fsi-occ.c | 125 ++++++++++++++++++++++++++++++------------ 1 file changed, 91 insertions(+), 34 deletions(-) -- 2.29.2 diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c index 9eeb856c8905..10ca2e290655 100644 --- a/drivers/fsi/fsi-occ.c +++ b/drivers/fsi/fsi-occ.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -24,8 +25,13 @@ #define OCC_CMD_DATA_BYTES 4090 #define OCC_RESP_DATA_BYTES 4089 -#define OCC_SRAM_CMD_ADDR 0xFFFBE000 -#define OCC_SRAM_RSP_ADDR 0xFFFBF000 +#define OCC_P9_SRAM_CMD_ADDR 0xFFFBE000 +#define OCC_P9_SRAM_RSP_ADDR 0xFFFBF000 + +#define OCC_P10_SRAM_CMD_ADDR 0xFFFFD000 +#define OCC_P10_SRAM_RSP_ADDR 0xFFFFE000 + +#define OCC_P10_SRAM_MODE 0x58 /* Normal mode, OCB channel 2 */ /* * Assume we don't have much FFDC, if we do we'll overflow and @@ -37,11 +43,14 @@ #define OCC_TIMEOUT_MS 1000 #define OCC_CMD_IN_PRG_WAIT_MS 50 +enum versions { occ_p9, occ_p10 }; + struct occ { struct device *dev; struct device *sbefifo; char name[32]; int idx; + enum versions version; struct miscdevice mdev; struct mutex occ_lock; }; @@ -235,29 +244,43 @@ static int occ_verify_checksum(struct occ_response *resp, u16 data_length) return 0; } -static int occ_getsram(struct occ *occ, u32 address, void *data, ssize_t len) +static int occ_getsram(struct occ *occ, u32 offset, void *data, ssize_t len) { u32 data_len = ((len + 7) / 8) * 8; /* must be multiples of 8 B */ - size_t resp_len, resp_data_len; - __be32 *resp, cmd[5]; - int rc; + size_t cmd_len, resp_len, resp_data_len; + __be32 *resp, cmd[6]; + int idx = 0, rc; /* * Magic sequence to do SBE getsram command. SBE will fetch data from * specified SRAM address. */ - cmd[0] = cpu_to_be32(0x5); + switch (occ->version) { + default: + case occ_p9: + cmd_len = 5; + cmd[2] = cpu_to_be32(1); /* Normal mode */ + cmd[3] = cpu_to_be32(OCC_P9_SRAM_RSP_ADDR + offset); + break; + case occ_p10: + idx = 1; + cmd_len = 6; + cmd[2] = cpu_to_be32(OCC_P10_SRAM_MODE); + cmd[3] = 0; + cmd[4] = cpu_to_be32(OCC_P10_SRAM_RSP_ADDR + offset); + break; + } + + cmd[0] = cpu_to_be32(cmd_len); cmd[1] = cpu_to_be32(SBEFIFO_CMD_GET_OCC_SRAM); - cmd[2] = cpu_to_be32(1); - cmd[3] = cpu_to_be32(address); - cmd[4] = cpu_to_be32(data_len); + cmd[4 + idx] = cpu_to_be32(data_len); resp_len = (data_len >> 2) + OCC_SBE_STATUS_WORDS; resp = kzalloc(resp_len << 2, GFP_KERNEL); if (!resp) return -ENOMEM; - rc = sbefifo_submit(occ->sbefifo, cmd, 5, resp, &resp_len); + rc = sbefifo_submit(occ->sbefifo, cmd, cmd_len, resp, &resp_len); if (rc) goto free; @@ -287,20 +310,21 @@ static int occ_getsram(struct occ *occ, u32 address, void *data, ssize_t len) return rc; } -static int occ_putsram(struct occ *occ, u32 address, const void *data, - ssize_t len) +static int occ_putsram(struct occ *occ, const void *data, ssize_t len) { size_t cmd_len, buf_len, resp_len, resp_data_len; u32 data_len = ((len + 7) / 8) * 8; /* must be multiples of 8 B */ __be32 *buf; - int rc; + int idx = 0, rc; + + cmd_len = (occ->version == occ_p10) ? 6 : 5; /* * We use the same buffer for command and response, make * sure it's big enough */ resp_len = OCC_SBE_STATUS_WORDS; - cmd_len = (data_len >> 2) + 5; + cmd_len += data_len >> 2; buf_len = max(cmd_len, resp_len); buf = kzalloc(buf_len << 2, GFP_KERNEL); if (!buf) @@ -312,11 +336,23 @@ static int occ_putsram(struct occ *occ, u32 address, const void *data, */ buf[0] = cpu_to_be32(cmd_len); buf[1] = cpu_to_be32(SBEFIFO_CMD_PUT_OCC_SRAM); - buf[2] = cpu_to_be32(1); - buf[3] = cpu_to_be32(address); - buf[4] = cpu_to_be32(data_len); - memcpy(&buf[5], data, len); + switch (occ->version) { + default: + case occ_p9: + buf[2] = cpu_to_be32(1); /* Normal mode */ + buf[3] = cpu_to_be32(OCC_P9_SRAM_CMD_ADDR); + break; + case occ_p10: + idx = 1; + buf[2] = cpu_to_be32(OCC_P10_SRAM_MODE); + buf[3] = 0; + buf[4] = cpu_to_be32(OCC_P10_SRAM_CMD_ADDR); + break; + } + + buf[4 + idx] = cpu_to_be32(data_len); + memcpy(&buf[5 + idx], data, len); rc = sbefifo_submit(occ->sbefifo, buf, cmd_len, buf, &resp_len); if (rc) @@ -356,21 +392,35 @@ static int occ_putsram(struct occ *occ, u32 address, const void *data, static int occ_trigger_attn(struct occ *occ) { __be32 buf[OCC_SBE_STATUS_WORDS]; - size_t resp_len, resp_data_len; - int rc; + size_t cmd_len, resp_len, resp_data_len; + int idx = 0, rc; - BUILD_BUG_ON(OCC_SBE_STATUS_WORDS < 7); + BUILD_BUG_ON(OCC_SBE_STATUS_WORDS < 8); resp_len = OCC_SBE_STATUS_WORDS; - buf[0] = cpu_to_be32(0x5 + 0x2); /* Chip-op length in words */ + switch (occ->version) { + default: + case occ_p9: + cmd_len = 7; + buf[2] = cpu_to_be32(3); /* Circular mode */ + buf[3] = 0; + break; + case occ_p10: + idx = 1; + cmd_len = 8; + buf[2] = cpu_to_be32(0xd0); /* Circular mode, OCB Channel 1 */ + buf[3] = 0; + buf[4] = 0; + break; + } + + buf[0] = cpu_to_be32(cmd_len); /* Chip-op length in words */ buf[1] = cpu_to_be32(SBEFIFO_CMD_PUT_OCC_SRAM); - buf[2] = cpu_to_be32(0x3); /* Mode: Circular */ - buf[3] = cpu_to_be32(0x0); /* Address: ignore in mode 3 */ - buf[4] = cpu_to_be32(0x8); /* Data length in bytes */ - buf[5] = cpu_to_be32(0x20010000); /* Trigger OCC attention */ - buf[6] = 0; + buf[4 + idx] = cpu_to_be32(8); /* Data length in bytes */ + buf[5 + idx] = cpu_to_be32(0x20010000); /* Trigger OCC attention */ + buf[6 + idx] = 0; - rc = sbefifo_submit(occ->sbefifo, buf, 7, buf, &resp_len); + rc = sbefifo_submit(occ->sbefifo, buf, cmd_len, buf, &resp_len); if (rc) goto error; @@ -429,7 +479,7 @@ int fsi_occ_submit(struct device *dev, const void *request, size_t req_len, /* Extract the seq_no from the command (first byte) */ seq_no = *(const u8 *)request; - rc = occ_putsram(occ, OCC_SRAM_CMD_ADDR, request, req_len); + rc = occ_putsram(occ, request, req_len); if (rc) goto done; @@ -440,7 +490,7 @@ int fsi_occ_submit(struct device *dev, const void *request, size_t req_len, /* Read occ response header */ start = jiffies; do { - rc = occ_getsram(occ, OCC_SRAM_RSP_ADDR, resp, 8); + rc = occ_getsram(occ, 0, resp, 8); if (rc) goto done; @@ -476,8 +526,7 @@ int fsi_occ_submit(struct device *dev, const void *request, size_t req_len, /* Grab the rest */ if (resp_data_length > 1) { /* already got 3 bytes resp, also need 2 bytes checksum */ - rc = occ_getsram(occ, OCC_SRAM_RSP_ADDR + 8, - &resp->data[3], resp_data_length - 1); + rc = occ_getsram(occ, 8, &resp->data[3], resp_data_length - 1); if (rc) goto done; } @@ -517,6 +566,7 @@ static int occ_probe(struct platform_device *pdev) if (!occ) return -ENOMEM; + occ->version = (uintptr_t)of_device_get_match_data(dev); occ->dev = dev; occ->sbefifo = dev->parent; mutex_init(&occ->occ_lock); @@ -575,7 +625,14 @@ static int occ_remove(struct platform_device *pdev) } static const struct of_device_id occ_match[] = { - { .compatible = "ibm,p9-occ" }, + { + .compatible = "ibm,p9-occ", + .data = (void *)occ_p9 + }, + { + .compatible = "ibm,p10-occ", + .data = (void *)occ_p10 + }, { }, }; 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Add a new temperature sensor version to handle this data. Signed-off-by: Eddie James Reviewed-by: Joel Stanley Signed-off-by: Joel Stanley --- drivers/hwmon/occ/common.c | 75 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) -- 2.29.2 diff --git a/drivers/hwmon/occ/common.c b/drivers/hwmon/occ/common.c index a71777990d49..7a5e539b567b 100644 --- a/drivers/hwmon/occ/common.c +++ b/drivers/hwmon/occ/common.c @@ -41,6 +41,14 @@ struct temp_sensor_2 { u8 value; } __packed; +struct temp_sensor_10 { + u32 sensor_id; + u8 fru_type; + u8 value; + u8 throttle; + u8 reserved; +} __packed; + struct freq_sensor_1 { u16 sensor_id; u16 value; @@ -307,6 +315,60 @@ static ssize_t occ_show_temp_2(struct device *dev, return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); } +static ssize_t occ_show_temp_10(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int rc; + u32 val = 0; + struct temp_sensor_10 *temp; + struct occ *occ = dev_get_drvdata(dev); + struct occ_sensors *sensors = &occ->sensors; + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + + rc = occ_update_response(occ); + if (rc) + return rc; + + temp = ((struct temp_sensor_10 *)sensors->temp.data) + sattr->index; + + switch (sattr->nr) { + case 0: + val = get_unaligned_be32(&temp->sensor_id); + break; + case 1: + val = temp->value; + if (val == OCC_TEMP_SENSOR_FAULT) + return -EREMOTEIO; + + /* + * VRM doesn't return temperature, only alarm bit. This + * attribute maps to tempX_alarm instead of tempX_input for + * VRM + */ + if (temp->fru_type != OCC_FRU_TYPE_VRM) { + /* sensor not ready */ + if (val == 0) + return -EAGAIN; + + val *= 1000; + } + break; + case 2: + val = temp->fru_type; + break; + case 3: + val = temp->value == OCC_TEMP_SENSOR_FAULT; + break; + case 4: + val = temp->throttle * 1000; + break; + default: + return -EINVAL; + } + + return snprintf(buf, PAGE_SIZE - 1, "%u\n", val); +} + static ssize_t occ_show_freq_1(struct device *dev, struct device_attribute *attr, char *buf) { @@ -745,6 +807,10 @@ static int occ_setup_sensor_attrs(struct occ *occ) num_attrs += (sensors->temp.num_sensors * 4); show_temp = occ_show_temp_2; break; + case 0x10: + num_attrs += (sensors->temp.num_sensors * 5); + show_temp = occ_show_temp_10; + break; default: sensors->temp.num_sensors = 0; } @@ -844,6 +910,15 @@ static int occ_setup_sensor_attrs(struct occ *occ) attr->sensor = OCC_INIT_ATTR(attr->name, 0444, show_temp, NULL, 3, i); attr++; + + if (sensors->temp.version == 0x10) { + snprintf(attr->name, sizeof(attr->name), + "temp%d_max", s); + attr->sensor = OCC_INIT_ATTR(attr->name, 0444, + show_temp, NULL, + 4, i); + attr++; + } } }