From patchwork Mon Nov 23 14:10:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330670 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026398ilh; Mon, 23 Nov 2020 06:04:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwynXjkaskp1YUbRKSGvq59AA898rGwXPoJVNxITcJzs4HojTQyTlubMxBTXKHo6awmVn2 X-Received: by 2002:a19:8110:: with SMTP id c16mr12616022lfd.372.1606140294805; Mon, 23 Nov 2020 06:04:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140294; cv=none; d=google.com; s=arc-20160816; b=N3pYubrBmefHE9rlRbJ7EzE6klyQl2I6yHkCh69kVBOdjiuXfBIFX1KWlD5Lnun2O+ Q7HzwLcdg7rtlMc/UwFg3VRSkYBDgz3W84EetVJ54xnmarVTpcveBe51BJ1qOZzAlbq6 0pzMa8hVep3r7gld0ayNmCKK0J+n7nS7z28NxDlnkENIgv7JNWEMiXCLTVGJ7J9wvxU1 KafoB1NgKyKV024efbbj1ewhm/DAfse3AZFW12lepk5RyE9Wm6FVdiwbJVA9GwtKZwlw LQ6XZDsXaY3uJ/FHzpj+W2niW1vSLlg1qHzgGhJ2sqgsIsL4SOV+HwdFWolGS2SQrYIP Hw+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=4dySM6ga3g1JccS9VpKiXH/tknJsBk9CHeAdOMBOgi8=; b=0wFOZrO3KBULHNLyQkZXsJ4gV7LA404v7PlPsYHKHjW+F38lz8AauF939lsh+M7Eq0 7rvuvrzxzG8WQeArxV+gei6YxUMlTF1aDF6WM6Az0m92YqVsOWKi3bBTB4Afv1B7tgyy rV+dowVu3yXsnj7Pmt2j2xeFll71MlY11+jGG+CjnKQrNRb2KpVHfNe3X7DM5+Kaimdy 3W6UFH2T4bZOa+3TBiSYMC4m1YYHbCBgewyBkeStKxd+NJWygjIHZwaWGS8feLxqIgeu w/nj+RouURpkN6iSL0BfXXSK0OFsLXoep9NX58r5U533DUHYiu0AlFMOuAnyfVf6jCS1 Snsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wmQ/SWXh"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r18si6917042edm.82.2020.11.23.06.04.54; Mon, 23 Nov 2020 06:04:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wmQ/SWXh"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730217AbgKWOEY (ORCPT + 15 others); Mon, 23 Nov 2020 09:04:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729293AbgKWOEX (ORCPT ); Mon, 23 Nov 2020 09:04:23 -0500 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F71AC0613CF for ; Mon, 23 Nov 2020 06:04:23 -0800 (PST) Received: by mail-wm1-x343.google.com with SMTP id w24so17365142wmi.0 for ; Mon, 23 Nov 2020 06:04:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4dySM6ga3g1JccS9VpKiXH/tknJsBk9CHeAdOMBOgi8=; b=wmQ/SWXhQATuAMF2bttR04zNFBN1ch30xgUQLiLKDGapsjUJjlydNZqj1hOAXTLR9T TK6WyoZ5UAPbu5w1v24IKVZnXoCmaxTd6Gv+0+c6/f8slx0mDrkF34z4j+G1sg7Xs6x8 l/q1NGpZb1E4yDdliqUHlnrJt0prki1kSKs/ef8OEHYNEviX3C32rrdVJUJTQcLimEMd lkiNuXGSpDsLOiR+t4DQ3FzzaKxigtAHnMovRHrwBU0QGG0gnBRnSgZiJJQfeRNI9GMh 6X7DRHSNjjDW4R+Fk+vf90VC9D3rsR0nASyBAaDSqOIYaYdFf+6PKqYrPRcFDIqOPE5E jqqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4dySM6ga3g1JccS9VpKiXH/tknJsBk9CHeAdOMBOgi8=; b=i7k+oURNJVcAkxzyzaU/wz7ubjLSwuW7mog5F8Dn6eD9RU6ub9/e031UfCDu7jiSXy a3vAly49kFtssJHmex8WWmo3EnqhsDPuT6/cNAT0WPYwSLfNE8dzsBb0fXvdaLuuUgt8 gpa4paVIPTBS+CVfalLanBpvJfvK22p0hsv8YKldLMDymnG7eeUTmCWiF92njmpVm+xZ ENGlQgoPnkyGeAXdFRCo0kuafGhcx6hq2rGbiTgwbbt39gVyYpvgPrplMX357QNWTqJc JT1G4dwoLUbev3vzeKdGc4g6z/ZjutDRAbqPBEn1qdEkEF22SSw36wRO44wIwH3JhgsO 4q+A== X-Gm-Message-State: AOAM53042e60s1NgaQmiOfmqcKhEsismaAddquBioKiKLS8wjZwDcxL8 2cjRzELLZSs5P0wqiG5wrM6zXA== X-Received: by 2002:a1c:4c16:: with SMTP id z22mr23467876wmf.14.1606140262059; Mon, 23 Nov 2020 06:04:22 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:f5cd:e791:e88b:e3b7]) by smtp.gmail.com with ESMTPSA id m9sm7102727wrx.59.2020.11.23.06.04.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Nov 2020 06:04:19 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v2 1/8] mhi: pci-generic: Increase number of hardware events Date: Mon, 23 Nov 2020 15:10:59 +0100 Message-Id: <1606140666-4986-2-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> References: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If the IPA (IP hardware accelerator) is starved of event ring elements, the modem is crashing (SDX55). That can be prevented by setting a larger number of events (i.e 2 x number of channel ring elements). Tested with FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index e3df838..13a7e4f 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -91,7 +91,7 @@ struct mhi_pci_dev_info { #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ { \ - .num_elements = 128, \ + .num_elements = 256, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ From patchwork Mon Nov 23 14:11:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330672 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026409ilh; Mon, 23 Nov 2020 06:04:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJyiTkYs/lNtPsNW4O5OHpaFuT5FGR/nvQlv4iSccVkYIXK+fTH/PuQv9Gj+P2XvYuCzglkD X-Received: by 2002:a17:906:6091:: with SMTP id t17mr14455543ejj.476.1606140295356; Mon, 23 Nov 2020 06:04:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140295; cv=none; d=google.com; s=arc-20160816; b=kam1B3mPEXrN6jTJNli2DrRm0gCJyjTNmoiBfrQ6tDJGbDOC4l5HzQhvPn6WAwraPF thPRk6yGl25rN3aNn/feo75EIU9huYtWDM2GU1pzOAA44oIOVty7FhFYuuq9gq8NLsWf JKskMeD9VvL1PKOeaVjy++agzC5yZVbu+xuuaWZJakYrA/aIa/GbMv8Myz8Hbig+5wg1 BVHSvQs75qK96dgt0eZKc/mY/qBW7NqSP5h7VTDdLqZU69f7FOt0ImcyRlKeTjgJpTN9 WRbwVrF5KREliS8buOzSx44DfjN0vTC9+geJtldtr3+tfP7SrCNy7Sho4t7x+oSjleFF FQXg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=NI5nyGOY3ERNyQJVul1TRTO9hhACB1gWUuV76MrEk5M=; b=Kldng8Rl34E2TLuK6ztYutiQVmwXSU04CAIha7rIjTK02tUz48KlzZR+5Jg+FUEssw 55h6NePaEL6dw9BtxW8kw6fXN3mXLqz0qD1gP8RBea9vFMjBh4bi7lTN34nw0LzQ2AZd fpQatRFICTRUO8wd0V54HXRj17vRqKxrjJBrSBQw+5RSdtD2gEQHBTpbQI82SovqQZ2j EcdMmoxU1ic1bq+JCnaBHQJKCnh4gNwRPVrNquGsDGWxhAk6pVdRQc1Isex2uoqjGl2l ZAEnMC2eUTUBDqUVjtvmv/OgTy1EMeZf+EIn5G6ZWehYaQmR/jZ3sfO82NbjWHyYkgA6 Jhcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dgYlI6LD; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This has been tested with Telit FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 13a7e4f..09c6b26 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -15,6 +15,8 @@ #define MHI_PCI_DEFAULT_BAR_NUM 0 +#define DEV_RESET_REG (0xB0) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -166,6 +168,11 @@ static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, /* Nothing to do for now */ } +static inline void mhi_pci_reset(struct mhi_controller *mhi_cntrl) +{ + writel(1, mhi_cntrl->regs + DEV_RESET_REG); +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -329,6 +336,10 @@ static void mhi_pci_remove(struct pci_dev *pdev) mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); + + /* MHI-layer reset could not be enough, always hard-reset the device */ + mhi_pci_reset(mhi_cntrl); + mhi_free_controller(mhi_cntrl); } From patchwork Mon Nov 23 14:11:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330673 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026454ilh; Mon, 23 Nov 2020 06:04:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJxu6aX5WvHja7OW7g1WIRE1QlCdGfz2M6LS7FTGLSB9yMuWgKEhSUbFdEWXvFJ1ir5JC1Fw X-Received: by 2002:a19:6a0c:: with SMTP id u12mr12775705lfu.492.1606140295960; Mon, 23 Nov 2020 06:04:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140295; cv=none; d=google.com; s=arc-20160816; b=kBUBrpOV6DdslIgwu9AV6bgDvvNbkaMhdLceSX4vP52V0A3k+qWSJvnUXxL8mxwziv 4nN7SUNbg1z5MuwuI1eMS/Ph8vjbQ9+LU6kiczHEuh4OvZ/iXcZTahenYxGfTGMKban8 wRDX3BwXZtKZt1HTKvI9chn626yBe2xIkdcMZU+k9EX9b/YNjfzQ8N5aEzYkw6N1+CNc lbnQ4fLCwUng2GqnKbhDDWs8GfOxL8oSb3Wsci0Ms2h9tcJRo0QxALC6bdvxRHDtNQwx 9swHiK7r7jU97gtQsApNAK+o/qhwM+Bwbv0aKHJUBACGduAGfyTN4PWGVg0Fkn4tjBLD S+IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=gYIKCcN8WQ/EbGFIHV1x88OAZPf2nkJY+y3eCrkB1Og=; b=FZUfeqNQfcrxG5BXwmh6ea8j3W9s+P9e7AWRM5ZN1FUrkAo2iIkLP3Hb1u3iMy51y7 2kPh3xcAQN+3/zwfDn9TR7M+2V7dJC2ujSsaqU2IvHsobM8F06NUys/EAXKAoYxffiN4 fVvUhLNp5WHBMW6AqN3kr7X1Cwizi3cWhS+nrqFIN/Qo2DdzF/Ad0oy0195aUII1Zpk7 cetvqQn5KHaJWg/iQ8cqcCgKqVb6tsMgjnTUNAwJ9Qnk1/arqY/iVhugwl/ziM4NStJ2 gBa+4D2E5jFmbL2fhTgL2yVbLil3XKf+IvvuxkP3y5U3CgJ/FPL37YUoUaBn9yhr7pLI tN+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AKIjlBTu; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r18si6917042edm.82.2020.11.23.06.04.55; Mon, 23 Nov 2020 06:04:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AKIjlBTu; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730238AbgKWOEa (ORCPT + 15 others); Mon, 23 Nov 2020 09:04:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730232AbgKWOEa (ORCPT ); Mon, 23 Nov 2020 09:04:30 -0500 Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9032C0613CF for ; Mon, 23 Nov 2020 06:04:29 -0800 (PST) Received: by mail-wr1-x443.google.com with SMTP id 64so5299978wra.11 for ; Mon, 23 Nov 2020 06:04:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gYIKCcN8WQ/EbGFIHV1x88OAZPf2nkJY+y3eCrkB1Og=; b=AKIjlBTuJv9zdqcpLJHX+cjyDxMwH1ui0yz7N3JR4vzpC8jB3ZmKqhdnf7e2/Jm0lD 59c0qp9RXkAZaBIf6NQ2vih8ksaqWhCyAXGnVlge0OvrllK9v1ZSVcqx0w8gCEmJ7JMf Thr1kUgcmdL/+MA/sogeGCUIFhIh4woTa9ytxQFkmp0Ec0Fnbbo6AdxnQlp/OKkJHOb7 lAZQc7Wx04O2sD+h0jfAiL8eMjrklo03wXVZ1Ngjyapo3LUpfORFezvRYt4wWjWt3yYJ EQ7Li4JtG1wlfUdtQvCZoiwbaNY/g6ewzhXNtVaAauwFvL3DClJhmGYNevck6tw+yrJt XSbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gYIKCcN8WQ/EbGFIHV1x88OAZPf2nkJY+y3eCrkB1Og=; b=ZA/J8epnHEXAaaO7/hRQABbIazWQQf1UjIdCSdSsTe66lywNuHhqxbqUujK8Q2jOkf JyYag+AsBNhBXU3rgDJ1MsUPgWyVBestm7mtASP3TUQcM6A1Zrzy3QI96PdTYb6Ajnnq uZU4uCBL+H2XjBOQzmtaMBFixmVD6pTB9cDLc9kTrdIR9Z6zXj4p8Cz2GbimMvvLJn+0 YKi2dXbT411P4azcCUUdE+NmfMOj+W+sDmzkL8IuUyOnlwNcKhIEHkHy3NADi1bw869p CN5ZK5H5ySLjQJ2gEnBLe2x7MFPlpYtJvS9GdLRScEO9UgsxvQS8XxY+izkqCho2BSQn OcEw== X-Gm-Message-State: AOAM5311hnqjiKF32SqCRdRiQpl2p4E487TUCje62SNBVu/Nuoy/WeEh 5JM0lIKMYtJ/U9Oi0oiBtLxkvA== X-Received: by 2002:a5d:4ec8:: with SMTP id s8mr10130565wrv.349.1606140268338; Mon, 23 Nov 2020 06:04:28 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:f5cd:e791:e88b:e3b7]) by smtp.gmail.com with ESMTPSA id m9sm7102727wrx.59.2020.11.23.06.04.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Nov 2020 06:04:26 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v2 3/8] mhi: pci_generic: Enable burst mode for hardware channels Date: Mon, 23 Nov 2020 15:11:01 +0100 Message-Id: <1606140666-4986-4-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> References: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hardware channels have a feature called burst mode that allows to queue transfer ring element(s) (TRE) to a channel without ringing the device doorbell. In that mode, the device is polling the channel context for new elements. This reduces the frequency of host initiated doorbells and increase throughput. Create a new dedicated macro for hardware channels with burst enabled. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 09c6b26..0c07cf5 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -78,6 +78,36 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } +#define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_AMSS), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_ENABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring) \ { \ .num_elements = 128, \ @@ -112,8 +142,8 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), - MHI_CHANNEL_CONFIG_UL(100, "IP_HW0", 128, 1), - MHI_CHANNEL_CONFIG_DL(101, "IP_HW0", 128, 2), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), }; static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { From patchwork Mon Nov 23 14:11:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330674 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026529ilh; Mon, 23 Nov 2020 06:05:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJzZV3A9Dy5ToIbcOuKk524SwlRzpESna8djm8IaWHCw/QzF/BPztvvb8WzAUEi21AFMkfOy X-Received: by 2002:a50:d4dc:: with SMTP id e28mr7870674edj.357.1606140303507; Mon, 23 Nov 2020 06:05:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140303; cv=none; d=google.com; s=arc-20160816; b=OiBDOZPltIIKh29m565BKdXSTh1RgYzKCzKcT/1kc1sAbdhU3Is74y6J2DRYY0WG24 jnzUWn/f65BbILZPoUtDrHQd2hWvVwK5QH0Mxfm5w2Sddqod8YoN2LYlj/Y2WhJ7jSqi EMcNuSmd8chpYnW20kzTPYZA31NyyEByIiem/9msmqMLcsjkC2zxhvXWKAS1cURbmEDw ynpRIt8XDOtiUIqWOFUQvU6WkCU9hK/hrE0npeaYPdrw6h2Uj811vWEbDzHpK6mIRriW Um7j9A4VEtBfrOMxNLkN61/9tHKQqaLcZl4T8V5e2W0KpHEDlxB1lomkvE45nXzPS5Mk IZ3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=dQci3mBBoR0tqqcwGOSS/7KOqdTfROUDHNeFyEKodBo=; b=UIe6+e3zPRd3Mm10vTyLqvWCR5ialAmYvh8r3f4tBX239cANc86eq7Vwf6norTcwkl ZL+GzL8IXtlzFXD2zpHe0Ef+FvsBETp4N9AER6OmSkqx4JmDLJHOfxx5PJ8XVroxrs2W gvOV2aNKFBGMf3lKMiniyJrMMFAG5gGuDRlJafI+9n/s7N6w7S3UnIVexVsrhu5N6q46 VQEz0xqBYhZeSsOGsk/nSoEaTtjNv/sZbXN3L3jg4VQICQrN3qM3U35vyoLNCjM+oZRw FHqvv+i6tKQHgKKLqnmMtcGL1cfLe1eeqH5owYqqi4Z8qiq3sjFePN0L7QW7+e1SUnUO IYfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LFB+qPMH; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id r18si6917042edm.82.2020.11.23.06.04.58; Mon, 23 Nov 2020 06:05:03 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LFB+qPMH; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730232AbgKWOEf (ORCPT + 15 others); Mon, 23 Nov 2020 09:04:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730130AbgKWOEf (ORCPT ); Mon, 23 Nov 2020 09:04:35 -0500 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFAA3C0613CF for ; Mon, 23 Nov 2020 06:04:34 -0800 (PST) Received: by mail-wm1-x344.google.com with SMTP id a186so15186303wme.1 for ; Mon, 23 Nov 2020 06:04:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dQci3mBBoR0tqqcwGOSS/7KOqdTfROUDHNeFyEKodBo=; b=LFB+qPMHlWpiQk6y0xgQO8Jy1uMq+Ygq6fFfnU/vAs12KP8o0ZV+/zcCT6HRpknKoA plVgFZDJn+TEDkqZusrzQ+Eu2Ve+9cSIvaTlxbxlsiyXuThtNuOGrfSQrZAZOtWmtVre q5z6iC1jKTLqG2hG7fmUbES/+TLwYcneVFeqdbMg0TZofqrAW21ysRhC8wv4kfz5ZWCo nvYNk72CK7fMtitr4tlsS+2H9hAvheO24c5umCZfgilqbZbb+nsm1O3CqtU2GyjX6sm0 kQsuSA+8z/HvM1UGwhExAi8duRF+vRsoWbZbBEgOaJsLqaP55g57drSJuPNce4HQ7BUS lF/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dQci3mBBoR0tqqcwGOSS/7KOqdTfROUDHNeFyEKodBo=; b=lAcWtK0uJU2Hme661ea4mZcE7e9sIlUg2fESg9SYMpF3kxEIqvbDoPuX1v6DrPyiev eEe2mPj313oKUHSTi3+WGYykuDN6z/Q9CErT66XVdH/Q//qEaesxeTnWQ51xv/wEHWu/ kesZ9lYaFsXQzsHHZtYHeuWcukjTJRbf/QiInmeaKVg6DSnLAeOwcA40xW/Aua5kR7Ri FBhKx5r6ciMCTH5hkW/t72xXnQTauI7wuPATbHRmTV+4EVuRW8GHiXNRPKqQw1+2gADU gmx2UiTIPzhZPMc51rTm+P8cs3dIUKqK2V+ZYcpUZ3VTL+CMAgI3lTEiwvjXns4R933c jQKA== X-Gm-Message-State: AOAM5318fo8yk0ETp5BJ9ja3hlRqu32p+5aU6t74zVXEXKptYuxstSNX uzL+FFY1iDJV6h2KO/UFNzGucHOD75Z5teRAtZE= X-Received: by 2002:a7b:c015:: with SMTP id c21mr24651646wmb.79.1606140272963; Mon, 23 Nov 2020 06:04:32 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:490:8730:f5cd:e791:e88b:e3b7]) by smtp.gmail.com with ESMTPSA id m9sm7102727wrx.59.2020.11.23.06.04.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Nov 2020 06:04:30 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, Loic Poulain Subject: [PATCH v2 4/8] mhi: pci_generic: Add support for reset Date: Mon, 23 Nov 2020 15:11:02 +0100 Message-Id: <1606140666-4986-5-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> References: <1606140666-4986-1-git-send-email-loic.poulain@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for resetting the device, reset can be triggered in case of error or manually via sysfs (/sys/bus/pci/devices/*/reset). Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 117 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 104 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 0c07cf5..b48c382 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -179,6 +180,16 @@ static const struct pci_device_id mhi_pci_id_table[] = { }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); +enum mhi_pci_device_status { + MHI_PCI_DEV_STARTED, +}; + +struct mhi_pci_device { + struct mhi_controller mhi_cntrl; + struct pci_saved_state *pci_state; + unsigned long status; +}; + static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, void __iomem *addr, u32 *out) { @@ -203,6 +214,20 @@ static inline void mhi_pci_reset(struct mhi_controller *mhi_cntrl) writel(1, mhi_cntrl->regs + DEV_RESET_REG); } +static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) +{ + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + u16 vendor = 0; + + if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) + return false; + + if (vendor == (u16) ~0 || vendor == 0) + return false; + + return true; +} + static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, unsigned int bar_num, u64 dma_mask) { @@ -298,16 +323,18 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; const struct mhi_controller_config *mhi_cntrl_config; + struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; int err; dev_dbg(&pdev->dev, "MHI PCI device found: %s\n", info->name); - mhi_cntrl = mhi_alloc_controller(); - if (!mhi_cntrl) + mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); + if (!mhi_pdev) return -ENOMEM; mhi_cntrl_config = info->config; + mhi_cntrl = &mhi_pdev->mhi_cntrl; mhi_cntrl->cntrl_dev = &pdev->dev; mhi_cntrl->iova_start = 0; mhi_cntrl->iova_stop = DMA_BIT_MASK(info->dma_data_width); @@ -322,17 +349,21 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) - goto err_release; + return err; err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; + + pci_set_drvdata(pdev, mhi_pdev); - pci_set_drvdata(pdev, mhi_cntrl); + /* Have stored pci confspace at hand for restore in sudden PCI error */ + pci_save_state(pdev); + mhi_pdev->pci_state = pci_store_saved_state(pdev); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) - goto err_release; + return err; /* MHI bus does not power up the controller by default */ err = mhi_prepare_for_power_up(mhi_cntrl); @@ -347,37 +378,97 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) goto err_unprepare; } + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return 0; err_unprepare: mhi_unprepare_after_power_down(mhi_cntrl); err_unregister: mhi_unregister_controller(mhi_cntrl); -err_release: - mhi_free_controller(mhi_cntrl); return err; } static void mhi_pci_remove(struct pci_dev *pdev) { - struct mhi_controller *mhi_cntrl = pci_get_drvdata(pdev); + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, true); + mhi_unprepare_after_power_down(mhi_cntrl); + } - mhi_power_down(mhi_cntrl, true); - mhi_unprepare_after_power_down(mhi_cntrl); mhi_unregister_controller(mhi_cntrl); /* MHI-layer reset could not be enough, always hard-reset the device */ mhi_pci_reset(mhi_cntrl); +} + +void mhi_pci_reset_prepare(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_info(&pdev->dev, "reset\n"); - mhi_free_controller(mhi_cntrl); + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* cause internal device reset */ + mhi_pci_reset(mhi_cntrl); + + /* Be sure device reset has been executed */ + msleep(500); } +void mhi_pci_reset_done(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + /* Restore initial known working PCI state */ + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + /* Is device status available ? */ + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(&pdev->dev, "reset failed\n"); + return; + } + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to prepare MHI controller\n"); + return; + } + + err = mhi_sync_power_up(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to power up MHI controller\n"); + mhi_unprepare_after_power_down(mhi_cntrl); + return; + } + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); +} + +static const struct pci_error_handlers mhi_pci_err_handler = { + .reset_prepare = mhi_pci_reset_prepare, + .reset_done = mhi_pci_reset_done, +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, - .remove = mhi_pci_remove + .remove = mhi_pci_remove, + .err_handler = &mhi_pci_err_handler, }; module_pci_driver(mhi_pci_driver); From patchwork Mon Nov 23 14:11:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330676 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026541ilh; Mon, 23 Nov 2020 06:05:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJzBTSTXLQCgYPBaMYtzgW6FDJAfYTRP9OtloNUWPfwgBdJ9qw4oeNXcsC8hsaaLRBHYlPNx X-Received: by 2002:a50:d701:: with SMTP id t1mr17617294edi.177.1606140304182; Mon, 23 Nov 2020 06:05:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140304; cv=none; d=google.com; s=arc-20160816; b=Ya6JG4hBG0YYAjlyXvTeOLZOb7HPGa00TjOQ06y61kN4yJp+0Gk8Zs27/WaVA/c5SY +56RYpoxssFxpmGEz/QI9JUcQleDZS05TcikAoqe/VF/bJleefU8X8nxXQeaYUE+IgcA cPXl5/Eyov7s9iLt+Upo59XYV+UnjJgVTaKbRSsyQXVg6TVuzfyoLLFj2b1Wzl/NQr7y PPtpnjGcsmWuPd/PHwW41/4ltW4i4HWSnDvVhkAHP+4CJ65zJzV3jLAzKBek+oAPM4+z o009hRdL3En0DK2+I7OPz/Nj1IN52fE7pEArQHcSqB5uQWYuxxS6+wR72icCH0b3rhDb 2OJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=7hGqz0DXG1r/91eN8wyw/In0sVZggxxLUfBYKuvAK5E=; b=NMq96wOZRKB5vPZNRMbXiS6Aip7e4DxotZ4yepjqgk/h6Ru7p/mHSahCDZ8Hv4YJOH 4qQB+7zF17dhIg6BTBC5HvlRmzN4x9aeYSaddfMcGSqe+GFRXlXIDeMODSvwMnK6Egft CKZcZzYeUI9D4QKa5vxf01n3kLOpkZyU6nWd1j8mdHKIMUgc6seMtWtcArcvHttkkCkP i9ZKSQ1Ki+A/AAD1Li+9pGh1cx22x3qpo7ohuL4xHY0AlnSTqUjIBAJBD47Iyd5ar5VT FBGjtR/EaLuC0GKCtfWfxJUTGukf/ep7pYhu92aUbuUb6Jwxf1tQnF46DxH7uZUQnPpf l2/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ij/wqtdP"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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During suspend, MHI device controller must be put in M3 state and PCI bus in D3 state. Add a recovery procedure allowing to reinitialize the device in case of error during resume steps, which can happen if device loses power (and so its context) while system suspend. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 102 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index b48c382..3eefef3 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -13,6 +13,7 @@ #include #include #include +#include #define MHI_PCI_DEFAULT_BAR_NUM 0 @@ -187,6 +188,7 @@ enum mhi_pci_device_status { struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; + struct work_struct recovery_work; unsigned long status; }; @@ -319,6 +321,48 @@ static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) /* no PM for now */ } +static void mhi_pci_recovery_work(struct work_struct *work) +{ + struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, + recovery_work); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); + int err; + + dev_warn(&pdev->dev, "device recovery started\n"); + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } + + /* Check if we can recover without full reset */ + pci_set_power_state(pdev, PCI_D0); + pci_load_saved_state(pdev, mhi_pdev->pci_state); + pci_restore_state(pdev); + + if (!mhi_pci_is_alive(mhi_cntrl)) + goto err_try_reset; + + err = mhi_prepare_for_power_up(mhi_cntrl); + if (err) + goto err_try_reset; + + err = mhi_sync_power_up(mhi_cntrl); + if (err) + goto err_unprepare; + + set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + return; + +err_unprepare: + mhi_unprepare_after_power_down(mhi_cntrl); +err_try_reset: + if (pci_reset_function(pdev)) + dev_err(&pdev->dev, "Recovery failed\n"); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -333,6 +377,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (!mhi_pdev) return -ENOMEM; + INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; mhi_cntrl->cntrl_dev = &pdev->dev; @@ -395,6 +441,8 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + cancel_work_sync(&mhi_pdev->recovery_work); + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, true); mhi_unprepare_after_power_down(mhi_cntrl); @@ -463,12 +511,66 @@ static const struct pci_error_handlers mhi_pci_err_handler = { .reset_done = mhi_pci_reset_done, }; +int __maybe_unused mhi_pci_suspend(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + cancel_work_sync(&mhi_pdev->recovery_work); + + /* Transition to M3 state */ + mhi_pm_suspend(mhi_cntrl); + + pci_save_state(pdev); + pci_disable_device(pdev); + pci_wake_from_d3(pdev, true); + pci_set_power_state(pdev, PCI_D3hot); + + return 0; +} + +static int __maybe_unused mhi_pci_resume(struct device *dev) +{ + struct pci_dev *pdev = to_pci_dev(dev); + struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + int err; + + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + pci_set_master(pdev); + + err = pci_enable_device(pdev); + if (err) + goto err_recovery; + + /* Exit M3, transition to M0 state */ + err = mhi_pm_resume(mhi_cntrl); + if (err) { + dev_err(&pdev->dev, "failed to resume device: %d\n", err); + goto err_recovery; + } + + return 0; + +err_recovery: + /* The device may have loose power or crashed, try recovering it */ + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return 0; +} + +static const struct dev_pm_ops mhi_pci_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(mhi_pci_suspend, mhi_pci_resume) +}; + static struct pci_driver mhi_pci_driver = { .name = "mhi-pci-generic", .id_table = mhi_pci_id_table, .probe = mhi_pci_probe, .remove = mhi_pci_remove, .err_handler = &mhi_pci_err_handler, + .driver.pm = &mhi_pci_pm_ops }; module_pci_driver(mhi_pci_driver); From patchwork Mon Nov 23 14:11:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330675 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026553ilh; Mon, 23 Nov 2020 06:05:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJwGRp0/p/MmmqWZMIMKSDGgbz6euSMwq2J2uk9MBPAz7prqkCWDeNyVbdHT9REI19oQIvRL X-Received: by 2002:a17:906:d96e:: with SMTP id rp14mr23696288ejb.214.1606140304834; Mon, 23 Nov 2020 06:05:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140304; cv=none; d=google.com; s=arc-20160816; b=dTjonAUzkDenqkDlKWrGZNi9Kzltl5U6Yo63kTabKiyP89GYROdlDuPJAxkLwgtpvB rWNbQYgSD6h2B3VQySMT8swxctYCKFDJMNBZFl4DTYzzzvWlkmUPp+kdPS1KzDlRoLL7 FFQpYvMc0kFkEoNIWlqvIx+PwOMav4kVkDmeBC1djk5psXvEx0lbSCp+pjgfX3WD2gnx qfrFLofiU6HAqDbivU/jOCU0dBR95TcXQMrjXoFbOCBIpuM+GmgfneW3DyIxrLu4is1g pF0swizM/iDizSijPFpRk76zULYlPndKR2brC4jsi6B6BI7TO+1+WKN1Wn/Ea811hwH+ iSzg== ARC-Message-Signature: i=1; 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This patch enables error reporting and implements error_detected, slot_reset and resume callbacks. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 50 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3eefef3..b01b279 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -8,6 +8,7 @@ * Copyright (C) 2020 Linaro Ltd */ +#include #include #include #include @@ -407,6 +408,8 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) pci_save_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev); + pci_enable_pcie_error_reporting(pdev); + err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); if (err) return err; @@ -506,7 +509,54 @@ void mhi_pci_reset_done(struct pci_dev *pdev) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); } +static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); + + if (state == pci_channel_io_perm_failure) + return PCI_ERS_RESULT_DISCONNECT; + + /* Clean up MHI state */ + if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { + mhi_power_down(mhi_cntrl, false); + mhi_unprepare_after_power_down(mhi_cntrl); + } else { + /* Nothing to do */ + return PCI_ERS_RESULT_RECOVERED; + } + + pci_disable_device(pdev); + + return PCI_ERS_RESULT_NEED_RESET; +} + +static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) +{ + if (pci_enable_device(pdev)) { + dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + + return PCI_ERS_RESULT_RECOVERED; +} + +static void mhi_pci_io_resume(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); + + dev_err(&pdev->dev, "PCI slot reset done\n"); + + queue_work(system_long_wq, &mhi_pdev->recovery_work); +} + static const struct pci_error_handlers mhi_pci_err_handler = { + .error_detected = mhi_pci_error_detected, + .slot_reset = mhi_pci_slot_reset, + .resume = mhi_pci_io_resume, .reset_prepare = mhi_pci_reset_prepare, .reset_done = mhi_pci_reset_done, }; From patchwork Mon Nov 23 14:11:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 330678 Delivered-To: patch@linaro.org Received: by 2002:a92:ae0b:0:0:0:0:0 with SMTP id s11csp2026576ilh; Mon, 23 Nov 2020 06:05:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJymCISmxt+fGmXKV3nb2MjGX3BnQT2dXuQo7N1CbMjCwBWfsy+5Jrwtn0tHp3BE9aaoLFCf X-Received: by 2002:a2e:9f08:: with SMTP id u8mr12092749ljk.352.1606140305462; Mon, 23 Nov 2020 06:05:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606140305; cv=none; d=google.com; s=arc-20160816; b=rTWokLmW76p18EB5vd1t4NnIh54UE16A6DbHWrSehoH5ykrZ2DQDMlVAQQHua+cufV fM14JnOoR1ehMqF5eDp4o26CMnEYeirVwrCDB+PWfMAVIghJnQGZ7xAkFlBydrNyt9g0 aOkFEYq4GDih/saaD0ISs2MVEExWfR2oWWikt2INTH9AyvnJdE3msh1WlwYyWDN6/V4R aW6iQJ6/dk3Cyo6kMTEx6YkEsD9SKtssVPnvettEttBzhtMI6XK4KqppptSWAkdUUJR+ K4katiAd6m8UzC/CmIs1X+jryMxfdCdhtSn/zD7CUFXqANkRX2T7AXGCxQwti3hXxNem UPLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=1HI0pCo2+/oozX8CtYZKHUpelVlKiv7qQ+fzYe8BBCY=; b=gSt8D6I18/MvNNrv28wG8wrvs/jSS1O7C5tN3W8wptHgyhkVTJ3c4t5UDXss5VsrNe aCwnNCiI3LEDKJiJcbs8VRRhtv4LuzP/A7MrdOba9J7JgxH8E28hl/x3LyRWtiMOv7Zl BHLO/nUoVbwvVjrOcBIbkJjRQEpHvOzF0hFpHKxwkwrmkrh9G2vUsfV03l78hfX2kU0I w7ONE4YkDHKfiR8iIWXMYG+h8xTOOm70ooUi3K2UbW3Z7TNFXCn5yIt4MknB3TUh0by6 hEXMQn3QH0VD6xCJZXL2jiZ/WByx65G1BjJZ9Y3UdfYvmO2+TnkKTVk+j9Fuy4IRqBsB jz6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="sP/fqK9g"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This patch implements a health-check mechanism to check regularly that device is alive (MHI layer can communicate with). If device is not alive (because a crash or unexpected reset), the recovery procedure is triggered. Tested successfully with Telit FN980m module. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index b01b279..3e00658 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -14,12 +14,15 @@ #include #include #include +#include #include #define MHI_PCI_DEFAULT_BAR_NUM 0 #define DEV_RESET_REG (0xB0) +#define HEALTH_CHECK_PERIOD (HZ * 5) + /** * struct mhi_pci_dev_info - MHI PCI device specific information * @config: MHI controller configuration @@ -190,6 +193,7 @@ struct mhi_pci_device { struct mhi_controller mhi_cntrl; struct pci_saved_state *pci_state; struct work_struct recovery_work; + struct timer_list health_check_timer; unsigned long status; }; @@ -332,6 +336,8 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_warn(&pdev->dev, "device recovery started\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -355,6 +361,7 @@ static void mhi_pci_recovery_work(struct work_struct *work) goto err_unprepare; set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); return; err_unprepare: @@ -364,6 +371,21 @@ static void mhi_pci_recovery_work(struct work_struct *work) dev_err(&pdev->dev, "Recovery failed\n"); } +static void health_check(struct timer_list *t) +{ + struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); + struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + + if (!mhi_pci_is_alive(mhi_cntrl)) { + dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); + queue_work(system_long_wq, &mhi_pdev->recovery_work); + return; + } + + /* reschedule in two seconds */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); +} + static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; @@ -379,6 +401,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return -ENOMEM; INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); + timer_setup(&mhi_pdev->health_check_timer, health_check, 0); mhi_cntrl_config = info->config; mhi_cntrl = &mhi_pdev->mhi_cntrl; @@ -429,6 +452,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + /* start health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_unprepare: @@ -444,6 +470,7 @@ static void mhi_pci_remove(struct pci_dev *pdev) struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { @@ -464,6 +491,8 @@ void mhi_pci_reset_prepare(struct pci_dev *pdev) dev_info(&pdev->dev, "reset\n"); + del_timer(&mhi_pdev->health_check_timer); + /* Clean up MHI state */ if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { mhi_power_down(mhi_cntrl, false); @@ -507,6 +536,7 @@ void mhi_pci_reset_done(struct pci_dev *pdev) } set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); } static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, @@ -567,6 +597,7 @@ int __maybe_unused mhi_pci_suspend(struct device *dev) struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; + del_timer(&mhi_pdev->health_check_timer); cancel_work_sync(&mhi_pdev->recovery_work); /* Transition to M3 state */ @@ -602,6 +633,9 @@ static int __maybe_unused mhi_pci_resume(struct device *dev) goto err_recovery; } + /* Resume health check */ + mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); + return 0; err_recovery: From patchwork Mon Nov 23 14:11:06 2020 Content-Type: text/plain; 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Increase the timeout to prevent MHI power-up issues. Signed-off-by: Loic Poulain --- drivers/bus/mhi/pci_generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 3e00658..672c5f5 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -162,7 +162,7 @@ static const struct mhi_event_config modem_qcom_v1_mhi_events[] = { static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { .max_channels = 128, - .timeout_ms = 5000, + .timeout_ms = 8000, .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), .ch_cfg = modem_qcom_v1_mhi_channels, .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),