From patchwork Fri Jan 19 08:13:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125110 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp184238ljf; Fri, 19 Jan 2018 00:14:17 -0800 (PST) X-Google-Smtp-Source: ACJfBouK+R3BWTRHcULRyHyxmykHot0nACryDumGp4Q8a0SzngFoqD3xKugbin5Rpe2wLawKuAa0 X-Received: by 10.99.6.72 with SMTP id 69mr30145464pgg.50.1516349657378; Fri, 19 Jan 2018 00:14:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516349657; cv=none; d=google.com; s=arc-20160816; b=smLC0acMFZHgpHNezEs9myyy5YhZAmYhmd1nLvBUW9kClNC5xtZiZq7bMplKCUHLiG BIIG1r4XzY5kJvVlsAt8LBoxkmFkOVegooXXChKW/VF2qmf2zJ7bmQF8tWJxIAaPpBaw v2l7tCZZyLmzOjnh3qUMbLS963kVSd6/whibMLLJbMkofAg020cllNa3B+cBeVk8WXGv HIjBJdgdbfKGxUfnTVZM5zXLfLz+JCPW4/OhuounmvATYaLCP7xqZvHEis9dINNNAD6G Q0pPvNnGxhocdVweESTarLZCZl5lpA/4vr8cvm6LRzd9ky4QeKB2c8o2fLG518kO5Gtt EKDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Hn2ZR8qQyO/3FtH340kDoI7aN/RaZtzgRDrqax/Io3c=; b=qVtGQBd3y/IqBwmidblBblMyn2SvMGqEZw3GjXz9sOigZ1EfurbKveXK0dgdK+sQyN FIyGHumEDtneWkaX2+Nh31yBLpGqSg51CqbE0BQAFhKlBewBXl13UtpN7PGVdENFcL1r d7ToiWR0t52Ni7Ss1bbRrCfb36LaX8iS8DFa/y+yYa6A9kK0Ss1gbjmvISsyarLbXyAD ggxCy9lPaJCQWdqseG6ctFLrntwQAz6M1EyS37jPPva05Ib8PlPf0a/q5JautGakNjNv 54zGtsLio2WIGYhh1o9Vcusy60mT0MUqXScEkAYtF8P1/SgsfBrs39Sr4UPHu8jE1rwH B87A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si7682824pgb.825.2018.01.19.00.14.16; Fri, 19 Jan 2018 00:14:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753618AbeASIOO (ORCPT + 6 others); Fri, 19 Jan 2018 03:14:14 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:33495 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751548AbeASION (ORCPT ); Fri, 19 Jan 2018 03:14:13 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 3D8B92098C; Fri, 19 Jan 2018 09:14:12 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id EE1CD2046F; Fri, 19 Jan 2018 09:13:58 +0100 (CET) From: Maxime Ripard To: Mauro Carvalho Chehab , Mark Rutland , Rob Herring Cc: Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , =?utf-8?q?Niklas_S=C3=B6derlund?= , Hans Verkuil , Sakari Ailus , Benoit Parrot , nm@ti.com, Simon Hatliff , Maxime Ripard Subject: [PATCH v5 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings Date: Fri, 19 Jan 2018 09:13:56 +0100 Message-Id: <20180119081357.20799-2-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119081357.20799-1-maxime.ripard@free-electrons.com> References: <20180119081357.20799-1-maxime.ripard@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Acked-by: Rob Herring Acked-by: Benoit Parrot Acked-by: Sakari Ailus Reviewed-by: Laurent Pinchart Signed-off-by: Maxime Ripard --- .../devicetree/bindings/media/cdns,csi2rx.txt | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt new file mode 100644 index 000000000000..56d51902b2eb --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt @@ -0,0 +1,100 @@ +Cadence MIPI-CSI2 RX controller +=============================== + +The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI +lanes in input, and 4 different pixel streams in output. + +Required properties: + - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible + - reg: base address and size of the memory mapped region + - clocks: phandles to the clocks driving the controller + - clock-names: must contain: + * sys_clk: main clock + * p_clk: register bank clock + * pixel_if[0-3]_clk: pixel stream output clock, one for each stream + implemented in hardware, between 0 and 3 + +Optional properties: + - phys: phandle to the external D-PHY, phy-names must be provided + - phy-names: must contain dphy, if the implementation uses an + external D-PHY + +Required subnodes: + - ports: A ports node with one port child node per device input and output + port, in accordance with the video interface bindings defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + port nodes numbered as follows. + + Port Description + ----------------------------- + 0 CSI-2 input + 1 Stream 0 output + 2 Stream 1 output + 3 Stream 2 output + 4 Stream 3 output + + The stream output port nodes are optional if they are not + connected to anything at the hardware level or implemented + in the design.Since there is only one endpoint per port, + the endpoints are not numbered. + + +Example: + +csi2rx: csi-bridge@0d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock> + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi2rx_in_sensor: endpoint { + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + csi2rx_out_grabber0: endpoint { + remote-endpoint = <&grabber0_in_csi2rx>; + }; + }; + + port@2 { + reg = <2>; + + csi2rx_out_grabber1: endpoint { + remote-endpoint = <&grabber1_in_csi2rx>; + }; + }; + + port@3 { + reg = <3>; + + csi2rx_out_grabber2: endpoint { + remote-endpoint = <&grabber2_in_csi2rx>; + }; + }; + + port@4 { + reg = <4>; + + csi2rx_out_grabber3: endpoint { + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; +}; From patchwork Fri Jan 19 08:13:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 125112 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp184265ljf; Fri, 19 Jan 2018 00:14:22 -0800 (PST) X-Google-Smtp-Source: ACJfBouRS/q0Znbo6LzwRZ+h46r5VZVGqCG/pksRsetu9r1k2E+RhERtNMo5gDp3VQBDZQvvM2we X-Received: by 10.101.86.4 with SMTP id l4mr28345468pgs.276.1516349662568; Fri, 19 Jan 2018 00:14:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516349662; cv=none; d=google.com; s=arc-20160816; b=oZwsqDzuApBHVxsTdjfij1phraxKEK7C1upuCLkAZDoI4V8+Oz5yT2GP4TOeCHWUoM 44gwXtEuEPX4csLozvBmY78wT38fz5DlAqG31EjBgRwCA14k2+kjrkqMaaGDg9hES8XD Skj+6yiwEyMZljBZS9L38/G9bCjoo5iBhSu7CqgXMbbKzW3rYprwaGC2SdYfhR/nPR+f 2F+4escOyqyuAqXduCSET2Ng1jFwl2YlmNDv+4un8OiAh20d+w4rWAQlg4Z2iEK3z+Si K3iO/K6CFw1k3o6r2kmO03q02lZ5bsu2Drl0jCrX9Sw3lZON0kSOraTt9A1Do/5s0qta 6BZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=mjeKiuCgUGPLa61Pn5HzNkN7BDS4vVhFGjP910JCBuY=; b=Zkxt0eEVrid/5v0ncFxhZCVNDeR1pKxu6WS+x/nBi77pM8Hfq4nl/HPnNl9NOzvhpT F0zboFfmbmJGuHruGEvDBoAfQGyRXIfM9T3xMxBIjZp8OaBxVL2Kl1rFm61qtSvQvp7u TnKnRvYoLOLs37RBAkacMvDhzxZlzVc0/QQdWHy3s5aJJvnTWWq0L+Qn7BcSiEGqOjT1 IaF6g9bwR+/cRLKJ4SdxwEUFpibNCuDJkwA5MkAenQSi61W9JALtlP0gzeSa206/ywfa 0A9yj+PAOr5fVDWbKWnUBd67VPEg2ieSoTo1mwY7RRgSh6MkL9umgeNscEIMmGLmHkgF bjUg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v11si7682824pgb.825.2018.01.19.00.14.22; Fri, 19 Jan 2018 00:14:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754542AbeASIOT (ORCPT + 6 others); Fri, 19 Jan 2018 03:14:19 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:33531 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753841AbeASIOP (ORCPT ); Fri, 19 Jan 2018 03:14:15 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 16D9B20885; Fri, 19 Jan 2018 09:14:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 014452088F; Fri, 19 Jan 2018 09:13:59 +0100 (CET) From: Maxime Ripard To: Mauro Carvalho Chehab , Mark Rutland , Rob Herring Cc: Laurent Pinchart , linux-media@vger.kernel.org, devicetree@vger.kernel.org, Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , =?utf-8?q?Niklas_S=C3=B6derlund?= , Hans Verkuil , Sakari Ailus , Benoit Parrot , nm@ti.com, Simon Hatliff , Maxime Ripard Subject: [PATCH v5 2/2] v4l: cadence: Add Cadence MIPI-CSI2 RX driver Date: Fri, 19 Jan 2018 09:13:57 +0100 Message-Id: <20180119081357.20799-3-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180119081357.20799-1-maxime.ripard@free-electrons.com> References: <20180119081357.20799-1-maxime.ripard@free-electrons.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Cadence CSI-2 RX Controller is an hardware block meant to be used as a bridge between a CSI-2 bus and pixel grabbers. It supports operating with internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the former case. It also support dynamic mapping of the CSI-2 virtual channels to the associated pixel grabbers, but that isn't allowed at the moment either. Signed-off-by: Maxime Ripard --- drivers/media/platform/Kconfig | 1 + drivers/media/platform/Makefile | 2 + drivers/media/platform/cadence/Kconfig | 12 + drivers/media/platform/cadence/Makefile | 1 + drivers/media/platform/cadence/cdns-csi2rx.c | 463 +++++++++++++++++++++++++++ 5 files changed, 479 insertions(+) create mode 100644 drivers/media/platform/cadence/Kconfig create mode 100644 drivers/media/platform/cadence/Makefile create mode 100644 drivers/media/platform/cadence/cdns-csi2rx.c -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index fd0c99859d6f..6e790a317fbc 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -26,6 +26,7 @@ config VIDEO_VIA_CAMERA # # Platform multimedia device configuration # +source "drivers/media/platform/cadence/Kconfig" source "drivers/media/platform/davinci/Kconfig" diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 003b0bb2cddf..1cd2984c55d1 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -3,6 +3,8 @@ # Makefile for the video capture/playback device drivers. # +obj-$(CONFIG_VIDEO_CADENCE) += cadence/ + obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o obj-$(CONFIG_VIDEO_VIA_CAMERA) += via-camera.o diff --git a/drivers/media/platform/cadence/Kconfig b/drivers/media/platform/cadence/Kconfig new file mode 100644 index 000000000000..d1b6bbb6a0eb --- /dev/null +++ b/drivers/media/platform/cadence/Kconfig @@ -0,0 +1,12 @@ +config VIDEO_CADENCE + bool "Cadence Video Devices" + +if VIDEO_CADENCE + +config VIDEO_CADENCE_CSI2RX + tristate "Cadence MIPI-CSI2 RX Controller v1.3" + depends on MEDIA_CONTROLLER + depends on VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + +endif diff --git a/drivers/media/platform/cadence/Makefile b/drivers/media/platform/cadence/Makefile new file mode 100644 index 000000000000..99a4086b7448 --- /dev/null +++ b/drivers/media/platform/cadence/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_VIDEO_CADENCE_CSI2RX) += cdns-csi2rx.o diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c new file mode 100644 index 000000000000..ce042b9d403c --- /dev/null +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -0,0 +1,463 @@ +/* + * Driver for Cadence MIPI-CSI2 RX Controller v1.3 + * + * Copyright (C) 2017 Cadence Design Systems Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define CSI2RX_DEVICE_CFG_REG 0x000 + +#define CSI2RX_SOFT_RESET_REG 0x004 +#define CSI2RX_SOFT_RESET_PROTOCOL BIT(1) +#define CSI2RX_SOFT_RESET_FRONT BIT(0) + +#define CSI2RX_STATIC_CFG_REG 0x008 +#define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) +#define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) + +#define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) + +#define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_START BIT(0) + +#define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) +#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) +#define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) + +#define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) +#define CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF (1 << 8) + +#define CSI2RX_LANES_MAX 4 +#define CSI2RX_STREAMS_MAX 4 + +enum csi2rx_pads { + CSI2RX_PAD_SINK, + CSI2RX_PAD_SOURCE_STREAM0, + CSI2RX_PAD_SOURCE_STREAM1, + CSI2RX_PAD_SOURCE_STREAM2, + CSI2RX_PAD_SOURCE_STREAM3, + CSI2RX_PAD_MAX, +}; + +struct csi2rx_priv { + struct device *dev; + atomic_t count; + + void __iomem *base; + struct clk *sys_clk; + struct clk *p_clk; + struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; + struct phy *dphy; + + u8 lanes[CSI2RX_LANES_MAX]; + u8 num_lanes; + u8 max_lanes; + u8 max_streams; + bool has_internal_dphy; + + struct v4l2_subdev subdev; + struct v4l2_async_notifier notifier; + struct media_pad pads[CSI2RX_PAD_MAX]; + + /* Remote source */ + struct v4l2_async_subdev asd; + struct v4l2_subdev *source_subdev; + int source_pad; +}; + +static inline +struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) +{ + return container_of(subdev, struct csi2rx_priv, subdev); +} + +static void csi2rx_reset(struct csi2rx_priv *csi2rx) +{ + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, + csi2rx->base + CSI2RX_SOFT_RESET_REG); + + usleep_range(10, 20); + + writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); +} + +static int csi2rx_start(struct csi2rx_priv *csi2rx) +{ + unsigned int i; + u32 reg; + int ret; + + /* + * We're not the first users, there's no need to enable the + * whole controller. + */ + if (atomic_inc_return(&csi2rx->count) > 1) + return 0; + + clk_prepare_enable(csi2rx->p_clk); + + csi2rx_reset(csi2rx); + + reg = csi2rx->num_lanes << 8; + for (i = 0; i < csi2rx->num_lanes; i++) + reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); + + for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) + reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, i + 1); + + writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); + + ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); + if (ret) + return ret; + + /* + * Create a static mapping between the CSI virtual channels + * and the output stream. + * + * This should be enhanced, but v4l2 lacks the support for + * changing that mapping dynamically. + * + * We also cannot enable and disable independant streams here, + * hence the reference counting. + */ + for (i = 0; i < csi2rx->max_streams; i++) { + clk_prepare_enable(csi2rx->pixel_clk[i]); + + writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, + csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); + + writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | + CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), + csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); + + writel(CSI2RX_STREAM_CTRL_START, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } + + clk_prepare_enable(csi2rx->sys_clk); + + clk_disable_unprepare(csi2rx->p_clk); + + return 0; +} + +static int csi2rx_stop(struct csi2rx_priv *csi2rx) +{ + unsigned int i; + + /* + * Let the last user turn off the lights + */ + if (!atomic_dec_and_test(&csi2rx->count)) + return 0; + + clk_prepare_enable(csi2rx->p_clk); + + for (i = 0; i < csi2rx->max_streams; i++) { + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + + clk_disable_unprepare(csi2rx->pixel_clk[i]); + } + + clk_disable_unprepare(csi2rx->p_clk); + + return v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false); +} + +static int csi2rx_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(sd); + int ret; + + if (enable) + ret = csi2rx_start(csi2rx); + else + ret = csi2rx_stop(csi2rx); + + return ret; +} + +static const struct v4l2_subdev_video_ops csi2rx_video_ops = { + .s_stream = csi2rx_s_stream, +}; + +static const struct v4l2_subdev_ops csi2rx_subdev_ops = { + .video = &csi2rx_video_ops, +}; + +static int csi2rx_async_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *s_subdev, + struct v4l2_async_subdev *asd) +{ + struct v4l2_subdev *subdev = notifier->sd; + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + csi2rx->source_pad = media_entity_get_fwnode_pad(&s_subdev->entity, + s_subdev->fwnode, + MEDIA_PAD_FL_SOURCE); + if (csi2rx->source_pad < 0) { + dev_err(csi2rx->dev, "Couldn't find output pad for subdev %s\n", + s_subdev->name); + return csi2rx->source_pad; + } + + csi2rx->source_subdev = s_subdev; + + dev_dbg(csi2rx->dev, "Bound %s pad: %d\n", s_subdev->name, + csi2rx->source_pad); + + return media_create_pad_link(&csi2rx->source_subdev->entity, + csi2rx->source_pad, + &csi2rx->subdev.entity, 0, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); +} + +static const struct v4l2_async_notifier_operations csi2rx_notifier_ops = { + .bound = csi2rx_async_bound, +}; + +static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, + struct platform_device *pdev) +{ + struct resource *res; + unsigned char i; + u32 reg; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csi2rx->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(csi2rx->base)) + return PTR_ERR(csi2rx->base); + + csi2rx->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); + if (IS_ERR(csi2rx->sys_clk)) { + dev_err(&pdev->dev, "Couldn't get sys clock\n"); + return PTR_ERR(csi2rx->sys_clk); + } + + csi2rx->p_clk = devm_clk_get(&pdev->dev, "p_clk"); + if (IS_ERR(csi2rx->p_clk)) { + dev_err(&pdev->dev, "Couldn't get P clock\n"); + return PTR_ERR(csi2rx->p_clk); + } + + csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy"); + if (IS_ERR(csi2rx->dphy)) { + dev_err(&pdev->dev, "Couldn't get external D-PHY\n"); + return PTR_ERR(csi2rx->dphy); + } + + /* + * FIXME: Once we'll have external D-PHY support, the check + * will need to be removed. + */ + if (csi2rx->dphy) { + dev_err(&pdev->dev, "External D-PHY not supported yet\n"); + return -EINVAL; + } + + clk_prepare_enable(csi2rx->p_clk); + reg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); + clk_disable_unprepare(csi2rx->p_clk); + + csi2rx->max_lanes = (reg & 7); + if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { + dev_err(&pdev->dev, "Invalid number of lanes: %u\n", + csi2rx->max_lanes); + return -EINVAL; + } + + csi2rx->max_streams = ((reg >> 4) & 7); + if (csi2rx->max_streams > CSI2RX_STREAMS_MAX) { + dev_err(&pdev->dev, "Invalid number of streams: %u\n", + csi2rx->max_streams); + return -EINVAL; + } + + csi2rx->has_internal_dphy = (reg & BIT(3)) ? true : false; + + /* + * FIXME: Once we'll have internal D-PHY support, the check + * will need to be removed. + */ + if (csi2rx->has_internal_dphy) { + dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); + return -EINVAL; + } + + for (i = 0; i < csi2rx->max_streams; i++) { + char clk_name[16]; + + snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i); + csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); + if (IS_ERR(csi2rx->pixel_clk[i])) { + dev_err(&pdev->dev, "Couldn't get clock %s\n", clk_name); + return PTR_ERR(csi2rx->pixel_clk[i]); + } + } + + return 0; +} + +static int csi2rx_parse_dt(struct csi2rx_priv *csi2rx) +{ + struct v4l2_fwnode_endpoint v4l2_ep; + struct fwnode_handle *fwh; + struct device_node *ep; + int ret; + + ep = of_graph_get_endpoint_by_regs(csi2rx->dev->of_node, 0, 0); + if (!ep) + return -EINVAL; + + fwh = of_fwnode_handle(ep); + ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); + if (ret) { + dev_err(csi2rx->dev, "Could not parse v4l2 endpoint\n"); + of_node_put(ep); + return ret; + } + + if (v4l2_ep.bus_type != V4L2_MBUS_CSI2) { + dev_err(csi2rx->dev, "Unsupported media bus type: 0x%x\n", + v4l2_ep.bus_type); + of_node_put(ep); + return -EINVAL; + } + + memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, + sizeof(csi2rx->lanes)); + csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; + if (csi2rx->num_lanes > csi2rx->max_lanes) { + dev_err(csi2rx->dev, "Unsupported number of data-lanes: %d\n", + csi2rx->num_lanes); + of_node_put(ep); + return -EINVAL; + } + + csi2rx->asd.match.fwnode.fwnode = fwnode_graph_get_remote_port_parent(fwh); + csi2rx->asd.match_type = V4L2_ASYNC_MATCH_FWNODE; + of_node_put(ep); + + csi2rx->notifier.subdevs = devm_kzalloc(csi2rx->dev, + sizeof(*csi2rx->notifier.subdevs), + GFP_KERNEL); + if (!csi2rx->notifier.subdevs) + return -ENOMEM; + + csi2rx->notifier.subdevs[0] = &csi2rx->asd; + csi2rx->notifier.num_subdevs = 1; + csi2rx->notifier.ops = &csi2rx_notifier_ops; + + return v4l2_async_subdev_notifier_register(&csi2rx->subdev, + &csi2rx->notifier); +} + +static int csi2rx_probe(struct platform_device *pdev) +{ + struct csi2rx_priv *csi2rx; + unsigned int i; + int ret; + + /* + * Since the v4l2_subdev structure is embedded in our + * csi2rx_priv structure, and that the structure is exposed to + * the user-space, we cannot just use the devm_variant + * here. Indeed, that would lead to a use-after-free in a + * open() - unbind - close() pattern. + */ + csi2rx = kzalloc(sizeof(*csi2rx), GFP_KERNEL); + if (!csi2rx) + return -ENOMEM; + platform_set_drvdata(pdev, csi2rx); + csi2rx->dev = &pdev->dev; + + ret = csi2rx_get_resources(csi2rx, pdev); + if (ret) + goto err_free_priv; + + ret = csi2rx_parse_dt(csi2rx); + if (ret) + goto err_free_priv; + + csi2rx->subdev.owner = THIS_MODULE; + csi2rx->subdev.dev = &pdev->dev; + v4l2_subdev_init(&csi2rx->subdev, &csi2rx_subdev_ops); + v4l2_set_subdevdata(&csi2rx->subdev, &pdev->dev); + snprintf(csi2rx->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.%s", + KBUILD_MODNAME, dev_name(&pdev->dev)); + + /* Create our media pads */ + csi2rx->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; + csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + for (i = CSI2RX_PAD_SOURCE_STREAM0; i < CSI2RX_PAD_MAX; i++) + csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; + + ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, + csi2rx->pads); + if (ret) + goto err_free_priv; + + ret = v4l2_async_register_subdev(&csi2rx->subdev); + if (ret < 0) + goto err_free_priv; + + dev_info(&pdev->dev, + "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", + csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, + csi2rx->has_internal_dphy ? "internal" : "no"); + + return 0; + +err_free_priv: + kfree(csi2rx); + return ret; +} + +static int csi2rx_remove(struct platform_device *pdev) +{ + struct csi2rx_priv *csi2rx = platform_get_drvdata(pdev); + + v4l2_async_unregister_subdev(&csi2rx->subdev); + kfree(csi2rx); + + return 0; +} + +static const struct of_device_id csi2rx_of_table[] = { + { .compatible = "cdns,csi2rx" }, + { }, +}; +MODULE_DEVICE_TABLE(of, csi2rx_of_table); + +static struct platform_driver csi2rx_driver = { + .probe = csi2rx_probe, + .remove = csi2rx_remove, + + .driver = { + .name = "cdns-csi2rx", + .of_match_table = csi2rx_of_table, + }, +}; +module_platform_driver(csi2rx_driver);