From patchwork Tue Nov 24 10:21:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 332738 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3ADFCC2D0E4 for ; Tue, 24 Nov 2020 10:16:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DC3CD20708 for ; Tue, 24 Nov 2020 10:16:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731477AbgKXKQ6 (ORCPT ); Tue, 24 Nov 2020 05:16:58 -0500 Received: from mx0a-00128a01.pphosted.com ([148.163.135.77]:45536 "EHLO mx0a-00128a01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731266AbgKXKQ6 (ORCPT ); Tue, 24 Nov 2020 05:16:58 -0500 Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 0AOAET4c031145; Tue, 24 Nov 2020 05:16:56 -0500 Received: from nwd2mta4.analog.com ([137.71.173.58]) by mx0a-00128a01.pphosted.com with ESMTP id 34y0p884gn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 24 Nov 2020 05:16:55 -0500 Received: from ASHBMBX9.ad.analog.com (ASHBMBX9.ad.analog.com [10.64.17.10]) by nwd2mta4.analog.com (8.14.7/8.14.7) with ESMTP id 0AOAGs9v022101 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=FAIL); Tue, 24 Nov 2020 05:16:54 -0500 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 24 Nov 2020 05:16:53 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 24 Nov 2020 05:16:53 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 24 Nov 2020 05:16:53 -0500 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0AOAGpgw028996; Tue, 24 Nov 2020 05:16:51 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v2 1/3] spi: convert to BIT() all spi_device flags Date: Tue, 24 Nov 2020 12:21:50 +0200 Message-ID: <20201124102152.16548-1-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-24_04:2020-11-24,2020-11-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011240062 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This change converts all bit flags for the 'struct spi_device' mode to the BIT() macro. The change is mostly for readability. Since adding more bit fields, might as well convert it now. Signed-off-by: Alexandru Ardelean --- Changelog v1 -> v2: * https://lore.kernel.org/linux-spi/20201111141529.98147-1-alexandru.ardelean@analog.com/ * add patch 'spi: convert to BIT() all spi_device flags' * for patch 'spi: Add SPI_NO_TX/RX support' convert comment to new multi-line format * add patch 'spi: dt-bindings: document zero value for spi-{rx,tx}-bus-width properties' include/linux/spi/spi.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index aa09fdc8042d..66c7d8e45563 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -165,27 +165,27 @@ struct spi_device { u8 bits_per_word; bool rt; u32 mode; -#define SPI_CPHA 0x01 /* clock phase */ -#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_CPHA BIT(0) /* clock phase */ +#define SPI_CPOL BIT(1) /* clock polarity */ #define SPI_MODE_0 (0|0) /* (original MicroWire) */ #define SPI_MODE_1 (0|SPI_CPHA) #define SPI_MODE_2 (SPI_CPOL|0) #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) #define SPI_MODE_X_MASK (SPI_CPOL|SPI_CPHA) -#define SPI_CS_HIGH 0x04 /* chipselect active high? */ -#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ -#define SPI_3WIRE 0x10 /* SI/SO signals shared */ -#define SPI_LOOP 0x20 /* loopback mode */ -#define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ -#define SPI_READY 0x80 /* slave pulls low to pause */ -#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ -#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ -#define SPI_RX_DUAL 0x400 /* receive with 2 wires */ -#define SPI_RX_QUAD 0x800 /* receive with 4 wires */ -#define SPI_CS_WORD 0x1000 /* toggle cs after each word */ -#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */ -#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */ -#define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */ +#define SPI_CS_HIGH BIT(2) /* chipselect active high? */ +#define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */ +#define SPI_3WIRE BIT(4) /* SI/SO signals shared */ +#define SPI_LOOP BIT(5) /* loopback mode */ +#define SPI_NO_CS BIT(6) /* 1 dev/bus, no chipselect */ +#define SPI_READY BIT(7) /* slave pulls low to pause */ +#define SPI_TX_DUAL BIT(8) /* transmit with 2 wires */ +#define SPI_TX_QUAD BIT(9) /* transmit with 4 wires */ +#define SPI_RX_DUAL BIT(10) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(11) /* receive with 4 wires */ +#define SPI_CS_WORD BIT(12) /* toggle cs after each word */ +#define SPI_TX_OCTAL BIT(13) /* transmit with 8 wires */ +#define SPI_RX_OCTAL BIT(14) /* receive with 8 wires */ +#define SPI_3WIRE_HIZ BIT(15) /* high impedance turnaround */ int irq; void *controller_state; void *controller_data; From patchwork Tue Nov 24 10:21:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 331843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D19B9C56201 for ; Tue, 24 Nov 2020 10:17:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BA562076B for ; Tue, 24 Nov 2020 10:17:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731540AbgKXKRA (ORCPT ); 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Tue, 24 Nov 2020 02:16:55 -0800 Received: from zeus.spd.analog.com (10.66.68.11) by SCSQMBX11.ad.analog.com (10.77.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 24 Nov 2020 02:16:55 -0800 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0AOAGpgx028996; Tue, 24 Nov 2020 05:16:53 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v2 2/3] spi: Add SPI_NO_TX/RX support Date: Tue, 24 Nov 2020 12:21:51 +0200 Message-ID: <20201124102152.16548-2-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124102152.16548-1-alexandru.ardelean@analog.com> References: <20201124102152.16548-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-24_04:2020-11-24,2020-11-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 spamscore=0 mlxlogscore=901 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011240062 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Dragos Bogdan Transmit/receive only is a valid SPI mode. For example, the MOSI/TX line might be missing from an ADC while for a DAC the MISO/RX line may be optional. This patch adds these two new modes: SPI_NO_TX and SPI_NO_RX. This way, the drivers will be able to identify if any of these two lines is missing and to adjust the transfers accordingly. Signed-off-by: Dragos Bogdan Signed-off-by: Alexandru Ardelean --- Changelog v1 -> v2: * https://lore.kernel.org/linux-spi/20201111141529.98147-1-alexandru.ardelean@analog.com/ * convert comment to new multi-line format drivers/spi/spi.c | 26 +++++++++++++++++++++----- include/linux/spi/spi.h | 2 ++ 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 0c3f3a962448..5784fa8d9d74 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1939,6 +1939,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, /* Device DUAL/QUAD mode */ if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) { switch (value) { + case 0: + spi->mode |= SPI_NO_TX; + break; case 1: break; case 2: @@ -1960,6 +1963,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) { switch (value) { + case 0: + spi->mode |= SPI_NO_RX; + break; case 1: break; case 2: @@ -3327,12 +3333,17 @@ int spi_setup(struct spi_device *spi) unsigned bad_bits, ugly_bits; int status; - /* check mode to prevent that DUAL and QUAD set at the same time + /* + * check mode to prevent that any two of DUAL, QUAD and NO_MOSI/MISO + * are set at the same time */ - if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) || - ((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) { + if ((hweight_long(spi->mode & + (SPI_TX_DUAL | SPI_TX_QUAD | SPI_NO_TX)) > 1) || + (hweight_long(spi->mode & + (SPI_RX_DUAL | SPI_RX_QUAD | SPI_NO_RX)) > 1)) { dev_err(&spi->dev, - "setup: can not select dual and quad at the same time\n"); + "setup: can not select any two of dual, quad and no-rx/tx " + "at the same time\n"); return -EINVAL; } /* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden @@ -3346,7 +3357,8 @@ int spi_setup(struct spi_device *spi) * SPI_CS_WORD has a fallback software implementation, * so it is ignored here. */ - bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD); + bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD | + SPI_NO_TX | SPI_NO_RX); /* nothing prevents from working with active-high CS in case if it * is driven by GPIO. */ @@ -3607,6 +3619,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) * 2. check tx/rx_nbits match the mode in spi_device */ if (xfer->tx_buf) { + if (spi->mode & SPI_NO_TX) + return -EINVAL; if (xfer->tx_nbits != SPI_NBITS_SINGLE && xfer->tx_nbits != SPI_NBITS_DUAL && xfer->tx_nbits != SPI_NBITS_QUAD) @@ -3620,6 +3634,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) } /* check transfer rx_nbits */ if (xfer->rx_buf) { + if (spi->mode & SPI_NO_RX) + return -EINVAL; if (xfer->rx_nbits != SPI_NBITS_SINGLE && xfer->rx_nbits != SPI_NBITS_DUAL && xfer->rx_nbits != SPI_NBITS_QUAD) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 66c7d8e45563..8f3343d3ac27 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -186,6 +186,8 @@ struct spi_device { #define SPI_TX_OCTAL BIT(13) /* transmit with 8 wires */ #define SPI_RX_OCTAL BIT(14) /* receive with 8 wires */ #define SPI_3WIRE_HIZ BIT(15) /* high impedance turnaround */ +#define SPI_NO_TX BIT(16) /* no transmit wire */ +#define SPI_NO_RX BIT(17) /* no receive wire */ int irq; void *controller_state; void *controller_data; From patchwork Tue Nov 24 10:21:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru Ardelean X-Patchwork-Id: 332737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F071C2D0E4 for ; Tue, 24 Nov 2020 10:17:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 42E7120708 for ; Tue, 24 Nov 2020 10:17:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731584AbgKXKRB (ORCPT ); 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Tue, 24 Nov 2020 05:16:56 -0500 Received: from ASHBMBX9.ad.analog.com (10.64.17.10) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1779.2; Tue, 24 Nov 2020 05:16:56 -0500 Received: from zeus.spd.analog.com (10.66.68.11) by ASHBMBX9.ad.analog.com (10.64.17.10) with Microsoft SMTP Server id 15.1.1779.2 via Frontend Transport; Tue, 24 Nov 2020 05:16:56 -0500 Received: from localhost.localdomain ([10.48.65.12]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 0AOAGph0028996; Tue, 24 Nov 2020 05:16:54 -0500 From: Alexandru Ardelean To: , , CC: , , , , Alexandru Ardelean Subject: [PATCH v2 3/3] spi: dt-bindings: document zero value for spi-{rx, tx}-bus-width properties Date: Tue, 24 Nov 2020 12:21:52 +0200 Message-ID: <20201124102152.16548-3-alexandru.ardelean@analog.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201124102152.16548-1-alexandru.ardelean@analog.com> References: <20201124102152.16548-1-alexandru.ardelean@analog.com> MIME-Version: 1.0 X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-24_04:2020-11-24,2020-11-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 spamscore=0 mlxlogscore=684 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011240062 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Following a change to the SPI framework, providing a value of zero for 'spi-rx-bus-width' and 'spi-tx-bus-width' is now possible and will essentially mean than no RX or TX is allowed. Signed-off-by: Alexandru Ardelean --- Changelog v1 -> v2: * https://lore.kernel.org/linux-spi/20201111141529.98147-1-alexandru.ardelean@analog.com/ * add patch 'spi: dt-bindings: document zero value for spi-{rx,tx}-bus-width properties' Documentation/devicetree/bindings/spi/spi-controller.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 1b56d5e40f1f..f1aaaf9b3709 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -125,8 +125,9 @@ patternProperties: spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. + If 0 is provided, then no RX will be possible on this devices. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0, 1, 2, 4, 8] default: 1 spi-rx-delay-us: @@ -136,8 +137,9 @@ patternProperties: spi-tx-bus-width: description: Bus width to the SPI bus used for write transfers. + If 0 is provided, then no RX will be possible on this devices. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4, 8] + enum: [0, 1, 2, 4, 8] default: 1 spi-tx-delay-us: