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Tue, 24 Nov 2020 20:06:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD Date: Tue, 24 Nov 2020 20:06:32 -0800 Message-Id: <20201125040642.2339476-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d04ca3a8a..17883d00f4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6458,7 +6458,7 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); @@ -6487,7 +6487,7 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); @@ -6595,7 +6595,7 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = tcg_temp_new_i32(); - gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data); store_reg(s, a->rt, tmp); tcg_gen_addi_i32(addr, addr, 4); @@ -6634,7 +6634,7 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); - gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN_4 | s->be_data); tcg_temp_free_i32(tmp); tcg_gen_addi_i32(addr, addr, 4); From patchwork Wed Nov 25 04:06:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332356 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp122718ilb; Tue, 24 Nov 2020 20:09:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJxv9zVzIW6s0Hc5SbX2sH3ctQzv8NXOEJ+25Hwf0A9scRLQ68xXDKsxWhjB3kthYv4BiW11 X-Received: by 2002:a25:8401:: with SMTP id u1mr2567726ybk.96.1606277366422; Tue, 24 Nov 2020 20:09:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277366; cv=none; d=google.com; s=arc-20160816; b=Zbp8dA6v6oBc+GQyjGWH9/98DajgBxmm9+xWm2i9spLrWIdTfRxp8UqdRIb0Ipn/wX rTHmRnpbc2tca+XZEm40VU7GO2z8AJ9/waJKgtVOMK3mnDo4xh64y66Fh+HaSiFqGTpf mA6VOFLt/kH7bFORgvRxFgNi9h8hwLX1nOs4h3bEW+l9qHEkP7e7sgU+OvgsFUxfU1hx 7IovGDsDtqiqFh8+Ubzszs8ATiXfIoZILrfZfsOlZHSqAmJF03vKKbKbiMi9oWXga+Do vLOf22VGQKcHmoTSFq1f/lgPYSkINbcOri9ueh1hpAzqOCfg5RDOwjygzDUWgmC+ZXtw VM0g== ARC-Message-Signature: i=1; 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Tue, 24 Nov 2020 20:06:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Date: Tue, 24 Nov 2020 20:06:33 -0800 Message-Id: <20201125040642.2339476-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate.c b/target/arm/translate.c index 17883d00f4..73b3d8cbbf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6876,7 +6876,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) static bool trans_STL(DisasContext *s, arg_STL *a) { - return op_stl(s, a, MO_UL); + return op_stl(s, a, MO_UL | MO_ALIGN); } static bool trans_STLB(DisasContext *s, arg_STL *a) @@ -6886,7 +6886,7 @@ static bool trans_STLB(DisasContext *s, arg_STL *a) static bool trans_STLH(DisasContext *s, arg_STL *a) { - return op_stl(s, a, MO_UW); + return op_stl(s, a, MO_UW | MO_ALIGN); } static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) @@ -7033,7 +7033,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) static bool trans_LDA(DisasContext *s, arg_LDA *a) { - return op_lda(s, a, MO_UL); + return op_lda(s, a, MO_UL | MO_ALIGN); } static bool trans_LDAB(DisasContext *s, arg_LDA *a) @@ -7043,7 +7043,7 @@ static bool trans_LDAB(DisasContext *s, arg_LDA *a) static bool trans_LDAH(DisasContext *s, arg_LDA *a) { - return op_lda(s, a, MO_UW); + return op_lda(s, a, MO_UW | MO_ALIGN); } /* From patchwork Wed Nov 25 04:06:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332358 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp123454ilb; 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Tue, 24 Nov 2020 20:06:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/11] target/arm: Enforce alignment for LDM/STM Date: Tue, 24 Nov 2020 20:06:34 -0800 Message-Id: <20201125040642.2339476-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x544.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 73b3d8cbbf..fe4400fa6c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7814,7 +7814,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) } else { tmp = load_reg(s, i); } - gen_aa32_st32(s, tmp, addr, mem_idx); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN | s->be_data); tcg_temp_free_i32(tmp); /* No need to add after the last transfer. */ @@ -7889,7 +7889,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) } tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, mem_idx); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN | s->be_data); if (user) { tmp2 = tcg_const_i32(i); gen_helper_set_user_reg(cpu_env, tmp2, tmp); From patchwork Wed Nov 25 04:06:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332353 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp121604ilb; Tue, 24 Nov 2020 20:07:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJwX30C9czcSMUQM+Z8blyUdRe659BcJoiqQTLt5sL1OCp5JShKiVBBrR1iAIJ4lDVhKaMFv X-Received: by 2002:a25:680d:: with SMTP id d13mr1736678ybc.92.1606277228033; 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Tue, 24 Nov 2020 20:06:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/11] target/arm: Enforce alignment for RFE Date: Tue, 24 Nov 2020 20:06:35 -0800 Message-Id: <20201125040642.2339476-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index fe4400fa6c..4406f6a67c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8250,10 +8250,12 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a) /* Load PC into tmp and CPSR into tmp2. */ t1 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t1, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); tcg_gen_addi_i32(addr, addr, 4); t2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, t2, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); if (a->w) { /* Base writeback. */ From patchwork Wed Nov 25 04:06:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332360 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp124382ilb; Tue, 24 Nov 2020 20:13:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJxdOMqTz5DRR2na1oFfic7NzYU6LGYePdrz71MiZet3GEC2FBp1BaaCoQ7YM4R3QYFNKORC X-Received: by 2002:a25:6986:: with SMTP id e128mr1871800ybc.93.1606277596624; Tue, 24 Nov 2020 20:13:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277596; cv=none; d=google.com; s=arc-20160816; b=u53baPdhUzXeSMi2v07zRi6epS3KAeu5YqWQ9gTdtO8pvpIWE5SCYZAefLPhNfL1B+ bkrbs4ODG1hTPrWOgouTXGl/GTZdXlgnTyAhip2AuRtJelHoybf5wY+adbcqkP1a7jDs xbpiO02Ush/NHl5LiqZvyBstRwh5MM5BRXWOJT1WXOO3nMZH/z9sg9LRHIl5PARpU8QZ EjCSRGH1PRvbPnVyU7ez1OxUWONv78VnjQk3R/DExYLIfKMa3biEET0TvhPN4B3Pw0+Y vSfAkPQtCCxPFNwbkgnQRvaIUS4aonzbOgjBFWlwsINEU70rDYpPwlguHxmmNInzmCID ATFw== ARC-Message-Signature: i=1; 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Tue, 24 Nov 2020 20:06:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/11] target/arm: Enforce alignment for SRS Date: Tue, 24 Nov 2020 20:06:36 -0800 Message-Id: <20201125040642.2339476-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 4406f6a67c..b1f43bfb8f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5124,11 +5124,13 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); tcg_temp_free_i32(tmp); tmp = load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { From patchwork Wed Nov 25 04:06:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332357 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp123066ilb; Tue, 24 Nov 2020 20:10:16 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwJeIjhRXodi873uUlA6zaBxHFEnK6FhqEBKQPYKmkRtH+ix4x17tOHUaCJRTG955SqpXL X-Received: by 2002:a25:df82:: with SMTP id w124mr1762100ybg.347.1606277416374; Tue, 24 Nov 2020 20:10:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; 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Tue, 24 Nov 2020 20:06:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM Date: Tue, 24 Nov 2020 20:06:37 -0800 Message-Id: <20201125040642.2339476-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 96948f5a2d..58b31ecc3f 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -1065,12 +1065,14 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); vfp_store_reg32(tmp, a->vd + i); } else { /* store */ vfp_load_reg32(tmp, a->vd + i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); } tcg_gen_addi_i32(addr, addr, offset); } @@ -1148,12 +1150,14 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) for (i = 0; i < n; i++) { if (a->l) { /* load */ - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), + MO_Q | MO_ALIGN_4 | s->be_data); vfp_store_reg64(tmp, a->vd + i); } else { /* store */ vfp_load_reg64(tmp, a->vd + i); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), + MO_Q | MO_ALIGN_4 | s->be_data); } tcg_gen_addi_i32(addr, addr, offset); } From patchwork Wed Nov 25 04:06:38 2020 Content-Type: text/plain; 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Tue, 24 Nov 2020 20:06:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR Date: Tue, 24 Nov 2020 20:06:38 -0800 Message-Id: <20201125040642.2339476-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 58b31ecc3f..51e85c2767 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -926,11 +926,13 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + MO_UW | MO_ALIGN | s->be_data); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + MO_UW | MO_ALIGN | s->be_data); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -960,11 +962,13 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); vfp_store_reg32(tmp, a->vd); } else { vfp_load_reg32(tmp, a->vd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), + MO_UL | MO_ALIGN | s->be_data); } tcg_temp_free_i32(tmp); tcg_temp_free_i32(addr); @@ -1001,11 +1005,13 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i64(); if (a->l) { - gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); + gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), + MO_Q | MO_ALIGN_4 | s->be_data); vfp_store_reg64(tmp, a->vd); } else { vfp_load_reg64(tmp, a->vd); - gen_aa32_st64(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), + MO_Q | MO_ALIGN_4 | s->be_data); } tcg_temp_free_i64(tmp); tcg_temp_free_i32(addr); From patchwork Wed Nov 25 04:06:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332362 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp125442ilb; Tue, 24 Nov 2020 20:15:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJyKhSZKAjiA3aB3GuT9Djh0UtOcXIbE7Yg6jpvisvDh1z+bhgUWSPbLekKJCTKra5WIjPOT X-Received: by 2002:a25:5f07:: with SMTP id t7mr1514449ybb.121.1606277743754; Tue, 24 Nov 2020 20:15:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277743; 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MO_ALIGN : 0); int nregs = a->n + 1; TCGv_i32 addr, tmp; @@ -559,8 +560,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); for (reg = 0; reg < nregs; reg++) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); if ((vd & 1) && vec_size == 16) { /* * We cannot write 16 bytes at once because the From patchwork Wed Nov 25 04:06:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332359 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp123669ilb; Tue, 24 Nov 2020 20:11:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJyIjQtkGN1iwnU7TFYYGrZU64YUfal+qEI7ZM+UjG80dSmNFevp6K5xbetA1XbwdgUKUQTR X-Received: by 2002:a25:dbcf:: with SMTP id g198mr1689901ybf.110.1606277495186; Tue, 24 Nov 2020 20:11:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277495; cv=none; d=google.com; s=arc-20160816; b=A6zu5Ln+C8ba3aijGcSY4e/+QeYnOhRtGyBa7TkPLyLyiDky569dpqCbNyEGF5away CDNllZWZsBA531QYRKf4Ll6Jlz7z1CQ5r+pHW1r0mwx8ABnBfQLg2TO5KdbvUUEYwbP6 htFiocqLuA7+ncYhFLFHOQg9NLnhKhl+lGo0wzu81qIsIFhmRtlmM5zMMGXK3A23EZqk btVSqu+UnH0H491za3+zPYVCllTLVG2vzUksVDcm0mMn11IRIASBQhD/HZYI5qSx/o8b 0BHczdyKuJ5SplDngIsPseVZlnKU6WN3UCOoncphQJp+UzFKwN1XYaxoqPzix+QDBNc6 +JMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hIrGetngsQpn6DynYHLevrPArG00BLTGCrdQJNoe/Gs=; b=ZNJry+7TvDbRxld5pfOQP1tNnKQ7x3lpX7d73iF3qbvmu6MNGWxWzQ0D0kh0RKWo+9 DX3ksTmUvmf4xgwMVTacfrNodC67U49yYLQtgCJQPlaPc9DZD2DJUueqHqjDl1szsSyz jYRLY1Q298HVX/0+F/f+X2CmbLHx9HOPh857JGmW/nPzDmX090/dHP1jwnTSAmcphtVE ULma6A7C32Uha2LqdrxakM2e0qWTN+k3PdMNjNkuQYKLvbvLwahHx4DMfOKNs1X5GBEh nY6Fo/w/W/9TVMxBkq//AhYIjoq4Av4r9HJNAf5afEUMn+zad76t87pTUFNyb4fQJimL 3DDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m64eETgy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 24 Nov 2020 20:06:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple) Date: Tue, 24 Nov 2020 20:06:40 -0800 Message-Id: <20201125040642.2339476-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 32e47331a5..c4be019d9c 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -427,9 +427,12 @@ static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn, static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) { + static const MemOp mop_align[4] = { + 0, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 + }; /* Neon load/store multiple structures */ int nregs, interleave, spacing, reg, n; - MemOp endian = s->be_data; + MemOp mop, endian = s->be_data; int mmu_idx = get_mem_index(s); int size = a->size; TCGv_i64 tmp64; @@ -487,6 +490,10 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) addr = tcg_temp_new_i32(); tmp = tcg_const_i32(1 << size); load_reg_var(s, addr, a->rn); + + /* Enforce the requested alignment for the first memory operation. */ + mop = endian | size | mop_align[a->align]; + for (reg = 0; reg < nregs; reg++) { for (n = 0; n < 8 >> size; n++) { int xs; @@ -494,13 +501,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) int tt = a->vd + reg + spacing * xs; if (a->l) { - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, mop); neon_store_element64(tt, n, size, tmp64); } else { neon_load_element64(tmp64, tt, n, size); - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); + gen_aa32_st_i64(s, tmp64, addr, mmu_idx, mop); } tcg_gen_add_i32(addr, addr, tmp); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } } } From patchwork Wed Nov 25 04:06:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332361 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp124548ilb; Tue, 24 Nov 2020 20:13:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJwSjcoU12l8p5OQMTwln5FGo5KGqS4plRxLzCSItIR6VJV4Wp37Y2Qrma8hveLmW8LPHYnF X-Received: by 2002:a25:8b82:: with SMTP id j2mr1520701ybl.276.1606277621203; Tue, 24 Nov 2020 20:13:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277621; cv=none; d=google.com; s=arc-20160816; b=WNGpntjuA1bqJJspZ4aBWfrNz+D+z0g5Bn1TwTJMiPaNR9Jchfnb8p5r+zHWxjXaZ5 Kq+Pn3EQxOZeeaxrxRFBYMudYdpFRSjSFHkaHPlhjcyEsnlR5tM3QaeH7tV83F3LBwp8 yKb4TXqdhJAur/AhJ+vEkFED2DckRxLkN/+3esd0+LXzERJ0wmDXxGUOpMgNI+csY2y8 uS7RgfLzwwyCuTIqeoH84wclby4QqPFWS1PnMYrD9N3UQU20YPL01W6+D0D8U/qEAd8D jVtR5BPpJEJsafcMVfMpH3JG1pTWX8uI57pLQaOQiRLPryb+0e3EQAQ1q0CnenqSyyIy fh+Q== ARC-Message-Signature: i=1; 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This error was hidden by what should have been unnecessary masking in translate. Signed-off-by: Richard Henderson --- target/arm/neon-ls.decode | 4 ++-- target/arm/translate-neon.c.inc | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode index c17f5019e3..0a2a0e15db 100644 --- a/target/arm/neon-ls.decode +++ b/target/arm/neon-ls.decode @@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ vd=%vd_dp size=0 stride=1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \ vd=%vd_dp size=1 stride=%imm1_5_p1 -VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \ +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \ vd=%vd_dp size=2 stride=%imm1_6_p1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index c4be019d9c..330b5fc7b0 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -616,7 +616,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) switch (nregs) { case 1: if (((a->align & (1 << a->size)) != 0) || - (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { + (a->size == 2 && (a->align == 1 || a->align == 2))) { return false; } break; @@ -631,7 +631,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) } break; case 4: - if ((a->size == 2) && ((a->align & 3) == 3)) { + if (a->size == 2 && a->align == 3) { return false; } break; From patchwork Wed Nov 25 04:06:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 332363 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp126176ilb; Tue, 24 Nov 2020 20:17:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJzmM7JOdBEsG31RW8UiK7vGg1mGU9mTv84GHIY1ABfdNbBaN7TvWehCPRAcRwIooNSdEAdd X-Received: by 2002:a25:4088:: with SMTP id n130mr1587170yba.483.1606277846134; Tue, 24 Nov 2020 20:17:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606277846; cv=none; d=google.com; s=arc-20160816; b=TJzXO95i7lZXbJH7QatRvGIVgQZriFknIt8LaFNMIN/g8wd4PQCOPYsZ5yj8iG9ixl FFX92wrTQ7OcH4WlX0c0dwm5NPtABrw1fwGy9z9/kunOTqhNtI2QiLKI0Z8vE8mw3sMN C9wIwb2aaRGY3Fv7Ov0BVIZPnJfFkGj7UqznCkBkxHY6XoAY7Qo+NsVwhfuyFsYKxEG6 hwXwVhPq8cNPPW+0CGYF8wl+pD0Cv9O6cypoX1m5nPYSrXQQTLRGUp3Wq+S3F9qij9Hy MPrUMVG6g4svaukv6uhIpIxNH1rf4JB2l1UOwArj1s2pQwUsa604LTazHTApV45i5t89 VlWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=bswwFH6M3LzgrGioTuBuBml8sz+8WXNnbRNFMSINy5c=; b=j8j8LsbktY18sT2peqiAQj2xvjRtXMpFK7/VvwBWL1tS1ylNXhIbMFZPOU6sMPt8Xk OkX6+YwrK16umm2oi2sTaTb4qYaDDeEccjvRongmyFQEOB4PwBPoCvDYoQvVzWYvzB+R 0L7r2FYIBtIMPT/CqPRJl/OS6Q0zqOSvzS1EAaFwZV+oTaCImQYQ/5efKXHjKaApJ+84 r1f/HcWgBktRmftfnr3nB0fDrQm0K7XX2jm4WS3l+zdHJGr57MsrMBpuMR3F+3tvmG21 CVbjnHjreda/I2v4Tk2qGn1MzqxGLZcMknrov5lLkjKhr100j7GD/28MKnYHr1oNrhrj PPyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cPfStF8Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 24 Nov 2020 20:06:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single) Date: Tue, 24 Nov 2020 20:06:42 -0800 Message-Id: <20201125040642.2339476-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org> References: <20201125040642.2339476-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-neon.c.inc | 39 ++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc index 330b5fc7b0..160dc3d755 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -602,6 +602,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) int nregs = a->n + 1; int vd = a->vd; TCGv_i32 addr, tmp; + MemOp mop; if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -651,25 +652,47 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) return true; } + mop = s->be_data | a->size; + if (a->align) { + static const MemOp mop_align[] = { + MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16 + }; + + switch (nregs) { + case 1: + mop |= MO_ALIGN; + break; + case 2: + mop |= mop_align[a->size]; + break; + case 3: + /* the align field is repurposed for VLD3 */ + break; + case 4: + mop |= mop_align[a->size + a->align]; + break; + default: + g_assert_not_reached(); + } + } + tmp = tcg_temp_new_i32(); addr = tcg_temp_new_i32(); load_reg_var(s, addr, a->rn); - /* - * TODO: if we implemented alignment exceptions, we should check - * addr against the alignment encoded in a->align here. - */ + for (reg = 0; reg < nregs; reg++) { if (a->l) { - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop); neon_store_element(vd, a->reg_idx, a->size, tmp); } else { /* Store */ neon_load_element(tmp, vd, a->reg_idx, a->size); - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), - s->be_data | a->size); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop); } vd += a->stride; tcg_gen_addi_i32(addr, addr, 1 << a->size); + + /* Subsequent memory operations inherit alignment */ + mop &= ~MO_AMASK; } tcg_temp_free_i32(addr); tcg_temp_free_i32(tmp);