From patchwork Fri Jan 19 13:40:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125412 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1133496ljf; Mon, 22 Jan 2018 04:39:42 -0800 (PST) X-Google-Smtp-Source: AH8x225nnv23YGMEvq4Bc56+hh3JPtkZnd8VjmtQ6DDnle/cazhyKUjJNi/6azlhhvOU6RF98SMU X-Received: by 10.36.25.196 with SMTP id b187mr8050462itb.18.1516624782362; Mon, 22 Jan 2018 04:39:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516624782; cv=none; d=google.com; s=arc-20160816; b=R8GzkRymsrwWAifwrxoo3DoeWpWEoNm1oc6tbAv8FMKWt8UFqWvAPAqtwZcuX9YvU1 YI48gpMM25fcTnlmR5niEjhXCdqm/69tydI07mxOur+F2HgaLeU/5BkN3lBnEKzdusdA 3QuAqS44JaPqd3zglkoBWm5+N7puuIO4mkRfu1lCm4bfwDvIE1WgTnOIWc2gosCP0dPq i035wfCHec0eDSoefKkMzvn8eHZ/zceL4Y9LlwT8npCFjWz5p22a/kScPuM/5mXi7uB9 JYsIhBpxyyaShBm16mb+TBZDGZVoBv6NIaNp2K3PUnpzZHQHWln/pCyaA5mN2IYVlKEA 1gBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=VZUtIxZZZzSZ3Dre7PKo7dj94C4i5Rm4y8PVMcRoAXY=; b=ISAK9xVqqJ+2ECYvcL6OwJsHBEV+sTERfy8Xe2Piq57fw00LKzHpkxn4Kmo4cjpMju obiZ51RlzOU+R8Ab9kNegen5PrilrkyjjcB/z2AzGlgBRKsEyDlA5vDa4z2Yf2Y8Fggt rW2EvvkOVnQaWwsWG5mP8iTwlZM5kbi8GArZRim5wHRhUy2Prsu7uT3QoZF5gpRKgxr3 7fvkdaI+VW78PuSCVAJ003Z/NxD+R3g7WzFzh/VY9mvIe8YbC3bn2+sfoveNPtGw+d4I wtjWjjfqVpz8u6lEMbYrNs1a4dLnaudivaSoIJsjqDbCvmHOy+eVYJHJLQa08miXBqvq GTUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=grCvKbIN; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id f2si11136674iob.94.2018.01.22.04.39.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jan 2018 04:39:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=grCvKbIN; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edbKf-0001HE-Sn; Mon, 22 Jan 2018 12:36:13 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edbKf-0001Gy-48 for xen-devel@lists.xen.org; Mon, 22 Jan 2018 12:36:13 +0000 X-Inumbo-ID: d342659c-ff70-11e7-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id d342659c-ff70-11e7-ba59-bc764e045a96; Mon, 22 Jan 2018 13:36:11 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id t74so16112197wme.3 for ; Mon, 22 Jan 2018 04:36:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AKESHymqzBZWBb53EH1NdvAguZN0V5+i3qROjUDk2so=; b=grCvKbINI4Dd/Dc0DTaygX7Xm13BbPCqLSuMFLvV7EnbU717bfnnoT5T+oq5NSSTQ+ mLfUDVSyspszU1Ah0xCa3XTP0l53kl4oTShwXzI69gVY5G7kq4BEMcX8iQCrcXiNkuaU +QG+ZUZ0dy01kMKbilp+ZNKmCObQuMhI6BpbU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AKESHymqzBZWBb53EH1NdvAguZN0V5+i3qROjUDk2so=; b=OkA5AZ0k2p7G9Mc7QszQiPG+/cfu8BHOktS2nZViGb7xqX43I0LstFWvzqypwdQ0YQ Lj34wuz3p6iScNczZS31+GEL8ueWYUXpv1MwG5r8DkjCjZbtvMvrX5WjYgL9xO/F/Uyd Zv0QtIIS7X2JAfnpfXgIravy2mAtQE986YyfGBkRWS7KuZ77V+414D7Hi1/mQBJhe33g 7PXNleOWfx0G4ftvVLQ3r9BQ+6dx2big0gdMBXaBSvaw+bIqT/WlI70b+lE3v5SlCEWp WLe2m/jSjLifbuWKDzyO7PXHKkYNpAPwVt158XJI60LGMWvIZyxbZ4mka1UBVpC+Z+G9 y91w== X-Gm-Message-State: AKwxytdQjn4iz164KNVwDxgWGTVZAPo78YSASVaWUmMP6HqvaDa3AiGn mZyOwyAOEVERJAOOwAlIAPSG04hPYQI= X-Received: by 10.28.51.12 with SMTP id z12mr7501441wmz.16.1516369266502; Fri, 19 Jan 2018 05:41:06 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:06 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:40:57 +0000 Message-Id: <20180119134103.3390-2-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 1/7] xen/arm32: entry: Consolidate DEFINE_TRAP_ENTRY_* macros X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The only difference between all the DEFINE_TRAP_ENTRY_* macros are the interrupts (Asynchronous Abort, IRQ, FIQ) unmasked. Rather than duplicating the code, introduce __DEFINE_TRAP_ENTRY macro that will take the list of interrupts to unmask. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm32/entry.S | 36 +++++++++++++----------------------- 1 file changed, 13 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index 120922e64e..c6490d2847 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -111,39 +111,29 @@ abort_guest_exit_end: skip_check: mov pc, lr -#define DEFINE_TRAP_ENTRY(trap) \ +/* + * Macro to define trap entry. The iflags corresponds to the list of + * interrupts (Asynchronous Abort, IRQ, FIQ) to unmask. + */ +#define __DEFINE_TRAP_ENTRY(trap, iflags) \ ALIGN; \ trap_##trap: \ SAVE_ALL; \ - cpsie i; /* local_irq_enable */ \ - cpsie a; /* asynchronous abort enable */ \ + cpsie iflags; \ adr lr, return_from_trap; \ mov r0, sp; \ mov r11, sp; \ bic sp, #7; /* Align the stack pointer (noop on guest trap) */ \ b do_trap_##trap -#define DEFINE_TRAP_ENTRY_NOIRQ(trap) \ - ALIGN; \ -trap_##trap: \ - SAVE_ALL; \ - cpsie a; /* asynchronous abort enable */ \ - adr lr, return_from_trap; \ - mov r0, sp; \ - mov r11, sp; \ - bic sp, #7; /* Align the stack pointer (noop on guest trap) */ \ - b do_trap_##trap +/* Trap handler which unmask IRQ/Abort, keep FIQ masked */ +#define DEFINE_TRAP_ENTRY(trap) __DEFINE_TRAP_ENTRY(trap, ai) -#define DEFINE_TRAP_ENTRY_NOABORT(trap) \ - ALIGN; \ -trap_##trap: \ - SAVE_ALL; \ - cpsie i; /* local_irq_enable */ \ - adr lr, return_from_trap; \ - mov r0, sp; \ - mov r11, sp; \ - bic sp, #7; /* Align the stack pointer (noop on guest trap) */ \ - b do_trap_##trap +/* Trap handler which unmask Abort, keep IRQ/FIQ masked */ +#define DEFINE_TRAP_ENTRY_NOIRQ(trap) __DEFINE_TRAP_ENTRY(trap, a) + +/* Trap handler which unmask IRQ, keep Abort/FIQ masked */ +#define DEFINE_TRAP_ENTRY_NOABORT(trap) __DEFINE_TRAP_ENTRY(trap, i) .align 5 GLOBAL(hyp_traps_vector) From patchwork Fri Jan 19 13:40:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125236 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp172068ljf; Fri, 19 Jan 2018 23:14:03 -0800 (PST) X-Google-Smtp-Source: AH8x227YiHtWDXuKMBAEoqicdJctRrA+PHdButEqDMYeK+WJW4MyKqeFEWpPAbdiTLSXWzGeAOZA X-Received: by 10.36.254.4 with SMTP id w4mr798725ith.65.1516432443483; Fri, 19 Jan 2018 23:14:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516432443; cv=none; d=google.com; s=arc-20160816; b=gH51daXad0mkIeqY0IE55cuZ4nVBuAIQiMnzHxU5OMAFA5nWnkfP6DZqumlsCtEXwJ v12C+jQlSvz+5ifgoiRpQZivhYPLfVuXu9OZecnh8CvZqjOwJSLhD8hR1lhaq3M+PoNF SCyfPd3Hzc5MD79D5dpVNRaXkxcJ1p5ndK/TGfn9qf2BONLKcPifBA6EFhnqKB0A3vTq Lb6qZg5LHtzfDbf/ekI7+lUvstZ4cFuBn49BKgXLLlCt2qBRQ0oPeLco9U+7CH09NtIG r32+Eu/OeuMm3JNDyQ6Ee8N6+b2wuzydmTpI3y4P5tJuEtJK7DVVNNkYjxNJiVBSLVwA KEZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=2GvU2qGJLuHZlK8YooDHDwPbZGFQyGuBLUIS1C4t3Ss=; b=Q6ZdnTYqg6CI5+LxK4Xz3NuFkkPG5kwVApxZ23+i5zBc13kIVo20N87rNRf8T0QusU xXUIayGYxcptiLyMkbm4l7FfJLSKxzP4UazxRq+wZSZxTC8Bf/OO77Hzf39/6s6WuiD6 ENMpw2dqaSSMP8zod0NrtBjr8oFkH7gtZldxcSA7dnMxEwhqoCzgAPfD/605n4jt3dGK tCmPJk9Y8Miub+7MvLLjelfO/5pVwWpG0CNG1L4tKTFDQEPw7L/M0QziVKkzDlvRtM9T U09CEbe5aRlXUr/CDBEYzwi0ALUSch9c+mYRWtprlierx7ggd7b8nFXuY42rTzOjEVS0 08lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fmmBs+tJ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z143si10798498ioe.237.2018.01.19.23.14.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 23:14:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fmmBs+tJ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ecnJH-0001qv-Bm; Sat, 20 Jan 2018 07:11:27 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ecnJG-0001qp-IQ for xen-devel@lists.xen.org; Sat, 20 Jan 2018 07:11:26 +0000 X-Inumbo-ID: 7c5ddd44-fdb1-11e7-b0d7-9f685aff125f Received: from mail-wm0-f65.google.com (unknown [74.125.82.65]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTPS id 7c5ddd44-fdb1-11e7-b0d7-9f685aff125f; Sat, 20 Jan 2018 07:14:00 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id g1so7191311wmg.2 for ; Fri, 19 Jan 2018 23:11:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rilL2LWe0XKMLAgMTUHZJpReCQZ4Bbq240zzTDisO6M=; b=fmmBs+tJD282EH6LNr0XUk2snPhcL/R27yiGuEaNFsRhFc/yMh7RGL+BL9lj0QW9oO a08IskNIXWIUTPh5X69FGtYS5HGDqewD+uS/HerJR761zdmGduY4+YumDC8jHIg7ansr 9BI/1gXo3Rr6NyCzPgTCiJgODP6RTycWB9D8c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rilL2LWe0XKMLAgMTUHZJpReCQZ4Bbq240zzTDisO6M=; b=liiOcEeonsa7E/XIDrdNoudsOXhLHzGitKky4uSjCDZKs01oHmkwoAmp92hpevZReX JMM6lXU4nfd3BBsjTWnjCIB+D3RP7iNmDWUynQAEo16nwfJ+y8+pquGydOmdKhDxylAr mA6HfIgBT7+uQZvyEnXquzZyt/Cdubw8y0cZGk8SrXNWLCgxnMeC5TeeL2zAckXZSLLy ujuTPqXJ84x+PEnyzsmq4AIGRQ1lp3ddOoTCwuYP3B3YABjBf+HQ3Z1UewhI9k0j+tVN OiljZq6B9UPD4DF7k2dsu9mRpWtoT5uKSGIhoosM8HlrRyjme5M7EfP4LnTkEWK0jZKI ToNQ== X-Gm-Message-State: AKwxyte1M1H/o+XRx6ohShUsMCZp/RZilawMJfsAFB7J6a5XI+Oo/7+M ttD5kXA+R3v0QRITTbwRViwIlS94Uuk= X-Received: by 10.28.108.4 with SMTP id h4mr7394296wmc.161.1516369267266; Fri, 19 Jan 2018 05:41:07 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:06 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:40:58 +0000 Message-Id: <20180119134103.3390-3-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 2/7] xen/arm32: Add missing MIDR values for Cortex-A17 and A12 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Cortex-A17 and A12 MIDR will be used in a follow-up patch for hardening the branch predictor. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/include/asm-arm/processor.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 466da5da86..c0f79d0093 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -44,6 +44,8 @@ #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_PART_CORTEX_A12 0xC0D +#define ARM_CPU_PART_CORTEX_A17 0xC0E #define ARM_CPU_PART_CORTEX_A15 0xC0F #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A57 0xD07 @@ -51,6 +53,8 @@ #define ARM_CPU_PART_CORTEX_A73 0xD09 #define ARM_CPU_PART_CORTEX_A75 0xD0A +#define MIDR_CORTEX_A12 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A12) +#define MIDR_CORTEX_A17 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A17) #define MIDR_CORTEX_A15 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A15) #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) From patchwork Fri Jan 19 13:40:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125399 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1098931ljf; Mon, 22 Jan 2018 03:20:00 -0800 (PST) X-Google-Smtp-Source: AH8x224lDxje05fatYkz+qbcnO2VcEQTFRMvbbIeiOkqVbilk6AF1k1KASRktPzbwUJSsGD+5WA8 X-Received: by 10.107.35.84 with SMTP id j81mr459242ioj.226.1516620000477; Mon, 22 Jan 2018 03:20:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516620000; cv=none; d=google.com; s=arc-20160816; b=cvnRGkaL+VIVId/fhFl6vaQVjgzzyTf1AKNd/YseukXmClGMTvlI318qzfB0RMxV1t hC0u2Q5CgIBP4cKmeq1heS5ihDhl2vkAIcBmBFXZoXAGSEu0tBk0+phnuiKeAwwbBOgW 7IQEVQFERlxAZSZd2419XtWjI2BKZ/eHrPSWmhRbyzve41e6PKiUjviJgyfEAzFnnfWd Iv2a/RM0XjDKTGAgGZ1rP7x8rGZJ/tvC4xsbD4XAWRV/S3d1vavPfVBkCGf2I8qKE0TO i1u/dLrdjKRfW2Q0wjIZyZamIl92GdrcoYc3uGsX+A9BWPTIPwW7TtKFQXxAXadQBv0s 14BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=4MfQhhnzk08RdQQvjlXdrA22hqK2LxvLIPmfT2u0J+s=; b=Qcsgy++c33vEATB/R2Vhy+vFJupiHbaWoP8I3KYGLmKW5zt/PDp5kWvPlK1QlyXDgX D1cOh6LdMP5AanUonpDNXYBty46KfFtsl3x8jKPlU7f/yroVZmHfBma0XSQ+LSu7cyoF E1O2YGqKj06ssWj8rdAvUQPv7zofd1tl0KpvmBXiD9d6tqepzM6StRS9KTsAWcLYk5fD D1FRa+2wuhYSSoqbq1HlchbpoupU0wCxKz7+lYizaURpFi7Rz4CKEgPiBSttLr8oFSXO RxpdIeYefbQxlSAy0a1f5logM1XdOXYpIIyOKPXQgKrKK7aqxg1c4Q6L8Hfu2b+N0L5B UXgw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hhu3m6lW; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b2si12458593iog.275.2018.01.22.03.20.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jan 2018 03:20:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hhu3m6lW; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eda5q-0002Vf-Vz; Mon, 22 Jan 2018 11:16:50 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eda5p-0002VZ-HA for xen-devel@lists.xen.org; Mon, 22 Jan 2018 11:16:49 +0000 X-Inumbo-ID: bb51af38-ff65-11e7-ba59-bc764e045a96 Received: from mail-wm0-x242.google.com (unknown [2a00:1450:400c:c09::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id bb51af38-ff65-11e7-ba59-bc764e045a96; Mon, 22 Jan 2018 12:16:46 +0100 (CET) Received: by mail-wm0-x242.google.com with SMTP id b21so16048186wme.4 for ; Mon, 22 Jan 2018 03:16:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V8wYS3VQq+eHn1NICfBSQ7OtxcmmRfydgdVHXdYrqOA=; b=Hhu3m6lWSF8UTwDXQloHz9GX6CifzR2uI31T47s8+mF4djgOQrwhqtnw5Or3S7HK2D ohjM9MLXUSNEdlRvlT4tOJVU/qcQLRrufhxees8nkLwb1y06LtAFXX4Majkt8mC3reEp xsPETcsO5M3cJ67aDOjY8KBn1/6kopKFB0IHE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V8wYS3VQq+eHn1NICfBSQ7OtxcmmRfydgdVHXdYrqOA=; b=WlR2oQ5JZXIB05l0ZxMbIluYXtysXBffALI2uV7RKiuylnvKHZu0ArisL/2MVlyLMM I0IAVtOvuOCjuq27hste9VBiK8b/vNmwgmqiFvLlqwxRHb/NtGFrcAXds1wqrnTJupoD al1EpdVogH10wARNKS/OM2/VnxipGDdOptF8R5/Kve49czF0pWPhnsXkuNmBzp0ehOcV war3n3RjND5Klneq7jssuqO9uft6vQw9U63EmLxmCtopjXolwRyoTEFFoewmXMVhD4EJ WJZ5utVA1TWf3kaG79VmscPl5mecXggE4xGsPcQxZO6MwoFoSIlRpJHsk94VNYkOC5SC P1ew== X-Gm-Message-State: AKwxyteKQ//xHytQUf/4Bm9bCFdIS85/9TOd+NabXo7/btWQTb1/OFbs wlJ7deAT/Ml/ozWn+KY6OvMxkKM/DXI= X-Received: by 10.28.105.193 with SMTP id z62mr7407729wmh.77.1516369267987; Fri, 19 Jan 2018 05:41:07 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:07 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:40:59 +0000 Message-Id: <20180119134103.3390-4-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 3/7] xen/arm32: entry: Add missing trap_reset entry X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment, the reset vector is defined as .word 0 (e.g andeq r0, r0, r0). This is rather unintuitive and will result to execute the trap undefined. Instead introduce trap helpers for reset and will generate an error message in the unlikely case that reset will be called. This is part of XSA-254. Signed-off-by: Julien Grall --- xen/arch/arm/arm32/entry.S | 1 + xen/arch/arm/arm32/traps.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c6490d2847..c2fad5fe9b 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -146,6 +146,7 @@ GLOBAL(hyp_traps_vector) b trap_irq /* 0x18 - IRQ */ b trap_fiq /* 0x1c - FIQ */ +DEFINE_TRAP_ENTRY(reset) DEFINE_TRAP_ENTRY(undefined_instruction) DEFINE_TRAP_ENTRY(hypervisor_call) DEFINE_TRAP_ENTRY(prefetch_abort) diff --git a/xen/arch/arm/arm32/traps.c b/xen/arch/arm/arm32/traps.c index 705255883e..4f27543dec 100644 --- a/xen/arch/arm/arm32/traps.c +++ b/xen/arch/arm/arm32/traps.c @@ -23,6 +23,11 @@ #include +void do_trap_reset(struct cpu_user_regs *regs) +{ + do_unexpected_trap("Reset", regs); +} + void do_trap_undefined_instruction(struct cpu_user_regs *regs) { uint32_t pc = regs->pc; From patchwork Fri Jan 19 13:41:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125371 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1055753ljf; Mon, 22 Jan 2018 01:31:09 -0800 (PST) X-Google-Smtp-Source: AH8x2251fG/4NMicbe+AlW2f7FFT+85oxza97ep5RPHKVznV8SzvhPVQBvdyP6BLvpNICklmcOTy X-Received: by 10.107.59.87 with SMTP id i84mr6632005ioa.99.1516613469802; Mon, 22 Jan 2018 01:31:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516613469; cv=none; d=google.com; s=arc-20160816; b=KcPJ2xUmrMFBKlIqPeG0wD2vYOko+KvGCF0TlszdjK5KVC0ObvUG54FHgQg+vSZsat JCdH+dOYlD+BtEAtiofm5wdXwUM2/aR5eIjy9EMaTPKCHtU+YU2OoDuqvKv8KIsmi2BW lmnH61BlPIXL7HoMLC48ZG9j2pXWLOhhbI6ttbeWPZYw975wkSPuIFrxrFTrpV0NYfMI bmbMYY+eSgZr0ZhdMjtXLBAtCSQZp1QLid/seEDmHahtcWoEWZK6VIv/2nrZvO0wLTWy wIbD0GG6rU5aGaJXdoqRVoTogpF+s/0alJAl9yc4XS12P74ue7IV0aQniPFSKEn0l/Bc bEqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=pUoQhZhyEa9ejzZ45eHS6/MTQPMJZC/o5MyoqhYS5Pg=; b=DEJTiS3YbJMdC8K0lpOEa1luhbGrLlEvW+ecJYDyT9VPUAteXmY3t/IO370A9qWZqL SPYjsNFs2Xooum+bkqe4jskB1cGhskZnQyjJTep5v/3OMtlaVU/eGwkO6iHCFwIZcPmi egOAAvdSvN9OfCHY3XLWsqjs2VEG8+jr/o2BHLfViwvbIXtXG54w09iL3KNLSGbHTnHR ohTdlZuXUwcSWWzOvSHQuq23/VnMe7iRDsPXIDCWWZ0gGPkmMnvuFLUqih6OmOxmnTeD VRy5gBtLubgMC7ZuR/MdmUTHqh3oqEZXzCu1LkM7STXSdGjnGWj/j/qg25/0W5iafxhk QYOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IuqWHEED; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id r62si5651857itg.35.2018.01.22.01.31.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 Jan 2018 01:31:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IuqWHEED; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edYOg-0001sn-Ss; Mon, 22 Jan 2018 09:28:10 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1edYOg-0001sh-0d for xen-devel@lists.xen.org; Mon, 22 Jan 2018 09:28:10 +0000 X-Inumbo-ID: 8cd2bcc0-ff56-11e7-ba59-bc764e045a96 Received: from mail-wr0-x242.google.com (unknown [2a00:1450:400c:c0c::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 8cd2bcc0-ff56-11e7-ba59-bc764e045a96; Mon, 22 Jan 2018 10:28:06 +0100 (CET) Received: by mail-wr0-x242.google.com with SMTP id g21so7807856wrb.13 for ; Mon, 22 Jan 2018 01:28:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gOdEzGyfOsrSClsrr0dvYywk8hzJrtFR4HQpiieVJSE=; b=IuqWHEED1bS8jwPfCRkNB/PQV9AccrvuQa90z5Se6wyO+G6m/DKMQWFb82L1WLV/Wn kOyuZnDf/iqEk4ABf4CCbXL7IDcvx7/0Y7E7u92P9UGrMRKmHxC4nUO92PtdsPmCXphM HJ6RQ3wxxH9Gj9ceKfGtveivb1psBH1ON8BvA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gOdEzGyfOsrSClsrr0dvYywk8hzJrtFR4HQpiieVJSE=; b=ir+rPn9W32ViwmeS/t3fIihrqJaZDnaOKWE+ExZSIzcBuSjffsnM0To02L7moobW5E S5gTZT5yo+qF4MfRibmT8ralTohE5it+TMl2L0YsQl+LZDgVN35ObS2/HYV+4zwrVdoA foWzxG/9XLXYgdxoxcKdxIrzP+lgoVbohP6Z8Awn+7qOdAtaBiVtUzXnGONV33vrF/u7 RfZBaINH72ClARF1RD8AAyXLexqjvevZZGHS1YEFpdPLydOKJHUw4P7PugVavnrUSk/m TVTIzJhzrBRo+Qf+VOvpmh1Qfcfmvn/avpqWTSuFiFJHP1C1HfOjV9l3XIfBNup+ZqN0 fMsg== X-Gm-Message-State: AKwxytefBdd9JeacqunBymFjVSRaooNpqKubS5tSfottRRLH8MaxeLHW BWZfMW0BjL6Z0KNXpPQp9H98vgtRgb4= X-Received: by 10.223.152.109 with SMTP id v100mr9026536wrb.222.1516369268740; Fri, 19 Jan 2018 05:41:08 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:08 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:41:00 +0000 Message-Id: <20180119134103.3390-5-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 4/7] xen/arm32: Add skeleton to harden branch predictor aliasing attacks X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Aliasing attacked against CPU branch predictors can allow an attacker to redirect speculative control flow on some CPUs and potentially divulge information from one context to another. This patch adds initiatial skeleton code behind a new Kconfig option to enable implementation-specific mitigations against these attacks for CPUs that are affected. Most of mitigations will have to be applied when entering to the hypervisor from the guest context. Because the attack is against branch predictor, it is not possible to safely use branch instruction before the mitigation is applied. Therefore this has to be done in the vector entry before jump to the helper handling a given exception. However, on arm32, each vector contain a single instruction. This means that the hardened vector tables may rely on the state of registers that does not hold when in the hypervisor (e.g SP is 8 bytes aligned). Therefore hypervisor code running with guest vectors table should be minimized and always have interrupts masked to reduce the risk to use them. This patch provides an infrastructure to switch vector tables before entering to the guest and when leaving it. Note that alternative could have been used, but older Xen (4.8 or earlier) doesn't have support. So avoid using alternative to ease backporting. This is part of XSA-254. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/Kconfig | 3 +++ xen/arch/arm/arm32/entry.S | 41 ++++++++++++++++++++++++++++++++++++++++- xen/arch/arm/cpuerrata.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 06fd85cc77..2782ee6589 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -191,6 +191,9 @@ config HARDEN_BRANCH_PREDICTOR config ARM64_HARDEN_BRANCH_PREDICTOR def_bool y if ARM_64 && HARDEN_BRANCH_PREDICTOR +config ARM32_HARDEN_BRANCH_PREDICTOR + def_bool y if ARM_32 && HARDEN_BRANCH_PREDICTOR + source "common/Kconfig" source "drivers/Kconfig" diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c2fad5fe9b..54a1733f87 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -34,6 +34,20 @@ blne save_guest_regs save_guest_regs: +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + /* + * Restore vectors table to the default as it may have been + * changed when returning to the guest (see + * return_to_hypervisor). We need to do that early (e.g before + * any interrupts are unmasked) because hardened vectors requires + * SP to be 8 bytes aligned. This does not hold when running in + * the hypervisor. + */ + ldr r1, =hyp_traps_vector + mcr p15, 4, r1, c12, c0, 0 + isb +#endif + ldr r11, =0xffffffff /* Clobber SP which is only valid for hypervisor frames. */ str r11, [sp, #UREGS_sp] SAVE_ONE_BANKED(SP_usr) @@ -179,12 +193,37 @@ return_to_guest: RESTORE_ONE_BANKED(R11_fiq); RESTORE_ONE_BANKED(R12_fiq); /* Fall thru */ return_to_hypervisor: - cpsid i + cpsid ai ldr lr, [sp, #UREGS_lr] ldr r11, [sp, #UREGS_pc] msr ELR_hyp, r11 ldr r11, [sp, #UREGS_cpsr] msr SPSR_hyp, r11 +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + /* + * Hardening branch predictor may require to setup a different + * vector tables before returning to the guests. Those vectors + * may rely on the state of registers that does not hold when + * running in the hypervisor (e.g SP is 8 bytes aligned). So setup + * HVBAR very late. + * + * Default vectors table will be restored on exit (see + * save_guest_regs). + */ + mov r9, #0 /* vector tables = NULL */ + /* + * Load vector tables pointer from the per-cpu bp_harden_vecs + * when returning to the guest only. + */ + and r11, #PSR_MODE_MASK + cmp r11, #PSR_MODE_HYP + ldrne r11, =per_cpu__bp_harden_vecs + mrcne p15, 4, r10, c13, c0, 2 /* r10 = per-cpu offset (HTPIDR) */ + addne r11, r11, r10 /* r11 = offset of the vector tables */ + ldrne r9, [r11] /* r9 = vector tables */ + cmp r9, #0 /* Only update HVBAR when the vector */ + mcrne p15, 4, r9, c12, c0, 0 /* tables is not NULL. */ +#endif pop {r0-r12} add sp, #(UREGS_SP_usr - UREGS_sp); /* SP, LR, SPSR, PC */ clrex diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index f1ea7f3c5b..0a138fa735 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -170,6 +170,36 @@ static int enable_psci_bp_hardening(void *data) #endif /* CONFIG_ARM64_HARDEN_BRANCH_PREDICTOR */ +/* Hardening Branch predictor code for Arm32 */ +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + +/* + * Per-CPU vector tables to use when returning to the guests. They will + * only be used on platform requiring to harden the branch predictor. + */ +DEFINE_PER_CPU_READ_MOSTLY(const char *, bp_harden_vecs); + +extern char hyp_traps_vector_bp_inv[]; + +static void __maybe_unused +install_bp_hardening_vecs(const struct arm_cpu_capabilities *entry, + const char *hyp_vecs, const char *desc) +{ + /* + * Enable callbacks are called on every CPU based on the + * capabilities. So double-check whether the CPU matches the + * entry. + */ + if ( !entry->matches(entry) ) + return; + + printk(XENLOG_INFO "CPU%u will %s on guest exit\n", + smp_processor_id(), desc); + this_cpu(bp_harden_vecs) = hyp_vecs; +} + +#endif + #define MIDR_RANGE(model, min, max) \ .matches = is_affected_midr_range, \ .midr_model = model, \ From patchwork Fri Jan 19 13:41:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125245 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp186970ljf; Sat, 20 Jan 2018 00:10:59 -0800 (PST) X-Google-Smtp-Source: AH8x224uF+A/9MBlBW7g7emEd6VsNrieaUSw3CJMhZ3YBYA73Dc3C8aMITWP+QzLIImrqxF1c48U X-Received: by 10.107.97.18 with SMTP id v18mr1095770iob.7.1516435859580; Sat, 20 Jan 2018 00:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516435859; cv=none; d=google.com; s=arc-20160816; b=OfLXdu2sy/avuS1l5ZpXfRyY3NBLkDwkhmvuSY2EDsEyhXCtPbLjREaqXg8ffHKTRg pI/3FdIfsuX+iuW8q+AFB+9Z34Qc/Oe1vus7s9ItaWS0xyLWx0zdP5nv8iic9+2hB8/w spanjQvWmHaqPyfJUrX/1JjpTghGvyWgDwHZtlTSfVXxnh3BCKwwbd0o/Fzcr8ECHuMr VOLZc38PsXYVmsjx73QaV13Px0AShWIv58lSkTc1TN3kEVZZDtdCHNZTS+cg65Njz9ko 71138Y/2FExZecaPyIzu53tJ0R+hHMxvL2guCW5qQYmwX+wnyHA8MX82HAhcO2MeOrr0 B/kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Lt9j+aAce6/Ow3uKx0t3fJoXUng1HPL4zXN1QmyO4tM=; b=b4HdxVVJYR54a5aemL/UyP5lb1FLmZxgqGZdlaiMsy6Q8VseMIxJzPuZ//VUEv/z+a sTBSytBEaONg8pBRngzc1tlXEJ/T7juevzKthkImaIRA/CuYgLCC/CnttZYMvZJZE4VB kxj4IlvlcVhVl0WSKYgbnvm//vb7zZtmyGUNcli93rkPgCjY31C3M/mS3sNQXIksVpf5 b3JWylmSsUS/fyNQp87M8+70H/jB5jR+f0t11FW6aumQOC+7R1fPskTtZ8NjUoMGEti+ 0a8TE5T2vuMltPvxN4dFe3RFf0mqU+209i56XIyYto4cvCbqyf+BbZXHIe2NaJXo/+yr narA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KOY3OpLh; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o17si2409993ita.69.2018.01.20.00.10.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Jan 2018 00:10:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KOY3OpLh; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ecoBn-0005fu-Lp; Sat, 20 Jan 2018 08:07:47 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ecoBm-0005fo-PM for xen-devel@lists.xen.org; Sat, 20 Jan 2018 08:07:46 +0000 X-Inumbo-ID: 5b2f5853-fdb9-11e7-b0d7-9f685aff125f Received: from mail-wm0-f66.google.com (unknown [74.125.82.66]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTPS id 5b2f5853-fdb9-11e7-b0d7-9f685aff125f; Sat, 20 Jan 2018 08:10:20 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id b21so7590814wme.4 for ; Sat, 20 Jan 2018 00:07:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yLnbnyBqEC0roE3wcJdZQ8BkXE/g3IL1ge4p4Mcf97o=; b=KOY3OpLhsmQI9sC14MbwNlOIzPqLDDBJU8l9ixzL4+yf1+gRxKF/R7QEC5cF0GQz/P nq8HwXWdfGIpWIA5ha/a0Xmw+/Ohx0PF250HAv8cjztuyGovZydzA+WuLXjQQ9mPRfTI FBJ+tH6ptJ/P1GdSdKr954El2tBvuV7jUrPyo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yLnbnyBqEC0roE3wcJdZQ8BkXE/g3IL1ge4p4Mcf97o=; b=eKhIpp+/zt79Fye4+zurw5yDxE787RvUwJojwvOVg9/kOSLPOC5+vkmL1lamyo2nBU MArF7s5eJPvsCkvf1rQReKXuLfQuyr3d9g1wPFtBlf0FqacULcmXl4zuyL8TqTk4Et+6 9S+QmDbAipB5Umvl88dZEtIhwlBuaFBq/RxIKEhCaW+d99pHxEiSMYd5T5ouV5n7LNJT w5OVjOKRQJu7Y6UJuVljrHxHnFTUNhyztf6Xo1K8Z/VNx6NxSITXYEQI4LNXl0WNh4nv HXavlBkPkpaZ7ECs0gNHTQs3cG1bpENlaJjrs1NnpPVwn0JuPjS4xUbO8buwg5cVkobf Y9oA== X-Gm-Message-State: AKwxytfJ+7DUzM2pWLvaDgLsAqZEFf1o88uqgQTbOBDJ7vhivLMVB8tO YosYoYCcvJiZ7GOfCfuD65SA+en2Sv0= X-Received: by 10.28.92.75 with SMTP id q72mr7351853wmb.21.1516369269544; Fri, 19 Jan 2018 05:41:09 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:09 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:41:01 +0000 Message-Id: <20180119134103.3390-6-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 5/7] xen/arm32: Invalidate BTB on guest exit for Cortex A17 and 12 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In order to avoid aliasing attackes agains the branch predictor, let's invalidate the BTB on guest exist. This is made complicated by the fact that we cannot take a branch invalidating the BTB. This is based on the first version posrted by Marc Zyngier on Linux-arm mailing list (see [1]). This is part of XSA-254. Signed-off-by: Marc Zyngier Signed-off-by: Julien Grall [1] https://www.spinics.net/lists/arm-kernel/msg627032.html Signed-off-by: Stefano Stabellini --- xen/arch/arm/arm32/entry.S | 55 ++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/cpuerrata.c | 19 ++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index 54a1733f87..c6ec0aa399 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -160,6 +160,61 @@ GLOBAL(hyp_traps_vector) b trap_irq /* 0x18 - IRQ */ b trap_fiq /* 0x1c - FIQ */ + .align 5 +GLOBAL(hyp_traps_vector_bp_inv) + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + add sp, sp, #1 /* Reset 7 */ + add sp, sp, #1 /* Undef 6 */ + add sp, sp, #1 /* Hypervisor Call 5 */ + add sp, sp, #1 /* Prefetch abort 4 */ + add sp, sp, #1 /* Data abort 3 */ + add sp, sp, #1 /* Hypervisor 2 */ + add sp, sp, #1 /* IRQ 1 */ + nop /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + + /* + * As we cannot use any temporary registers and cannot + * clobber SP, we can decode the exception entry using + * an unrolled binary search. + */ + tst sp, #4 + bne 1f + + tst sp, #2 + bne 3f + + tst sp, #1 + bic sp, sp, #0x7 + bne trap_irq + b trap_fiq + +1: + tst sp, #2 + bne 2f + + tst sp, #1 + bic sp, sp, #0x7 + bne trap_hypervisor_call + b trap_prefetch_abort + +2: + tst sp, #1 + bic sp, sp, #0x7 + bne trap_reset + b trap_undefined_instruction + +3: + tst sp, #1 + bic sp, sp, #0x7 + bne trap_data_abort + b trap_guest_sync + DEFINE_TRAP_ENTRY(reset) DEFINE_TRAP_ENTRY(undefined_instruction) DEFINE_TRAP_ENTRY(hypervisor_call) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 0a138fa735..c79e6d65d3 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -198,6 +198,13 @@ install_bp_hardening_vecs(const struct arm_cpu_capabilities *entry, this_cpu(bp_harden_vecs) = hyp_vecs; } +static int enable_bp_inv_hardening(void *data) +{ + install_bp_hardening_vecs(data, hyp_traps_vector_bp_inv, + "execute BPIALL"); + return 0; +} + #endif #define MIDR_RANGE(model, min, max) \ @@ -284,6 +291,18 @@ static const struct arm_cpu_capabilities arm_errata[] = { .enable = enable_psci_bp_hardening, }, #endif +#ifdef CONFIG_ARM32_HARDEN_BRANCH_PREDICTOR + { + .capability = ARM_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A12), + .enable = enable_bp_inv_hardening, + }, + { + .capability = ARM_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A17), + .enable = enable_bp_inv_hardening, + }, +#endif {}, }; From patchwork Fri Jan 19 13:41:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125252 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp425937ljf; Sat, 20 Jan 2018 12:48:46 -0800 (PST) X-Google-Smtp-Source: AH8x225C+1x2M28jw+PafuFS9m5xpNRpcwWQVe9iD/aimY2M2OJK1qh2d8ccFL3TI0ieohp4OSa4 X-Received: by 10.36.210.133 with SMTP id z127mr2920815itf.116.1516481326018; Sat, 20 Jan 2018 12:48:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516481326; cv=none; d=google.com; s=arc-20160816; b=DX0MVmaET+T+Y15LJRcL0hR2AL46+bvi2Fwh8V/gFHbC4K5j21Tpbau0RPWrntEV4z Zhm+x9U9nOAc+aeDpdIDsLmgIRKdGyD980gsl0STtYV/PPHbgFSCIkeWR4zYiqhSS0LF 69kNaxmtLi7eFHyLvN/vB4MejhS+y0f/6a3ZahJr+Rtd09CE6ix5YEE7NfZX1ecTcI34 YXuU6amz18aYRcOnUiMTf4h4asm33SBrPsvW9pbAk9WvH+qsJmXpWb+e4Oip55cVPjML 278fVBlXXl40GXOZ/nj5hIk0VRpMxMmm4bAY9IWXN4L9vZnJFSGirLo65wVcJp0gTdul yluQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=sS8V1a+T3XQeQXdEKXe1QXa5/bg6RXQj+GmhpMeu68E=; b=XBH0YrpJcN0djSiGOiuPpfD4EgUj3c3lxsQltPoANpSJV+y3X3tET6Nqhp2jTX+xpF uIQQWRZQXoSSZyvI0te46Bhgc7lCJhg/BV53fQxvwdVaQykGVwX+bDQOPHxnFHRFjD8r Qm9eTK+CNJ03g7F+vApKLvDmC4ENgwQ0HgP4fInPpGavW4+mYVYT0xLvUiyhp+0WRl7r /P/Q+G2uL+eeWfs88+sHiE7idvADqQ72cQCJKJTVipDaj2kixY774e6vro4onIxr6JYZ 3RwClvlFfLGtBGRQ97NhXLwtpFd6fHRkcJe9zFx6eb9NwZ+EActwfWoGbRej0EvvLnlx UJBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JICkUcsY; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 21si3481515itu.74.2018.01.20.12.48.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Jan 2018 12:48:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JICkUcsY; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ed01A-0004i3-0n; Sat, 20 Jan 2018 20:45:36 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ed018-0004hR-Bd for xen-devel@lists.xen.org; Sat, 20 Jan 2018 20:45:34 +0000 X-Inumbo-ID: 388f0cb5-fe23-11e7-b0d7-9f685aff125f Received: from mail-wm0-f67.google.com (unknown [74.125.82.67]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTPS id 388f0cb5-fe23-11e7-b0d7-9f685aff125f; Sat, 20 Jan 2018 20:48:09 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id i186so9472849wmi.4 for ; Sat, 20 Jan 2018 12:45:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gGF4fA9+h7PrU1mFoShz0EdWaJ/sLBHBmL17tQPzzks=; b=JICkUcsYVF9udvPB6OU8JIgTryohkspEaZdEhZCQDYe3KcW8pG/F5Fm3RSPkOMYe9w 52sHmsIPm4Uial4foC+7sCgwhEoghuCYz3MbbQtg+uZPnzDz1xR5OL0TUhgw6tg0YP2p jnriT7cjrkNmivysZ8HEI3Jlfj5rfv62aMSPs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gGF4fA9+h7PrU1mFoShz0EdWaJ/sLBHBmL17tQPzzks=; b=c5n5mtUSN8ikgw3p+wSiQ1R/njFOAcWoZToP5GP2b/PDnE1rqH/ncFVPGQWD53N/E/ n1/+Rj+txVbfg7hEmODxubm7J1/9Tk7wIgB0XlFckcyI2PVNaTG237xz9mOdXHbfqWB7 aPgrjS+BNx+r0Ww0fRfPQSLiYt7AwgrM9Bwm11ywtU/civWucdAMWv3c5ulBAG0oDGR4 pxsVmj6XgSLSNzICM3JUI70gGsEYOhfjKhEWkPU5M1xAsVKh0lHiXBf8gudfihbXCm5/ /+6Rp3ycJOFUjpDOfWigkAqds8NL1BMoOW1Qw8RXDWWFUinJuMJj3etNrGvB1coHaRhw EQbA== X-Gm-Message-State: AKwxytfkLtx7NT65mrKyCUexSf27k2QLB1BVSFOEfb71mjvlVFkt1ahL oXOEaKZ+g91GDHE9JjzWG90EvVPyLTw= X-Received: by 10.28.211.67 with SMTP id k64mr7691986wmg.95.1516369270404; Fri, 19 Jan 2018 05:41:10 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:09 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:41:02 +0000 Message-Id: <20180119134103.3390-7-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 6/7] xen/arm32: Invalidate icache on guest exist for Cortex-A15 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In order to avoid aliasing attacks against the branch predictor on Cortex A-15, let's invalidate the BTB on guest exit, which can only be done by invalidating the icache (with ACTLR[0] being set). We use the same hack as for A12/A17 to perform the vector decoding. This is based on Linux patch from the kpti branch in [1]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git Signed-off-by: Marc Zyngier Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm32/entry.S | 21 +++++++++++++++++++++ xen/arch/arm/cpuerrata.c | 13 +++++++++++++ 2 files changed, 34 insertions(+) diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c6ec0aa399..c529592d20 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -161,6 +161,26 @@ GLOBAL(hyp_traps_vector) b trap_fiq /* 0x1c - FIQ */ .align 5 +GLOBAL(hyp_traps_vector_ic_inv) + /* + * We encode the exception entry in the bottom 3 bits of + * SP, and we have to guarantee to be 8 bytes aligned. + */ + add sp, sp, #1 /* Reset 7 */ + add sp, sp, #1 /* Undef 6 */ + add sp, sp, #1 /* Hypervisor call 5 */ + add sp, sp, #1 /* Prefetch abort 4 */ + add sp, sp, #1 /* Data abort 3 */ + add sp, sp, #1 /* Hypervisor 2 */ + add sp, sp, #1 /* IRQ 1 */ + nop /* FIQ 0 */ + + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + + b decode_vectors + + .align 5 GLOBAL(hyp_traps_vector_bp_inv) /* * We encode the exception entry in the bottom 3 bits of @@ -178,6 +198,7 @@ GLOBAL(hyp_traps_vector_bp_inv) mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ isb +decode_vectors: /* * As we cannot use any temporary registers and cannot * clobber SP, we can decode the exception entry using diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index c79e6d65d3..9c7458ef06 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -180,6 +180,7 @@ static int enable_psci_bp_hardening(void *data) DEFINE_PER_CPU_READ_MOSTLY(const char *, bp_harden_vecs); extern char hyp_traps_vector_bp_inv[]; +extern char hyp_traps_vector_ic_inv[]; static void __maybe_unused install_bp_hardening_vecs(const struct arm_cpu_capabilities *entry, @@ -205,6 +206,13 @@ static int enable_bp_inv_hardening(void *data) return 0; } +static int enable_ic_inv_hardening(void *data) +{ + install_bp_hardening_vecs(data, hyp_traps_vector_ic_inv, + "execute ICIALLU"); + return 0; +} + #endif #define MIDR_RANGE(model, min, max) \ @@ -302,6 +310,11 @@ static const struct arm_cpu_capabilities arm_errata[] = { MIDR_ALL_VERSIONS(MIDR_CORTEX_A17), .enable = enable_bp_inv_hardening, }, + { + .capability = ARM_HARDEN_BRANCH_PREDICTOR, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A15), + .enable = enable_ic_inv_hardening, + }, #endif {}, }; From patchwork Fri Jan 19 13:41:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 125255 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp436621ljf; Sat, 20 Jan 2018 13:28:32 -0800 (PST) X-Google-Smtp-Source: AH8x22743wgBgHmG68Tlr83h/qqYzd5ZA1xgY3+XL5sIDqss4tFr+BCzJuhBgRHkkBxNM/Ji9PXl X-Received: by 10.107.133.163 with SMTP id p35mr3037750ioi.44.1516483712726; Sat, 20 Jan 2018 13:28:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516483712; cv=none; d=google.com; s=arc-20160816; b=s2dOMwpuf8SZ2/zVP6ZtX87lOFyAtFYU66W9qD24nmr1Cu3UczC1c+uu2p7wm/l517 7QBYEowgHq8P1AkKeixkGioBlDwbpiKlqjO83TGbHYMyilhQLBOGUznaz5600ZdFdLjz p/sOmJulYuMVUwsarY6m0saRr8OIoh2uRL1Th0eLYwudEKH8K3l5WCEOwakvIxhUd7oW EAEHsy+pjQSCRSpyYw4l4pqiY/BlJ/TPHuU4ObsUGFkkQRAwnZrk/i05cG36K/60x1wq SwsQS4ximcmNwdHrzgb0W4FZu1d5R3Qqv89e+B3SsyEdnfA+6xE+DNzIgnUt2Rs9rzpC MsjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=DwPcjAn0da1qt+jUEicZizmhuY0n85tV/u0gXZFIQ34=; b=wWg8t8Py/eEuZDu8faKoItIGtQUjb0TLA62FfkIRTo6FqH3jpMbZwxNkWMgOtyjF00 A0pGCTznAxK3dtPrQmJBNnan+ulPjjsG0Ne9plkJcNRmgmdCOiFioVfwEk29rbj6CbKL jBalSk0NZLAMQKaWJtwSRk0py/S1duVWvBYuFbhoR1Cw9G4owj/rAYkNG2nnJ99hu8VX wtbLMarRXtKMviKzcdrYAjKMpo2aUuetWj713+bRdFXnIQmbDAQY5TIShR4FiS1/B1sL SILRgHzm0/GhFWJkkLiSLDhOe4hp+1SZ1VqYKgwlw/N8nlFcKMNoVCypiCvitpSHsesL HDfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QEGlffBp; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id i190si3391319itg.13.2018.01.20.13.28.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Jan 2018 13:28:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QEGlffBp; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ed0dz-0007KJ-0Z; Sat, 20 Jan 2018 21:25:43 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ed0dy-0007KD-Bj for xen-devel@lists.xen.org; Sat, 20 Jan 2018 21:25:42 +0000 X-Inumbo-ID: d46ced41-fe28-11e7-b0d7-9f685aff125f Received: from mail-wm0-f67.google.com (unknown [74.125.82.67]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTPS id d46ced41-fe28-11e7-b0d7-9f685aff125f; Sat, 20 Jan 2018 21:28:17 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id b141so9638787wme.1 for ; Sat, 20 Jan 2018 13:25:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ndD4Cyhh+hJQe/eNI/MygqK4VBjp1r9v0wZNTSBrBKc=; b=QEGlffBpB3o4mJ4afQCR4rcpaga00KuDN/oXe4Hsb7Ya6vwUo1/fJ9kwdOxy/OHmnd ghFL80GRfB8pqdHIjqcLa8BtDXmnulUZPftzpgLFlAurdU7uX3QO8FDzdEHieFHxsSHw /mDb7drqKgGWfrQbRyQoZ1Pr7SsqR086xtnhk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ndD4Cyhh+hJQe/eNI/MygqK4VBjp1r9v0wZNTSBrBKc=; b=Qnb8A1iLaVXBxAilpfuDjROx0q1gS3RgxV7V+8qo77K8crSsAGEr4wmRKXr4qRq12F Qfnm3srUTfM2apbg21XdvsN/xsEKRg4R6kuX88DJp1P7knky3Wy/Ss2xem7uCywjSlUe 2VM92ATl3C/ZySLKSUhShPs4Eq6JmIXXlK/AeRomhnrlcnShL9Vzj1jIOCnxqurBDFLo N3BwAhtCyzqEVL4vuJS2Pp1axaNZcJ81/6oCbLc/s0uV3QAViDR7du8C3XOT4ad4FDne 9OqEnG83sy8vcxOe6CmTSws9+xN6Tz7Qdkwn86Tn2nzp8/jHJGVmEqEsxu9yMCKL6RfG PwJw== X-Gm-Message-State: AKwxyte3jWRmot/KhWT2a8964idpeSxew0bLTbABtQojqjIbg+jHJXbv /BKiBs4KQYolkcp7YRmJn4Kb07KqgSY= X-Received: by 10.28.236.24 with SMTP id k24mr8411609wmh.8.1516369271464; Fri, 19 Jan 2018 05:41:11 -0800 (PST) Received: from e108454-lin.cambridge.arm.com ([2001:41d0:1:6c23::1]) by smtp.gmail.com with ESMTPSA id s44sm5113642wrc.64.2018.01.19.05.41.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Jan 2018 05:41:10 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 19 Jan 2018 13:41:03 +0000 Message-Id: <20180119134103.3390-8-julien.grall@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180119134103.3390-1-julien.grall@linaro.org> References: <20180119134103.3390-1-julien.grall@linaro.org> Cc: sstabellini@kernel.org, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH 7/7] xen/arm32: entry: Document the purpose of r11 in the traps handler X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" It took me a bit of time to understand why __DEFINE_TRAP_ENTRY is storing the original stack pointer in r11. It is working in pair with return_traps_entry where sp will be restored from r11. This is fine because per the AAPCS r11 must be preserved by the subroutine. So in return_from_trap, r11 will still contain the original stack pointer. Add some documentation in the code to point the 2 sides to each other. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm32/entry.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/arm/arm32/entry.S b/xen/arch/arm/arm32/entry.S index c529592d20..7f323de484 100644 --- a/xen/arch/arm/arm32/entry.S +++ b/xen/arch/arm/arm32/entry.S @@ -136,6 +136,10 @@ trap_##trap: \ cpsie iflags; \ adr lr, return_from_trap; \ mov r0, sp; \ + /* \ + * Save the stack pointer in r11. It will be restored after the \ + * trap has been handled (see return_from_trap). \ + */ \ mov r11, sp; \ bic sp, #7; /* Align the stack pointer (noop on guest trap) */ \ b do_trap_##trap @@ -246,6 +250,10 @@ DEFINE_TRAP_ENTRY_NOIRQ(fiq) DEFINE_TRAP_ENTRY_NOABORT(data_abort) return_from_trap: + /* + * Restore the stack pointer from r11. It was saved on exception + * entry (see __DEFINE_TRAP_ENTRY). + */ mov sp, r11 ENTRY(return_to_new_vcpu32) ldr r11, [sp, #UREGS_cpsr]