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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:13 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:11 +0000 Message-Id: <20180124143517.18469-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 1/7] tools: ARM: vGICv3: avoid inserting optional DT properties X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When creating a GICv3 devicetree node, we currently insert the redistributor-stride and #redistributor-regions properties, with fixed values which are actually the architected ones. But those properties are optional and only needed to cover for broken platforms, where the values differ from the architected one. This will never be the case for the constructed DomU memory map. So we drop those properties altogether and provide a clean and architected GICv3 DT node for DomUs. Signed-off-by: Andre Przywara --- tools/libxl/libxl_arm.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..b5bba3cd33 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -524,14 +524,6 @@ static int make_gicv3_node(libxl__gc *gc, void *fdt) res = fdt_property(fdt, "interrupt-controller", NULL, 0); if (res) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - GUEST_GICV3_RDIST_STRIDE); - if (res) return res; - - res = fdt_property_cell(fdt, "#redistributor-regions", - GUEST_GICV3_RDIST_REGIONS); - if (res) return res; - res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, 2, gicd_base, gicd_size, From patchwork Wed Jan 24 14:35:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125673 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp457022ljf; Wed, 24 Jan 2018 06:37:42 -0800 (PST) X-Google-Smtp-Source: AH8x225t5ZHwd9V2Jx8TayuvmCACmPbZmjylYWk/UucwzAmarzRMF/agxh/3Aqm6OI9HBe0RUQhE X-Received: by 10.36.90.137 with SMTP id v131mr9197850ita.41.1516804662302; Wed, 24 Jan 2018 06:37:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804662; cv=none; d=google.com; s=arc-20160816; b=a/LblNw9PeNsg6yVpXbznn5L4V/cbi7fjKqQ44NUm/D44A2bvOulUM9jlTV7ZhNSsW 2ZxmGXxi+ggw2wUVbdavQ2/pctdg4Ixb8e6A3XXJz3/RC0iwxJxiFYz/iQSm3dFUyZjD +25LrH7tzvCjRRlphaUWaLS/vz19aOSfpwMtnAlOa4oJiV3lTloYFMZMqesWVFdASfYX Zn0vNPYxRsOgfuXDa6Tl0Z72pbqf0DlSmlwBhtGqIt4UVT9tMybGC6AFMMCcVcYkIxuB gKZ0LBaXZ4AtnBw8aFm5VF0sxdNYgGxfvKL1TLrLoaDdmgXXbNh7KsQe5gkpALWQnF5E kw2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=ouEpdbQm3pc4IjDc4WwiKJir3MSEl3NnmfrdIR9uZW0=; b=D2uogeY5Bp1FHznulDtPjLJLg2qeY1DUcig/9HINe/ROsXxTLfc31sHzpYbdICqFwc 7tFyJyuV2xgUFD53u3/3UyaGNRDKDfPwHMh4nXcCJAPfAfOzT1G77i1Z+k8SZbolhFhr wHBW8sN/0ZUfKuZkNc5N9yQq+gqGYiDG7AjBSfoe+JsykZCM6xSm3ZMG+oZDdEARXWZp BSSX+HIivciJ3xlALYxTFteK62PHg7guinDwQ52bMXN9oVpW0RslFgzwU43eykHKjPjv WtoRdpy72d8Wm8BFiNObC/6BSyVBPRPUN6zyqOwUi5yvDbXqK+n/8q4/tw9EEszeQNNv OcEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=dsU2v4G5; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:14 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:12 +0000 Message-Id: <20180124143517.18469-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 2/7] ARM: vGICv3: drop GUEST_GICV3_RDIST_REGIONS symbol X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Architecturally there is only one GICv3 redistributor region. Drop the symbol which suggested that was a delibarate choice for Xen guests, instead hard code the "1" in the appropriate places, along with a comment to explain the reasons. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3.c | 17 ++++++++++++----- xen/include/public/arch-arm.h | 1 - 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index af16dfd005..7d3ea171b4 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1640,8 +1640,18 @@ static int vgic_v3_vcpu_init(struct vcpu *v) static inline unsigned int vgic_v3_rdist_count(struct domain *d) { - return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : - GUEST_GICV3_RDIST_REGIONS; + /* + * Architecturally there is only one GICv3 redistributor region. + * The GICv3 DT binding provisions for multiple regions, since there are + * platforms out there which break this architectural assumption. + * ACPI does not support this workaround at all. + * For Dom0 we have to live with the MMIO layout the hardware provides, + * so we have to copy the multiple regions - as the first region may not + * provide enough space to hold all redistributors we need. + * However DomU get a constructed memory map, so we can go with + * the architected single redistributor region. + */ + return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : 1; } static int vgic_v3_domain_init(struct domain *d) @@ -1700,9 +1710,6 @@ static int vgic_v3_domain_init(struct domain *d) { d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE; - /* XXX: Only one Re-distributor region mapped for the guest */ - BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1); - d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; /* The first redistributor should contain enough space for all CPUs */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 05fd11ca38..ca79ab6284 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -402,7 +402,6 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) #define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000) -#define GUEST_GICV3_RDIST_REGIONS 1 #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) From patchwork Wed Jan 24 14:35:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125669 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp456991ljf; Wed, 24 Jan 2018 06:37:40 -0800 (PST) X-Google-Smtp-Source: AH8x226HepYTGnY/6FlOtY76nhjLpi5N0/GKuRGIf9dXbcku0nz7Be5X2y+xJPU1AEsjedMozhC1 X-Received: by 10.36.70.211 with SMTP id j202mr8985246itb.38.1516804660193; Wed, 24 Jan 2018 06:37:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804660; cv=none; d=google.com; s=arc-20160816; b=efUwAjBy/iZwGnaNneF1Evafs9ejWl/ts8IXZo8AYeuse4xpoKkDf5AUxs6t7cfXh+ kcpTqkCtjZAYEN3HGsJzF9g1SHNJtwdeZUmz7pkUkDKj7ZJuDh1tE8a94SnR/5KTgvXY aPjqltDRTU/KBmprct7AAFy3jlPd2tJ5cXGUPiICwtyGRHphrPEEtOnUO6enpKYcHBGc 3H9xvtiDSCERux/208c8wlcRIzObIVUOuwryylSoL1OzYycjEetA3E0R2Fu4rxpNIKsT qqI7UeAfN5hLv3JZXtd/yivuB1WvKpc2T4SlSJmb6pC2YQDXOhEOAlbywP+zgS9bINk3 n2mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=LJux5cVVKln/dz10PzoygiSWMzqxx32GLdVaenmy+dI=; b=MLfyiwHhETuXYFgg5C38B8vAqRU6aeW7jf7Y9qRTSg/KDOPxJ/BeloyGszZMdqZyPI cptQWUohDkvXjraWgNmLVSKbql1i5xVFBkGKPyYDnIhaZHyRxea0/7NUNVRtc+OxZpJd V+37GAOvxP5C0dm3+gOZfxyA4Eksy7+rngA8jgZ+PMTLc42+1hoh0Mw9SQDmuQ6+Sucq YnD3927eXwpFeuemZQHY3ivbGBu5I1ix/5arO7WuLWb6TFP+GndJLLMalKyC2VYZe3dM 0uWZvj7Dbg0XpmQMGnW5lTxjSSuw7akz3eWNWoWC7aLkf+TZtQs1mkV0XltfRuausTTz u0Tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MEDGv1HK; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a16si293825itb.3.2018.01.24.06.37.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2018 06:37:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MEDGv1HK; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eeM94-00018I-MJ; Wed, 24 Jan 2018 14:35:22 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eeM93-00016I-El for xen-devel@lists.xenproject.org; Wed, 24 Jan 2018 14:35:21 +0000 X-Inumbo-ID: c9237d7c-0113-11e8-ba59-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c9237d7c-0113-11e8-ba59-bc764e045a96; Wed, 24 Jan 2018 15:35:15 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id d9so4262979wre.3 for ; Wed, 24 Jan 2018 06:35:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SGmFCZY5RubzHd6CJHD9VtsO9Zc3NpNH+jLe6+Ndj64=; b=MEDGv1HK1Wv8RiT5eUGEDkn4xCrPEosX5h6BSBmdoMzQ6a0uKKbiF73Lfs8ronJIpN DH61yh3+G+adfyBFy9UEBd1wAAwvpR0wqWKqenyXopJbqDG7cMxNGPKi41ZIlkcNk5ky E521LxqlXy22g8hrkg6kQdm4iaA25fnXOT6W4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SGmFCZY5RubzHd6CJHD9VtsO9Zc3NpNH+jLe6+Ndj64=; b=TvHlCJsH7eInVn+JYkAuDEP5z+Vl9SrvljY4RGn3mI5ymL22o10J4e/lfbSAkyRmL/ qNR6biHMU9UB4d+UghwQb5OQMVs1Ovdxf+7sTJ/kPn+oVD8SnTerNxxaQu8ZCmY6qAKk DzataqQ/26+3nJguc+qs/E4m5001sLBiZ2zypIMtkzEdCZT6yZyzoBZOkL6a12lx+BV5 7xwB+R75+cEfnEKkj3NsLWh/TuR4wmWxxV2q+B4VhfspI85BgpikzvcXYnHgViil+H7G y/ASXoD0NSVWVZbz8honbJhuLoogBiHSP4i5eSDOOfpAK40zCPXWALAAXbFssKbPOsM7 Ag1w== X-Gm-Message-State: AKwxytcbPoWO160qWCYcdJjaEscwGHerkJgIjhs8Y6ZH5nKDjFlH82Pj Ky0IZfQXtRXvPY5JicVJAdho7A== X-Received: by 10.223.160.87 with SMTP id l23mr5495943wrl.51.1516804515681; Wed, 24 Jan 2018 06:35:15 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:15 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:13 +0000 Message-Id: <20180124143517.18469-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 3/7] ARM: GICv3: emit optional DT property only when necessary X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM GICv3 DT property "#redistributor-regions" is optional and only useful if it has any other values than the architected "1". Keep our generated DT node clean by emitting this property only if we actually need more than one region. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a0d290b55c..9ad0cd19ef 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1168,10 +1168,13 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "#redistributor-regions", - d->arch.vgic.nr_regions); - if ( res ) - return res; + if ( d->arch.vgic.nr_regions > 1 ) + { + res = fdt_property_cell(fdt, "#redistributor-regions", + d->arch.vgic.nr_regions); + if ( res ) + return res; + } len = dt_cells_to_size(dt_n_addr_cells(gic) + dt_n_size_cells(gic)); /* From patchwork Wed Jan 24 14:35:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125670 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp456999ljf; Wed, 24 Jan 2018 06:37:40 -0800 (PST) X-Google-Smtp-Source: AH8x227GgrPL4Pf0c+bPripWg6mfrqiYHh9V/Qy6QTwMI+4ke58oMepOoSON30aloZSGFXemg50t X-Received: by 10.107.26.202 with SMTP id a193mr8684958ioa.19.1516804660629; Wed, 24 Jan 2018 06:37:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804660; cv=none; d=google.com; s=arc-20160816; b=s5xz2EM9b3qcb4WzLSw1CxtaA6j3cMu+YmlrGP2pKOWeVR3BQTH+4NjdUaWkUlyFv1 G8WUV7WaO3wbXr8XweaMtzJz2/Hdjpee9zsrvUq7KMT01IPxOdymaEj+HhLeSkMfm27B 2FouAZQY9fL8HiqqK+8vHjItk3mMQFGe2Ob/a/pZBq3jey4NEFbAatLmLPCrDTBH2EDv YFpQlVKG5eHwrCo2cjR5K066lBoUKPU3l1/EFJbivsfXnFB07cgg7zqsex8JvU1/Hf1W wFpwfPk6yiKWxANkSWgUqNlHiDisvuDsblnO7PjsKkHWyfbOFb0KT52XCqD1Uv3jdleB 4saA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=yAmzwuLLCo8MQoFMILtfSUIMjLWutbLcUwhzticnMyI=; b=I4Ho8YegAiwU505Q6Erir+fQbyRyFFVBk+9WMMy3qWsc7QG1+RrvcKhri/hyaiNbo3 feTlCx3WLWCeqoMpZVickAi/8AAF0ll8bRMmpproBJThE2d/+BajfaK1Wll0KMhwDemE Pqw0bwcbhCQFHf39no5HdUkWcjiJ5A+QEIFKR0vxP2my8yJL3R9498G4mjnwmB/HbZAs 1WAa/CNiKQOBKF1NjkaP7wf7W9ltF7zxv6krQEHDerUX5/PHpqChEx4rpmDxXbcLNCSo xawhqiYbistU+m1B/ZYu6lv4YBfAgyabOI7Po+2lSDnuw5/xVZ3eAzj2Pp+CWW+mxh4C bHoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=R+PbVQcv; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id 1si292511itj.89.2018.01.24.06.37.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 24 Jan 2018 06:37:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=R+PbVQcv; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eeM93-00016J-7a; Wed, 24 Jan 2018 14:35:21 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eeM92-000158-0z for xen-devel@lists.xenproject.org; Wed, 24 Jan 2018 14:35:20 +0000 X-Inumbo-ID: c9a7e403-0113-11e8-ba59-bc764e045a96 Received: from mail-wm0-x242.google.com (unknown [2a00:1450:400c:c09::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id c9a7e403-0113-11e8-ba59-bc764e045a96; Wed, 24 Jan 2018 15:35:14 +0100 (CET) Received: by mail-wm0-x242.google.com with SMTP id v71so9050780wmv.2 for ; Wed, 24 Jan 2018 06:35:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IjAi7w8qxTa4bp0P9zBdJ21qsAz+oEtbHGd3p4RFaDs=; b=R+PbVQcvpoUiwR9qCiLfijhuRw/0mNjfq8FAN64Beg80tdKuK+3qYCCGY4bApSBwZj Lu6ni+lJOwCIvho5SiYXCHKbv5V34VvKP8R4XR8GT9IxFD8t1XKeSrGE3QfNLVC540fk R8dqGawzzitgOhN2+cghViLeXaSLVKnreZCes= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IjAi7w8qxTa4bp0P9zBdJ21qsAz+oEtbHGd3p4RFaDs=; b=g4U9BTxZL5ONWq7Rn7E7P5PdH1mlWmTy9rzYG0XqRIwF4SlRH9xYq1KYre5UqjuDD5 o18Tko/v8SFVMhd8b0ua7oXcU/2bUwgUMK0IwKt6hcok8OleUMn/DGFcXUuBxuIz7MVM BTQ7+EBP5HUz5nNnct2AgWvWBmT0PpAIUjGApf4JB0y+pt2ekwH7NwAQ6qX/3fV6tzmt uYtDNqTGoGWSHn1fFF5E12eZ4llKIJbvzxI1lAaMPCRm9UqaFUbpTTOckjSUnytKReat +xS6eFX43Jyabk8Emz310mZy1HojxU0FBUjApXo96MiY2EMCvA9gqw5eZy9d3d+xofYq bXOA== X-Gm-Message-State: AKwxytfoQZoZWpw5RMCGGks5DlwUtyngH9KjmJdaOi8ns5+mZ4/C44m5 sxwlzPATgehrJAVUsYrYxjBcqw== X-Received: by 10.28.145.21 with SMTP id t21mr5791921wmd.136.1516804516575; Wed, 24 Jan 2018 06:35:16 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:16 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:14 +0000 Message-Id: <20180124143517.18469-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 4/7] ARM: GICv3: use hardware GICv3 redistributor regions for Dom0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The code to generate the DT node or MADT table for Dom0 reaches into the domain's VGIC structure to learn the number of redistributor regions and their base addresses. Since those values are copied from the hardware, we can as well use those hardware values directly when setting up the hardware domain. This avoids the hardware GIC code to reference vGIC data structures, making this variable VGIC internal. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 9ad0cd19ef..1c24ecbba7 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1168,10 +1168,10 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - if ( d->arch.vgic.nr_regions > 1 ) + if ( gicv3.rdist_count > 1 ) { res = fdt_property_cell(fdt, "#redistributor-regions", - d->arch.vgic.nr_regions); + gicv3.rdist_count); if ( res ) return res; } @@ -1182,7 +1182,7 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, * CPU interface and virtual cpu interfaces accessesed as System registers * So cells are created only for Distributor and rdist regions */ - len = len * (d->arch.vgic.nr_regions + 1); + len = len * (gicv3.rdist_count + 1); new_cells = xzalloc_bytes(len); if ( new_cells == NULL ) return -FDT_ERR_XEN(ENOMEM); @@ -1191,9 +1191,9 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, dt_set_range(&tmp, gic, d->arch.vgic.dbase, SZ_64K); - for ( i = 0; i < d->arch.vgic.nr_regions; i++ ) - dt_set_range(&tmp, gic, d->arch.vgic.rdist_regions[i].base, - d->arch.vgic.rdist_regions[i].size); + for ( i = 0; i < gicv3.rdist_count; i++ ) + dt_set_range(&tmp, gic, gicv3.rdist_regions[i].base, + gicv3.rdist_regions[i].size); res = fdt_property(fdt, "reg", new_cells, len); xfree(new_cells); @@ -1419,13 +1419,13 @@ static int gicv3_make_hwdom_madt(const struct domain *d, u32 offset) /* Add Generic Redistributor */ size = sizeof(struct acpi_madt_generic_redistributor); - for ( i = 0; i < d->arch.vgic.nr_regions; i++ ) + for ( i = 0; i < gicv3.rdist_count; i++ ) { gicr = (struct acpi_madt_generic_redistributor *)(base_ptr + table_len); gicr->header.type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; gicr->header.length = size; - gicr->base_address = d->arch.vgic.rdist_regions[i].base; - gicr->length = d->arch.vgic.rdist_regions[i].size; + gicr->base_address = gicv3.rdist_regions[i].base; + gicr->length = gicv3.rdist_regions[i].size; table_len += size; } @@ -1438,8 +1438,7 @@ static unsigned long gicv3_get_hwdom_extra_madt_size(const struct domain *d) { unsigned long size; - size = sizeof(struct acpi_madt_generic_redistributor) - * d->arch.vgic.nr_regions; + size = sizeof(struct acpi_madt_generic_redistributor) * gicv3.rdist_count; size += sizeof(struct acpi_madt_generic_translator) * vgic_v3_its_count(d); From patchwork Wed Jan 24 14:35:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125667 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp456907ljf; Wed, 24 Jan 2018 06:37:31 -0800 (PST) X-Google-Smtp-Source: AH8x224R0eL3/68jRpihztyLx8nTPukw2aESy8JQzs43B9/KAemQ0NGDPYqJUceVNEAmoV2UoVNu X-Received: by 10.107.178.70 with SMTP id b67mr8469070iof.139.1516804651454; Wed, 24 Jan 2018 06:37:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804651; cv=none; d=google.com; s=arc-20160816; b=nDXE+jER7asAdWLlHT/KDMk9PvLQRIJyWJFi08JkgC5ArxkJPvklE8TgCKxNLB+YPO ExNGeCxkdewKZ5MKp2CEzW77kVM5cr7SIOB/PmmjwxpJSdkh3H+Fhu6fDvovEZKEGBwe e4hXsHcUAwWoklVFx1kl382RLWb69NMVxcVTKM/QBLXaF2F3LtbcFwITTo88vRb75ei4 qqB4PDGrP7qmI7okpE2owxUlaiJkUQE7eaMeKaNrymDhK7rDrNiH3ZgL5j2HQktsebuk kFQvPpu4YHiWyWKi9VtflSgD9X6Mr/yYo2lbhcS93p+IbUefrJdR+LCIDIh4ywdU1Sga TwjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=u74rSD4PDkBrgzJCstEIPCW6n4ZDLvX5XHFHTvEGrhs=; b=ghHnlsJhcKQagZnQ4bZzGNrhDeCdRXDco4YyBkdqgSJ2OWKXuj8L/1p/Nbb055sseC TLIx+plVjiG9+tdjv4LkBaB7PivShE5BCGiMk35Drr2NT+HEXu7EVkFqdJv4qA4G01mI MOF1xC3mtfYGZgzym9HjFUN2EFD2vwh4Pf9SA8Gv6Qpk0CPdmgQHv6n0sDQIr/UJ2gtI Fg9WIaYIpXUKNPnRSWLeAHAJGpdYloqMiyqxeTg41AXrUTTEIecbI1RD8tWwQWEj4RUm Z0mHAD0/D1O+oF6aN5ZqL4nQrtCRdQZu+pE8u5lYd4hMtoSTpCzMlQxTNkay/0kpI1A6 YEFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UM5DieSR; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:17 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:15 +0000 Message-Id: <20180124143517.18469-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 5/7] ARM: GICv3: simplify GICv3 redistributor stride handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Instead of hard coding the architected redistributor stride into the code, lets use a clear #define to the two values for GICv3 and GICv4 and clarify the algorithm to determine the needed stride value. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 18 ++++++++++-------- xen/include/asm-arm/gic_v3_defs.h | 5 +++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 1c24ecbba7..2893c66492 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -690,6 +690,15 @@ static int __init gicv3_populate_rdist(void) do { typer = readq_relaxed(ptr + GICR_TYPER); + /* Set the architectural redist size if not overridden by DT. */ + if ( !gicv3.rdist_stride ) + { + if ( typer & GICR_TYPER_VLPIS ) + gicv3.rdist_stride = GICV4_GICR_SIZE; + else + gicv3.rdist_stride = GICV3_GICR_SIZE; + } + if ( (typer >> 32) == aff ) { this_cpu(rbase) = ptr; @@ -732,14 +741,7 @@ static int __init gicv3_populate_rdist(void) if ( gicv3.rdist_regions[i].single_rdist ) break; - if ( gicv3.rdist_stride ) - ptr += gicv3.rdist_stride; - else - { - ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ - if ( typer & GICR_TYPER_VLPIS ) - ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ - } + ptr += gicv3.rdist_stride; } while ( !(typer & GICR_TYPER_LAST) ); } diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 65c9dc47cf..412e41afed 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -18,6 +18,8 @@ #ifndef __ASM_ARM_GIC_V3_DEFS_H__ #define __ASM_ARM_GIC_V3_DEFS_H__ +#include + /* * Additional registers defined in GIC v3. * Common GICD registers are defined in gic.h @@ -68,6 +70,9 @@ #define GICV3_GICD_IIDR_VAL 0x34c #define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL +#define GICV3_GICR_SIZE (2 * SZ_64K) +#define GICV4_GICR_SIZE (4 * SZ_64K) + #define GICR_CTLR (0x0000) #define GICR_IIDR (0x0004) #define GICR_TYPER (0x0008) From patchwork Wed Jan 24 14:35:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125671 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp457005ljf; Wed, 24 Jan 2018 06:37:41 -0800 (PST) X-Google-Smtp-Source: AH8x225WMsZo5iU7MY89R6297w8QE4RBrpODDsSTQBcSA+43/oyHmQgEZn5vnLxt2QlywG9uq8hu X-Received: by 10.107.13.143 with SMTP id 137mr8349300ion.265.1516804661070; Wed, 24 Jan 2018 06:37:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804661; cv=none; d=google.com; s=arc-20160816; b=DzmD6BXYJp9KTW1jXSORbaXnW9gAQAEaVlXDKe4ubdNUB8kCQ/znjBVJLQyRI2gbEd 0agGOaBlZ2BvN8O77qYCWNVjRgnATyY+hr12qNvpz9WOzQQcs+oMRKcvQIUnTwQUrcYC +k9VETDAyY2Ky67r3wkVDhpBBSgElfbZm5kNz4h9UPoguHkbFNlh3mh01yupMsQYdrmT d1UugRL7ytWz0seKY2wCuU8EP+87A/O1eKmZr+rhjQwY3iv2VivLS2seHz1c2fE8ouRh /HbNf/ZHakVdnVlOMamEQd2IKh1ucoj8OYhSzeEcWQIQKvNYZTSjNr32q2tDb4yE9r3E OT/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=CmE32l0MxkUd9/tQNrRomYuaUkJQmE/gtW//OQw7fZQ=; b=PberrCV10Y27p2hq6ih9eWggst0XDHLd6iw5NMh884/Ob6S74gCy0KxfQyHp2c2x26 GvW5Cl636e2PViXX+XuNVvbsoCLXXQpM+/e6w3zjFbrmGuiXylgfgJKZVzY5G21zD2iQ cNrF7vyooDbeWSzVPx1Lri1XeXwj/p8a0XyEhqto0BpeVa8o/NX4FwVIocV2KUiGMdmG aVM5w2Zzq3OIVePCreETCWY07HWk1mrdtQdn0+f5oZbVVqNrk5bWtoY/DGB9AmcrrDkz Oszzv5O+enEu8Nh3unljmno9VWkQORJ5KDyZzfBl/jrwIK+nyxkL0H9M7bLFOEUolVYB mKGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TORzvEsA; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:18 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:16 +0000 Message-Id: <20180124143517.18469-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 6/7] ARM: vGICv3: always use architected redist stride X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The redistributor-stride property in a GICv3 DT node is only there to cover broken platforms where this value deviates from the architected one. Since we emulate the GICv3 distributor even for Dom0, we don't need to copy the broken behaviour. All the special handling for Dom0s using GICv3 is just for using the hardware's memory map, which is unaffected by the redistributor stride - it can never be smaller than the architected two pages. Remove the redistributor-stride property from Dom0's DT node and also remove the code that tried to reuse the hardware value for Dom0's GICv3 emulation. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/gic-v3.c | 5 ----- xen/arch/arm/vgic-v3.c | 14 ++++++-------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 2893c66492..1684d9cf1b 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1165,11 +1165,6 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - d->arch.vgic.rdist_stride); - if ( res ) - return res; - if ( gicv3.rdist_count > 1 ) { res = fdt_property_cell(fdt, "#redistributor-regions", diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 7d3ea171b4..b4159317dd 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1030,10 +1030,9 @@ static struct vcpu *get_vcpu_from_rdist(struct domain *d, paddr_t gpa, uint32_t *offset) { struct vcpu *v; - uint32_t stride = d->arch.vgic.rdist_stride; unsigned int vcpu_id; - vcpu_id = region->first_cpu + ((gpa - region->base) / stride); + vcpu_id = region->first_cpu + ((gpa - region->base) / GICV3_GICR_SIZE); if ( unlikely(vcpu_id >= d->max_vcpus) ) return NULL; @@ -1594,7 +1593,6 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Convenient alias */ struct domain *d = v->domain; - uint32_t rdist_stride = d->arch.vgic.rdist_stride; /* * Find the region where the re-distributor lives. For this purpose, @@ -1610,11 +1608,11 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Get the base address of the redistributor */ rdist_base = region->base; - rdist_base += (v->vcpu_id - region->first_cpu) * rdist_stride; + rdist_base += (v->vcpu_id - region->first_cpu) * GICV3_GICR_SIZE; /* Check if a valid region was found for the re-distributor */ if ( (rdist_base < region->base) || - ((rdist_base + rdist_stride) > (region->base + region->size)) ) + ((rdist_base + GICV3_GICR_SIZE) > (region->base + region->size)) ) { dprintk(XENLOG_ERR, "d%u: Unable to find a re-distributor for VCPU %u\n", @@ -1630,7 +1628,7 @@ static int vgic_v3_vcpu_init(struct vcpu *v) * VGIC_V3_RDIST_LAST flags. * Note that we are assuming max_vcpus will never change. */ - last_cpu = (region->size / rdist_stride) + region->first_cpu - 1; + last_cpu = (region->size / GICV3_GICR_SIZE) + region->first_cpu - 1; if ( v->vcpu_id == last_cpu || (v->vcpu_id == (d->max_vcpus - 1)) ) v->arch.vgic.flags |= VGIC_V3_RDIST_LAST; @@ -1701,7 +1699,7 @@ static int vgic_v3_domain_init(struct domain *d) /* Set the first CPU handled by this region */ d->arch.vgic.rdist_regions[i].first_cpu = first_cpu; - first_cpu += size / d->arch.vgic.rdist_stride; + first_cpu += size / GICV3_GICR_SIZE; } d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; @@ -1713,7 +1711,7 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; /* The first redistributor should contain enough space for all CPUs */ - BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GUEST_GICV3_RDIST_STRIDE) < MAX_VIRT_CPUS); + BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE; d->arch.vgic.rdist_regions[0].first_cpu = 0; From patchwork Wed Jan 24 14:35:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125674 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp457119ljf; Wed, 24 Jan 2018 06:37:50 -0800 (PST) X-Google-Smtp-Source: AH8x227wwtkawyH4VK/SjRypoUtPutnjpg3xlLVdvjq9QgBe/mAfiopCPqp4sBDkPlkd1nXlz/oR X-Received: by 10.36.87.83 with SMTP id u80mr9148706ita.140.1516804670665; Wed, 24 Jan 2018 06:37:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516804670; cv=none; d=google.com; s=arc-20160816; b=ACENNstFgmgUXhMtg5PnuvEX+8WDG1zAuejQtm0wx/M9McCVipO7kn9fjTPczVYDcP yjD+DYbm08GpQ0ou+tmLDFJ3WgddVSfx1S5ZDkC3Am4pTbqcJ3eywN1o1rdmHXLasWL7 SUafGHVxa6r38SLJGoMo8EOqw4zQyZHxVbIEyRVg/Nf6JlXc+lqCRWdt74rOKvog9Fx8 zkzLeNXq5lj209HDMSC9mpHmUrtDcazp2kWf9hxQ18SMWwcWh/Xtzbt2M/STjjZ74AMa syBdIL/O6V+Uuf6vxyN75xdVn5nkoLN2e16RNFCRiFZYpTQq404xFgs9j1LBTv+Kkina pK6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=DHxsZ3ox2nFM3dhV593ZBrB6wxZEW2LajFv0S99fG0Y=; b=H1/4zpwLAV6VemQEbTAt6Lw79M7UDeIySfL8+fAEU7SIIFnzqm7eQpcWPKqIlR+Pk0 vuqQtFI/iNQFPk5l8VQlema1mVCgybULhSqwRsHZCSrx5hSr/MNfOFEUSZGvQjnOldPs k1L2ejyoDKbqQJPfvl6cPqlXU/gjTaUPTQqDByYrg12pZZ/ifbv3q6u6fUbb/gYqRk+O 8A/395t3lnzLl7bz/UpaMySCIfGCXQz1KRIeKuI/5cfFzCWIiQqmnZu4k3QaRHhkC1v+ wwDdSdUStGP7S4wP3erj+P2flg7yy+ECv9rtwO8pRptDyYQf4g4786cheaKcQo1RZSu6 AI1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ai1CgRDF; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id l9sm3267923wrb.91.2018.01.24.06.35.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 06:35:18 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Wed, 24 Jan 2018 14:35:17 +0000 Message-Id: <20180124143517.18469-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124143517.18469-1-andre.przywara@linaro.org> References: <20180124143517.18469-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 7/7] ARM: vGICv3: remove rdist_stride from VGIC structure X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The last patch removed the usage of the hardware's redistributor-stride value from our (Dom0) GICv3 emulation. This means we no longer need to store this value in the VGIC data structure. Remove that variable and every code snippet that handled that, instead simply always use the architected value. Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/gic-v3.c | 3 +-- xen/arch/arm/vgic-v3.c | 14 -------------- xen/include/asm-arm/domain.h | 1 - xen/include/asm-arm/vgic.h | 1 - xen/include/public/arch-arm.h | 2 -- 5 files changed, 1 insertion(+), 20 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 1684d9cf1b..588fe94cab 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1693,8 +1693,7 @@ static int __init gicv3_init(void) reg = readl_relaxed(GICD + GICD_TYPER); intid_bits = GICD_TYPE_ID_BITS(reg); - vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, - gicv3.rdist_stride, intid_bits); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, intid_bits); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index b4159317dd..47856a0a73 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -58,21 +58,18 @@ static struct { /* Re-distributor regions */ unsigned int nr_rdist_regions; const struct rdist_region *regions; - uint32_t rdist_stride; /* Re-distributor stride */ unsigned int intid_bits; /* Number of interrupt ID bits */ } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits) { vgic_v3_hw.enabled = true; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; - vgic_v3_hw.rdist_stride = rdist_stride; vgic_v3_hw.intid_bits = intid_bits; } @@ -1680,15 +1677,6 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.dbase = vgic_v3_hw.dbase; - d->arch.vgic.rdist_stride = vgic_v3_hw.rdist_stride; - /* - * If the stride is not set, the default stride for GICv3 is 2 * 64K: - * - first 64k page for Control and Physical LPIs - * - second 64k page for Control and Generation of SGIs - */ - if ( !d->arch.vgic.rdist_stride ) - d->arch.vgic.rdist_stride = 2 * SZ_64K; - for ( i = 0; i < vgic_v3_hw.nr_rdist_regions; i++ ) { paddr_t size = vgic_v3_hw.regions[i].size; @@ -1708,8 +1696,6 @@ static int vgic_v3_domain_init(struct domain *d) { d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE; - d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; - /* The first redistributor should contain enough space for all CPUs */ BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 4fe189b1c3..3eda7196ff 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -108,7 +108,6 @@ struct arch_domain unsigned int first_cpu; /* First CPU handled */ } *rdist_regions; int nr_regions; /* Number of rdist regions */ - uint32_t rdist_stride; /* Re-Distributor stride */ unsigned long int nr_lpis; uint64_t rdist_propbase; struct rb_root its_devices; /* Devices mapped to an ITS */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 2a93a7bef9..7919cc53f4 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -255,7 +255,6 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits); #endif diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index ca79ab6284..3bca165fbf 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -401,8 +401,6 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) -#define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000) - #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000)