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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:53 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:51 +0000 Message-Id: <20180124181058.6157-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 1/8] ARM: VGIC: drop unneeded gic_restore_pending_irqs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In gic_restore_pending_irqs() we push our pending virtual IRQs into the list registers. This function is called once from gic_inject(), just before we return to the guest, but also in gic_restore_state(), when we context-switch a VCPU. Having a closer look it turns out that the later call is not needed, since we will always call gic_inject() anyway. So remove that call (and the forward declaration) to streamline this interface and make separating the GIC from the VGIC world later. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index bac8ada2bb..721a17a9d7 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,8 +36,6 @@ #include #include -static void gic_restore_pending_irqs(struct vcpu *v); - static DEFINE_PER_CPU(uint64_t, lr_mask); #define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) @@ -91,8 +89,6 @@ void gic_restore_state(struct vcpu *v) gic_hw_ops->restore_state(v); isb(); - - gic_restore_pending_irqs(v); } /* desc->irq needs to be disabled before calling this function */ From patchwork Wed Jan 24 18:10:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125697 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp581060ljf; Wed, 24 Jan 2018 10:13:45 -0800 (PST) X-Google-Smtp-Source: AH8x227NeY+FL1yuP9gQ8t984p4BTspGy1XWyfbMvpG/2Ty1XdK1NEM5xh9DD27pajcTZ9/6txfh X-Received: by 10.36.138.134 with SMTP id v128mr9774581itd.153.1516817625108; Wed, 24 Jan 2018 10:13:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817625; cv=none; d=google.com; s=arc-20160816; b=Zz55NQVbvEAxyIZC2FlKb+0vvcHAgTu+9zV2zT58OCx53ouOAQc2vDrbOiGTIDJVjV Q1Z3R9Ehn3IdpUXhY0ixueAyebYmU90QUnxg696L/Or1q6kACz9m54EDzG+H6Y2swGDv 6uBEFXLyCvCUh6zMxf+WTyulgbFxQbZpDr4pY6UhsX0Hzq+qs0oq48HP2iq1yFi55TBh FqayxL6xbE2Ik7DRZPpquRrcadakDa+gVdurX8WeRf8xLUxg4A3EYWLhiXUUGbn6Zwzv 7gJHb/wouaiZ3iwBILHQLnbbU8HCFh1gr4mTUhMSVHifUGvOF3LGATLB5eCpT8hUiAx1 IHLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=cqllmBJ8LG3TpOpE1zloj+6K8/G9z4Lz2sJjknSxQAM=; b=uA7A4zUntPToEO3+7+Zu2iihypYmzgqQyeKdv1zX0WQcRjOr+l8bMPieq3U8riHk4k AGQMIS8wMdIOTWl2inZjR1bvTe5pBgu800J6WBBdsH2pVDAcTvYZ+qtzHj4MWxahBB0d 39WHWyKExv0ExRtvw689QqMEVx73TzKf8Oz/kiu+A8XXShCSWBoUmVpJph2MNjMNl/F/ JBQ/ZRhC8oImDC197eSm43bbxZipW27iCmiU3L0oJDAVI6M1XrHde31SpQ2XdXzIfMV8 GocOcZhuEVC1SaDeGDdWB7mejo+hv8HT2csp6rBt7jDcGU3nkg/FMfQ9A1mAJFjTD/Ex aboA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SxEK41ZE; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:55 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:52 +0000 Message-Id: <20180124181058.6157-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 2/8] ARM: VGIC: split gic.c to observe hardware/virtual GIC separation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic.c holds code to handle hardware IRQs as well as code to bridge VGIC requests to the GIC virtualization hardware. Despite being named gic.c, this file reaches into the VGIC and uses data structures describing virtual IRQs. To improve abstraction, move the VGIC functions into a separate file, so that gic.c does what it says on the tin. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/Makefile | 1 + xen/arch/arm/gic-vgic.c | 410 ++++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 363 +----------------------------------------- 3 files changed, 413 insertions(+), 361 deletions(-) create mode 100644 xen/arch/arm/gic-vgic.c diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 30a2a6500a..41d7366527 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,6 +16,7 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o +obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c new file mode 100644 index 0000000000..98df84e3d5 --- /dev/null +++ b/xen/arch/arm/gic-vgic.c @@ -0,0 +1,410 @@ +/* + * xen/arch/arm/gic-vgic.c + * + * ARM Generic Interrupt Controller virtualization support + * + * Tim Deegan + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint64_t per_cpu__lr_mask; +extern const struct gic_hw_operations *gic_hw_ops; + +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) + +#undef GIC_DEBUG + +static void gic_update_one_lr(struct vcpu *v, int i); + +static inline void gic_set_lr(int lr, struct pending_irq *p, + unsigned int state) +{ + ASSERT(!local_irq_is_enabled()); + + clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); + + gic_hw_ops->update_lr(lr, p, state); + + set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); + p->lr = lr; +} + +static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) +{ + struct pending_irq *iter; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( !list_empty(&n->lr_queue) ) + return; + + list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) + { + if ( iter->priority > n->priority ) + { + list_add_tail(&n->lr_queue, &iter->lr_queue); + return; + } + } + list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); +} + +void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) +{ + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + list_del_init(&p->lr_queue); +} + +void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) +{ + struct pending_irq *n = irq_to_pending(v, virtual_irq); + + /* If an LPI has been removed meanwhile, there is nothing left to raise. */ + if ( unlikely(!n) ) + return; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + /* Don't try to update the LR if the interrupt is disabled */ + if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) + return; + + if ( list_empty(&n->lr_queue) ) + { + if ( v == current ) + gic_update_one_lr(v, n->lr); + } +#ifdef GIC_DEBUG + else + gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", + virtual_irq, v->domain->domain_id, v->vcpu_id); +#endif +} + +/* + * Find an unused LR to insert an IRQ into, starting with the LR given + * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to + * avoid inserting the same IRQ twice. This situation can occur when an + * event gets discarded while the LPI is in an LR, and a new LPI with the + * same number gets mapped quickly afterwards. + */ +static unsigned int gic_find_unused_lr(struct vcpu *v, + struct pending_irq *p, + unsigned int lr) +{ + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + unsigned int used_lr; + + for_each_set_bit(used_lr, lr_mask, nr_lrs) + { + gic_hw_ops->read_lr(used_lr, &lr_val); + if ( lr_val.virq == p->irq ) + return used_lr; + } + } + + lr = find_next_zero_bit(lr_mask, nr_lrs, lr); + + return lr; +} + +void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, + unsigned int priority) +{ + int i; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + struct pending_irq *p = irq_to_pending(v, virtual_irq); + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + if ( unlikely(!p) ) + /* An unmapped LPI does not need to be raised. */ + return; + + if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) + { + i = gic_find_unused_lr(v, p, 0); + + if (i < nr_lrs) { + set_bit(i, &this_cpu(lr_mask)); + gic_set_lr(i, p, GICH_LR_PENDING); + return; + } + } + + gic_add_to_lr_pending(v, p); +} + +static void gic_update_one_lr(struct vcpu *v, int i) +{ + struct pending_irq *p; + int irq; + struct gic_lr lr_val; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + ASSERT(!local_irq_is_enabled()); + + gic_hw_ops->read_lr(i, &lr_val); + irq = lr_val.virq; + p = irq_to_pending(v, irq); + /* + * An LPI might have been unmapped, in which case we just clean up here. + * If that LPI is marked as PRISTINE, the information in the LR is bogus, + * as it belongs to a previous, already unmapped LPI. So we discard it + * here as well. + */ + if ( unlikely(!p || + test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) + { + ASSERT(is_lpi(irq)); + + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + return; + } + + if ( lr_val.state & GICH_LR_ACTIVE ) + { + set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) + { + if ( p->desc == NULL ) + { + lr_val.state |= GICH_LR_PENDING; + gic_hw_ops->write_lr(i, &lr_val); + } + else + gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); + } + } + else if ( lr_val.state & GICH_LR_PENDING ) + { + int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); +#ifdef GIC_DEBUG + if ( q ) + gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", + irq, v->domain->domain_id, v->vcpu_id, i); +#endif + } + else + { + gic_hw_ops->clear_lr(i); + clear_bit(i, &this_cpu(lr_mask)); + + if ( p->desc != NULL ) + clear_bit(_IRQ_INPROGRESS, &p->desc->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); + p->lr = GIC_INVALID_LR; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && + !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + gic_raise_guest_irq(v, irq, p->priority); + else { + list_del_init(&p->inflight); + /* + * Remove from inflight, then change physical affinity. It + * makes sure that when a new interrupt is received on the + * next pcpu, inflight is already cleared. No concurrent + * accesses to inflight. + */ + smp_wmb(); + if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) + { + struct vcpu *v_target = vgic_get_target_vcpu(v, irq); + irq_set_affinity(p->desc, cpumask_of(v_target->processor)); + clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); + } + } + } +} + +void gic_clear_lrs(struct vcpu *v) +{ + int i = 0; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + + /* The idle domain has no LRs to be cleared. Since gic_restore_state + * doesn't write any LR registers for the idle domain they could be + * non-zero. */ + if ( is_idle_vcpu(v) ) + return; + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), + nr_lrs, i)) < nr_lrs ) { + gic_update_one_lr(v, i); + i++; + } + + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +static void gic_restore_pending_irqs(struct vcpu *v) +{ + int lr = 0; + struct pending_irq *p, *t, *p_r; + struct list_head *inflight_r; + unsigned long flags; + unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + int lrs = nr_lrs; + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + if ( list_empty(&v->arch.vgic.lr_pending) ) + goto out; + + inflight_r = &v->arch.vgic.inflight_irqs; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + { + lr = gic_find_unused_lr(v, p, lr); + if ( lr >= nr_lrs ) + { + /* No more free LRs: find a lower priority irq to evict */ + list_for_each_entry_reverse( p_r, inflight_r, inflight ) + { + if ( p_r->priority == p->priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && + !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) + goto found; + } + /* We didn't find a victim this time, and we won't next + * time, so quit */ + goto out; + +found: + lr = p_r->lr; + p_r->lr = GIC_INVALID_LR; + set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); + gic_add_to_lr_pending(v, p_r); + inflight_r = &p_r->inflight; + } + + gic_set_lr(lr, p, GICH_LR_PENDING); + list_del_init(&p->lr_queue); + set_bit(lr, &this_cpu(lr_mask)); + + /* We can only evict nr_lrs entries */ + lrs--; + if ( lrs == 0 ) + break; + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); +} + +void gic_clear_pending_irqs(struct vcpu *v) +{ + struct pending_irq *p, *t; + + ASSERT(spin_is_locked(&v->arch.vgic.lock)); + + v->arch.lr_mask = 0; + list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) + gic_remove_from_lr_pending(v, p); +} + +int gic_events_need_delivery(void) +{ + struct vcpu *v = current; + struct pending_irq *p; + unsigned long flags; + const unsigned long apr = gic_hw_ops->read_apr(0); + int mask_priority; + int active_priority; + int rc = 0; + + mask_priority = gic_hw_ops->read_vmcr_priority(); + active_priority = find_next_bit(&apr, 32, 0); + + spin_lock_irqsave(&v->arch.vgic.lock, flags); + + /* TODO: We order the guest irqs by priority, but we don't change + * the priority of host irqs. */ + + /* find the first enabled non-active irq, the queue is already + * ordered by priority */ + list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) + { + if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) + goto out; + if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) + goto out; + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + { + rc = 1; + goto out; + } + } + +out: + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + return rc; +} + +void gic_inject(void) +{ + ASSERT(!local_irq_is_enabled()); + + gic_restore_pending_irqs(current); + + if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 721a17a9d7..04e6d66b69 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -36,15 +36,11 @@ #include #include -static DEFINE_PER_CPU(uint64_t, lr_mask); - -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +DEFINE_PER_CPU(uint64_t, lr_mask); #undef GIC_DEBUG -static void gic_update_one_lr(struct vcpu *v, int i); - -static const struct gic_hw_operations *gic_hw_ops; +const struct gic_hw_operations *gic_hw_ops; void register_gic_ops(const struct gic_hw_operations *ops) { @@ -366,361 +362,6 @@ void gic_disable_cpu(void) gic_hw_ops->disable_interface(); } -static inline void gic_set_lr(int lr, struct pending_irq *p, - unsigned int state) -{ - ASSERT(!local_irq_is_enabled()); - - clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - - gic_hw_ops->update_lr(lr, p, state); - - set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); - p->lr = lr; -} - -static inline void gic_add_to_lr_pending(struct vcpu *v, struct pending_irq *n) -{ - struct pending_irq *iter; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( !list_empty(&n->lr_queue) ) - return; - - list_for_each_entry ( iter, &v->arch.vgic.lr_pending, lr_queue ) - { - if ( iter->priority > n->priority ) - { - list_add_tail(&n->lr_queue, &iter->lr_queue); - return; - } - } - list_add_tail(&n->lr_queue, &v->arch.vgic.lr_pending); -} - -void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p) -{ - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - list_del_init(&p->lr_queue); -} - -void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq) -{ - struct pending_irq *n = irq_to_pending(v, virtual_irq); - - /* If an LPI has been removed meanwhile, there is nothing left to raise. */ - if ( unlikely(!n) ) - return; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - /* Don't try to update the LR if the interrupt is disabled */ - if ( !test_bit(GIC_IRQ_GUEST_ENABLED, &n->status) ) - return; - - if ( list_empty(&n->lr_queue) ) - { - if ( v == current ) - gic_update_one_lr(v, n->lr); - } -#ifdef GIC_DEBUG - else - gdprintk(XENLOG_DEBUG, "trying to inject irq=%u into d%dv%d, when it is still lr_pending\n", - virtual_irq, v->domain->domain_id, v->vcpu_id); -#endif -} - -/* - * Find an unused LR to insert an IRQ into, starting with the LR given - * by @lr. If this new interrupt is a PRISTINE LPI, scan the other LRs to - * avoid inserting the same IRQ twice. This situation can occur when an - * event gets discarded while the LPI is in an LR, and a new LPI with the - * same number gets mapped quickly afterwards. - */ -static unsigned int gic_find_unused_lr(struct vcpu *v, - struct pending_irq *p, - unsigned int lr) -{ - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(test_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - unsigned int used_lr; - - for_each_set_bit(used_lr, lr_mask, nr_lrs) - { - gic_hw_ops->read_lr(used_lr, &lr_val); - if ( lr_val.virq == p->irq ) - return used_lr; - } - } - - lr = find_next_zero_bit(lr_mask, nr_lrs, lr); - - return lr; -} - -void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, - unsigned int priority) -{ - int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - struct pending_irq *p = irq_to_pending(v, virtual_irq); - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - if ( unlikely(!p) ) - /* An unmapped LPI does not need to be raised. */ - return; - - if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) - { - i = gic_find_unused_lr(v, p, 0); - - if (i < nr_lrs) { - set_bit(i, &this_cpu(lr_mask)); - gic_set_lr(i, p, GICH_LR_PENDING); - return; - } - } - - gic_add_to_lr_pending(v, p); -} - -static void gic_update_one_lr(struct vcpu *v, int i) -{ - struct pending_irq *p; - int irq; - struct gic_lr lr_val; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - ASSERT(!local_irq_is_enabled()); - - gic_hw_ops->read_lr(i, &lr_val); - irq = lr_val.virq; - p = irq_to_pending(v, irq); - /* - * An LPI might have been unmapped, in which case we just clean up here. - * If that LPI is marked as PRISTINE, the information in the LR is bogus, - * as it belongs to a previous, already unmapped LPI. So we discard it - * here as well. - */ - if ( unlikely(!p || - test_and_clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status)) ) - { - ASSERT(is_lpi(irq)); - - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - return; - } - - if ( lr_val.state & GICH_LR_ACTIVE ) - { - set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status) ) - { - if ( p->desc == NULL ) - { - lr_val.state |= GICH_LR_PENDING; - gic_hw_ops->write_lr(i, &lr_val); - } - else - gdprintk(XENLOG_WARNING, "unable to inject hw irq=%d into d%dv%d: already active in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); - } - } - else if ( lr_val.state & GICH_LR_PENDING ) - { - int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); -#ifdef GIC_DEBUG - if ( q ) - gdprintk(XENLOG_DEBUG, "trying to inject irq=%d into d%dv%d, when it is already pending in LR%d\n", - irq, v->domain->domain_id, v->vcpu_id, i); -#endif - } - else - { - gic_hw_ops->clear_lr(i); - clear_bit(i, &this_cpu(lr_mask)); - - if ( p->desc != NULL ) - clear_bit(_IRQ_INPROGRESS, &p->desc->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - clear_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); - p->lr = GIC_INVALID_LR; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && - test_bit(GIC_IRQ_GUEST_QUEUED, &p->status) && - !test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - gic_raise_guest_irq(v, irq, p->priority); - else { - list_del_init(&p->inflight); - /* - * Remove from inflight, then change physical affinity. It - * makes sure that when a new interrupt is received on the - * next pcpu, inflight is already cleared. No concurrent - * accesses to inflight. - */ - smp_wmb(); - if ( test_bit(GIC_IRQ_GUEST_MIGRATING, &p->status) ) - { - struct vcpu *v_target = vgic_get_target_vcpu(v, irq); - irq_set_affinity(p->desc, cpumask_of(v_target->processor)); - clear_bit(GIC_IRQ_GUEST_MIGRATING, &p->status); - } - } - } -} - -void gic_clear_lrs(struct vcpu *v) -{ - int i = 0; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - - /* The idle domain has no LRs to be cleared. Since gic_restore_state - * doesn't write any LR registers for the idle domain they could be - * non-zero. */ - if ( is_idle_vcpu(v) ) - return; - - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - while ((i = find_next_bit((const unsigned long *) &this_cpu(lr_mask), - nr_lrs, i)) < nr_lrs ) { - gic_update_one_lr(v, i); - i++; - } - - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -static void gic_restore_pending_irqs(struct vcpu *v) -{ - int lr = 0; - struct pending_irq *p, *t, *p_r; - struct list_head *inflight_r; - unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; - int lrs = nr_lrs; - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - if ( list_empty(&v->arch.vgic.lr_pending) ) - goto out; - - inflight_r = &v->arch.vgic.inflight_irqs; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - { - lr = gic_find_unused_lr(v, p, lr); - if ( lr >= nr_lrs ) - { - /* No more free LRs: find a lower priority irq to evict */ - list_for_each_entry_reverse( p_r, inflight_r, inflight ) - { - if ( p_r->priority == p->priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status) && - !test_bit(GIC_IRQ_GUEST_ACTIVE, &p_r->status) ) - goto found; - } - /* We didn't find a victim this time, and we won't next - * time, so quit */ - goto out; - -found: - lr = p_r->lr; - p_r->lr = GIC_INVALID_LR; - set_bit(GIC_IRQ_GUEST_QUEUED, &p_r->status); - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p_r->status); - gic_add_to_lr_pending(v, p_r); - inflight_r = &p_r->inflight; - } - - gic_set_lr(lr, p, GICH_LR_PENDING); - list_del_init(&p->lr_queue); - set_bit(lr, &this_cpu(lr_mask)); - - /* We can only evict nr_lrs entries */ - lrs--; - if ( lrs == 0 ) - break; - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); -} - -void gic_clear_pending_irqs(struct vcpu *v) -{ - struct pending_irq *p, *t; - - ASSERT(spin_is_locked(&v->arch.vgic.lock)); - - v->arch.lr_mask = 0; - list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) - gic_remove_from_lr_pending(v, p); -} - -int gic_events_need_delivery(void) -{ - struct vcpu *v = current; - struct pending_irq *p; - unsigned long flags; - const unsigned long apr = gic_hw_ops->read_apr(0); - int mask_priority; - int active_priority; - int rc = 0; - - mask_priority = gic_hw_ops->read_vmcr_priority(); - active_priority = find_next_bit(&apr, 32, 0); - - spin_lock_irqsave(&v->arch.vgic.lock, flags); - - /* TODO: We order the guest irqs by priority, but we don't change - * the priority of host irqs. */ - - /* find the first enabled non-active irq, the queue is already - * ordered by priority */ - list_for_each_entry( p, &v->arch.vgic.inflight_irqs, inflight ) - { - if ( GIC_PRI_TO_GUEST(p->priority) >= mask_priority ) - goto out; - if ( GIC_PRI_TO_GUEST(p->priority) >= active_priority ) - goto out; - if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - { - rc = 1; - goto out; - } - } - -out: - spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return rc; -} - -void gic_inject(void) -{ - ASSERT(!local_irq_is_enabled()); - - gic_restore_pending_irqs(current); - - if ( !list_empty(¤t->arch.vgic.lr_pending) && lr_all_full() ) - gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); -} - static void do_sgi(struct cpu_user_regs *regs, enum gic_sgi sgi) { /* Lower the priority */ From patchwork Wed Jan 24 18:10:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125696 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp581024ljf; Wed, 24 Jan 2018 10:13:40 -0800 (PST) X-Google-Smtp-Source: AH8x227ulauNAwrjexO81D9QS9UJzsRQk4EMPs00gvsih+qxDtp61fFi8khWf5Y6tYfUnBax4GSC X-Received: by 10.36.144.198 with SMTP id x189mr2097845itd.94.1516817620409; Wed, 24 Jan 2018 10:13:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817620; cv=none; d=google.com; s=arc-20160816; b=UOKKxLalRtrrH5pIBAJ6HkPRu6TAix508pF9O7UAUjdou5ea+GZfOZr1GS78/E0KsP JSAq/WMgvlHH9vZMs0/AgfgpOzYXNUiVSAS6FXVgUoQbpnbeyptwP1OOBCQC+hwZR1eD 1Vnu4OPriL2Cxi2KAArHqMAwMEH7jpjjRqgwxH/Fzin0nSd85Jt+20iacwGy3NOSUul8 VIxhRpwk87wR60SCqFseAKcc4wB5V4KlO5nrXJ2dMOLVSe3Aj8cbwvRrcSJE4QUMbXa3 bay8D5t3umfog8vOD0MKOkC+YQzoDaU1lExqdOi+47lsaj/iwnBw/aEcVxnbxCZbRH2W a+pw== ARC-Message-Signature: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:56 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:53 +0000 Message-Id: <20180124181058.6157-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 3/8] ARM: VGIC: split up gic_dump_info() to cover virtual part separately X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently gic_dump_info() not only dumps the hardware state of the GIC, but also the VGIC internal virtual IRQ lists. Split the latter off and move it into gic-vgic.c to observe the abstraction. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/domain.c | 1 + xen/arch/arm/gic-vgic.c | 11 +++++++++++ xen/arch/arm/gic.c | 12 ------------ xen/include/asm-arm/gic.h | 1 + 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a74ff1c07c..8d7f1b7138 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -941,6 +941,7 @@ long arch_do_vcpu_op(int cmd, struct vcpu *v, XEN_GUEST_HANDLE_PARAM(void) arg) void arch_dump_vcpu_info(struct vcpu *v) { gic_dump_info(v); + gic_dump_vgic_info(v); } void vcpu_mark_events_pending(struct vcpu *v) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 98df84e3d5..0a2958c5db 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -400,6 +400,17 @@ void gic_inject(void) gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct pending_irq *p; + + list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) + printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); + + list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) + printk("Pending irq=%d\n", p->irq); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 04e6d66b69..4cb74d449e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -443,20 +443,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r void gic_dump_info(struct vcpu *v) { - struct pending_irq *p; - printk("GICH_LRs (vcpu %d) mask=%"PRIx64"\n", v->vcpu_id, v->arch.lr_mask); gic_hw_ops->dump_state(v); - - list_for_each_entry ( p, &v->arch.vgic.inflight_irqs, inflight ) - { - printk("Inflight irq=%u lr=%u\n", p->irq, p->lr); - } - - list_for_each_entry( p, &v->arch.vgic.lr_pending, lr_queue ) - { - printk("Pending irq=%d\n", p->irq); - } } void init_maintenance_interrupt(void) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 587a14f8b9..b51b485c20 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -285,6 +285,7 @@ extern void send_SGI_allbutself(enum gic_sgi sgi); /* print useful debug info */ extern void gic_dump_info(struct vcpu *v); +extern void gic_dump_vgic_info(struct vcpu *v); /* Number of interrupt lines */ extern unsigned int gic_number_lines(void); From patchwork Wed Jan 24 18:10:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125691 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp580968ljf; Wed, 24 Jan 2018 10:13:35 -0800 (PST) X-Google-Smtp-Source: AH8x226iYjp2YlqPAk0ylRparMyae6zFLQd1q9lTBrdYtpNeobjH0GuPCMcLXFMI2jtG/lI1NC3V X-Received: by 10.107.158.211 with SMTP id h202mr9283024ioe.129.1516817615335; Wed, 24 Jan 2018 10:13:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817615; cv=none; d=google.com; s=arc-20160816; b=rR2z8efvIFChu18qQRqyAPJ+fBqLaZz/0fD6fnFM8/XZsIr9tmj2+sMnfuN1hukWwM v1X2J8dbDhbGvEyWhY1mTmBcyMkIfFhcGRO7hg+8FEED4+Ze++9sKOLPZX+VgbDLaAuf wzDU54Pan099SERaMeQr67dm4n5n5EWo/c1gFPFKv5xF58nViQ7z7mFTE96oWdOV9qGJ tT+4nQqNFxVWm0ZJrLKjBsz9k50jtgWdkMEocnCRBZxne42v7K8MNa6AuJlshgmsBuKI hb1QkL+s9dOxnu4IyPyEAR1s42PMv3dO/9NUKRcqVMlZrKYcMeZ/HjGmvRLY+wmPs1v8 PB6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=y5ktjJOtWPYWWuE5kkDxIRcwaIzR764pgG3fZeHlgKg=; b=ZFYJ3SOlBmnK6sq0tBCXjQpaCRJ1628uA/N7q6Abc28Uy7oJG2SVMDGXG4QTCZ7t+U DmzzcWt3r/MNEAktjwzP7cHk8sJsMONWnvaVLwZF+fN31r9g2TPgFsFXNzp4Gj4msvF6 agwY0McQDgMSErRBkI6PvwghuxaVZM9C5GIL1ct9sSnxtEDgXVInURHrd901OXanc8sl QnQSKED9tjNi6QFqdifrT8tAfx8vIN+brE44n5XcB5xphECU8Tsz8w83W/q3GiBxoE5C Qm5XsCW88zcMPihrh+b8tdoJQydoUrIv6zD7W5CiZy9HTd8DIMIx8s0is+jNmSrb5RR1 uGkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ObyiaqhW; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:57 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:54 +0000 Message-Id: <20180124181058.6157-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 4/8] ARM: VGIC: rework events_need_delivery() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" In event.h we very deeply dive into the VGIC to learn if an event for a guest is pending. Rework that function to abstract the VGIC specific part out. Also reorder the queries there, as we only actually need to check for the event channel if there are no other pending IRQs. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/vgic.c | 11 +++++++++++ xen/include/asm-arm/event.h | 13 +++---------- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 6e933a86d3..9921769b15 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -593,6 +593,17 @@ void arch_evtchn_inject(struct vcpu *v) vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); } +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct pending_irq *p; + + p = irq_to_pending(v, v->domain->arch.evtchn_irq); + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + return list_empty(&p->inflight); +} + bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) { struct vcpu *v = current; diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index caefa506a9..67684e9763 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -16,12 +16,6 @@ static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) static inline int local_events_need_delivery_nomask(void) { - struct pending_irq *p = irq_to_pending(current, - current->domain->arch.evtchn_irq); - - /* Does not work for LPIs. */ - ASSERT(!is_lpi(current->domain->arch.evtchn_irq)); - /* XXX: if the first interrupt has already been delivered, we should * check whether any other interrupts with priority higher than the * one in GICV_IAR are in the lr_pending queue or in the LR @@ -33,11 +27,10 @@ static inline int local_events_need_delivery_nomask(void) if ( gic_events_need_delivery() ) return 1; - if ( vcpu_info(current, evtchn_upcall_pending) && - list_empty(&p->inflight) ) - return 1; + if ( !vcpu_info(current, evtchn_upcall_pending) ) + return 0; - return 0; + return vgic_evtchn_irq_pending(current); } static inline int local_events_need_delivery(void) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 2a93a7bef9..22c8502c95 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -218,6 +218,8 @@ extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); +bool vgic_evtchn_irq_pending(struct vcpu *v); + extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, From patchwork Wed Jan 24 18:10:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125695 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp581009ljf; Wed, 24 Jan 2018 10:13:39 -0800 (PST) X-Google-Smtp-Source: AH8x227Nif64vESL4l5ASTQRBHSzDUW3QVCSnla6SzDykTZlgEhs6VGnVRxvcoshYJrzcl+OmxYy X-Received: by 10.36.23.140 with SMTP id 134mr9708465ith.1.1516817619506; Wed, 24 Jan 2018 10:13:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817619; cv=none; d=google.com; s=arc-20160816; b=A//+kVb5CN4dJIsFC18CUaN+8od50FgfGbMO/C4R2wmIAaHeIgSZZ0tMvEDUDDMZkU sG48euDHx282MVEEgwPstRfmtfsK30R/Mh6uZzvXOpCjxRvCTuwEWyhjpB+QCGuBKYi6 zRR8d/4fX5XUdviA1AKQIFofW1OOB1T1GVLNUqbJ8pdpl+JnstDgjd6wlNgn/85UuY6q w3PYCycWDGYoXwoK5KNnHF9olnDqJWz7nvhrjryH/2+uTizSw6FcuWAP1nUUFLmH9pEa XREoGhGSBOfc6ccebQojyLCj3jDRS9gIBW7C9qpYK/usp7drwVzlWqqRNxBICe4mTNYO mGOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=25zqqhxj32ALlkF4BQTbo4KpB9zfAPrVScSO23B+k7g=; b=ZoI84zSNm+s5o6K30ttkAQycsVwq+qKspISQDalD8o/mOmtqypeSPJEj++y3CczMZk ercvTdxvJeeIavBxwC4MFUBw5LjHV+bVHiFfWgPfsUqTxwn3s0PudptlzcEDkoZxZ4oS fpKznE9aOI2oNerpRUp5R+XCeZfFURF+m3Uj7xy9Zko/dadya6RuhX//lpAObCSpZhEr FMY5j5vOJ5v9awG4SfrRze9K1FcGdCdzNWPXfiLNpJZjShzxB77fr+dCc304DLGDmeiJ T1qHntGSIaJo5Rfa+VULPY1x3Hku76wR2nkNPlG0raO0KSdaqicBFq3pzx7Xm6eRfXk9 O8Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=AbbNrLK1; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:58 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:55 +0000 Message-Id: <20180124181058.6157-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 5/8] ARM: VGIC: factor out vgic_connect_hw_irq() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access VGIC internal data structures like the rank and struct pending_irq in gic.c, which should be VGIC agnostic. Factor out a new function vgic_connect_hw_irq(), which allows a virtual IRQ to be connected to a hardware IRQ (using the hw bit in the LR). This removes said accesses to VGIC data structures and improves abstraction. Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini --- xen/arch/arm/gic-vgic.c | 31 +++++++++++++++++++++++++++++++ xen/arch/arm/gic.c | 42 ++++++------------------------------------ xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 39 insertions(+), 36 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 0a2958c5db..d44e4dacd3 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -411,6 +411,37 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc) +{ + unsigned long flags; + /* Use vcpu0 to retrieve the pending_irq struct. Given that we only + * route SPIs to guests, it doesn't make any difference. */ + struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); + struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); + struct pending_irq *p = irq_to_pending(v_target, virq); + int ret = 0; + + /* We are taking to rank lock to prevent parallel connections. */ + vgic_lock_rank(v_target, rank, flags); + + if ( desc ) + { + /* The VIRQ should not be already enabled by the guest */ + if ( !p->desc && + !test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) + p->desc = desc; + else + ret = -EBUSY; + } + else + p->desc = NULL; + + vgic_unlock_rank(v_target, rank, flags); + + return ret; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 4cb74d449e..d46a6d54b3 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -128,27 +128,12 @@ void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority) int gic_route_irq_to_guest(struct domain *d, unsigned int virq, struct irq_desc *desc, unsigned int priority) { - unsigned long flags; - /* Use vcpu0 to retrieve the pending_irq struct. Given that we only - * route SPIs to guests, it doesn't make any difference. */ - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - int res = -EBUSY; - ASSERT(spin_is_locked(&desc->lock)); /* Caller has already checked that the IRQ is an SPI */ ASSERT(virq >= 32); ASSERT(virq < vgic_num_irqs(d)); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - - if ( p->desc || - /* The VIRQ should not be already enabled by the guest */ - test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) ) - goto out; - desc->handler = gic_hw_ops->gic_guest_irq_type; set_bit(_IRQ_GUEST, &desc->status); @@ -156,31 +141,19 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int virq, gic_set_irq_type(desc, desc->arch.type); gic_set_irq_priority(desc, priority); - p->desc = desc; - res = 0; - -out: - vgic_unlock_rank(v_target, rank, flags); - - return res; + return vgic_connect_hw_irq(d, NULL, virq, desc); } /* This function only works with SPIs for now */ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, struct irq_desc *desc) { - struct vcpu *v_target = vgic_get_target_vcpu(d->vcpu[0], virq); - struct vgic_irq_rank *rank = vgic_rank_irq(v_target, virq); - struct pending_irq *p = irq_to_pending(v_target, virq); - unsigned long flags; + int ret; ASSERT(spin_is_locked(&desc->lock)); ASSERT(test_bit(_IRQ_GUEST, &desc->status)); - ASSERT(p->desc == desc); ASSERT(!is_lpi(virq)); - vgic_lock_rank(v_target, rank, flags); - if ( d->is_dying ) { desc->handler->shutdown(desc); @@ -198,19 +171,16 @@ int gic_remove_irq_from_guest(struct domain *d, unsigned int virq, */ if ( test_bit(_IRQ_INPROGRESS, &desc->status) || !test_bit(_IRQ_DISABLED, &desc->status) ) - { - vgic_unlock_rank(v_target, rank, flags); return -EBUSY; - } } + ret = vgic_connect_hw_irq(d, NULL, virq, NULL); + if ( ret ) + return ret; + clear_bit(_IRQ_GUEST, &desc->status); desc->handler = &no_irq_type; - p->desc = NULL; - - vgic_unlock_rank(v_target, rank, flags); - return 0; } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 22c8502c95..f4240df371 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc); extern int domain_vgic_register(struct domain *d, int *mmio_count); extern int vcpu_vgic_free(struct vcpu *v); From patchwork Wed Jan 24 18:10:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125693 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp580988ljf; Wed, 24 Jan 2018 10:13:37 -0800 (PST) X-Google-Smtp-Source: AH8x226sZBD3jpM4R4/oQjHEbuTFJ27XzKe3phzWmFYxSS5H0yPwaX6N4wH5o+piNsXpro+VCjKn X-Received: by 10.36.122.79 with SMTP id a76mr9933647itc.36.1516817617316; Wed, 24 Jan 2018 10:13:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817617; cv=none; d=google.com; s=arc-20160816; b=rsy/vpilTrrma1gZc+CaUgnJou8cQgAKHGs+aK/zwnlcB3U/QwRrWsiAZtr4HoxFVy nM+RaWVU/OLCMEre6H0XcmQG00gdIvI4dMeuFd9mhmbCclfgXfEu4IOjrVVv//MoVr8J 3sn6fQi/95WRQ67RZRAXXSiRTtZVQc09zNoVZegp3Z+kwWxonbpMi0FOocZgyQ1BKwT8 2jbcl7pOrn+RkwxuYnDgiuSN6EGfZUJbtLqKWMFhRJ3dks17yn3zrW1HwKE+RzezMtyi rn2eGh5DuxYk1yqFrOj7ml9wF0Bb2Pf6+3yfTBpAFWWABoST0AhXyaqdCyRPh41U94sD dsvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=xhecCOAnTw847wCUvSeyPYCRhvP/eFEh8xa52OxtnSE=; b=nv6vw3MMIZPgjQyXmIjND1Wx/OcDUHydI1bWlo0c5tE+mSznJ320Z9qnxuP/Mq3vh+ +cYvZ5rN3H8ltQgnTWihUmBFTlI2BhbzA6VdFpsXsa70Lzmc3YdGx7Oc6i4q6SOtU0sB 4OJrtgEn4o7qmxqGMgRynppAn9ucHybjcp7QfjOXvovbX+ogJzmgrs+hkSKmVTYuPj2k 5BOitu21acIO5s5iOer8JIK5jDtTyPUerOT6OLvIhKWgw5Wc25dMExB6DG2v9ndYLz9M Jbsae+odOkEfu98yrifeudw6qZYl3Zvre85gZqdc+q9gn50Z/5N9gvC80XIVQjS20BMy LKYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EqXrlxJx; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:10:59 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:56 +0000 Message-Id: <20180124181058.6157-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 6/8] ARM: VGIC: factor out vgic_get_hw_irq_desc() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we happily access the VGIC internal struct pending_irq (which describes a virtual IRQ) in irq.c. Factor out the actually needed functionality to learn the associated hardware IRQ and move that into gic-vgic.c to improve abstraction. Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini --- xen/arch/arm/gic-vgic.c | 15 +++++++++++++++ xen/arch/arm/irq.c | 7 ++----- xen/include/asm-arm/vgic.h | 2 ++ 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d44e4dacd3..3ad98dcd3a 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -411,6 +411,21 @@ void gic_dump_vgic_info(struct vcpu *v) printk("Pending irq=%d\n", p->irq); } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct pending_irq *p; + + if ( !v ) + v = d->vcpu[0]; + + p = irq_to_pending(v, virq); + if ( !p ) + return NULL; + + return p->desc; +} + int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc) { diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 7f133de549..62103a20e3 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -534,19 +534,16 @@ int release_guest_irq(struct domain *d, unsigned int virq) struct irq_desc *desc; struct irq_guest *info; unsigned long flags; - struct pending_irq *p; int ret; /* Only SPIs are supported */ if ( virq < NR_LOCAL_IRQS || virq >= vgic_num_irqs(d) ) return -EINVAL; - p = spi_to_pending(d, virq); - if ( !p->desc ) + desc = vgic_get_hw_irq_desc(d, NULL, virq); + if ( !desc ) return -EINVAL; - desc = p->desc; - spin_lock_irqsave(&desc->lock, flags); ret = -EINVAL; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index f4240df371..ebc0cfaee8 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -219,6 +219,8 @@ int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); bool vgic_evtchn_irq_pending(struct vcpu *v); +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq); int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, struct irq_desc *desc); From patchwork Wed Jan 24 18:10:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125694 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp581001ljf; Wed, 24 Jan 2018 10:13:38 -0800 (PST) X-Google-Smtp-Source: AH8x224EEIW6JqUUxJ4UBgjL9h1lJzexOse9xBSv55wBZq8+pbko6KSCfX8QtMkcyh4VaMufni6n X-Received: by 10.107.141.147 with SMTP id p141mr9274675iod.79.1516817618771; Wed, 24 Jan 2018 10:13:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817618; cv=none; d=google.com; s=arc-20160816; b=UyWIDfzvK2fitWBqiaxdQBAdsWCJFuPWYkWj9lYpxEhhTdQNwKv0vkFSzGWyibceqO PcHYm0YsoYlQlSHDbPbhqCdZ7G3WV4GHzN4IY/NiZJHtI+iA9NsKONt1i9oIviTDHary DyuQt11Onklb8f92JrH4sxuTjqle3gCAZMeFbKJ97GiQRPZX10Z2gNYskwPpjx3XIndB jAaNkCBWoUjn8y5SdYrniph01R3LJ9OvKFtLeakNVY1e6AK4o2gzf5ZCQlg4TKemoTs7 Hd+jfFOUZDyl3eIDgI/IOM2ZiqEPJPVaS3jUuGs1ReNb4ymM0K2UNesBG58qf8jof5Ap UTSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=Iw7ZJwLR8SXwlxYevOn56fwm6VskNwGcSXdGiO6lxOU=; b=FuEF2tsrvuR4M6AisILxoEnwUTzj2ReX9/lgS1RXIUVzTb0XscCwzEsKwi6Mffhfhx lqAFHDVi6bUaHY36NnkHD4PONftbOLGS959QcGfDDjf73czcW1i7rQyBUqzFtCD5XhRk 1q1AuXURuZOx8Z36xR+WEzXNkkZ9LAIjWPCFQWXlM7125HPwLu/tFYHXdns6NqIoPdiT jd5MBWEIgf6xP8of9ZlpJbdgl+JeBxg3V440wiwFUYKQIlZuA6l9598yOhY1RTZJGExO EBVNROxNgXtHE1KwhREOQac3YMSzxI959rXQaoujfpihsqil3LHhmRlXZDfMENi0i/Vd Z1WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jGf+3dek; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.10.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:11:00 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:57 +0000 Message-Id: <20180124181058.6157-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 7/8] ARM: VGIC: rework gicv[23]_update_lr to not use pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The functions to actually populate a list register were accessing the VGIC internal pending_irq struct, although they should be abstracting from that. Break the needed information down to remove the reference to pending_irq from gic-v[23].c. Signed-off-by: Andre Przywara Reviewed-by: Stefano Stabellini --- xen/arch/arm/gic-v2.c | 14 +++++++------- xen/arch/arm/gic-v3.c | 12 ++++++------ xen/arch/arm/gic-vgic.c | 3 ++- xen/include/asm-arm/gic.h | 4 ++-- xen/include/asm-arm/irq.h | 3 +++ 5 files changed, 20 insertions(+), 16 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 511c8d7294..2b271ba322 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -428,8 +428,8 @@ static void gicv2_disable_interface(void) spin_unlock(&gicv2.lock); } -static void gicv2_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv2_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint32_t lr_reg; @@ -437,12 +437,12 @@ static void gicv2_update_lr(int lr, const struct pending_irq *p, BUG_ON(lr < 0); lr_reg = (((state & GICH_V2_LR_STATE_MASK) << GICH_V2_LR_STATE_SHIFT) | - ((GIC_PRI_TO_GUEST(p->priority) & GICH_V2_LR_PRIORITY_MASK) - << GICH_V2_LR_PRIORITY_SHIFT) | - ((p->irq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); + ((GIC_PRI_TO_GUEST(priority) & GICH_V2_LR_PRIORITY_MASK) + << GICH_V2_LR_PRIORITY_SHIFT) | + ((virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT)); - if ( p->desc != NULL ) - lr_reg |= GICH_V2_LR_HW | ((p->desc->irq & GICH_V2_LR_PHYSICAL_MASK ) + if ( hw_irq != INVALID_IRQ ) + lr_reg |= GICH_V2_LR_HW | ((hw_irq & GICH_V2_LR_PHYSICAL_MASK ) << GICH_V2_LR_PHYSICAL_SHIFT); writel_gich(lr_reg, GICH_LR + lr * 4); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index a0d290b55c..9ecb62b113 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -966,8 +966,8 @@ static void gicv3_disable_interface(void) spin_unlock(&gicv3.lock); } -static void gicv3_update_lr(int lr, const struct pending_irq *p, - unsigned int state) +static void gicv3_update_lr(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state) { uint64_t val = 0; @@ -983,11 +983,11 @@ static void gicv3_update_lr(int lr, const struct pending_irq *p, if ( current->domain->arch.vgic.version == GIC_V3 ) val |= GICH_LR_GRP1; - val |= ((uint64_t)p->priority & 0xff) << GICH_LR_PRIORITY_SHIFT; - val |= ((uint64_t)p->irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; + val |= (uint64_t)priority << GICH_LR_PRIORITY_SHIFT; + val |= ((uint64_t)virq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT; - if ( p->desc != NULL ) - val |= GICH_LR_HW | (((uint64_t)p->desc->irq & GICH_LR_PHYSICAL_MASK) + if ( hw_irq != INVALID_IRQ ) + val |= GICH_LR_HW | (((uint64_t)hw_irq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT); gicv3_ich_write_lr(lr, val); diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index 3ad98dcd3a..319617babe 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -52,7 +52,8 @@ static inline void gic_set_lr(int lr, struct pending_irq *p, clear_bit(GIC_IRQ_GUEST_PRISTINE_LPI, &p->status); - gic_hw_ops->update_lr(lr, p, state); + gic_hw_ops->update_lr(lr, p->irq, p->priority, + p->desc ? p->desc->irq : INVALID_IRQ, state); set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index b51b485c20..30e62c37ec 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -342,8 +342,8 @@ struct gic_hw_operations { /* Disable CPU physical and virtual interfaces */ void (*disable_interface)(void); /* Update LR register with state and priority */ - void (*update_lr)(int lr, const struct pending_irq *pending_irq, - unsigned int state); + void (*update_lr)(int lr, unsigned int virq, uint8_t priority, + unsigned int hw_irq, unsigned int state); /* Update HCR status register */ void (*update_hcr_status)(uint32_t flag, bool set); /* Clear LR register */ diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index abc8f06a13..0d110ecb08 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -31,6 +31,9 @@ struct arch_irq_desc { /* LPIs are always numbered starting at 8192, so 0 is a good invalid case. */ #define INVALID_LPI 0 +/* This is a spurious interrupt ID which never makes it into the GIC code. */ +#define INVALID_IRQ 1023 + extern unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS From patchwork Wed Jan 24 18:10:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 125699 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp581317ljf; Wed, 24 Jan 2018 10:14:18 -0800 (PST) X-Google-Smtp-Source: AH8x2271nvPfvAX1FrXsIm0fv9Hh1Kl1ItoadgW6LSwXX3ruyNoIpMunt98Azv8WLS/c2DqZ7Ikf X-Received: by 10.36.230.3 with SMTP id e3mr9363192ith.99.1516817658016; Wed, 24 Jan 2018 10:14:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516817658; cv=none; d=google.com; s=arc-20160816; b=zJ8nUDrgZHWY5nvdj0qRnaaksQtVS+SQ6GpmDLD8QLLIPB4voG2sGrJ/K+bpKSJRxW W+iv8rxr3nfthtlAVqzuaglZadhSvRCwztmpCgHFAxggwBZs/DFJrYZbH/x1aFb4aNh3 1Yx/K25aDzAPiqx6W1Gmn7qrl9ntsIMKVcmUVDTL09VHN4b3ye+batS0WAM/QwD+CKPz iDlAfy5GOi5mrDalJcDEoBb0sZl8J1kYqAdUcP9+KeR8SoeT35RlVau98BM1jDi5+fpB nLaVia+izV1l+xmXM/vffVkK9SjATbY7MMbih1BpZqCsirT4GSVYmyYfvWDzx1yQYGsb d8rQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:dkim-signature:arc-authentication-results; bh=glT/3Sev27juvX3wYqWMDDsnIrFi2KkkXa0pRhUQkug=; b=LfioJ9ag69Bda9luk47qA/mCuVMmRjOoc6H+qCB0GRta0t1hnzEQnHAC+luQVx0Q02 TcqabPc0FqvLri0s3lNimt1iSngOHhKLhB8tfhSFiWgpLQsdgcy/A9m5g9Ui0mQMT0Ka 6XrSNW4kSMf9804zgMZ78dUeIfjtoR62Maxh9//bEpHPULbcojANYVvx655PJu6m4FRV /+hZSf4bVCiytUlrcdXUXaT5L/g/WAg7cpApiuEYxQXrl7EM/F06hJUpCgWMR+CUMjYm iWnIKD444Y2ojjJ2/rLNlnBJKyVauh0Erh1xTDMdhUFShMSLnpQyF9M43ALun8CNFE/6 mWIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ki/zzG60; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id r68sm899379wmd.47.2018.01.24.10.11.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Jan 2018 10:11:01 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 24 Jan 2018 18:10:58 +0000 Message-Id: <20180124181058.6157-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180124181058.6157-1-andre.przywara@linaro.org> References: <20180124181058.6157-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH v3 8/8] ARM: make nr_irqs a constant X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" On ARM the maximum number of IRQs is a constant, but we share it being a variable to match x86. Since we are not supposed to alter it, let's mark it as "const" to avoid accidental change. Suggested-by: Julien Grall Signed-off-by: Andre Przywara Acked-by: Julien Grall --- xen/arch/arm/irq.c | 2 +- xen/include/asm-arm/irq.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 62103a20e3..d229cb6871 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -27,7 +27,7 @@ #include #include -unsigned int __read_mostly nr_irqs = NR_IRQS; +const unsigned int __read_mostly nr_irqs = NR_IRQS; static unsigned int local_irqs_type[NR_LOCAL_IRQS]; static DEFINE_SPINLOCK(local_irqs_type_lock); diff --git a/xen/include/asm-arm/irq.h b/xen/include/asm-arm/irq.h index 0d110ecb08..9d55e9b122 100644 --- a/xen/include/asm-arm/irq.h +++ b/xen/include/asm-arm/irq.h @@ -34,7 +34,7 @@ struct arch_irq_desc { /* This is a spurious interrupt ID which never makes it into the GIC code. */ #define INVALID_IRQ 1023 -extern unsigned int nr_irqs; +extern const unsigned int nr_irqs; #define nr_static_irqs NR_IRQS #define arch_hwdom_irqs(domid) NR_IRQS