From patchwork Thu Jan 25 12:27:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125823 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1078908ljf; Thu, 25 Jan 2018 04:27:49 -0800 (PST) X-Google-Smtp-Source: AH8x226xM4ozDQuhJy3vmTkvEXgm/eI5SYHMz8h2j6MlyVPYnByLeba4y5AlkBfCeRhpT2e1Jspy X-Received: by 10.101.91.66 with SMTP id y2mr13614827pgr.11.1516883269421; Thu, 25 Jan 2018 04:27:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883269; cv=none; d=google.com; s=arc-20160816; b=VgTV02Uz7AlBU/3bKpo+M1sbm5/QpXZm6yPA4HYC0+j1luBgV+ldXR9N3BAPqmNvdo okv0aF8M9+4TnN63duRVT65h1fUOCL8KLlXXbLUYHN1WKRO/6SoWfGLVuNnFlofPYbeH CJu0RXM083AdnGWsolvWILHHfFgpZzcVxON4vqxessadLSq5wtAz4SgVEmVJ5ptIxePc uELmWBFe99URQwESRJcCWe+OGLh5Z9Vecsg7WUbpmxgpR30IC4wgRERPYusI//mtDyzG YscwkW9txWlf0gOQ0AQE+mr16+Dz2cVMn1hO36I0N9SI/l1B4tPFPgqfbvjf9dj5wFVG +mWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=tROagzFp7r42nmM+iMd7VIFb2s3y+VW4spc+nkHQx6c=; b=DV7A00WvC3DF5zbz9XgnnklORAmQtZL0fU78Qot7BtXPengcxyKX2yp0FLnHi0mxvL nuOXX1Q2BCCA26tKF8ljH9HqZgZlDfwlHQKpMiFGzbvCljwbsTiTCS0SCwbZ3IIjEsWg 59vqjhoQX8nJUinu9tZr2rGcFelU1gc4ZJWhvkli2bd9hGPKIYQywjTaV6rJmhxCEvEy oWyq4jtU9KGgw4IYvlNqjZ3PD0rFrBVbzLOH3U1fZb5pxRaPxvv42vnxFfTtPSczbzwK DpuyVGZqB8AYTiShG3zoThSwEhF25eGweLLiNhb1GIDHjafNjEC250zDyxcwIkDsXdO1 WcWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TC1ka7sy; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id p11si4549624pfl.272.2018.01.25.04.27.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TC1ka7sy; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4668F222A337A; Thu, 25 Jan 2018 04:22:19 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CA458222A3348 for ; Thu, 25 Jan 2018 04:22:17 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id f71so14287234wmf.0 for ; Thu, 25 Jan 2018 04:27:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EdvE6GL7G1yfSByioV73p5dEQEERz0ddDEdPTQg9Nrk=; b=TC1ka7syAXhpBnAinwf70dL2VsajAGeh1Go66W6AqtuMHf3oXVyWMzG3OQr0UWkruB bdE98UhR9VuratyNQ9Xpr33m+bEFBw7mzuEHmVA7FbGLaumywJjD5RMuI3lbJZ3REG4o yYTZJaULXy30KouMSx8IcUoI/IF2lJghiU9MU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EdvE6GL7G1yfSByioV73p5dEQEERz0ddDEdPTQg9Nrk=; b=KoWnbM10SKt3bvM0epnRKjnumEAfsBErVCNM2qKP7IWjRAWKd1vmPQX1fvrkmZVY6u Esu5SOVzoBx4VsFpJPWzc6S2CzD5zqHJ2RJvjuS4RT7DLWYxuFYJwpf8oUUhagkqkqx6 iLyXtUT+t6Idg5gmGdXAeBZGhRa6pQyYVIuJQ5101oe7o1lVO4yOLGu+cTEbduRRxy7g UPTv/lSJWg3gQTv669gPYfmOnTwVBmvhQWhNhiXuEvZAPjMfelcpcKyQ0e52SH6yCIID O3GjBYE8Q0DwCzFxOsz6fV1dGsfcL476mRFhG+q6+RfllXuEVX87SBEk/rRvvaa7bmoT BQWw== X-Gm-Message-State: AKwxytc3Pnk3hUGHzJwR+a5j0WcmRCFBNozcDJh4945zF0Duc19KaWiM KmEsRmTMqJDVJTyQ5KlDHY7jj1vaP/U= X-Received: by 10.28.154.67 with SMTP id c64mr7987002wme.125.1516883265610; Thu, 25 Jan 2018 04:27:45 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:44 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:29 +0000 Message-Id: <20180125122736.5427-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/8] Silicon/SynQuacer/PlatformDxe: enable spread spectrum mode for ASM1061 SATA X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The ASM1061 SATA controller integrated into the DeveloperBox board emits too much electromagnetic radiation, so it needs spread spectrum mode enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/{Asmedia118x.c => Pci.c} | 83 +++++++++++++++----- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 +- 2 files changed, 64 insertions(+), 21 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c similarity index 64% rename from Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c rename to Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index 874e83a649b5..9af3dd942cdd 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Asmedia118x.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -15,9 +15,12 @@ #include "PlatformDxe.h" #define ASMEDIA_VID 0x1b21 +#define ASM1061_PID 0x0612 #define ASM1182E_PID 0x1182 #define ASM1184E_PID 0x1184 +#define ASM1061_SSC_OFFSET 0xA10 + #define ASM118x_PCIE_CAPABILITY_OFFSET 0x80 #define ASM118x_PCIE_LINK_CONTROL_OFFSET (ASM118x_PCIE_CAPABILITY_OFFSET + \ OFFSET_OF (PCI_CAPABILITY_PCIEXP, \ @@ -39,24 +42,10 @@ RetrainAsm1184eDownstreamPort ( IN EFI_PCI_IO_PROTOCOL *PciIo ) { - UINT16 PciVidPid[2]; EFI_STATUS Status; PCIE_CAP Cap; PCI_REG_PCIE_LINK_CONTROL LinkControl; - Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, - ARRAY_SIZE (PciVidPid), &PciVidPid); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", - __FUNCTION__, Status)); - return; - } - - if (PciVidPid[0] != ASMEDIA_VID || - (PciVidPid[1] != ASM1182E_PID && PciVidPid[1] != ASM1184E_PID)) { - return; - } - // // The upstream and downstream ports share the same PID/VID, so check // the port type. This assumes the PCIe Express capability block lives @@ -91,6 +80,34 @@ RetrainAsm1184eDownstreamPort ( STATIC VOID +EnableAsm1061SpreadSpectrum ( + IN EFI_PCI_IO_PROTOCOL *PciIo + ) +{ + EFI_STATUS Status; + UINT8 SscVal; + + DEBUG ((DEBUG_INFO, "%a: enabling spread spectrum mode 0 for ASM1061\n", + __FUNCTION__)); + + // SSC mode 0~-4000 ppm, 1:1 modulation + + SscVal = 0; + Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); + + MemoryFence (); + gBS->Stall (1); // delay at least 100 ns between writes of the same register + + SscVal = 1; + Status = PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, ASM1061_SSC_OFFSET, 1, + &SscVal); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID EFIAPI OnPciIoProtocolNotify ( IN EFI_EVENT Event, @@ -101,6 +118,7 @@ OnPciIoProtocolNotify ( EFI_STATUS Status; EFI_HANDLE HandleBuffer; UINTN BufferSize; + UINT16 PciVidPid[2]; while (TRUE) { BufferSize = sizeof (EFI_HANDLE); @@ -114,12 +132,37 @@ OnPciIoProtocolNotify ( (VOID **)&PciIo); ASSERT_EFI_ERROR (Status); - // - // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its - // 2-port sibling of which samples were used in development) needs a - // little nudge to get it to train the downstream links at Gen2 speed. - // - RetrainAsm1184eDownstreamPort (PciIo); + Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, PCI_VENDOR_ID_OFFSET, + ARRAY_SIZE (PciVidPid), &PciVidPid); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to read PCI vendor/product ID - %r\n", + __FUNCTION__, Status)); + continue; + } + + if (PciVidPid[0] != ASMEDIA_VID) { + continue; + } + + switch (PciVidPid[1]) { + case ASM1061_PID: + // + // The ASM1061 SATA controller as integrated into the DeveloperBox design + // emits too much electromagnetic radiation. So enable spread spectrum + // mode. + // + EnableAsm1061SpreadSpectrum (PciIo); + break; + case ASM1182E_PID: + case ASM1184E_PID: + // + // The ASM1184E 4-port PCIe switch on the DeveloperBox board (and its + // 2-port sibling of which samples were used in development) needs a + // little nudge to get it to train the downstream links at Gen2 speed. + // + RetrainAsm1184eDownstreamPort (PciIo); + break; + } } } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 7d3b88a5b52e..766f4041c826 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -23,7 +23,7 @@ [Defines] ENTRY_POINT = PlatformDxeEntryPoint [Sources] - Asmedia118x.c + Pci.c PlatformDxe.c [Packages] From patchwork Thu Jan 25 12:27:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125824 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1078930ljf; Thu, 25 Jan 2018 04:27:51 -0800 (PST) X-Google-Smtp-Source: AH8x227aYqMV6qWuz+LC4B0NorXR1WsXWWlPh+6cxPS5J1ME3IrgWnVN1lZH665oH8OmPfKLmHfM X-Received: by 10.99.111.10 with SMTP id k10mr13319366pgc.421.1516883271847; Thu, 25 Jan 2018 04:27:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883271; cv=none; d=google.com; s=arc-20160816; b=iScOSW9BJpbUC2Uz91KdZ8Io9j+Z8ZnxNdoyplmJJdPMqcQnmVKeYNWtwpHym7Iszy swgm0Ve3JdKkjWCin9GuffSZz5xNygRg9godfOBZzjQggzGr7FF9+lc8iRh+XJdcvD7s hZOCzvq+yjHpMEPFL6StrP4lGLlnWEtWFLbYABAV5tRkhTXgtbcZ2tGnPQYFKYuMlAzK nOjPcKmx6ZuNicvacpunSpdrtJ7Ko7twdWgPGFjXmK9HV3Df3tx90c665s7DmOL3Y8BJ YhrC2CPpIKCCnxQK3nUDNgBoJin4TZB0sJEJOXboX3JXJVkSCW/Zk64uTR40j1YK6lUr Ey2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=0oOu12b+EA6EYHI1y55LOYp3m03ZGtPSSXG6KfdtpoQ=; b=SE44GCHjpy0SEhJmkQy04697NjxnNA5oGeQfaT9PnXQ1G98+y5S8GS86cVsF+Nk8jc as1VbvKZAQoqtZZYADz+MUFbDBj62fKCN4uCmABuAU7jRutr0j4x0ydkC0SBFzHs0lDe ghYVzg59JkWPJEtockCWAu3BhJnKMMM6i8mSuVkBO89Fl8M/7qNVdEI41P6Cc+X1zjj9 1Px0IfmXSdVUwW9cd0RgpvGqmt2Pq+vol3UiLiQ3onoOGlqfvxLC1JxD/pt8yBQIaRXI oI9c2MPewwjCzdfpRDMAgAF7ipjcbV/5+s1LLwKOKTYleDGhQQvgeydjOtVU7P+NDg3R j+mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bsx3hm9I; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id c8-v6si1971321pli.19.2018.01.25.04.27.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bsx3hm9I; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B14A0222A337C; Thu, 25 Jan 2018 04:22:21 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8D4B4222A337C for ; Thu, 25 Jan 2018 04:22:19 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id r78so14627049wme.0 for ; Thu, 25 Jan 2018 04:27:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X/xNVgMJvcVN5+bQMF7p4ydDnTMNg4KvabrvZNklBYs=; b=bsx3hm9IubmCHC2JXfOmrIjkPGqsapZ/db4jHc8zTLt9ZMqb/8x2MD1TTWUvgBBEmG CKi2wD6TTHkco3+6PddHeECBoN1Aq9PbafjnzsooVnQfQYLARj+CS+RNlOGKOWAYTyJj lleZ94FFdjQxAUk/XwMLYF0/rQ6hPrHlhF8Pw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X/xNVgMJvcVN5+bQMF7p4ydDnTMNg4KvabrvZNklBYs=; b=RDsFPJHeH3WyBHaLQxRi5Gw6V5QAmQpOMWuU7rFM53ACOgef35itBGn8TUqTWhciv3 Amj3L3reLhdCZftwhVGD5RV6yKPjNw/csAVVwAbo+4I72fylYjsIKRNr5KbeDsIcKFKn HiHB+MisGpnRUN4p+7N2ONj2UEVtLGDYQiv03dI3knUCmgr1iBKBTY8BUy1RzvJj6PWn FwWWewbKPT0o7Mov99KikN17eiR0wHz/w8yvn7z3D1qEbeRjPZqUE+2cw9V2NIGjNxO1 skSaHoPjUjmf1OAG0TdXPXtqXF5PWMa1hZtoT5BjBeWZ71JA1f0xLzaTxp2BJIjj8OEv Y1XA== X-Gm-Message-State: AKwxytemaWAXMs2vTwSnEbQgEkx/PNUm6Elt4vouEYLJUPJ/kv6cwq8k LrlIBHrYElFPIe/xTtROaQUqp4Ji4oE= X-Received: by 10.28.38.133 with SMTP id m127mr7102109wmm.40.1516883267206; Thu, 25 Jan 2018 04:27:47 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:46 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:30 +0000 Message-Id: <20180125122736.5427-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/8] Silicon: fix typo in gPcf8563RealTimeClockLibI2cMasterProtocolGuid X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Do a global replace of gPcf8563RealTimeClockLibI2cMasterProtolGuid with gPcf8563RealTimeClockLibI2cMasterProtocolGuid. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 2 +- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 2 +- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 4 ++-- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 2 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c index 67f8e7de4025..6bc4aef28849 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c @@ -373,7 +373,7 @@ LibRtcInitialize ( // BufferSize = sizeof (EFI_HANDLE); Status = gBS->LocateHandle (ByProtocol, - &gPcf8563RealTimeClockLibI2cMasterProtolGuid, NULL, + &gPcf8563RealTimeClockLibI2cMasterProtocolGuid, NULL, &BufferSize, &mI2cMasterHandle); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec index 3849056f164a..94c4a3f1ef4c 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec @@ -22,7 +22,7 @@ [Guids] gPcf8563RealTimeClockLibTokenSpaceGuid = { 0xaaf5b169, 0x93a0, 0x4d60, { 0xba, 0xe4, 0x06, 0x07, 0x92, 0x8e, 0x63, 0xdd }} [Protocols] - gPcf8563RealTimeClockLibI2cMasterProtolGuid = { 0xa6af18ae, 0x3bd5, 0x4af9, { 0xbb, 0x6a, 0xdb, 0x85, 0x07, 0x62, 0x81, 0x38 }} + gPcf8563RealTimeClockLibI2cMasterProtocolGuid = { 0xa6af18ae, 0x3bd5, 0x4af9, { 0xbb, 0x6a, 0xdb, 0x85, 0x07, 0x62, 0x81, 0x38 }} [PcdsFixedAtBuild] gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51|UINT8|0x00000001 diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf index 9907e343ba78..1a9a6f6c9cf3 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf @@ -42,11 +42,11 @@ [Guids] [Protocols] gEfiDriverBindingProtocolGuid ## CONSUMES gEfiI2cMasterProtocolGuid ## CONSUMES - gPcf8563RealTimeClockLibI2cMasterProtolGuid ## CONSUMES + gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES [FixedPcd] gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cBusFrequency [Depex] - gPcf8563RealTimeClockLibI2cMasterProtolGuid + gPcf8563RealTimeClockLibI2cMasterProtocolGuid diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 098a4dbd324e..91c1b66ea1f8 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -183,7 +183,7 @@ PlatformDxeEntryPoint ( // through the I2C driver stack (which cannot be used at runtime) // Status = gBS->InstallProtocolInterface (&Handle, - &gPcf8563RealTimeClockLibI2cMasterProtolGuid, + &gPcf8563RealTimeClockLibI2cMasterProtocolGuid, EFI_NATIVE_INTERFACE, NULL); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 766f4041c826..4d6a1d637922 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -53,7 +53,7 @@ [Guids] [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES gEfiPciIoProtocolGuid ## CONSUMES - gPcf8563RealTimeClockLibI2cMasterProtolGuid ## PRODUCES + gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase From patchwork Thu Jan 25 12:27:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125825 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1078954ljf; Thu, 25 Jan 2018 04:27:54 -0800 (PST) X-Google-Smtp-Source: AH8x226aDVMuoHzenho5bNK54MoCF3ddz4CpqCYpi/qQYEsLENNs3hvdgjRPK3vqaH4Z212iZXJj X-Received: by 2002:a17:902:1683:: with SMTP id h3-v6mr9986503plh.433.1516883274539; Thu, 25 Jan 2018 04:27:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883274; cv=none; d=google.com; s=arc-20160816; b=pibbe8ABDm/TL1L4a7FLu7++r17nDhxzTYur4Oqz0HU5ts1xeqCY9669T93l0MXP7P iUUBBdawE4OdKbG1ySPCjbpatYXWBNLS6z2snuC0xhMtLLK9sI/IghquFb2HtJ+VQdg3 17gesd+Dz0wWu5rAi9YvfVyzS+gePti9e7UQCYEET0PDd7AvGw6672wTh+/vPa8i1lIC zUuw9frs6c+G8Silh+9LuJxxPpxrKeb9bqJnFfpgaea9s7O8dd+NAaDhUtPTfhL96Njz IsOCE2CNTna2JsAW4/YNLfnwIEndMLdy70tWwVkDdYxZD6EClVhXc4iHIZNDXSNkQohR KCqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=jALQrmjuI+kbvXHCgw2I+DBv+iyMyphbykznkQ6vWPE=; b=lQDa6M0gw4fruXugVgzlYJtI6GTOmf0Z00VO8h4txXTVYrIqmrL+hWRA7TSKz9gWA8 60AINeU3R/Qr5N7reLrMwqfqihYxCr9vQAOibNO3Td6mubd5lYhS+Ht0iZA22OkC9DVE Iigm4NLTlgJ5u7ZrbmB0SmcRx6SvwgUXDYsqGtInh+szkIVI5X6SJusE+CN0ghwLqxb8 7BxDUaBENv2KrtoFAWcgTfcI10zvzh8BwlQ1VvAWMzjn8pPXrY44mmwTaSVQP6cZWbzf gcyDV6yOw0AakkAY9EoRDpcSP2DVyisEhT8Tvzz0jXT0IBbIyRkmA2iqly5rjSycWwcq KL5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PQQ6rorO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id m184si4540215pfb.373.2018.01.25.04.27.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PQQ6rorO; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1B166222CF1B2; Thu, 25 Jan 2018 04:22:22 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 395AB222A3356 for ; Thu, 25 Jan 2018 04:22:21 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id j21so22389296wmh.1 for ; Thu, 25 Jan 2018 04:27:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mYfkUwmOQm2oWGvmPBoBYxum1hPxS1NW1MLnfykGhRY=; b=PQQ6rorOnTZuuiPQkDXm62Y8nv8EdV9DKw62wWVybfLwojYZbfzYtEMeNRjXNT7gZA YWL+goRaS61n/pgPVp0GVdSe5GHMO+nniLJix/0468/kcKv2hytL7HFnULWdHjRi32Ld cjnEytK05j1J0lVDu+AQFhLTNyMe0zWXZ/H7U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mYfkUwmOQm2oWGvmPBoBYxum1hPxS1NW1MLnfykGhRY=; b=REPfA8a1eIir1W2t4wAkzyc4Kw0oYJud3/h/D3tlgfZJod9PNjdZbDmTSlucSfGMRM 70Gfklk4HSgAyYNhOpTllZui204xhbNBozjJVR9ompon7H9tXyG6DUjOYz/rYpliyR4f DYrXkritFmfaHnxMsyyYelt48HknWtfAUIXb2kUccFMUCGKSDPD8HppohfcSZBOp4v1t c6zvR/o+9A0EPSrL+mqJQuGwdeTkJmLOjFHm5f+ksHq4Cjuyz/RkAfuWvUMsc/fyyp1d Lw3hv+qpTdm4OAciNt3Ho+7leskgV771BTNMul/mqk0vBSA58LKmNm+gamT6SAUgtCjw mDbw== X-Gm-Message-State: AKwxytfeb8cq/scNTWOGb8Z3ztu0bp4AXpm9hx1cN3xvGOnXCtPdzMKE 6LzF24teO1WC96YIyOIY+KvoQpS83oA= X-Received: by 10.28.125.19 with SMTP id y19mr6989556wmc.101.1516883268946; Thu, 25 Jan 2018 04:27:48 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:48 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:31 +0000 Message-Id: <20180125122736.5427-4-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 3/8] Silicon/NXP/Pcf8563RealTimeClockLib: avoid driver binding protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Instead of registering a notification callback on the driver binding protocol, and attempting to connect our I2C master handle each time a new driver is registered, switch to the more obvious approach of registering a notification callback on the I2C master protocol directly. The original code was written under the assumption that it would make the RTC available at an earlier time, but given that all handles that are created during the execution of a driver entry point are connected by DXE core right away (i.e., before StartImage() returns), this is not really necessary, and in fact, may result in the driver already having been connected by the time we attempt to connect it. Note that it is now up to the platform to ensure that ConnectController() is called for the handle if DXE core does not call it by itself, or does call it but at a time when no I2C master protocol driver is available yet. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 31 ++++++++------------ Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 1 - 2 files changed, 13 insertions(+), 19 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c index 6bc4aef28849..fb58e1feb424 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c @@ -41,7 +41,7 @@ #define EPOCH_BASE 2000 STATIC EFI_HANDLE mI2cMasterHandle; -STATIC VOID *mDriverEventRegistration; +STATIC VOID *mI2cMasterEventRegistration; STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; @@ -263,12 +263,12 @@ LibSetWakeupTime ( STATIC VOID -DriverRegistrationEvent ( +I2cMasterRegistrationEvent ( IN EFI_EVENT Event, IN VOID *Context ) { - EFI_HANDLE Handle[2]; + EFI_HANDLE Handle; UINTN BufferSize; EFI_STATUS Status; EFI_I2C_MASTER_PROTOCOL *I2cMaster; @@ -280,10 +280,10 @@ DriverRegistrationEvent ( do { BufferSize = sizeof (EFI_HANDLE); Status = gBS->LocateHandle (ByRegisterNotify, - &gEfiDriverBindingProtocolGuid, - mDriverEventRegistration, + &gEfiI2cMasterProtocolGuid, + mI2cMasterEventRegistration, &BufferSize, - Handle); + &Handle); if (EFI_ERROR (Status)) { if (Status != EFI_NOT_FOUND) { DEBUG ((DEBUG_WARN, "%a: gBS->LocateHandle () returned %r\n", @@ -292,12 +292,7 @@ DriverRegistrationEvent ( break; } - // - // Check if we can connect our handle to this driver. - // - Handle[1] = NULL; - Status = gBS->ConnectController (mI2cMasterHandle, Handle, NULL, FALSE); - if (EFI_ERROR (Status)) { + if (Handle != mI2cMasterHandle) { continue; } @@ -378,16 +373,16 @@ LibRtcInitialize ( ASSERT_EFI_ERROR (Status); // - // Register a protocol registration notification callback on the driver - // binding protocol so we can attempt to connect our I2C master to it - // as soon as it appears. + // Register a protocol registration notification callback on the I2C master + // protocol. This will notify us even if the protocol instance we are looking + // for has already been installed. // EfiCreateProtocolNotifyEvent ( - &gEfiDriverBindingProtocolGuid, + &gEfiI2cMasterProtocolGuid, TPL_CALLBACK, - DriverRegistrationEvent, + I2cMasterRegistrationEvent, NULL, - &mDriverEventRegistration); + &mI2cMasterEventRegistration); // // Register for the virtual address change event diff --git a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf index 1a9a6f6c9cf3..e232902c6b5d 100644 --- a/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf +++ b/Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf @@ -40,7 +40,6 @@ [Guids] gEfiEventVirtualAddressChangeGuid [Protocols] - gEfiDriverBindingProtocolGuid ## CONSUMES gEfiI2cMasterProtocolGuid ## CONSUMES gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## CONSUMES From patchwork Thu Jan 25 12:27:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125826 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1078975ljf; Thu, 25 Jan 2018 04:27:57 -0800 (PST) X-Google-Smtp-Source: AH8x226B8DUmTinRVP1An4p+EA7ECCyYWJktxSs1sKX+SI4dxUe5P6DXYE5A+JGlpi+m310HwyB6 X-Received: by 2002:a17:902:6a16:: with SMTP id m22-v6mr11649035plk.142.1516883277571; Thu, 25 Jan 2018 04:27:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883277; cv=none; d=google.com; s=arc-20160816; b=aOgHtmc8e/FgJeFXPrPsq95PPCmeDXjgJaeyUrANJ/MHNSSIU0AjPnjjsc64LsOPem IN+AF3KBiONBVsRLZaduFnnDZpyjgZu0XVbYznNwnYHt3FUUJx0lm3qHdYdv9pM7DawL 2ZIrW/A0z0McbFCKzZoHQ9k6OtpPuwP8z/4bJ5vQz8aN04QtROE66zf3fINECTMjMjHX bkRMtIJrOniy1ndqBx8Z1SfOjdDG4IWxwv/Z5ShasNMftZHJH85yrVmBy08az8KnjGdh 6QP4iiv/Abzd3U2ImKeuOgKXVKISaftRFB5cTRezPqKCCcaWUaJC4QwTQ47DASxrZAdj txOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=tO//1DuJAPhFmj09c/wKY6OI99VHvyrbMSacYrzrOaE=; b=no72VwRDKMksPGxK8YiNRMZeb/UsH/AfRYTbsFMrj5/TCyH3gMcVHef34C1PqFhvcQ 9pSMvGBKoMKcvx1LOY0KGpqf5OM+tyfGPCSkuS8yHwetoLr94Sv5NOT/62sf1tyTzcb8 /C3SOeOUsRMA63dVrfYM44bQ/Q1bs1+8S2nOM/iFKuC+3pbPR4N0/77gWduIgp324868 15thAEN2jWwA1fDRFkigVQO1pTHPae0GGGEbqrKHCv0kfZU3uv0xevc0a+HGcidUS+X0 Jyel4aXO4f9+T+Rvi1Lr3PHiIgVDP56IfhoHkviCjQjllefMp8QRNLARNKjh0Gqt56iy DHBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hx+Jk0nw; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id g5-v6si1913150plt.563.2018.01.25.04.27.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hx+Jk0nw; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 76E6521E2568E; Thu, 25 Jan 2018 04:22:24 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE89F222A3356 for ; Thu, 25 Jan 2018 04:22:22 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id z48so7468902wrz.6 for ; Thu, 25 Jan 2018 04:27:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tftp2UE80/8QxkH+5zL9DVRzwGTyGZ4lxt+6iGbau7k=; b=hx+Jk0nwaxQwAm0yy8OMiSCy0S2/30qoO5M3A89YJNatyqViuxCbWyN1Tr/rGvufIs YlO1Z7GfUiq/20g2udT1dZTnd8Td1NeCkgLol9h06tsDnXkJVSc+Jii8RFEDfyVXf7ES r1NH1DMB+O87L6EsBVBybkKArYnQhe5dj0fek= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tftp2UE80/8QxkH+5zL9DVRzwGTyGZ4lxt+6iGbau7k=; b=Z7SR7VzsBahP4ragKPMgJCgxn3zxrJL35I8fpIkxQv+4E80rrlT+JWXKVgJtBC5wSq eELPzNd0d2b1eBkcGjPA+j9QV0yTGZcQYMM9wSlUpfTIwap9gltbGAb/GgRsuP2z3yGG pvC8N1PqkA8huEw7jVVF8bJqSut8gSuq4UrpNfX5IZQYxuiw327CiAh+9PbhLfqxEoYF YIx8p/cPVlrlyrUEeeYeRZurryWw4ppuULlNh19lY5wBSXpU1HcZ84QLImunKzx4UOS3 yCzAUEVqrhw1sRtOdB/vcM67p+BlyJ6UjOOjjGHpQKZC2DG4J2QbDTNQSv4y3kAa/P+S e3Qw== X-Gm-Message-State: AKwxytd6GLYH17+wYR0jgFNtkbE96R2+fHvGUA0xJNHgq7gISTZnwcJf 2L1xcNfRyjx5zhPE+7z6PAo1Gg9H7aA= X-Received: by 10.223.151.41 with SMTP id r38mr8018907wrb.133.1516883270619; Thu, 25 Jan 2018 04:27:50 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:49 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:32 +0000 Message-Id: <20180125122736.5427-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/8] Silicon/SynQuacerI2cDxe: remove spurious format specifier X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Remove a %r without an associated parameter. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c index c3703dfb6c33..46c512a20151 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c @@ -335,7 +335,7 @@ SynQuacerI2cStartRequest ( } if (MmioRead8 (I2c->MmioBase + F_I2C_REG_BSR) & F_I2C_BSR_LRB) { - BOOTTIME_DEBUG ((DEBUG_WARN, "%a: No ack received - %r\n", __FUNCTION__)); + BOOTTIME_DEBUG ((DEBUG_WARN, "%a: No ack received\n", __FUNCTION__)); Status = EFI_DEVICE_ERROR; break; } From patchwork Thu Jan 25 12:27:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125827 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1079006ljf; Thu, 25 Jan 2018 04:28:00 -0800 (PST) X-Google-Smtp-Source: AH8x226dYBjV9Vx/6ErGQR/tHOcM53npPeOAUWXBo3ogD04ONw2DKbWAfuhvYDzEF2F3rroG48pS X-Received: by 10.98.61.22 with SMTP id k22mr15840971pfa.133.1516883280709; Thu, 25 Jan 2018 04:28:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883280; cv=none; d=google.com; s=arc-20160816; b=sXN+agsc2qo75GoSYUdXDpj+q6SZ9V7hZjwZr32RqaPNSOXXbcYR7Fbub1UZZkhQ01 niYLQMniE9OI4IRD2u//z5jOR223fyQEVdHhWPTR6atAEeJ0yGVsqrWtsEsYQDaREmnZ /YFgdYU2ym8w5DhSfXFh6MuczUpXzCxego3KOC0zgzuiTM/qoIYMg55zl35Z8hwOxTjZ whBDNK/93PJzVL0DEKBrvCs5hCIqfyvSFvV9pLwQdn6J8cajReGNCmO6nBM70VGiUEER FgOyNlMDs/S6kWY+Prkj62dU95sB5DiphxoOX5VS/mgJWIJQLJaFj6PJ08gZ50Fvis8z 9kPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=5dwI26tPkcNm8Eh+crBqSDb11lJ/CBZZbcAKpd7+PGs=; b=m91RTRD8PhvyagOv0vgjigmmNA68i2v/zXiI5BsbK6d51nvjoO0ElJwkgMkflw/1H3 sfVHvEKzxhpFg//1S+qimpVemvLeY52su3s+pvVRrf5BVwi331txymGeFdilMUf89qfi mkTZlRfy+xoWycQROBGHphNzSrqHqFP33yRlLv0OuDy2mCyPQpy+WXe3dQQTzjIeTC96 h+Aidb+Qwu7zgERB+P1MRkqxsNWgmxaI8o4JT0UZsk8+77Z5roxtvRN/yK9u+M6d06tn d+hQW/jX8ERo3YAU+Y43CrMDbuE05wB64HDuxuI+3dwDPY/Kc8MKDFjLdh43xpo6/A5h BCJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TR3QqaHj; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id y128si4543152pfy.110.2018.01.25.04.28.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:28:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TR3QqaHj; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E1443222DDBEC; Thu, 25 Jan 2018 04:22:26 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BBA34222A3348 for ; Thu, 25 Jan 2018 04:22:24 -0800 (PST) Received: by mail-wm0-x243.google.com with SMTP id r71so14404461wmd.1 for ; Thu, 25 Jan 2018 04:27:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+z4ovW6TIaaC4nkL3RLs3j5MTR8XeOuNge1td5JF4Pg=; b=TR3QqaHjQQChvN0RdhHVcipSbduR5qUXfCNTLYnQq8ZfHXyC4jV4KrbUyYGb2E1Pny wGhu9zZ7c5sT1qa2LBRY2cJ99DAJgrMcZef32k8t1bwR1oih5PEeeCwjMxwz2XQTQvXL 7bgnVScjWBxALDf+htgKszzCLZvODzw3YBbKE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+z4ovW6TIaaC4nkL3RLs3j5MTR8XeOuNge1td5JF4Pg=; b=X70XNontOMj26rs43COofixlukBMFLk72Slt6OGNMvbqLDycUv0T4C+1S07JPBTd/F pXQP6Oy0yZKSWi6xQL+UztDSlG6kxXX/5JlyVXIxU/EuoK+KNOcBlXeumnjcoEOsYur3 Ye/J3hC9+PVWQQwCc0xh27WGrVY9xhdn2PvleelhM+h+QYT7IzvTTSYeH34PgMGn7YsO 8Y7MI8dy8E9FyPMwi3LlSNIpzS2u372bGNu7CPkRWbl8lo7Aw083UqHTikTChOTNaevG /9hZ5tzPQuCs4uet1b1k1ojCgeUiPBqxzcso/xuQYg3+X9wUuVkm+tj1UnKDGvMXJ/Rr QGFg== X-Gm-Message-State: AKwxytebfqRH65kh9r6UdxZJmVjut6MyLC476eQD2h8OtlFJLiELqQY7 EEKkPHYTuLwBl66C0LB85glua6LB7tg= X-Received: by 10.28.217.213 with SMTP id q204mr2579357wmg.154.1516883272475; Thu, 25 Jan 2018 04:27:52 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:51 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:33 +0000 Message-Id: <20180125122736.5427-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/8] Silicon/SynQuacer: load I2C driver before platform DXE driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" To ensure that the I2C master protocol is installed immediately onto the handles created by PlatformDxe in its entry point, force the SynQuacerI2cDxe driver to be loaded before PlatformDxe. These handles are recursively connected by the DXE core as soon as they appear, and so ensuring that the I2C master protocol driver is available at this time will ensure that these handles will be connected to it right away. This is useful when implementations of architectural protocols such as RTC or the EFI variable store, which should become available long before the ordinary dispatch of UEFI driver model drivers is started at the end of DXE, are based on I2C. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 +- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 2 +- Silicon/Socionext/SynQuacer/SynQuacer.dec | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 4d6a1d637922..f075957d7456 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION = 0x0001001A BASE_NAME = PlatformDxe - FILE_GUID = ac422cc1-d916-489a-b165-536fdfc633c2 + FILE_GUID = ac422cc1-d916-489a-b165-536fdfc633c2 # gSynQuacerPlatformDxeFileGuid MODULE_TYPE = DXE_DRIVER VERSION_STRING = 1.0 ENTRY_POINT = PlatformDxeEntryPoint diff --git a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf index fa715366878c..325816ba0b88 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf @@ -56,4 +56,4 @@ [FixedPcd] gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock [Depex] - TRUE + BEFORE gSynQuacerPlatformDxeFileGuid diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index a21f12b5bc32..76529e3c2164 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -25,6 +25,8 @@ [Guids] gSynQuacerNonDiscoverableI2cMasterGuid = { 0x364ee675, 0x9e44, 0x42b7, { 0xa5, 0xe4, 0x92, 0x84, 0xdb, 0x85, 0xda, 0x09 } } gSynQuacerNonDiscoverableRuntimeI2cMasterGuid = { 0x5f35aa9b, 0x8c6f, 0x4828, { 0xbd, 0x44, 0x7c, 0xc0, 0xeb, 0x2d, 0xfe, 0xb9 } } + gSynQuacerPlatformDxeFileGuid = { 0xac422cc1, 0xd916, 0x489a, { 0xb1, 0x65, 0x53, 0x6f, 0xdf, 0xc6, 0x33, 0xc2 } } + [Ppis] gSynQuacerDramInfoPpiGuid = { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } From patchwork Thu Jan 25 12:27:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125828 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1079025ljf; Thu, 25 Jan 2018 04:28:03 -0800 (PST) X-Google-Smtp-Source: AH8x225RqXac0AdIYJFELWqKv18maZeaLoTye8w1njOLO6cSTZtAuMbTJljXe5ZqMW9B/zqoWpoF X-Received: by 2002:a17:902:ab93:: with SMTP id f19-v6mr11397924plr.10.1516883283765; Thu, 25 Jan 2018 04:28:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883283; cv=none; d=google.com; s=arc-20160816; b=Ww+dnKs+tROW93ol0Xl6ctZ5GZumlbXK76CFz79EoHeMBLEtq7jUoVPp4TrANUsEFk WLjKzc7QQV4mjg83+lMVE6KX6teAtVOoUcNe8dMV5xjR+oEcFwvIMYJgmPXFOM2/oyHt uYCnbySYHAku1Ej3Iyo1Lxk7Qwy12DJjKcxkyB+km6/1AcMhjC7w4z9kSyQxRFyyNibN peGeUHJ/3hGXuacCz1bvYE5BHFj90kQP+1AQe91Vw3i6RDMYPRXGrMsP5IAZMLSoGi0c IFr2kbWBzTplAsgCZSa7SybgtO/Huaeh7I0AvK0HF9os0GFNmm+Gp8K9hXHT12GCc/SK 4CEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=yjwwNKRIU7EzgKeyAKFDIKEtB8bcN93gqweNtvoWlo8=; b=DAU+OSEfm9bLWLLtigBu43AjwM5veBH26026jP/sY/mrlOh2O4OgnQlrKepdofE6Jq MOSYDRkExI6KxWTam+Ivj7uxr9lkIVvLcbMfD9Q/kbSdJhz4zHmSl2l9kZ6iWCJFTpdh 8LfmWJv9cnMuyNn6aCBqDQwlvrxt2WFGFh3ib3L9Ku1Fpq88kd4Q0hOdzA8h7rYexB/E LY2scVC3v/ksFA4SalWUk8XN0IinqaUIGt9CuNNe5x7sbAeDEUrB146ihhgaRLIvuvYc zFUWbZATdrAsYh/8iKhsM5Z3lyPx3O2TC4FGISLStQnmHtk0piK8IOgFQjiNmfZqSxo/ Op9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ChFGgl63; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id w23-v6si1888475plk.537.2018.01.25.04.28.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:28:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ChFGgl63; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 465F7222A3356; Thu, 25 Jan 2018 04:22:29 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 27C50222A3356 for ; Thu, 25 Jan 2018 04:22:26 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id v71so14613572wmv.2 for ; Thu, 25 Jan 2018 04:27:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YwXCUsXGEZG7l0j2D4LD5Utf9ZA5PX8svNffjnw+wBc=; b=ChFGgl63yiJCi4XRnIv76icYMN0EeWO2NcJ2p1b35tGhjwaRx84VoTLqqDcG6iJAvS SGfxB0Z3GT1Ms+FsOGgnKcfwskSc804HmPY6iMLqsp3aFPUVU9sosBp8OMAHx6iyFHHj Ucyr6fSRSGV4G2/cH7BMUHXGNvoanXkdJWxXg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YwXCUsXGEZG7l0j2D4LD5Utf9ZA5PX8svNffjnw+wBc=; b=Eg14EKcoSJ5Ykr0rUyBfGUbN31RxfhUeYJH7LttL1lpTfCOqg+5rkoWnVJlPToAp71 iDNpW2nGt0mjXZFTjBetslFGVX8dTEiHMkcPLjvxxtZIoM3kesxuuJNc+JqflYMOfu2N XfjPPLVuxzWe0PkvG4sKIOVu6M2M+ZwvEIa2EBxkIFacL53lqPQMjV7o8L/6EyO8tbRS lWvsokFEbuTfPbSTd3Y2LnDxDasRVcSi9vU5nmNZvCULZRwtzcsL1TquNFOwob7+vNDY SmPSF9o7kUs/CcG0pSoElyo9yyDQL/H0Dq0mifFVwnTyaXjOLaONLOoetQXpaWSfqP6t eF5Q== X-Gm-Message-State: AKwxyteC2SQTrOwz+BrIbN38wcUit1rvXf+ScPtwoFxdhnl/sWxshsFg P7PNsPBhAe7kdHF/qxkjJoD3+HX/eLM= X-Received: by 10.28.232.72 with SMTP id f69mr6769848wmh.110.1516883273979; Thu, 25 Jan 2018 04:27:53 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:53 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:34 +0000 Message-Id: <20180125122736.5427-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 6/8] Silicon/SynQuacer/DeviceTree: align uart DT nodes X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Align the UART DT nodes: - use 'uart' not 'fuart' as node name for the second serial port - create an alias 'serial1' for the second serial port - use UART clock reference instead of hardcoded frequency - split 'clocks' property into 1 cell per phandle Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 37a3981f0360..7c3518facb98 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -32,6 +32,7 @@ aliases { serial0 = &soc_uart0; + serial1 = &fuart; }; chosen { @@ -436,15 +437,16 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x2a400000 0x0 0x1000>; interrupts = ; - clocks = <&clk_uart &clk_apb>; + clocks = <&clk_uart>, <&clk_apb>; clock-names = "uartclk", "apb_pclk"; }; - fuart: fuart@51040000 { + fuart: uart@51040000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x51040000 0x0 0x1000>; interrupts = ; - clock-frequency = <62500000>; + clocks = <&clk_uart>, <&clk_apb>; + clock-names = "baudclk", "apb_pclk"; reg-io-width = <4>; reg-shift = <2>; }; From patchwork Thu Jan 25 12:27:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125829 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1079045ljf; Thu, 25 Jan 2018 04:28:07 -0800 (PST) X-Google-Smtp-Source: AH8x225Fut1oiSIo9FR2Naxyv9ZWP4eX13rz9xwo2iunfiSVP6Xf8ZpP2k7jw3JAn+M0Rx6SqqZp X-Received: by 2002:a17:902:bd09:: with SMTP id p9-v6mr2142191pls.236.1516883287080; Thu, 25 Jan 2018 04:28:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883287; cv=none; d=google.com; s=arc-20160816; b=Hl5miCOQAkJ48DetfRqiGPHBvOZxZgln8o5W0DLYYkuxOzPSQADFnhklLSYF+PR1fu M2KuRYbPrp0ckIJXKGc1y6MCSPpQheWdMTZvuz83JCCp7D92PVgubmBUUOcSDF1LV5tg cnr2h13EIue4fPKjFyAdQGO5Sig8efvhYARfw4MlMsB+DQ3T97POaamVWAQGCnVHZWbv fIz3rCjnOJamkYCA75cthT33kXOf5VTX2cOW2Yve1838OiIFHxE5vb28IP++iRPiC6Ig YGiuTV78nYpq6kzX2id11UK25aZiIs2SzL0fcM9NKFofbI3VcfRyFUIQHfGILK0dnNVy hyvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=XzNsyGRsX687VYqwX3e0iPDhb68cQW5mVTefirOVbN0=; b=Q4f8eMqxS925Y2ieZ6fhUo8jZK0gVzhiiWYwNuwOCuocH+HIbTM0zMqucB4yTa5rAP bG5n4+YvJvOPWaNQvvDGzs2Xw5P0BFvZfTZrqNCMR7Kk536KXFM1DXxD5vbBD/vDSHjB O/E4KZG2DNEdZNDL9uzC+Yiim9XmLwPYpSyPPRZX56CU7adbG1vySZ7+95vxBvIH7h+C 4Xu8LutZAthY6X6u2SfxPWuoc6eZALUl7D7M984I5w6wTATIznR6394tJOK+hv4k2LXu YefVsx19l1Eu2ro/bytGGqTkpl9k/0WSzq6hAxGuVJBijB/5zT2xXrEG5ERswMknZRRX mtpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jSTtdCHf; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id l7-v6si1324456pli.238.2018.01.25.04.28.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:28:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jSTtdCHf; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B098E22344331; Thu, 25 Jan 2018 04:22:30 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A3E3D222A3348 for ; Thu, 25 Jan 2018 04:22:27 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id 36so7501622wrh.1 for ; Thu, 25 Jan 2018 04:27:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NvfxCgDaHWmqVfRQkqFieJ9TmnsQy574OKWfDO41e6I=; b=jSTtdCHfY1Tx2oeDRbUgaS/ShcrosdMJNPo36jTxvHxp4lNHA0B+0gejjoHjqwArOA q3XMI/FKS70twT+/WkXiIbkqjVBWbRQw9A07CWspwuJ8CXI8TfFBURrgHDz/dgsdXWdY 748IIA4loh1+4YJTlMkgo3yoSnWfVxgDx4owc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NvfxCgDaHWmqVfRQkqFieJ9TmnsQy574OKWfDO41e6I=; b=ix4RMJqq5yDiuRCmMVV2LKPqXzD4di/zwSb0i+T+orKwskRYt3sqnW/qSMp95CNItG I7Db536bcQWxjsgOTOSVTsiy9YEAYiXs8wdCH56+kKmIJ9LZQ+jkFrccr3qNh8PJa7Gs 9LGdvA4GgA1GVYLCmLLI1/HicyxDO/Il784nB+hXCvJlj+GQkrn0Qr2kg2pEzPxMAj2p IoMCo/e5Wvk3z+HcisAMiVWkXwumZ3etVtl/gNjV2d1Au/bERmp5zYHjLorG+xyoAuy9 xe86gXW/EJ6KYk5onFnhmT25IM8ZncTyoEWgA6s3IOhVr8iKcEppzac3H3CxmGxO1KCC qqIQ== X-Gm-Message-State: AKwxytccw+c8rwW+fWBDKbEzl66l/JU1yO+97yooJJkiwOBdvI9vddhj MOmfO7qEXMeIT9kLx5YVfUsTOD8O544= X-Received: by 10.223.184.102 with SMTP id u35mr8472318wrf.143.1516883275463; Thu, 25 Jan 2018 04:27:55 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:54 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:35 +0000 Message-Id: <20180125122736.5427-8-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 7/8] Silicon/SynQuacer/DeviceTree: update NETSEC DT node to latest binding X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The upstream version of the Linux NETSEC driver expects the PHY DT node to appear under a MDIO subnode, so fix this in the device tree. Fix the node name as well, this should be 'ethernet' not 'netsec', and add a clock-names property describing the single clock reference as 'phy_ref_clk'. Also, move the PHY subnode into the per-platform .dts file so we can set the unit address in the node name. This is necessary because recent versions of the DT compiler are more finicky about this. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++++----------- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ 3 files changed, 28 insertions(+), 16 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index d2cd7ef90e6f..488c51a0f793 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -44,3 +44,10 @@ "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; +}; diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 7c3518facb98..6ee7a0b7ccb4 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -457,25 +457,23 @@ #clock-cells = <0>; }; - eth0: netsec@522D0000 { - compatible = "socionext,synquacer-netsec"; - reg = <0 0x522d0000 0x0 0x10000>, - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; - interrupts = ; - clocks = <&clk_netsec>; - phy-mode = "rgmii"; - max-speed = <1000>; - max-frame-size = <9000>; - phy-handle = <ðphy0>; - dma-coherent; + ethernet@522d0000 { + compatible = "socionext,synquacer-netsec"; + reg = <0 0x522d0000 0x0 0x10000>, + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; + interrupts = ; + clocks = <&clk_netsec>; + clock-names = "phy_ref_clk"; + phy-mode = "rgmii"; + max-speed = <1000>; + max-frame-size = <9000>; + phy-handle = <&phy_netsec>; + dma-coherent; + mdio_netsec: mdio { #address-cells = <1>; #size-cells = <0>; - - ethphy0: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = ; - }; + }; }; smmu: iommu@582c0000 { diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index 132fd370a71b..97fddfedcb46 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -34,3 +34,10 @@ &sdhci { status = "okay"; }; + +&mdio_netsec { + phy_netsec: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; From patchwork Thu Jan 25 12:27:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 125830 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1079082ljf; Thu, 25 Jan 2018 04:28:10 -0800 (PST) X-Google-Smtp-Source: AH8x227InUAcFPoi1h8D2GQmfaVdcEmJZQprQxO1elVkvz7aqzMViJyRNaaefOQucLzT9SZMSHs0 X-Received: by 10.98.62.69 with SMTP id l66mr16130463pfa.20.1516883290349; Thu, 25 Jan 2018 04:28:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516883290; cv=none; d=google.com; s=arc-20160816; b=eXf/VJ7ogBSAyj3TMQjuCAwJfz4vjM7CZ9ACIedBqL8rpN7V7ONp6ntTQn2WQ13nnW eTjCypwxHU6ReTcntIicgpH91nh6qGarjmA7u06kFyohMM81QSG/K7ZxHLLb7Eqkh14o Yh4mjCRebedpWDnBIE2Fr++QrLb+2xvfbBZkOwk9r7Z1VPBB6vDj6D/JjBKrOrJGY4EI qVpmEEkKtnD4FtUm1j2YbRLCz5DSOhlrrXry1nKOB9I0Sd1AkmTfbNo5O4zEAJdMAf1C HVDXBzmhmoACb+wwLPDyixT9G+oSJiWq+EEiAPaU7Eynfo0WVLxuIO/Vd4BwEvgoautP xKLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=3vdgq9UplxEYFNSjXTI5iKYaowpvYg0ljVjZ+SZEh0Q=; b=eJuov+nl2nYTcXVBASHcbIO2/iMf78YXeo4Kxl2E/L5N6n70jT8OIAV19fU92a6b/J 6SIXO3Kq6k7rSnG7qew3jz0x5ptsn3MLO2wQyQ7RDRY2nsl294GEe6HJkP+4ngB5FgAF a8g+PrJ7uJKjq7BYC5OYnbp2490aqe5diw3KgzSf8WiRY0X4z7tgk5VSzP+pe0hQkTOu r4gMnh7X7dvU//76MKqICn2+hqB/Uyc2ER9bRReE0BgsWpwAXlTg+Av4XaT+xkCgdboT CS+m96mFi1dVG/8lt4bSgRhvW1fVUtUJjHBawgLAgofvuM1AKZpI5507JyzIMnXdYACp BnfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T1CUI2Lr; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id v25si1491412pgc.831.2018.01.25.04.28.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:28:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=T1CUI2Lr; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0DCE02234432F; Thu, 25 Jan 2018 04:22:33 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07E2522333776 for ; Thu, 25 Jan 2018 04:22:29 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id t74so14389804wme.3 for ; Thu, 25 Jan 2018 04:27:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KCdOyln+mQVUCOEz3XW4P5EGTBfcPZGrJS9xkHitAxk=; b=T1CUI2LrK/9UKGzX5rKIbC54Hw8v4ePIB1Vthi2qG/hv2YPUxp/LTHbDQNQSfuPDLX 6WlmF0epNTbCltIdYSvDdaU6e9tmpxGRdFwgt2tOEqj3yBquxe7erCz3rKf8Lzu6D8Ye 5F+FnYWqqgfQ4/qeFfBR4Mtjmu3Zs6tmzG+ZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KCdOyln+mQVUCOEz3XW4P5EGTBfcPZGrJS9xkHitAxk=; b=aaTbvg5RjaseWSW6Z6KSg9TmW52B7IZDu07bBZUJ2aP85Op0TGSQ0JP2C5Xttfj9sa 3SkrFNp41rhfzLVjFbVqk2O68qto8J/RQh5d7Tk9xJi6CgYTTeJ2k+P6iLJknVFCYERN qLrsjZyGl+Hdy1jL4SNSJ+5PPmcHJKLWELGSQtvuLM5+UglFqYvTaTaLWbpD3Hg9aA/X NYCR6rXzcLPHIKiCDDj6B3qk3Njm4Ivav1lHHI788b7vN1VFCC/ZmIJR9zyC6FjKzEiQ ygkAtO2sj0paPQwIJhMjoQpQSTbw6mUh8U6ayTVNt/1XjXtJlXTbR6m6/pYQPcj23HgZ ECtQ== X-Gm-Message-State: AKwxytdKA3ZU1rMmP72bERJj2DHALeAbxPgB317vllsEJ0Yc52lNKBKx mIogsNwWwEQljMEtVDqbhqWgFk56ZR8= X-Received: by 10.28.51.12 with SMTP id z12mr7065374wmz.16.1516883277473; Thu, 25 Jan 2018 04:27:57 -0800 (PST) Received: from localhost.localdomain ([160.167.127.168]) by smtp.gmail.com with ESMTPSA id v75sm5510001wrc.45.2018.01.25.04.27.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Jan 2018 04:27:56 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 25 Jan 2018 12:27:36 +0000 Message-Id: <20180125122736.5427-9-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180125122736.5427-1-ard.biesheuvel@linaro.org> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 8/8] Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add menu options to the SynQuacer Platform menu screen to limit the maximum PCIe link speed for each RC individually. This may be useful to work around potential PCIe issues. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 2 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c | 4 +- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 107 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 12 +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 11 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 28 +++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 61 +++++++++++ Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h | 23 +++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 28 +++++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 2 + Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 25 ++++- Silicon/Socionext/SynQuacer/SynQuacer.dec | 5 + 13 files changed, 304 insertions(+), 6 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc index 86685d1dec3b..2d46b4515749 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -405,6 +405,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|30 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings"|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc index b4b9239143bc..263b6454ff72 100644 --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc @@ -397,6 +397,8 @@ [PcdsDynamicExDefault.common.DEFAULT] [PcdsDynamicHii] gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|30 + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|L"SynQuacerPlatformSettings"|gSynQuacerPlatformFormSetGuid|0x0|0x0|NV,BS + [PcdsDynamicDefault] gArmTokenSpaceGuid.PcdSystemMemoryBase|0x0000000000000000 gArmTokenSpaceGuid.PcdSystemMemorySize|0xFFFFFFFFFFFFFFFF diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c index 9af3dd942cdd..2a0fefbd423f 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Pci.c @@ -160,7 +160,9 @@ OnPciIoProtocolNotify ( // 2-port sibling of which samples were used in development) needs a // little nudge to get it to train the downstream links at Gen2 speed. // - RetrainAsm1184eDownstreamPort (PciIo); + if (mHiiSettings->Pcie0MaxSpeed != PCIE_MAX_SPEED_GEN1) { + RetrainAsm1184eDownstreamPort (PciIo); + } break; } } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index 91c1b66ea1f8..b60607d05861 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -14,6 +14,36 @@ #include "PlatformDxe.h" +UINT64 mHiiSettingsVal; +SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +STATIC HII_VENDOR_DEVICE_PATH mPlatformDxeHiiVendorDevicePath = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) (sizeof (VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + SYNQUACER_PLATFORM_FORMSET_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + (UINT8) (END_DEVICE_PATH_LENGTH), + (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8) + } + } +}; + STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mNetsecDesc[] = { { ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc @@ -144,6 +174,77 @@ SmmuEnableCoherentDma ( SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB); } +STATIC +EFI_STATUS +InstallHiiPages ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HII_HANDLE HiiHandle; + EFI_HANDLE DriverHandle; + + DriverHandle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + HiiHandle = HiiAddPackages (&gSynQuacerPlatformFormSetGuid, + DriverHandle, + PlatformDxeStrings, + PlatformDxeHiiBin, + NULL); + + if (HiiHandle == NULL) { + gBS->UninstallMultipleProtocolInterfaces (DriverHandle, + &gEfiDevicePathProtocolGuid, + &mPlatformDxeHiiVendorDevicePath, + NULL); + return EFI_OUT_OF_RESOURCES; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EnableSettingsForm ( + VOID + ) +{ + EFI_STATUS Status; + UINTN VarSize; + SYNQUACER_PLATFORM_VARSTORE_DATA Settings; + + VarSize = sizeof (Settings); + Status = gRT->GetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, NULL, &VarSize, &Settings); + if (Status == EFI_NOT_FOUND) { + // + // Variable does not exist yet - create it + // + SetMem (&Settings, sizeof (Settings), 0); + Status = gRT->SetVariable (SYNQUACER_PLATFORM_VARIABLE_NAME, + &gSynQuacerPlatformFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (Settings), &Settings); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiSetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: EfiGetVariable failed - %r\n", __FUNCTION__, + Status)); + return Status; + } + + return InstallHiiPages (); +} + EFI_STATUS EFIAPI PlatformDxeEntryPoint ( @@ -156,6 +257,9 @@ PlatformDxeEntryPoint ( UINTN DtbSize; EFI_HANDLE Handle; + mHiiSettingsVal = PcdGet64 (PcdPlatformSettings); + mHiiSettings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&mHiiSettingsVal; + Dtb = NULL; Status = DtPlatformLoadDtb (&Dtb, &DtbSize); if (!EFI_ERROR (Status)) { @@ -197,5 +301,8 @@ PlatformDxeEntryPoint ( Status = RegisterPcieNotifier (); ASSERT_EFI_ERROR (Status); + Status = EnableSettingsForm (); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h index d1dad2a3eace..6fc4970cf472 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h @@ -16,18 +16,30 @@ #define __PLATFORM_DXE_H__ #include +#include #include #include #include +#include #include +#include #include #include +#include #include #include +#include #include +#include #include #include +extern UINT8 PlatformDxeHiiBin[]; +extern UINT8 PlatformDxeStrings[]; + +extern UINT64 mHiiSettingsVal; +extern SYNQUACER_PLATFORM_VARSTORE_DATA *mHiiSettings; + EFI_STATUS EFIAPI RegisterPcieNotifier ( diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index f075957d7456..de21ba33df75 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -25,6 +25,8 @@ [Defines] [Sources] Pci.c PlatformDxe.c + PlatformDxeHii.uni + PlatformDxeHii.vfr [Packages] EmbeddedPkg/EmbeddedPkg.dec @@ -37,18 +39,24 @@ [Packages] [LibraryClasses] BaseMemoryLib DebugLib + DevicePathLib DtPlatformDtbLoaderLib + HiiLib IoLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib UefiDriverEntryPoint UefiLib + UefiRuntimeServicesTableLib [Guids] + gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid gSynQuacerNonDiscoverableI2cMasterGuid gSynQuacerNonDiscoverableRuntimeI2cMasterGuid + gSynQuacerPlatformFormSetGuid [Protocols] gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES @@ -59,5 +67,8 @@ [FixedPcd] gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings + [Depex] TRUE diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni new file mode 100644 index 000000000000..0425d8e0d761 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -0,0 +1,28 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#langdef en-US "English" + +#string STR_FORM_SET_TITLE #language en-US "SynQuacer Platform Settings" +#string STR_FORM_SET_TITLE_HELP #language en-US "Press to set platform specific options." + +#string STR_MAIN_FORM_TITLE #language en-US "SynQuacer Platform Settings" +#string STR_NULL_STRING #language en-US "" + +#string STR_PCIE0_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #0 link speed" +#string STR_PCIE1_MAX_SPEED_PROMPT #language en-US "Maximum PCIe #1 link speed" +#string STR_PCIE_MAX_SPEED_HELP #language en-US "The maximum speed the PCIe root port is allowed to negotiate" + +#string STR_PCIE_MAX_SPEED_UNLIMITED #language en-US "Unlimited" +#string STR_PCIE_MAX_SPEED_GEN1 #language en-US "Gen1 (2.5 GT/s)" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr new file mode 100644 index 000000000000..0dd25c980b38 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -0,0 +1,61 @@ +/** @file +* +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +// +// EFI Variable attributes +// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_READ_ONLY 0x00000008 + +formset + guid = SYNQUACER_PLATFORM_FORMSET_GUID, + title = STRING_TOKEN(STR_FORM_SET_TITLE), + help = STRING_TOKEN(STR_FORM_SET_TITLE_HELP), + classguid = EFI_HII_PLATFORM_SETUP_FORMSET_GUID, + + efivarstore SYNQUACER_PLATFORM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE, // EFI variable attributes + name = SynQuacerPlatformSettings, + guid = SYNQUACER_PLATFORM_FORMSET_GUID; + + form formid = 0x1000, + title = STRING_TOKEN(STR_MAIN_FORM_TITLE); + + oneof varid = SynQuacerPlatformSettings.Pcie0MaxSpeed, + prompt = STRING_TOKEN(STR_PCIE0_MAX_SPEED_PROMPT), + help = STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = PCIE_MAX_SPEED_UNLIMITED, flags = DEFAULT; + option text = STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value = PCIE_MAX_SPEED_GEN1, flags = 0; + endoneof; + + oneof varid = SynQuacerPlatformSettings.Pcie1MaxSpeed, + prompt = STRING_TOKEN(STR_PCIE1_MAX_SPEED_PROMPT), + help = STRING_TOKEN(STR_PCIE_MAX_SPEED_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_PCIE_MAX_SPEED_UNLIMITED), value = PCIE_MAX_SPEED_UNLIMITED, flags = DEFAULT; + option text = STRING_TOKEN(STR_PCIE_MAX_SPEED_GEN1), value = PCIE_MAX_SPEED_GEN1, flags = 0; + endoneof; + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + + endform; + +endformset; diff --git a/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h new file mode 100644 index 000000000000..9a70bb873056 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Guid/SynQuacerPlatformFormSet.h @@ -0,0 +1,23 @@ +/** @file +* +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __SYNQUACER_PLATFORM_FORMSET_H__ +#define __SYNQUACER_PLATFORM_FORMSET_H__ + +#define SYNQUACER_PLATFORM_FORMSET_GUID \ + { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99, 0x54 } } + +extern EFI_GUID gSynQuacerPlatformFormSetGuid; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h new file mode 100644 index 000000000000..fb2db7479758 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -0,0 +1,28 @@ +/** @file + + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made available + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ + +#ifndef __VARSTORE_H__ +#define __VARSTORE_H__ + +#define SYNQUACER_PLATFORM_VARIABLE_NAME L"SynQuacerPlatformSettings" + +#define PCIE_MAX_SPEED_UNLIMITED 0x0 +#define PCIE_MAX_SPEED_GEN1 0x1 + +typedef struct { + UINT8 Pcie0MaxSpeed; + UINT8 Pcie1MaxSpeed; + UINT8 Reserved[6]; +} SYNQUACER_PLATFORM_VARSTORE_DATA; + +#endif diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 27fcba034418..e475529eaf58 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -45,6 +45,7 @@ [LibraryClasses] DebugLib DevicePathLib MemoryAllocationLib + PcdLib UefiBootServicesTableLib [FixedPcd] @@ -52,3 +53,4 @@ [FixedPcd] [Pcd] gSynQuacerTokenSpaceGuid.PcdPcieEnableMask + gSynQuacerTokenSpaceGuid.PcdPlatformSettings diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index bea40e3dcfe8..1bdfd012b902 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -18,9 +18,11 @@ #include #include #include +#include #include #include #include +#include #include #define IATU_VIEWPORT_OFF 0x900 @@ -268,7 +270,8 @@ PciInitControllerPost ( IN EFI_PHYSICAL_ADDRESS DbiBase, IN EFI_PHYSICAL_ADDRESS ConfigBase, IN EFI_PHYSICAL_ADDRESS IoMemBase, - IN CONST PCI_ROOT_BRIDGE *RootBridge + IN CONST PCI_ROOT_BRIDGE *RootBridge, + IN BOOLEAN EnableGen2Speed ) { // 4: Set Bifurcation 1=disable 4=able @@ -312,8 +315,10 @@ PciInitControllerPost ( EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER); - // Force link speed change to Gen2 at link up - MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + if (EnableGen2Speed) { + // Force link speed change to Gen2 at link up + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE); + } // Region 0: MMIO32 range ConfigureWindow (DbiBase, 0, @@ -392,7 +397,16 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - UINTN Idx; + UINTN Idx; + UINT64 SettingsVal; + SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; + BOOLEAN EnableGen2Speed[2]; + + SettingsVal = PcdGet64 (PcdPlatformSettings); + Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal; + + EnableGen2Speed[0] = (Settings->Pcie0MaxSpeed != PCIE_MAX_SPEED_GEN1); + EnableGen2Speed[1] = (Settings->Pcie1MaxSpeed != PCIE_MAX_SPEED_GEN1); for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { @@ -414,7 +428,8 @@ SynQuacerPciHostBridgeLibConstructor ( mBaseAddresses[Idx].DbiBase, mBaseAddresses[Idx].ConfigBase, mBaseAddresses[Idx].IoMemBase, - &mPciRootBridges[Idx]); + &mPciRootBridges[Idx], + EnableGen2Speed[Idx]); } } diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 76529e3c2164..eb4fc4ace2f7 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -27,6 +27,8 @@ [Guids] gSynQuacerPlatformDxeFileGuid = { 0xac422cc1, 0xd916, 0x489a, { 0xb1, 0x65, 0x53, 0x6f, 0xdf, 0xc6, 0x33, 0xc2 } } + gSynQuacerPlatformFormSetGuid = { 0xe9cd576a, 0xaf9a, 0x4d41, { 0xbf, 0x1a, 0x29, 0xe1, 0xbc, 0x99, 0x99, 0x54 } } + [Ppis] gSynQuacerDramInfoPpiGuid = { 0x3e1d7356, 0xdda4, 0x4b1a, { 0x93, 0x46, 0xbf, 0x89, 0x1c, 0x86, 0x46, 0xcc } } @@ -45,3 +47,6 @@ [PcdsFixedAtBuild] [PcdsPatchableInModule, PcdsDynamic] # Enable both RC #0 and RC #1 by default gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 + +[PcdsDynamic] + gSynQuacerTokenSpaceGuid.PcdPlatformSettings|0x0|UINT64|0x00000008