From patchwork Tue Jan 30 15:01:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126225 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3438541ljd; Tue, 30 Jan 2018 07:02:10 -0800 (PST) X-Google-Smtp-Source: AH8x225LzKC4PlFJokV7Ch3YRj3f9rb9+1O09IcrTRMGALo/uKU7oz7HGnybWN7I3jyF5o3rhONH X-Received: by 10.80.144.53 with SMTP id b50mr51473967eda.265.1517324530223; Tue, 30 Jan 2018 07:02:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517324530; cv=none; d=google.com; s=arc-20160816; b=mBpD43ZTgSe64n1QJlWMmk3hPsGJlfc9j+0U3lvdOAhu4ckmp9/TrwxSWi0SkT3izk UPeJsgmzXG9DllCak+iri6TvcflGhLKoU/90UTxWrTHAhC3DDAKRSWSmVQh9d3m15agD rQQlFY5MAULOwXFTS0SRQjjVdhmlJNWG5MuGeKUF3MmiTbbVzaLhglgvCGlqwLJ13Vkm j/3RQLhTJLs+EAU5+BoIQu0tLl0s6yQR6vTt73ynsT8HerUYd5J8zy4wXYBhyBqWTzEp dszv6ABsXKlqjB6ZqajW9xhIi935ir1Swf1D/NmF+Ipczv4+Xn+vtALDz4MV9yGfRXEN iNTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=/yM96DnWvthYqzSS50MfbJoZ9lgLbT8s6f1Y+Yw/8mg=; b=U5mU7aQfMv7Tq/dRnBebwvs8dgY1R5bw+FIpgFLMlcel631fD4eO77Dh6JvpWWL9+J EOMXeDfj6Uo42ieo+KF2poPOHSHFsbmtmdbNdyV809nIIXKnqmI0to55K4dWKHhEgaIL dSyjIb4c8Kudvo1a5LdGJISaeBSKBwnRzUlxjWX1gu/fyK45qMzbqayMXeB1HDsA7WfJ DUlhsM3Y2FuesdxJMMCi+/PolaEIHWWwIgxJDmsOqMoWJj1AWAta09E4Pm4swqAXUMfC cvV4xe7H31tfXkZFfwjHKf/BWZ/r2pvkzq9Iw7SIAVacSVg9e65i3yOabNIM0I0BLffz ID8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=K9N6SQfV; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i60si166551edd.278.2018.01.30.07.02.09; Tue, 30 Jan 2018 07:02:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=K9N6SQfV; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 9BC55C21E79; Tue, 30 Jan 2018 15:02:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 172A2C21DA6; Tue, 30 Jan 2018 15:02:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E12F0C21DD7; Tue, 30 Jan 2018 15:02:02 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 21F68C21C8F for ; Tue, 30 Jan 2018 15:02:01 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF1xNS024867; Tue, 30 Jan 2018 09:01:59 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324519; bh=rzA5u5Ca4VgD59j3Igg4GYd2ClqJKkkDA1weoqWjCug=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K9N6SQfVwvwBPTkmWD6uJPQdPhlyEOFtBN4H1IGf6q55ONyNqmQokQWjyJrRKM77l wZVYQWtM+TA63Uwukp8RvWXJvVvTjdkVIhsMs0184lVFu784gWEC2sV9TclOXQIdO4 Fy0RlXXoMPk9vbiFWtIzrGZG91Rk6A1lQEOtA4+w= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF1xV9004691; Tue, 30 Jan 2018 09:01:59 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:01:59 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:01:59 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF1wCn011698; Tue, 30 Jan 2018 09:01:58 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:31 +0100 Message-ID: <1517324513-13875-3-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 02/24] mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I No functional change. Move bus width configuration setting to a separate function and invoke it only if there is a change in the bus width. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None drivers/mmc/omap_hsmmc.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fa8681a..713faab 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -62,6 +62,7 @@ struct omap_hsmmc_data { #if !CONFIG_IS_ENABLED(DM_MMC) struct mmc_config cfg; #endif + uint bus_width; uint clock; #ifdef OMAP_HSMMC_USE_GPIO #if CONFIG_IS_ENABLED(DM_MMC) @@ -814,17 +815,9 @@ static void omap_hsmmc_set_clock(struct mmc *mmc) omap_hsmmc_start_clock(mmc_base); } -#if !CONFIG_IS_ENABLED(DM_MMC) -static int omap_hsmmc_set_ios(struct mmc *mmc) +static void omap_hsmmc_set_bus_width(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); -#else -static int omap_hsmmc_set_ios(struct udevice *dev) -{ - struct omap_hsmmc_data *priv = dev_get_priv(dev); - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct mmc *mmc = upriv->mmc; -#endif struct hsmmc *mmc_base; mmc_base = priv->base_addr; @@ -851,6 +844,24 @@ static int omap_hsmmc_set_ios(struct udevice *dev) break; } + priv->bus_width = mmc->bus_width; +} + +#if !CONFIG_IS_ENABLED(DM_MMC) +static int omap_hsmmc_set_ios(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); +#else +static int omap_hsmmc_set_ios(struct udevice *dev) +{ + struct omap_hsmmc_data *priv = dev_get_priv(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mmc *mmc = upriv->mmc; +#endif + + if (priv->bus_width != mmc->bus_width) + omap_hsmmc_set_bus_width(mmc); + if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); From patchwork Tue Jan 30 15:01:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126246 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3448165ljd; Tue, 30 Jan 2018 07:12:41 -0800 (PST) X-Google-Smtp-Source: AH8x224soKQiHPzvuN9mJOIDMmMCESP4vnnb4CGmg6hpQ4aq9q6HwZTB3HmVKrRClMrIc3CLTo1J X-Received: by 10.80.191.6 with SMTP id f6mr53334057edk.281.1517325161619; Tue, 30 Jan 2018 07:12:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325161; cv=none; d=google.com; s=arc-20160816; b=jTMGQFhvn8DQweWbxzyRQD2Nxo4O7ifD8fFbr9vOF+FYhmuISC0h2ZwzNyz4bdouFR 0UPb3l8Pctq6h44MiSD/ykkWeJPN2006/nyXQMXWNZX8m9GER9W3qvC58zmSueSRTnJU DuWinOka63GoGcMggv2AT3RFFhzpu2UPD0Fn5VdSrEa17JgUJ7h2HQc1078gXwvYwyiQ hjxwaHjrRguMJVoIRS02ZmJDL+cydzIvZNdv/zNr8gLNcFFTFyCiVUeF18/YMmSajakY luNH9tihtpg+SoECZkF2/Hd7SZMUMDlWICg6OuXR56hXYruj2twT4ZpiMUeNQ4w7WiLy G8bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=3mr0zwmTMp8L4yj1wzWs1SS03Bt7v8BeV0dLxzv3ATc=; b=acujQDmx5uKml4XnyBYyPsRkJnBJCDNaVrr8IjAemyyCloZs4GeodOh1aIJo9FuSeE 0QJf4helKj3nuetRZe52COnu1fgN7KWl5RwdRf2N4EpE2LknZrqNvvVoTE6GHKoO2lYh ipDP1O1cg2zelu4Zl5eOZi2Mpprv9KWAwtoqrEnGbQJrAuUJfkYWxdJdlem08s5jmU+r jeoyQVRHujX2B4DmAF15Bc9NgrDZVCuINcuVVm4I+TOEgJkYocjyqwD5HonAFSj+Hn46 vQa4iPE8VWzfdyk7Fzyi6GALXPWBGeGDnOG8nDVjubJjvjQQ0oW5ir7gWqxgRtffHUSq SArA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=tqv6rrMg; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id u34si3005268edc.179.2018.01.30.07.12.41; Tue, 30 Jan 2018 07:12:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=tqv6rrMg; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 0AA07C21EE5; Tue, 30 Jan 2018 15:03:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CB26AC21EC2; Tue, 30 Jan 2018 15:02:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 70CB6C21E37; Tue, 30 Jan 2018 15:02:11 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 9EA56C21E4A for ; Tue, 30 Jan 2018 15:02:05 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF21Uo005606; Tue, 30 Jan 2018 09:02:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324521; bh=1ypKoycZ9SRew6ZcwAu4cr92waludFlOXnIYZUc6Lcg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tqv6rrMgE5TRcNdc0rMIvhqAMMYLwT3UxlqH3nooa2Rc2Ow9NnBqnG5yeFv1Sm7Et AkhlFowsQfOiIUDv3FOamhOUf1ZxtI25+QYQDJwS8xFgA2qSh7xeaWkwKi2cRhtjYL ugYDHeOiz0ay0xS7NeI/DfzxyQEOW1QznKmnOQ3k= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF20i8000831; Tue, 30 Jan 2018 09:02:00 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:00 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:00 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF1xrG011711; Tue, 30 Jan 2018 09:02:00 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:32 +0100 Message-ID: <1517324513-13875-4-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 03/24] mmc: omap_hsmmc: add support to set default io voltage X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I "ti,dual-volt" is used in linux kernel to set the voltage capabilities. For host controller dt nodes that doesn't have "ti,dual-volt", it's assumed 1.8v is the io voltage. This is not always true (like in the case of beagle-x15 where the io lines are connected to 3.3v). Hence if "no-1-8-v" property is set, io voltage will be set to 3v. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/omap_mmc.h | 12 ++++++-- drivers/mmc/omap_hsmmc.c | 67 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 102aec2..c4d326d 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -65,6 +65,7 @@ struct omap_hsmmc_plat { struct hsmmc *base_addr; struct mmc mmc; bool cd_inverted; + u32 controller_flags; }; /* @@ -124,8 +125,10 @@ struct omap_hsmmc_plat { #define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/ #define SDBP_PWROFF (0x0 << 8) #define SDBP_PWRON (0x1 << 8) +#define SDVS_MASK (0x7 << 9) #define SDVS_1V8 (0x5 << 9) #define SDVS_3V0 (0x6 << 9) +#define SDVS_3V3 (0x7 << 9) #define DMA_SELECT (0x2 << 3) #define ICE_MASK (0x1 << 0) #define ICE_STOP (0x0 << 0) @@ -159,8 +162,13 @@ struct omap_hsmmc_plat { #define IE_CERR (0x01 << 28) #define IE_BADA (0x01 << 29) -#define VS30_3V0SUP (1 << 25) -#define VS18_1V8SUP (1 << 26) +#define VS33_3V3SUP BIT(24) +#define VS30_3V0SUP BIT(25) +#define VS18_1V8SUP BIT(26) + +#define IOV_3V3 3300000 +#define IOV_3V0 3000000 +#define IOV_1V8 1800000 /* Driver definitions */ #define MMCSD_SECTOR_SIZE 512 diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 713faab..5141bf6 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -74,6 +74,9 @@ struct omap_hsmmc_data { int wp_gpio; #endif #endif +#if CONFIG_IS_ENABLED(DM_MMC) + uint iov; +#endif u8 controller_flags; #ifndef CONFIG_OMAP34XX struct omap_hsmmc_adma_desc *adma_desc_table; @@ -111,6 +114,8 @@ struct omap_hsmmc_adma_desc { * that the bandwidth is always above 3MB/s). */ #define DMA_TIMEOUT_PER_MB 333 +#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) +#define OMAP_HSMMC_NO_1_8_V BIT(1) #define OMAP_HSMMC_USE_ADMA BIT(2) static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); @@ -252,6 +257,58 @@ void mmc_init_stream(struct hsmmc *mmc_base) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } +#if CONFIG_IS_ENABLED(DM_MMC) +static void omap_hsmmc_conf_bus_power(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + + val = readl(&mmc_base->hctl) & ~SDVS_MASK; + + switch (priv->iov) { + case IOV_3V3: + val |= SDVS_3V3; + break; + case IOV_3V0: + val |= SDVS_3V0; + break; + case IOV_1V8: + val |= SDVS_1V8; + break; + } + + writel(val, &mmc_base->hctl); +} + +static void omap_hsmmc_set_capabilities(struct mmc *mmc) +{ + struct hsmmc *mmc_base; + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + u32 val; + + mmc_base = priv->base_addr; + val = readl(&mmc_base->capa); + + if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { + val |= (VS30_3V0SUP | VS18_1V8SUP); + priv->iov = IOV_3V0; + } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) { + val |= VS30_3V0SUP; + val &= ~VS18_1V8SUP; + priv->iov = IOV_3V0; + } else { + val |= VS18_1V8SUP; + val &= ~VS30_3V0SUP; + priv->iov = IOV_1V8; + } + + writel(val, &mmc_base->capa); +} +#endif + static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); @@ -286,9 +343,15 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) if (reg_val & MADMA_EN) priv->controller_flags |= OMAP_HSMMC_USE_ADMA; #endif + +#if CONFIG_IS_ENABLED(DM_MMC) + omap_hsmmc_set_capabilities(mmc); + omap_hsmmc_conf_bus_power(mmc); +#else writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, &mmc_base->capa); +#endif reg_val = readl(&mmc_base->con) & RESERVED_MASK; @@ -1071,6 +1134,10 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) + plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; + if (fdtdec_get_bool(fdt, node, "no-1-8-v")) + plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); From patchwork Tue Jan 30 15:01:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126235 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3440420ljd; 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[81.169.180.215]) by mx.google.com with ESMTP id w15si9524441eda.32.2018.01.30.07.04.01; Tue, 30 Jan 2018 07:04:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=BGdH7BPd; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id DB5E3C21E3A; Tue, 30 Jan 2018 15:02:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A77DAC21E45; Tue, 30 Jan 2018 15:02:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3E034C21E8B; Tue, 30 Jan 2018 15:02:12 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 9FFEBC21E8A for ; Tue, 30 Jan 2018 15:02:07 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2408024879; Tue, 30 Jan 2018 09:02:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324524; bh=c542K6RVQoIH3cWkk7JM65B7xwWYPo7vxVkXvXht3x0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BGdH7BPdKqbO0gwDWFdfV30reaLIpMxgTDDqzwlV2U6lqAqzhCCIoDHru/Cktr35Q 6330C3GJS648okjYSnDsmYbkbICKuEtvlTp3XoNTLKwUifi8QcZpbnjlJzgkvNrOOe Sd464JJhjQIV6TxaOpVu57njkrOBc8gTNVN8W2s0= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2462004934; Tue, 30 Jan 2018 09:02:04 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:03 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:03 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF23Hf012031; Tue, 30 Jan 2018 09:02:03 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:34 +0100 Message-ID: <1517324513-13875-6-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 05/24] mmc: omap_hsmmc: Enable DDR mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I In order to enable DDR mode, Dual Data Rate mode bit has to be set in MMCHS_CON register. Set it here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/omap_mmc.h | 1 + drivers/mmc/omap_hsmmc.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 507435a..6aca9e9 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -89,6 +89,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index c6b74a1..2f4909e 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; + if (mmc_is_mode_ddr(priv->mode)) + writel(readl(&mmc_base->con) | DDR, &mmc_base->con); + else + writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); + switch (priv->mode) { case MMC_HS_200: case UHS_SDR104: From patchwork Tue Jan 30 15:01:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126242 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3446294ljd; Tue, 30 Jan 2018 07:10:32 -0800 (PST) X-Google-Smtp-Source: AH8x225PgyymQlaWJII1HJeMfEigvaANYoXkq8xEbuZ9m5ciBn/VSNtRqFJGhEvSMm1zATYj+Ldi X-Received: by 10.80.155.7 with SMTP id o7mr39271708edi.105.1517325032016; Tue, 30 Jan 2018 07:10:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325032; cv=none; d=google.com; s=arc-20160816; b=K5q7235zDp2N51ndVMI/NwqofTWJ5IOk2CsAUFi73LjJkTlkitf0qWqM0KFh/vlap7 E2oysrimmEP1HF6XY1lZ8kt0ef0nNo2y4dyoskkrj17QPJljOLHFiUqrJ5btoIJwbJTH htPIxwk1Y2a476tc282yUc5ZSRwnpcMVa/A78/K9QQtWzehXpqo+oRWLyb3kI39ilQ/2 c4Jf9wKH4rtKFFqMhfxHw0pnwhf+nwG0NZhwpGT67xqyVk8tOVhb1ILd4PxkjpCM3TlG APu35D3aCHg8T6mZpmyFzUiLK1ZIXJ7lwNTaxUsnlrlr7+laicD+41eHbTb/jx4CczHO g+zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=fuWwZ5uUTnPW9x+RcmUh1uzj/GMWBx0EABcULPGGsxs=; b=cnRKGQqB+U6sl4znV48d6RHWhc/2cqAqdGTkrrPpHbdgP5dCUYXUUD49/mGkWWSQlQ PxBP1a+ej6hicEdnkPWJuHUnlyea4TggNgPZu/LjuF3WsRzYADEUAG8ccOpJim7/ETeM wWx7b8Cf+emDsu+lvtv9mak6mI7ksOZ4J/R8/oGVEbSd9EKxYh7362B1R3s5cUB+A0v8 LKLUAlZCu9g/tAC1sRvf9kGZJ5N3otyX83WFAVDEZfsvLdhPqtsxD0XKl/pQRavZexOS M/yvxNu5X1JEWcWhlYNEfUcV164XIaMD3Fv91OHwALuFAD4VGKVm4QBDD6Ue2lTsv1JV AEYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Wu77VS7b; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. 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Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None drivers/mmc/omap_hsmmc.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index ab4a095..57548ee 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1297,32 +1297,18 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) struct mmc_config *cfg = &plat->cfg; const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - int val; + int ret; plat->base_addr = map_physmem(devfdt_get_addr(dev), sizeof(struct hsmmc *), MAP_NOCACHE); - cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; - val = fdtdec_get_int(fdt, node, "bus-width", -1); - if (val < 0) { - printf("error: bus-width property missing\n"); - return -ENOENT; - } - - switch (val) { - case 0x8: - cfg->host_caps |= MMC_MODE_8BIT; - case 0x4: - cfg->host_caps |= MMC_MODE_4BIT; - break; - default: - printf("error: invalid bus-width property\n"); - return -ENOENT; - } + ret = mmc_of_parse(dev, cfg); + if (ret < 0) + return ret; + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; cfg->f_min = 400000; - cfg->f_max = fdtdec_get_int(fdt, node, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; if (fdtdec_get_bool(fdt, node, "ti,dual-volt")) From patchwork Tue Jan 30 15:01:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126243 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3446312ljd; Tue, 30 Jan 2018 07:10:32 -0800 (PST) X-Google-Smtp-Source: AH8x225d73wQWKH1nzd8eBIa+zJd8lhtrog6wvJ2LxzYmHBGQ5h91aOwPaV7u17d+fi3BghBJh0A X-Received: by 10.80.178.99 with SMTP id o90mr5143776edd.255.1517325032677; Tue, 30 Jan 2018 07:10:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325032; cv=none; d=google.com; s=arc-20160816; b=rQ4VJbGDwYM9G8TFoFcEJ8SdCgaUW6k7xP97qktNuSTIJvvSl0fj5aN0kWxO9LLagj esEvzdWqRRWXMMdlm/8r3lp1RKmzCLMF9cos3yamEkW8BYlU4U8ZiLmnlxYTxaWJn8zY ypbdlr6j51nYgI5kFs8C5qZep8SIq3IGPjw7ssAF1lMR29prEV+UIObVG+VcGFb47ZnH DtyWpjmXsqwjlkjqQrVKht10k6NSq0wFNhrU2q0Y7o+ntSal68ktgh3zLPQDU3+xnNlC hgN9tqhhaUV8mEXNHlGZDLEhkQuBgyNT4oZ0wcxoY8ipyWcXu/YfGgZ4gJHkw3iR4WXg euGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=4VaxPb1EUXiHu0aay2cqxqEIUKGXp79LL0v10lqIE7k=; b=hjADg//jjCLCoDpi05DY3O2ERgv/tJYDsJPusbL5Gnq1xefDrw/BhDw//JwN8Aczf5 GHOufYDK114L730NRD72YGXqkqXuwjBA0pwwEKAwWbTP3/a6/TjAWxtuui08LU9xa0G+ dRyrlQJ69X2uIC8+sujK+v5XAJuSrI4gBbi3ofH7ee59x+zmTqYj8QprcY3mkpi6emgT bEMGDJ45mjjxEv6NRQp7oW1Y5Se8w4mKreu41DzF5t5J4ZlnmtII6R8kC1F+yslvW5z/ YMt8cWuYvaW3pSUlakKnH54FO5YiEqUlOfq7nDJT8dn71amm4Eqez1KmmLSd+J03D94y uywA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=sliEm6V6; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g23si8327135edf.169.2018.01.30.07.10.32; Tue, 30 Jan 2018 07:10:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=sliEm6V6; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 4FEE4C21EA8; Tue, 30 Jan 2018 15:05:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 03623C21E40; Tue, 30 Jan 2018 15:02:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D561DC21DA6; Tue, 30 Jan 2018 15:02:17 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 21C1EC21E3A for ; Tue, 30 Jan 2018 15:02:12 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2Aui005641; Tue, 30 Jan 2018 09:02:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324530; bh=f/sd6mfJCtTQILJKzE3ZuywbqZsTaZtWupbczxg2ea8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sliEm6V6WVwm2MKds0CkXvZqgfsvsYwyLAw7bZUM243EJgiFUxOSuFMGihlwZBOU2 MQkL/7wCRBIuBkc5qSGgjL8g0IVi5kXb7vmY28+pUfpY9dG0h7s9CKOK/ccMa8yZgS z0+uL9Mpyv90UwvweNNj0fTJg/RnyYK45nYK6Q9Y= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2AYS001420; Tue, 30 Jan 2018 09:02:10 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:10 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:10 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF29Eu027915; Tue, 30 Jan 2018 09:02:09 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:39 +0100 Message-ID: <1517324513-13875-11-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 10/24] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 +++ arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 ++++++++++++++++++++++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index c997004..a8780ee 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -83,6 +83,9 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, struct iodelay_cfg_entry const *iodelay, int niodelays); +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); int __recalibrate_iodelay_start(void); void __recalibrate_iodelay_end(int ret); diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8798730..a9a9f75 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -272,3 +272,33 @@ err: __recalibrate_iodelay_end(ret); } + +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); +} diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 7546b3f..65465d1 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -15,9 +15,7 @@ #include #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index ff90b6d..975e6fd 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,9 +14,7 @@ #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_NR_DRAM_BANKS 2 From patchwork Tue Jan 30 15:01:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126249 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3449761ljd; Tue, 30 Jan 2018 07:14:32 -0800 (PST) X-Google-Smtp-Source: AH8x226PjcycZ2yTxFpUnZZH364ytLIDAKC87vMLxSZKzeDEAgk/Hv3+ws2cwI12R2s+fCW1US3T X-Received: by 10.80.240.205 with SMTP id a13mr51883945edm.77.1517325272060; Tue, 30 Jan 2018 07:14:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325272; cv=none; d=google.com; s=arc-20160816; b=xgmAO4ogAJNi4akmHh/m3NAc5YirqG0oT+7HvyyWIXcV8d/YJGQRXtZSOe4KTxlXCd 9RGa/gHL/JGNTGim+qY28gxtAu5Tw1UWOM2VBChVM9Gu9K17FSguyI/5r5rIpqNUa57b XTzYpvi5v44rjnGwEa456LO+TOufLcUxjvw3qqgpyFMsRtW9A+bFSuT9yYpDMrkGpzGH S8zBa8+IrcDpFqDi37g4l7Jyllhdmfi1it4Vb4tMmwXR2E0MLbmArAhxUU3rijJ1MCk2 2DgiCp9+b/2Ww0h1J2p+qbqYTf8/z3IFuVqDOYjGOoOtvVWwC7h7zDO3hHNOQ6bbcIjF uBDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=cgQRL1Heg0V/rbK0FDmOsbvrxNsYFE3ayzIuSYm7cL4=; b=nfDKF/kNWHtiou5Zy7SWDX4kNVAnuS7DlALb6166wQ+jgJQ+CRrW826EQcptVICEZ8 3dSzi0iguSOhKAE0qHMqUSIkEHRSBOMkgSuhz85NESS6+NQSpSe2XQtuL1DhOcNo6aez FBYh8E6MmTzp5x+llIZZpVspYkikR12Mc9E4zod/7eAQtt9y6Kh2gpoMoqjoCbhF7mCX OoeKAZw9rxDJy2H/Qny1en53jRz8LG/HWbikQxYLO+m5uqgE9VFRxIS33oI4VsJfSxYu qnP3eLsYhv0zLJ32gxQUq2efxG6u9aden75ijaZGrnGjG7bWeQYO5RSgRjSd9JAr0jUA hMlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=g8pJbGvx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id p4si1778495edm.328.2018.01.30.07.14.31; Tue, 30 Jan 2018 07:14:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=g8pJbGvx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 92EACC21E6C; Tue, 30 Jan 2018 15:06:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0517AC21EAB; Tue, 30 Jan 2018 15:02:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C03D9C21EE0; Tue, 30 Jan 2018 15:02:17 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 9AF89C21EAE for ; Tue, 30 Jan 2018 15:02:13 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2Clb005645; Tue, 30 Jan 2018 09:02:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324532; bh=tv8Z2Rik43jVdZ7Pr6lA9olZI6BGNP3+DaGkfnS9dOM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g8pJbGvx0/OLS8ILmfQSwtR7gUHeeL5eK/HPKY7eloe7J5EGLawim7/3ocGMYLv4m th8v1X3uEkkdyibm5XyzDREj2zYzWaFE8sl0Y2i5BOgRxcacpCrX8Mr+GVJzmdgCGP JeBlP6dAuiUKzYY8Q9/NbC2gO9Q8gtFkFIfZnE5w= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2BWW001450; Tue, 30 Jan 2018 09:02:11 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:11 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:11 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2A5S008182; Tue, 30 Jan 2018 09:02:11 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:40 +0100 Message-ID: <1517324513-13875-12-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 11/24] mmc: omap_hsmmc: Add support to set IODELAY values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. Add support to parse mux values and iodelay values from device tree and set these depending on the enumerated MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None drivers/mmc/omap_hsmmc.c | 372 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 372 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 57548ee..2b77422 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -34,6 +34,10 @@ #endif #include #include +#ifdef CONFIG_OMAP54XX +#include +#include +#endif #if !defined(CONFIG_SOC_KEYSTONE) #include #include @@ -57,6 +61,15 @@ DECLARE_GLOBAL_DATA_PTR; #define SYSCTL_SRC (1 << 25) #define SYSCTL_SRD (1 << 26) +#ifdef CONFIG_IODELAY_RECALIBRATION +struct omap_hsmmc_pinctrl_state { + struct pad_conf_entry *padconf; + int npads; + struct iodelay_cfg_entry *iodelay; + int niodelays; +}; +#endif + struct omap_hsmmc_data { struct hsmmc *base_addr; #if !CONFIG_IS_ENABLED(DM_MMC) @@ -83,6 +96,21 @@ struct omap_hsmmc_data { struct omap_hsmmc_adma_desc *adma_desc_table; uint desc_slot; #endif +#ifdef CONFIG_IODELAY_RECALIBRATION + struct omap_hsmmc_pinctrl_state *default_pinctrl_state; + struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; + struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state; + struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state; + struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state; + struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state; +#endif +}; + +struct omap_mmc_of_data { + u8 controller_flags; }; #ifndef CONFIG_OMAP34XX @@ -119,6 +147,7 @@ struct omap_hsmmc_adma_desc { #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0) #define OMAP_HSMMC_NO_1_8_V BIT(1) #define OMAP_HSMMC_USE_ADMA BIT(2) +#define OMAP_HSMMC_REQUIRE_IODELAY BIT(3) static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size); static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, @@ -261,6 +290,56 @@ void mmc_init_stream(struct hsmmc *mmc_base) } #if CONFIG_IS_ENABLED(DM_MMC) +#ifdef CONFIG_IODELAY_RECALIBRATION +static void omap_hsmmc_io_recalibrate(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct omap_hsmmc_pinctrl_state *pinctrl_state; + + switch (priv->mode) { + case MMC_HS_200: + pinctrl_state = priv->hs200_1_8v_pinctrl_state; + break; + case UHS_SDR104: + pinctrl_state = priv->sdr104_pinctrl_state; + break; + case UHS_SDR50: + pinctrl_state = priv->sdr50_pinctrl_state; + break; + case UHS_DDR50: + pinctrl_state = priv->ddr50_pinctrl_state; + break; + case UHS_SDR25: + pinctrl_state = priv->sdr25_pinctrl_state; + break; + case UHS_SDR12: + pinctrl_state = priv->sdr12_pinctrl_state; + break; + case SD_HS: + case MMC_HS: + case MMC_HS_52: + pinctrl_state = priv->hs_pinctrl_state; + break; + case MMC_DDR_52: + pinctrl_state = priv->ddr_1_8v_pinctrl_state; + default: + pinctrl_state = priv->default_pinctrl_state; + break; + } + + if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) { + if (pinctrl_state->iodelay) + late_recalibrate_iodelay(pinctrl_state->padconf, + pinctrl_state->npads, + pinctrl_state->iodelay, + pinctrl_state->niodelays); + else + do_set_mux32((*ctrl)->control_padconf_core_base, + pinctrl_state->padconf, + pinctrl_state->npads); + } +} +#endif static void omap_hsmmc_set_timing(struct mmc *mmc) { u32 val; @@ -269,6 +348,7 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) mmc_base = priv->base_addr; + omap_hsmmc_stop_clock(mmc_base); val = readl(&mmc_base->ac12); val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; @@ -306,6 +386,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) break; } writel(val, &mmc_base->ac12); + +#ifdef CONFIG_IODELAY_RECALIBRATION + omap_hsmmc_io_recalibrate(mmc); +#endif + omap_hsmmc_start_clock(mmc_base); } static void omap_hsmmc_conf_bus_power(struct mmc *mmc) @@ -1290,10 +1375,271 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, return 0; } #else + +#ifdef CONFIG_IODELAY_RECALIBRATION +static struct pad_conf_entry * +omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count) +{ + int index = 0; + struct pad_conf_entry *padconf; + + padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count); + if (!padconf) { + debug("failed to allocate memory\n"); + return 0; + } + + while (index < count) { + padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]); + padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]); + index++; + } + + return padconf; +} + +static struct iodelay_cfg_entry * +omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count) +{ + int index = 0; + struct iodelay_cfg_entry *iodelay; + + iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count); + if (!iodelay) { + debug("failed to allocate memory\n"); + return 0; + } + + while (index < count) { + iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]); + iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]); + iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]); + index++; + } + + return iodelay; +} + +static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle, + const char *name, int *len) +{ + const void *fdt = gd->fdt_blob; + int offset; + const fdt32_t *pinctrl; + + offset = fdt_node_offset_by_phandle(fdt, phandle); + if (offset < 0) { + debug("failed to get pinctrl node %s.\n", + fdt_strerror(offset)); + return 0; + } + + pinctrl = fdt_getprop(fdt, offset, name, len); + if (!pinctrl) { + debug("failed to get property %s\n", name); + return 0; + } + + return pinctrl; +} + +static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc, + char *prop_name) +{ + const void *fdt = gd->fdt_blob; + const __be32 *phandle; + int node = dev_of_offset(mmc->dev); + + phandle = fdt_getprop(fdt, node, prop_name, NULL); + if (!phandle) { + debug("failed to get property %s\n", prop_name); + return 0; + } + + return fdt32_to_cpu(*phandle); +} + +static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc, + char *prop_name) +{ + const void *fdt = gd->fdt_blob; + const __be32 *phandle; + int len; + int count; + int node = dev_of_offset(mmc->dev); + + phandle = fdt_getprop(fdt, node, prop_name, &len); + if (!phandle) { + debug("failed to get property %s\n", prop_name); + return 0; + } + + /* No manual mode iodelay values if count < 2 */ + count = len / sizeof(*phandle); + if (count < 2) + return 0; + + return fdt32_to_cpu(*(phandle + 1)); +} + +static struct pad_conf_entry * +omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads) +{ + int len; + int count; + struct pad_conf_entry *padconf; + u32 phandle; + const fdt32_t *pinctrl; + + phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name); + if (!phandle) + return ERR_PTR(-EINVAL); + + pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins", + &len); + if (!pinctrl) + return ERR_PTR(-EINVAL); + + count = (len / sizeof(*pinctrl)) / 2; + padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count); + if (!padconf) + return ERR_PTR(-EINVAL); + + *npads = count; + + return padconf; +} + +static struct iodelay_cfg_entry * +omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay) +{ + int len; + int count; + struct iodelay_cfg_entry *iodelay; + u32 phandle; + const fdt32_t *pinctrl; + + phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name); + /* Not all modes have manual mode iodelay values. So its not fatal */ + if (!phandle) + return 0; + + pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array", + &len); + if (!pinctrl) + return ERR_PTR(-EINVAL); + + count = (len / sizeof(*pinctrl)) / 3; + iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count); + if (!iodelay) + return ERR_PTR(-EINVAL); + + *niodelay = count; + + return iodelay; +} + +static struct omap_hsmmc_pinctrl_state * +omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode) +{ + int index; + int npads = 0; + int niodelays = 0; + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(mmc->dev); + char prop_name[11]; + struct omap_hsmmc_pinctrl_state *pinctrl_state; + + pinctrl_state = (struct omap_hsmmc_pinctrl_state *) + malloc(sizeof(*pinctrl_state)); + if (!pinctrl_state) { + debug("failed to allocate memory\n"); + return 0; + } + + index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode); + if (index < 0) { + debug("fail to find %s mode %s\n", mode, fdt_strerror(index)); + goto err_pinctrl_state; + } + + sprintf(prop_name, "pinctrl-%d", index); + + pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name, + &npads); + if (IS_ERR(pinctrl_state->padconf)) + goto err_pinctrl_state; + pinctrl_state->npads = npads; + + pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name, + &niodelays); + if (IS_ERR(pinctrl_state->iodelay)) + goto err_padconf; + pinctrl_state->niodelays = niodelays; + + return pinctrl_state; + +err_padconf: + kfree(pinctrl_state->padconf); + +err_pinctrl_state: + kfree(pinctrl_state); + return 0; +} + +#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ + do { \ + struct omap_hsmmc_pinctrl_state *s; \ + if (!(cfg->host_caps & capmask)) \ + break; \ + \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ + if (!s) { \ + debug("%s: no pinctrl for %s\n", \ + mmc->dev->name, #mode); \ + cfg->host_caps &= ~(capmask); \ + } else { \ + priv->mode##_pinctrl_state = s; \ + } \ + } while (0) + +static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc); + struct omap_hsmmc_pinctrl_state *default_pinctrl; + + if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) + return 0; + + default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default"); + if (!default_pinctrl) { + printf("no pinctrl state for default mode\n"); + return -EINVAL; + } + + priv->default_pinctrl_state = default_pinctrl; + + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12); + + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v); + OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs); + + return 0; +} +#endif + #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) { struct omap_hsmmc_plat *plat = dev_get_platdata(dev); + struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); + struct mmc_config *cfg = &plat->cfg; const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); @@ -1315,6 +1661,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; if (fdtdec_get_bool(fdt, node, "no-1-8-v")) plat->controller_flags |= OMAP_HSMMC_NO_1_8_V; + if (of_data) + plat->controller_flags |= of_data->controller_flags; #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); @@ -1340,9 +1688,13 @@ static int omap_hsmmc_probe(struct udevice *dev) struct omap_hsmmc_data *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; struct mmc *mmc; +#ifdef CONFIG_IODELAY_RECALIBRATION + int ret; +#endif cfg->name = "OMAP SD/MMC"; priv->base_addr = plat->base_addr; + priv->controller_flags = plat->controller_flags; #ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = plat->cd_inverted; #endif @@ -1363,14 +1715,34 @@ static int omap_hsmmc_probe(struct udevice *dev) mmc->dev = dev; upriv->mmc = mmc; +#ifdef CONFIG_IODELAY_RECALIBRATION + ret = omap_hsmmc_get_pinctrl_state(mmc); + /* + * disable high speed modes for the platforms that require IO delay + * and for which we don't have this information + */ + if ((ret < 0) && + (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) { + priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY; + cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) | + UHS_CAPS); + } +#endif + return omap_hsmmc_init_setup(mmc); } #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + +static const struct omap_mmc_of_data dra7_mmc_of_data = { + .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, +}; + static const struct udevice_id omap_hsmmc_ids[] = { { .compatible = "ti,omap3-hsmmc" }, { .compatible = "ti,omap4-hsmmc" }, { .compatible = "ti,am33xx-hsmmc" }, + { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data }, { } }; #endif From patchwork Tue Jan 30 15:01:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126250 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3449966ljd; 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[81.169.180.215]) by mx.google.com with ESMTP id d14si924230edj.432.2018.01.30.07.14.45; Tue, 30 Jan 2018 07:14:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=AyDo09KQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 05279C21EFB; Tue, 30 Jan 2018 15:05:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ECD53C21EE6; Tue, 30 Jan 2018 15:02:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id BEE5FC21E63; Tue, 30 Jan 2018 15:02:21 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 00994C21EA5 for ; Tue, 30 Jan 2018 15:02:16 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2Do1006639; Tue, 30 Jan 2018 09:02:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324533; bh=uDF951UHAxmKDFdx7wYZhJgcIcXIetgPxKHvXszOuZY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=AyDo09KQPgEv0npp5RLllsj/TvKqDkkbGJTqn957Ly+WuLC15RM9UKhFTXs3hBYjx pKi1LyGT0zRaFUHBbgSh0sa4lyVYYRY7kJ/MGVxFo21WxiukSnxqFivhF3SmSvxbdm oYw3H28jfk7Rfzm4o+f/c5jc+3J1xwAEX9taOzRM= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2D2B001474; Tue, 30 Jan 2018 09:02:13 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:12 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:12 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2Crp008207; Tue, 30 Jan 2018 09:02:12 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:41 +0100 Message-ID: <1517324513-13875-13-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 12/24] mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for different hw revisions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I AM572x SR1.1 requires different IODelay values to be used than that used in AM572x SR2.0. These values are populated in device tree. Add capability in omap_hsmmc driver to extract IOdelay values for different silicon revision. The maximum frequency is also reduced when using a ES1.1. To keep the ability to boot both revsions with the same dtb, those values can be provided by the platform code. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/arch-omap5/sys_proto.h | 7 ++++ arch/arm/include/asm/omap_mmc.h | 1 + drivers/mmc/omap_hsmmc.c | 58 ++++++++++++++++++++++------- 3 files changed, 52 insertions(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index a6b3557..d43cd7f 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -35,6 +35,12 @@ struct pad_conf_entry { u32 val; }; +struct mmc_platform_fixups { + const char *hw_rev; + u32 unsupported_caps; + u32 max_freq; +}; + struct omap_sysinfo { char *board_string; }; @@ -71,6 +77,7 @@ void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr); static inline u32 div_round_up(u32 num, u32 den) { diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 635ce1e..c50087e 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -70,6 +70,7 @@ struct omap_hsmmc_plat { struct mmc mmc; bool cd_inverted; u32 controller_flags; + const char *hw_rev; }; /* diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 2b77422..766cd09 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -96,6 +96,7 @@ struct omap_hsmmc_data { struct omap_hsmmc_adma_desc *adma_desc_table; uint desc_slot; #endif + const char *hw_rev; #ifdef CONFIG_IODELAY_RECALIBRATION struct omap_hsmmc_pinctrl_state *default_pinctrl_state; struct omap_hsmmc_pinctrl_state *hs_pinctrl_state; @@ -1368,6 +1369,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21)) cfg->b_max = 1; #endif + mmc = mmc_create(cfg, priv); if (mmc == NULL) return -1; @@ -1587,20 +1589,28 @@ err_pinctrl_state: return 0; } -#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ - do { \ - struct omap_hsmmc_pinctrl_state *s; \ - if (!(cfg->host_caps & capmask)) \ - break; \ - \ - s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ - if (!s) { \ - debug("%s: no pinctrl for %s\n", \ - mmc->dev->name, #mode); \ - cfg->host_caps &= ~(capmask); \ - } else { \ - priv->mode##_pinctrl_state = s; \ - } \ +#define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode) \ + do { \ + struct omap_hsmmc_pinctrl_state *s = NULL; \ + char str[20]; \ + if (!(cfg->host_caps & capmask)) \ + break; \ + \ + if (priv->hw_rev) { \ + sprintf(str, "%s-%s", #mode, priv->hw_rev); \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \ + } \ + \ + if (!s) \ + s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \ + \ + if (!s) { \ + debug("%s: no pinctrl for %s\n", \ + mmc->dev->name, #mode); \ + cfg->host_caps &= ~(capmask); \ + } else { \ + priv->mode##_pinctrl_state = s; \ + } \ } while (0) static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) @@ -1635,12 +1645,22 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) #endif #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#ifdef CONFIG_OMAP54XX +__weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + return NULL; +} +#endif + static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) { struct omap_hsmmc_plat *plat = dev_get_platdata(dev); struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev); struct mmc_config *cfg = &plat->cfg; +#ifdef CONFIG_OMAP54XX + const struct mmc_platform_fixups *fixups; +#endif const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); int ret; @@ -1664,6 +1684,15 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) if (of_data) plat->controller_flags |= of_data->controller_flags; +#ifdef CONFIG_OMAP54XX + fixups = platform_fixups_mmc(devfdt_get_addr(dev)); + if (fixups) { + plat->hw_rev = fixups->hw_rev; + cfg->host_caps &= ~fixups->unsupported_caps; + cfg->f_max = fixups->max_freq; + } +#endif + #ifdef OMAP_HSMMC_USE_GPIO plat->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); #endif @@ -1695,6 +1724,7 @@ static int omap_hsmmc_probe(struct udevice *dev) cfg->name = "OMAP SD/MMC"; priv->base_addr = plat->base_addr; priv->controller_flags = plat->controller_flags; + priv->hw_rev = plat->hw_rev; #ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = plat->cd_inverted; #endif From patchwork Tue Jan 30 15:01:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126240 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3445461ljd; Tue, 30 Jan 2018 07:09:37 -0800 (PST) X-Google-Smtp-Source: AH8x225TCA2hDAbkZSK4isX8VaJiaPandJT8r9kDT8EqExVFHrz4yxZ+r7lscXyJUdWtSFXtJzbI X-Received: by 10.80.245.92 with SMTP id w28mr51902273edm.73.1517324977670; Tue, 30 Jan 2018 07:09:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517324977; cv=none; d=google.com; s=arc-20160816; b=CtPVVwZUq6HQljaX4ExIbWzgrBdttj2StPU2a6Wno9kfyLnTGmY2p/baAkHh1Mefta ftXrQzCXqOM5TNUstM+fonEUFyZ/9lTabkd5HRtvdaDdH0CCmsSqoikLnjRmwciskb+U VYSxli1pXEBMCM+LAJGIMgA0wYzuJFYBXfbJn8WZ91oRyHMhM9eaeeT+o4jkuhl0aI2y qIK37JlLQabSa5grzkBqflFRuc2SKq9AJRGCMcmftdzcltnJN7GQWcUEASCDC6AFEpYK 2LKqGXWf+oLUIBhiiBN8TlVLWF4o8hQ9hbEFWmcCqcFNVCXMIpUOvEwX+XsPBO48fdOB pc8g== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id f35si322386edd.85.2018.01.30.07.09.37; Tue, 30 Jan 2018 07:09:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=IyzysEvN; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 1311BC21EAE; Tue, 30 Jan 2018 15:06:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B521BC21E3E; Tue, 30 Jan 2018 15:02:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A48D7C21E92; Tue, 30 Jan 2018 15:02:24 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id C02A0C21E64 for ; Tue, 30 Jan 2018 15:02:19 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2IY5005657; Tue, 30 Jan 2018 09:02:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324538; bh=STKFg1/ZjC+tN/XQHNFmINnCzvGfoWHfGi5MiNVvLnA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IyzysEvNm5llUljCAU/RT47ZnyLnv7hwlMwqf6jJ/DnuOIoozIHGN/Pt0+Xnjh4BT L3sRSU68fqVf3/0/zom6/6Hr5JJv6QDNGsH1dNRCkprlcKeXAPwxvrzgTxeMrnSG/J txCmONTTaYNp2JrmcTk5eiHkCG14uWLUBwtW7340= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2IGb001573; Tue, 30 Jan 2018 09:02:18 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:17 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:17 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2H9Q028028; Tue, 30 Jan 2018 09:02:17 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:45 +0100 Message-ID: <1517324513-13875-17-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 16/24] mmc: omap_hsmmc: allow mmc clock to be gated X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I mmc core has defined a new parameter *clk_disable* to gate the clock. Disable the clock here if *clk_disable* is set. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None drivers/mmc/omap_hsmmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 71608d1..0e80420 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1207,6 +1207,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; #endif + struct hsmmc *mmc_base = priv->base_addr; if (priv->bus_width != mmc->bus_width) omap_hsmmc_set_bus_width(mmc); @@ -1214,6 +1215,11 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); + if (mmc->clk_disable) + omap_hsmmc_stop_clock(mmc_base); + else + omap_hsmmc_start_clock(mmc_base); + #if CONFIG_IS_ENABLED(DM_MMC) if (priv->mode != mmc->selected_mode) omap_hsmmc_set_timing(mmc); From patchwork Tue Jan 30 15:01:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126254 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3451428ljd; Tue, 30 Jan 2018 07:16:24 -0800 (PST) X-Google-Smtp-Source: AH8x225vRBEHQ5euzCIi09BmSCwAV8ixNybhPpCX1Phm7MUJjztE2nGGEyAiPJp77utsoFP7Cqfi X-Received: by 10.80.175.4 with SMTP id g4mr37238368edd.156.1517325384085; Tue, 30 Jan 2018 07:16:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325384; cv=none; d=google.com; s=arc-20160816; b=quPeTW/BNV49bIan5FFJWHK/R/thEwXYKoDltfO4mlqAz5BKFKG56TITa/iVnPHzJv 9cLZ5b/tqzFc6hewwF/3k9N5RyYH1HpznV1v/JEaokq2IXn1NpUCOBg306MgVZ3UoB6n OITfYLU/XQysRJV94sbxIKfuYzwy/shpAk/+11SG1Uj33WN9fruQxsBPjNf5r6EjkpW6 EA6aHAZn+Lgn6SZrDJonp71qYQOMkZD6IHHcDfBuTxy/w1Qz9MnlyMgW/MWhb6f4+Czk LIJtnCvoT+fkhc5JQaKMTzfM7mMXkLifQcENr4/gFto6EdMg6gX2IqUPvj24KhJvyI/W yCLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=c6CoIpuTZihhDMoLddXd/S22fDX9ETMctiRG+ny3+OU=; b=izqXD1ig9NNdlxj399CeTjqLS6GBjUvz0K8FKcrHFAvarGmfpRYe3MR4ycy2BHql+B ajVTAgRcdySVTEPuuUeLUZarCgqPPgK3HDP/ksMwqY64UJWaYTkdWM1kQwJbjrw6krAA p0A1jTaN8+vVwpFeW//lpUiMvO12aT5w/SJJEzHGo8Qtxqsr0qS2iahUKTXr5FqQXvBJ wEbkRkPnE7pdq0wPMKEhivT8cpGe/ZHu0j5CXqIxLanMUL53j1x4btjnsekkH7npioah gXJ6B1jvtOtkhqBlgDClHoe8ErNUp/NmjU+l6mJB1OUBmMMmWtPqF88ab4A2oQAzuhH0 WazQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=lk4c5Vcc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id s7si682161edh.554.2018.01.30.07.16.23; Tue, 30 Jan 2018 07:16:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=lk4c5Vcc; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id AB164C21EEB; Tue, 30 Jan 2018 15:05:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CCE9AC21F01; Tue, 30 Jan 2018 15:02:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6AAC4C21E8A; Tue, 30 Jan 2018 15:02:29 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id D9A4FC21E64 for ; Tue, 30 Jan 2018 15:02:24 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2K1s027041; Tue, 30 Jan 2018 09:02:20 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324541; bh=oNowqrIF8WpelG/6n1o8PSdGGd5+O6E8bU7EPPCtoHw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lk4c5VccC6C+Q1nMvafEgPcardo7w6LQ5Jr3IyxMmst/AzvYNfgkTXN34cs9PF/ZD Z462XB8MBriKt14M08a/tCT6IKidbnYj2uQ6OHc+DU+XFmi+4vMo1lvOO7N4QIbdJg ZLQc3GpdpQrYhsdKbHfynt/sygLw4XN7cvIBN+tM= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2Ksg005261; Tue, 30 Jan 2018 09:02:20 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:20 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:20 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2JY2008309; Tue, 30 Jan 2018 09:02:20 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:47 +0100 Message-ID: <1517324513-13875-19-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Praneeth Bajjuri , u-boot@lists.denx.de, Vishal Mahaveer Subject: [U-Boot] [PATCH v3 18/24] ARM: OMAP5: set mmc clock frequency to 192MHz X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Now that omap_hsmmc has support for hs200 mode, change the clock frequency to 192MHz. Also change the REFERENCE CLOCK frequency to 192MHz based on which the internal mmc clock divider is calculated. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/omap_mmc.h | 4 ++++ arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index ee2e78b..3d718c0 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -135,7 +135,7 @@ /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) /* CM_L3INIT_SATA_CLKCTRL */ #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index c6129c5..3d70148 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -199,7 +199,11 @@ struct omap_hsmmc_plat { #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) /* Clock Configurations and Macros */ +#ifdef CONFIG_OMAP54XX +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#else #define MMC_CLOCK_REFERENCE 96 /* MHz */ +#endif /* DLL */ #define DLL_SWT BIT(20) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index bb05e19..7fc3836 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -438,17 +438,17 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); - /* Enable 96 MHz clock for MMC1 & MMC2 */ + /* Enable 192 MHz clock for MMC1 & MMC2 */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, From patchwork Tue Jan 30 15:01:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126237 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3444139ljd; Tue, 30 Jan 2018 07:08:07 -0800 (PST) X-Google-Smtp-Source: AH8x227+8FQRuaxeFYvObxsZLrnB8FFnX9+fPxcqBucSfTbPnWucmKxAvEqB1YlfCB4k3Tj3jCvF X-Received: by 10.80.179.146 with SMTP id s18mr53348973edd.190.1517324887000; Tue, 30 Jan 2018 07:08:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517324886; cv=none; d=google.com; s=arc-20160816; b=CjPjf0lYIesjMRQWMsNGFJbiotA+tO39gsmL2hWlEPyqJ7cUEv2q01/bow5qWUemDX OfT/QKVS9A0Kb1nUb9tOxekVAyG2a5saw79wFGXP/H9doyl/XJ7t0gf0QXaP6EG7W/QH RpSzSw9FUzrHx1PUVzSOTivruCS8BvaWYwVGd0KwgErwCWMmD6G+xUhBgzBpD//NYxoc JNPZ2RizZxKbjJGXu1+e6yUK3AzqmxNhw1LLhfVkcB9tHr7FhPc6hHHm1RLw8EOq6B6o pm2SMYrG715W8pHzP7fjTryYLXgXKxnVs2P47SSuuEY/9uSKq+dppYdqU72dRJ3R7yvF zSlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=d35WbpoGy6elY1ofQs7jJiecnmvjZzrVghF9hiJtNoU=; b=WGmZ/ZghGNPv93CbrY2vOfCX8BPoAfWJemev+/CvqEF47Z5TrEWd3pCx0XuhGBg6/n xv3hGvZoraqgs+bJs9iuXMX3S2SFYgz1AWZW3w8qHFhNJxEyA+leeaOYTShOch2kBK7F rENmxRMT/ieb5PR4I0yMwoNM1FZOOLh1FfkW0yM9lQ2H6uv+hqMtF/iNxTifh3py0Bss w1/uOMUTgvV+iiBF34D/4nmwoiLMpw2unr/dnPmCbuSKbNaJLsToJ7r8ApDOE51Y7VA6 7fL0t+eDE5iMtJPTyGD7YHhOO0rAGlmNiBSMOGh0za39MlWY489PI2+QrVbN0esGtqSN VJ2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DtRdiy1c; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g27si3305732edf.136.2018.01.30.07.08.06; Tue, 30 Jan 2018 07:08:06 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DtRdiy1c; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 9127CC21EF1; Tue, 30 Jan 2018 15:05:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0CCD5C21E5D; Tue, 30 Jan 2018 15:02:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EAF84C21EF1; Tue, 30 Jan 2018 15:02:29 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id 07CC0C21E93 for ; Tue, 30 Jan 2018 15:02:24 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2M59027049; Tue, 30 Jan 2018 09:02:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324542; bh=/E+BMZ52W2QYp7pg5qn9bZujRoNR3i0xfWcF01F+VEk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DtRdiy1ck0H8ZurwRc+2oO+TBGJAo00GpNa/0ssrxJXkhyf1WVcj5LhjpEbzA+VRR HpsYUXVRsK+tGfX/79sGZBsLp4n0h+h7+VJ67Wws3y8om5GVExYQv1XWBigENw4+VZ Y7iqnahopPs1bEkB37nBR4H+CeJNVCh+WGF22YPE= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2LQA005298; Tue, 30 Jan 2018 09:02:21 -0600 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:21 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:21 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2Kqf008333; Tue, 30 Jan 2018 09:02:21 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:48 +0100 Message-ID: <1517324513-13875-20-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 19/24] ARM: dts: DRA7: use new dra7-specific compatible string X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Use the new compatible string "ti,dra7-hsmmc" that was specifically added for dra7 and dra72. This is required since for dra7 and dra72 processors iodelay values has to be set unlike other processors. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None arch/arm/dts/dra7.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi index 02a136a..9061843 100644 --- a/arch/arm/dts/dra7.dtsi +++ b/arch/arm/dts/dra7.dtsi @@ -1056,7 +1056,7 @@ }; mmc1: mmc@4809c000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x4809c000 0x400>; interrupts = ; ti,hwmods = "mmc1"; @@ -1070,7 +1070,7 @@ }; mmc2: mmc@480b4000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480b4000 0x400>; interrupts = ; ti,hwmods = "mmc2"; @@ -1082,7 +1082,7 @@ }; mmc3: mmc@480ad000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480ad000 0x400>; interrupts = ; ti,hwmods = "mmc3"; @@ -1095,7 +1095,7 @@ }; mmc4: mmc@480d1000 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,dra7-hsmmc", "ti,omap4-hsmmc"; reg = <0x480d1000 0x400>; interrupts = ; ti,hwmods = "mmc4"; From patchwork Tue Jan 30 15:01:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 126252 Delivered-To: patch@linaro.org Received: by 10.46.84.92 with SMTP id y28csp3450786ljd; Tue, 30 Jan 2018 07:15:40 -0800 (PST) X-Google-Smtp-Source: AH8x225ZIO7tPLO1ctDS+IiIGRolX3n8UzU6qKRqjd+oBatbKsiLsORHrpGrGhbhiOcW3muO1uE9 X-Received: by 10.80.145.79 with SMTP id f15mr52877770eda.283.1517325340871; Tue, 30 Jan 2018 07:15:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517325340; cv=none; d=google.com; s=arc-20160816; b=zdy7xlUW47LdB2ebkLbs+cQhYDJvWrO+xz3dXtJcUi0NkX7kCtOThoQI7SW5e3RuEp SNUEW7zreuISLIdGC5FteKFhn88zXQ88Ju4lNoB7tIpDyE0VE6eL0gLwSe7stk6wQfht xfM0HCQoMJwmHQxQMVKV9+woy9iP4CPPi2t4J3Z52H+Pf5gTzMpVHTnH2hFtk/52F22x VueGIcDXoq1GYLFphKKfnohYDnOe/CiNglHfvynd+PXgCCaWq8gzHD6vLvnlCIMoxdkp KKDH2PoKks0aEc5wYRWRSO0xj4iUeb8JclMSHg/DGDnqCQH49pztCib5YaQY/w3rBQ7a Y++w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=6TQtSdh+ehnBsSig9kO1gpnOXCBOAjiPicYkp4/S7KA=; b=dOKv7o5KtttEKTpvfMHMoWPzXKsUIN3f1r5SZL53M2WVcfyofz9AB/TZIMlba7UQ9T BxTCohhqnY/yrFFIEMVjNPvjlsX5H1ukoniE7NIC3YdkXDr4YHmBg1/vSfIeW49xIabc RB/kxAOUymLtafqHxY/25XRhHTcUODkiRLg8TaeHgf7j29PBcJLA2TcWmts4XPKurw8X NnJw5hKUgcWElKDwl9Xc1ywok0CDnbBMSyWk/75G97PtkOIJh4OOfQKxLYd+kFqArVck qKYl5LfYtiSnqQkY2yrQskSmAa8dUfgfKk7mCtrBT/kNEl60RXPYjSVwUA1sWV+ocJpT 8pDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jJ/kW/0E; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id w36si5666701edd.51.2018.01.30.07.15.40; Tue, 30 Jan 2018 07:15:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=jJ/kW/0E; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 7D028C21E37; Tue, 30 Jan 2018 15:10:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3C099C21DE5; Tue, 30 Jan 2018 15:04:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C8FBC21EC2; Tue, 30 Jan 2018 15:02:34 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id C8828C21E40 for ; Tue, 30 Jan 2018 15:02:28 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2RYo005688; Tue, 30 Jan 2018 09:02:27 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324547; bh=H8eWX13Nkht1JgtWxDkIZyJEkl4CtebKSqxvTiKCNQI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jJ/kW/0E59otuxrixOG3ZAeS/z0uH2zaOglSeEhxZCmjiael8R6L5uq33S1Z2lFs8 01pr4F8nOMxB5bGz0vb+deTFQnjKZvjfO5/A0z3tV7vGgN0ob0HmsPeFBfoaaLnVII tg2FyLGdPN5e8bgzJgVTeRoJSkCWDE29haERxguQ= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2RN9001738; Tue, 30 Jan 2018 09:02:27 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:26 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:26 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2QbT032396; Tue, 30 Jan 2018 09:02:26 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:52 +0100 Message-ID: <1517324513-13875-24-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 23/24] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None board/ti/am57xx/board.c | 30 ++++++++++++++++++++++++++++++ board/ti/dra7xx/evm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 1128784..9c1e2ef 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "../common/board_detect.h" #include "mux_data.h" @@ -815,6 +816,35 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &am57x_es1_1_mmc1_fixups; + else + return &am57x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6ecf971..c62724e 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -866,6 +866,35 @@ void board_mmc_poweron_ldo(uint voltage) palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } } + +static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &dra7x_es1_1_mmc1_fixups; + else + return &dra7x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #ifdef CONFIG_USB_DWC3