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Wed, 31 Jan 2018 10:09:50 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:50 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/19] clk: meson: use dev pointer where possible Date: Wed, 31 Jan 2018 19:09:27 +0100 Message-Id: <20180131180945.18025-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 'dev' pointer is directly available in gxbb and axg clock controller, so consistently use it instead of going the through the 'pdev' pointer once in while Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 8 ++++---- drivers/clk/meson/gxbb.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index b5dacfde64bb..0db0fc0762e2 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -804,7 +804,7 @@ static int axg_clkc_probe(struct platform_device *pdev) void __iomem *clk_base; int ret, clkid, i; - clkc_data = of_device_get_match_data(&pdev->dev); + clkc_data = of_device_get_match_data(dev); if (!clkc_data) return -EINVAL; @@ -812,9 +812,9 @@ static int axg_clkc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; - clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + clk_base = devm_ioremap(dev, res->start, resource_size(res)); if (!clk_base) { - dev_err(&pdev->dev, "Unable to map clk base\n"); + dev_err(dev, "Unable to map clk base\n"); return -ENXIO; } @@ -849,7 +849,7 @@ static int axg_clkc_probe(struct platform_device *pdev) ret = devm_clk_hw_register(dev, clkc_data->hw_onecell_data->hws[clkid]); if (ret) { - dev_err(&pdev->dev, "Clock registration failed\n"); + dev_err(dev, "Clock registration failed\n"); return ret; } } diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index a5f25cc1944c..423abcb8ef88 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -1950,7 +1950,7 @@ static int gxbb_clkc_probe(struct platform_device *pdev) int ret, clkid, i; struct device *dev = &pdev->dev; - clkc_data = of_device_get_match_data(&pdev->dev); + clkc_data = of_device_get_match_data(dev); if (!clkc_data) return -EINVAL; From patchwork Wed Jan 31 18:09:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126404 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp972959ljc; Wed, 31 Jan 2018 10:15:45 -0800 (PST) X-Google-Smtp-Source: AH8x224YU/I6cO6nLtG+9dyRWBpuol96kpZXoQPVLBs2q9YyILDSi1PeMqlU1elwiOIO/pWMBwt6 X-Received: by 2002:a17:902:b7cb:: with SMTP id v11-v6mr29377137plz.393.1517422545670; Wed, 31 Jan 2018 10:15:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422545; cv=none; d=google.com; s=arc-20160816; b=fp8oNnme4XdSIuk3P0Tq1ZrzoQRNL9qkgnzGFc+wnNICzHWyvPyLfA1liUaCXH8RTK Lrc0nqEB7eZGxLBw+uz2MI1Z0HNSU5RREnlyYsTVnoZu68PYPkkrWN4Dq4q/Ysawjl+G oNXZZx1EroCQLVmT4mi1X5TeqOSYUcx6uhjil2LjGBuj4II6GNyPqqObDcucAxPrLurC S1G6u/AA9QWftCTrH+4654zyckmDzz6j82H5U+4VrG50Jw9My5a/4rTgv2BoVlBCIPpS NV2BHS24yuKKiunQGpIr/XqaxI8ofGSk76WJe3iPiGX3ivCNjTyX2NbDG5IxTSwf8Bce qnew== ARC-Message-Signature: i=1; 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Fixing this by the using the devm variant. In reality, the leak would never happen since these controllers are never unloaded once in use ... still, this is worth cleaning. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 4 ++-- drivers/clk/meson/gxbb.c | 5 +++-- drivers/clk/meson/meson8b.c | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 0db0fc0762e2..2f2b3845c01d 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -854,8 +854,8 @@ static int axg_clkc_probe(struct platform_device *pdev) } } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - clkc_data->hw_onecell_data); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clkc_data->hw_onecell_data); } static struct platform_driver axg_driver = { diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 423abcb8ef88..17f44ac751b3 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2002,8 +2002,9 @@ static int gxbb_clkc_probe(struct platform_device *pdev) goto iounmap; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - clkc_data->hw_onecell_data); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clkc_data->hw_onecell_data); iounmap: iounmap(clk_base); diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 3ffea80c1308..abac079ff77f 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -878,8 +878,8 @@ static int meson8b_clkc_probe(struct platform_device *pdev) return ret; } - return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, - &meson8b_hw_onecell_data); + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &meson8b_hw_onecell_data); } static const struct of_device_id meson8b_clkc_match_table[] = { From patchwork Wed Jan 31 18:09:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126403 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp972615ljc; Wed, 31 Jan 2018 10:15:23 -0800 (PST) X-Google-Smtp-Source: AH8x226Q+86/I7Y/7jxsJpOIlZTsLYutuuvW0fCEEQzZSlDfgyGTDWcRa/OoPUIiByJH2XkuIY1t X-Received: by 10.99.109.77 with SMTP id i74mr252624pgc.380.1517422523135; Wed, 31 Jan 2018 10:15:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422523; cv=none; d=google.com; s=arc-20160816; b=VRGDd7uZSJLfHiPS6Ce7MUjfK4xQeiwAUsdBRFZ1flqHqghfsJS5z5ktOHjMzLXzsr nKAagFpiCU7zDu3gn1choC9PRwJ/rnjyO056vbD7Mz1vP/nFl6CWiCnYDt8n3fnQ0vLd LaWARBd4r0vHFzKvrxrD14aBTQBjSPkRc9xm9COKONlw8TJ+x/73VvJRNW9YXLoT1kkE ScZUXAvImKCm4XyuvLH5oK0dxc6veejQYyCMjkMQx0Y7E8F0i1UhN2yqHYUNVU0L6ik2 /9XUBMv9dc6i8mM8NWG0CyubA5P+jSlvSgPbC3fdl6ixlxFHR0DI1e56K9Kc5NOKM3ma p7GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=01ty/OQ+wCVmfw367gGl5UXJI0td1BrQUYLs9s91Cds=; b=cdi6tedAjdlsSeJMoeK3JUpxMc1Uywev0h7gxB5b8IBhbruJ0iZej8B2AzmlhIgx9p CNVF85cZa7m9NScAlxfN6qByluy+SYy7QPVryeDjuxf66GMoH3UWqMaHqG4578ZhX9qN h0iw3yz7+6VtyxEAk3SghGjZkEQZPfIgo5q56hdrO6hQG4iHmyulfm4J6+6Eq49AK7TD mYmI4htmwWY0p1y5+tyjF6lZL/b2AJ0FqYLOVKRvhr3RBpyhquEDAj8T+h+LKvKDC/JB 750yOPXRWhHja3L/BUAfTh98cIJgN/1zksOG/IOheY8LWG/D8RKl/cgn+fvKtiz7qsjd 0OtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=RgJ/mnp9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 31 Jan 2018 10:09:52 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:52 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/19] clk: meson: only one loop index is necessary in probe Date: Wed, 31 Jan 2018 19:09:29 +0100 Message-Id: <20180131180945.18025-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We don't need several loop index variables in the probe function This is far from being critical but since we are doing a vast rework of meson clock controllers, now is the time to lower the entropy a bit Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 8 ++++---- drivers/clk/meson/gxbb.c | 13 ++++++------- drivers/clk/meson/meson8b.c | 8 ++++---- 3 files changed, 14 insertions(+), 15 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 2f2b3845c01d..81565b025b70 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -802,7 +802,7 @@ static int axg_clkc_probe(struct platform_device *pdev) const struct clkc_data *clkc_data; struct resource *res; void __iomem *clk_base; - int ret, clkid, i; + int ret, i; clkc_data = of_device_get_match_data(dev); if (!clkc_data) @@ -841,13 +841,13 @@ static int axg_clkc_probe(struct platform_device *pdev) clkc_data->clk_dividers[i]->reg = clk_base + (u64)clkc_data->clk_dividers[i]->reg; - for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { + for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { /* array might be sparse */ - if (!clkc_data->hw_onecell_data->hws[clkid]) + if (!clkc_data->hw_onecell_data->hws[i]) continue; ret = devm_clk_hw_register(dev, - clkc_data->hw_onecell_data->hws[clkid]); + clkc_data->hw_onecell_data->hws[i]); if (ret) { dev_err(dev, "Clock registration failed\n"); return ret; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 17f44ac751b3..e6adab49c0ba 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -1947,7 +1947,7 @@ static int gxbb_clkc_probe(struct platform_device *pdev) { const struct clkc_data *clkc_data; void __iomem *clk_base; - int ret, clkid, i; + int ret, i; struct device *dev = &pdev->dev; clkc_data = of_device_get_match_data(dev); @@ -1988,16 +1988,15 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; - /* - * register all clks - */ - for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) { + + /* Register all clks */ + for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { /* array might be sparse */ - if (!clkc_data->hw_onecell_data->hws[clkid]) + if (!clkc_data->hw_onecell_data->hws[i]) continue; ret = devm_clk_hw_register(dev, - clkc_data->hw_onecell_data->hws[clkid]); + clkc_data->hw_onecell_data->hws[i]); if (ret) goto iounmap; } diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index abac079ff77f..ffadad27375e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -806,7 +806,7 @@ static const struct reset_control_ops meson8b_clk_reset_ops = { static int meson8b_clkc_probe(struct platform_device *pdev) { - int ret, clkid, i; + int ret, i; struct clk_hw *parent_hw; struct clk *parent_clk; struct device *dev = &pdev->dev; @@ -844,13 +844,13 @@ static int meson8b_clkc_probe(struct platform_device *pdev) * register all clks * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 */ - for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) { + for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) { /* array might be sparse */ - if (!meson8b_hw_onecell_data.hws[clkid]) + if (!meson8b_hw_onecell_data.hws[i]) continue; /* FIXME convert to devm_clk_register */ - ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]); + ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]); if (ret) return ret; } From patchwork Wed Jan 31 18:09:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126402 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp972310ljc; Wed, 31 Jan 2018 10:15:02 -0800 (PST) X-Google-Smtp-Source: AH8x225kOtFZoF/pFZGQOkqwMtFWoYS2ZvA3xwxGm1eIq3TZa3ierCbX/tOileZ491hxlKNedfAH X-Received: by 10.101.74.129 with SMTP id b1mr27728301pgu.317.1517422502383; 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[209.132.180.67]) by mx.google.com with ESMTP id 33-v6si2776255plu.508.2018.01.31.10.15.02; Wed, 31 Jan 2018 10:15:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=YwFEPemc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754030AbeAaSO3 (ORCPT + 27 others); Wed, 31 Jan 2018 13:14:29 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:39170 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753298AbeAaSJy (ORCPT ); Wed, 31 Jan 2018 13:09:54 -0500 Received: by mail-wr0-f196.google.com with SMTP id f6so14388304wra.6 for ; Wed, 31 Jan 2018 10:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XoCwyv3z7MI/oYAqi2dpM7HJlI5GXUwayYtCQqMMLwE=; b=YwFEPemcnVscz36PXu16HOhTSp57QalI1ewgSQ7mCWpSbG8qeNhK2FTHs/hHkLOqfF q9I1ZuSw+wlY/zKJvIIKm8NLnbRJ8akCSUBH1qQZ6P5q+syLergKiGgino8YAV1OOusl 1Uqax4hMw80nb/meahV/LG5ajINZqPTMPHhTd5n/1JjKOjUhJq2BONbP08QDvAIEVW7u 1iC6Jxrx7k+1J5l2nm2mmHd6Cqi9gAnRclWvFVBkgOOSUdNnrkl+uD50+c4fFlGkgoV0 IwG31l9Geqr8UivTgCZAuaEJ78CZUL+huMz/5S43KXB4+EbIvh8fOH12mwc0bU1Vu1kp 723g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XoCwyv3z7MI/oYAqi2dpM7HJlI5GXUwayYtCQqMMLwE=; b=PpnyOnWd1kaxE61lSV5/pthZYRo9H/yqT6tZqsuxC+MzYzIp0Pq6fWdF/+lMvY1WnX NpTBV/7N5/WC2KMP59cld9miEIcCrF7/8p+V6B7ICpbd77SPKi5uag7E3CWUYMn6ucJ1 bt9ryTJks/HKzniJjCAnwFYG5/dow4y5KrdckRkOurk9nBxgRmPPNIhukR9cfSV2Pbhd zCmHI1wM4D6ayl0W82sVodUU21cUZCEARRnCnOuc29FPGL4owaf8wTF637v8L2OmygLj WdabdaxqHnfcpv/yDuh1xS9JOTskSEYJsL6Qg73a1TcGl50uLnx7WYq236+s3wW3kA0G +ngA== X-Gm-Message-State: AKwxytcQ2CeqDVgwEZ0NAFVeByLqbLReGac7YKSKojIxPWB5DGnuRbL/ 3SMQNrfxgM0bl4XcvmTZYysgzA== X-Received: by 10.223.173.119 with SMTP id p110mr16001416wrc.69.1517422193522; Wed, 31 Jan 2018 10:09:53 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:53 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/19] clk: meson: remove obsolete comments Date: Wed, 31 Jan 2018 19:09:30 +0100 Message-Id: <20180131180945.18025-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 5 ----- drivers/clk/meson/gxbb.c | 6 ------ drivers/clk/meson/meson8b.c | 1 - 3 files changed, 12 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 81565b025b70..f84927e76f88 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e6adab49c0ba..6609024eee00 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -575,12 +575,6 @@ static struct meson_clk_mpll gxbb_mpll2 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ - static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index ffadad27375e..db017c29a84c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -849,7 +849,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (!meson8b_hw_onecell_data.hws[i]) continue; - /* FIXME convert to devm_clk_register */ ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]); if (ret) return ret; From patchwork Wed Jan 31 18:09:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126388 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp968211ljc; Wed, 31 Jan 2018 10:10:13 -0800 (PST) X-Google-Smtp-Source: AH8x226ueitSpbKQWvZ47qdqwjb3L4qs6kt0+slDgglr7WyTrJH8WmNoFriatnzhmdMwar4WssWi X-Received: by 2002:a17:902:8b88:: with SMTP id ay8-v6mr16009036plb.197.1517422213096; Wed, 31 Jan 2018 10:10:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422213; cv=none; d=google.com; s=arc-20160816; b=PnuNC38d7dFO9/O9GqbKoxc8A0GEytym0gLfU106MtOVOrF1ZKfczHPMPBPkqGmmQk 7H3Nl5aFnIamWPaLj87RbgLKZiDt8JjSM8h3KLE3w4rKQaR3zNnJxIwa2cbHqbW8RF9q 3rNZ5B6pqufmVHMf7SQ591myrHoTsaswv+TdBwPsk8s46DfaFxIY0chlDTgDNuqEBXRG n43yFyN6n3A13SWlNkWQFJiyzHnCfkE+F7enU4VKB39tlGoJPHrKoASi3zawioM46Gv4 zY88m9uDFFHDmWRidBqZrmecGD3oS21fct4cF13HVOmdOW57UAR4cdXAcz+wtSM0neKK A5vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Hrir8fzh5kJeAHIC9JwsbQQEbOmxLuwpuC8dWLdAMfU=; b=Vl2c2EcVVxF39JnpgmZ0czsYU1HAEzdXJFTuZFGKCXgApdBgx8oFxyspw9UjCdeZvc F8CIJtew6LnAFQhN4eF9BFJ2Gj4NkKoR/A2FIGBMC7vubrjodZhQRQkMEf2olwXVlfjK ioAk999jW9F8o5U2vMP169jTZ2eQjQDD6j689K2IA7H/Ekl97/rwjJUFBbHRSUS+59Wq cvGP0tMQQTApqXZ7jBSngsBDcapRdx9Ax3onQCngWDROwVtJroirylUpaSX5Hdn+X4Xc SBg5IRKiJ5RA76nhfss0bAstX8RLjZgwgsYsyPRcec2lLCrRd+NUSU/bApphzUONJW2z y2hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=mVYNYw0H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9-v6si5973908pln.211.2018.01.31.10.10.12; Wed, 31 Jan 2018 10:10:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=mVYNYw0H; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753883AbeAaSKK (ORCPT + 28 others); Wed, 31 Jan 2018 13:10:10 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:35229 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753635AbeAaSJ4 (ORCPT ); Wed, 31 Jan 2018 13:09:56 -0500 Received: by mail-wr0-f195.google.com with SMTP id w50so16033694wrc.2 for ; Wed, 31 Jan 2018 10:09:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Hrir8fzh5kJeAHIC9JwsbQQEbOmxLuwpuC8dWLdAMfU=; b=mVYNYw0HnSvDk2V8IDLynrHMVJPl7CFNP0kbuftyzvbKDXUvJzPopYArTsmQT3OcJP lEOAZKVCOeevLBGCKh4XQO+82tMaYTfkqHuyVlGn01dyuaW4N1JX6GgxYyf5IK3YlBvl QjPdr/yH5UOTacOBCX2yPJRP0iPikw4QYTlqbbIb0D+nIzgotLc0LiEdfsfxJDsbj32S upQuRYnBu0a5zs2E4A3nBVI+DEx6TR6vgp56kI+91gNUuZW5UqBhZL+Xf+ED58Wp5c2k X93x0k9ew7u6SpATfNCNIuB6lxguqJp3aTzV79vzqNVZaEkdXEswVM1im5wuMDg+0kV/ eeqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Hrir8fzh5kJeAHIC9JwsbQQEbOmxLuwpuC8dWLdAMfU=; b=DdwvEHUJa36gAl/OntOjANw7gmjMrgU9LPSA3gR1L3CnXEoiMEiOGRyg9iIFyeD0EH sS8uS1lRwmiuVREqxSsYYDemi2BcaBYKFWl6WP3PrJhhWVEXspb0/hqgXJdTs2xq7AKK PuFhH7e9blQto4ydDukulV0rfcr/bn8E2/YrjSSVff4Kh3BZq0KGY2Xd+eTw5NXPUxIm YjB4Pbs8zKpBKdQsHGjYIuosmXmjtZQdff7tW0THJ5vY4g6DYcfviugpp6iD6LgVJ7IP GqyehGpWMmSHRUxVoYohL616VAOtV8pe/a2Cud3akL1IswH2ajKwaG9xcuXracH4A1wc IcCg== X-Gm-Message-State: AKwxytdWr9/CE/Dsgm61nnBVmn3RB5s66lTZuR8Xa8cZMSPoiHI/v513 8SzAN5O4aEc+sMijgeZS3znPSQ== X-Received: by 10.223.135.184 with SMTP id b53mr21969683wrb.204.1517422194646; Wed, 31 Jan 2018 10:09:54 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:54 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/19] clk: meson: add regmap clocks Date: Wed, 31 Jan 2018 19:09:31 +0100 Message-Id: <20180131180945.18025-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Meson clock controllers needs to move the classical iomem registers to regmap. This is triggered because the HHI controllers found on the GXBB and GXL host more than just clocks. To properly handle this, we would like to migrate HHI to syscon. Also GXBB AO clock controller already use regmap, AXG AO and Audio clock controllers will as well. The purpose of this change is to provide a common structure to these meson controllers (and possibly others) for regmap based clocks. This change provides the basic gate, mux and divider, based on the helpers provided by the related generic clocks Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 4 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-regmap.c | 166 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clk-regmap.h | 111 +++++++++++++++++++++++++++ 4 files changed, 282 insertions(+) create mode 100644 drivers/clk/meson/clk-regmap.c create mode 100644 drivers/clk/meson/clk-regmap.h -- 2.14.3 diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 7694302c70a4..e97e85077da1 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -3,6 +3,10 @@ config COMMON_CLK_AMLOGIC depends on OF depends on ARCH_MESON || COMPILE_TEST +config COMMON_CLK_REGMAP_MESON + bool + select REGMAP + config COMMON_CLK_MESON8B bool depends on COMMON_CLK_AMLOGIC diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 3c03ce583798..11a50586666a 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-div obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o +obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c new file mode 100644 index 000000000000..3645fdb62343 --- /dev/null +++ b/drivers/clk/meson/clk-regmap.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 BayLibre, SAS. +// Author: Jerome Brunet + +#include "clk-regmap.h" + +static int clk_regmap_gate_endisable(struct clk_hw *hw, int enable) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); + int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; + + set ^= enable; + + return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), + set ? BIT(gate->bit_idx) : 0); +} + +static int clk_regmap_gate_enable(struct clk_hw *hw) +{ + return clk_regmap_gate_endisable(hw, 1); +} + +static void clk_regmap_gate_disable(struct clk_hw *hw) +{ + clk_regmap_gate_endisable(hw, 0); +} + +static int clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_gate_data *gate = clk_get_regmap_gate_data(clk); + unsigned int val; + + regmap_read(clk->map, gate->offset, &val); + if (gate->flags & CLK_GATE_SET_TO_DISABLE) + val ^= BIT(gate->bit_idx); + + val &= BIT(gate->bit_idx); + + return val ? 1 : 0; +} + +const struct clk_ops clk_regmap_gate_ops = { + .enable = clk_regmap_gate_enable, + .disable = clk_regmap_gate_disable, + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); + +static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret = regmap_read(clk->map, div->offset, &val); + if (ret) + /* Gives a hint that something is wrong */ + return 0; + + val >>= div->shift; + val &= clk_div_mask(div->width); + return divider_recalc_rate(hw, prate, val, div->table, div->flags, + div->width); +} + +static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + /* if read only, just return current value */ + if (div->flags & CLK_DIVIDER_READ_ONLY) { + ret = regmap_read(clk->map, div->offset, &val); + if (ret) + /* Gives a hint that something is wrong */ + return 0; + + val >>= div->shift; + val &= clk_div_mask(div->width); + + return divider_ro_round_rate(hw, rate, prate, div->table, + div->width, div->flags, val); + } + + return divider_round_rate(hw, rate, prate, div->table, div->width, + div->flags); +} + +static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); + unsigned int val; + int ret; + + ret = divider_get_val(rate, parent_rate, div->table, div->width, + div->flags); + if (ret < 0) + return ret; + + val = (unsigned int)ret << div->shift; + return regmap_update_bits(clk->map, div->offset, + clk_div_mask(div->width) << div->shift, val); +}; + +/* Would prefer clk_regmap_div_ro_ops but clashes with qcom */ + +const struct clk_ops clk_regmap_divider_ops = { + .recalc_rate = clk_regmap_div_recalc_rate, + .round_rate = clk_regmap_div_round_rate, + .set_rate = clk_regmap_div_set_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_divider_ops); + +const struct clk_ops clk_regmap_divider_ro_ops = { + .recalc_rate = clk_regmap_div_recalc_rate, + .round_rate = clk_regmap_div_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_divider_ro_ops); + +static u8 clk_regmap_mux_get_parent(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); + unsigned int val; + int ret; + + ret = regmap_read(clk->map, mux->offset, &val); + if (ret) + return ret; + + val >>= mux->shift; + val &= mux->mask; + return clk_mux_val_to_index(hw, mux->table, mux->flags, val); +} + +static int clk_regmap_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct clk_regmap_mux_data *mux = clk_get_regmap_mux_data(clk); + unsigned int val = clk_mux_index_to_val(mux->table, mux->flags, index); + + return regmap_update_bits(clk->map, mux->offset, + mux->mask << mux->shift, + val << mux->shift); +} + +const struct clk_ops clk_regmap_mux_ops = { + .get_parent = clk_regmap_mux_get_parent, + .set_parent = clk_regmap_mux_set_parent, + .determine_rate = __clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ops); + +const struct clk_ops clk_regmap_mux_ro_ops = { + .get_parent = clk_regmap_mux_get_parent, +}; +EXPORT_SYMBOL_GPL(clk_regmap_mux_ro_ops); diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h new file mode 100644 index 000000000000..ab00a0578edf --- /dev/null +++ b/drivers/clk/meson/clk-regmap.h @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 BayLibre, SAS. +// Author: Jerome Brunet + +#ifndef __CLK_REGMAP_H +#define __CLK_REGMAP_H + +#include +#include + +/** + * struct clk_regmap - regmap backed clock + * + * @hw: handle between common and hardware-specific interfaces + * @map: pointer to the regmap structure controlling the clock + * @data: data specific to the clock type + * + * Clock which is controlled by regmap backed registers. The actual type of + * of the clock is controlled by the clock_ops and data. + */ +struct clk_regmap { + struct clk_hw hw; + struct regmap *map; + void *data; +}; + +#define to_clk_regmap(_hw) container_of(_hw, struct clk_regmap, hw) + +/** + * struct clk_regmap_gate_data - regmap backed gate specific data + * + * @offset: offset of the register controlling gate + * @bit_idx: single bit controlling gate + * @flags: hardware-specific flags + * + * Flags: + * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored + */ +struct clk_regmap_gate_data { + unsigned int offset; + u8 bit_idx; + u8 flags; +}; + +static inline struct clk_regmap_gate_data * +clk_get_regmap_gate_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_gate_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_gate_ops; + +/** + * struct clk_regmap_div_data - regmap backed adjustable divider specific data + * + * @offset: offset of the register controlling the divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @table: array of value/divider pairs, last entry should have div = 0 + * + * Flags: + * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored + */ +struct clk_regmap_div_data { + unsigned int offset; + u8 shift; + u8 width; + u8 flags; + const struct clk_div_table *table; +}; + +static inline struct clk_regmap_div_data * +clk_get_regmap_div_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_div_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_divider_ops; +extern const struct clk_ops clk_regmap_divider_ro_ops; + +/** + * struct clk_regmap_mux_data - regmap backed multiplexer clock specific data + * + * @hw: handle between common and hardware-specific interfaces + * @offset: offset of theregister controlling multiplexer + * @table: array of parent indexed register values + * @shift: shift to multiplexer bit field + * @width: width of mutliplexer bit field + * @flags: hardware-specific flags + * + * Flags: + * Same as clk_divider except CLK_MUX_HIWORD_MASK which is ignored + */ +struct clk_regmap_mux_data { + unsigned int offset; + u32 *table; + u32 mask; + u8 shift; + u8 flags; +}; + +static inline struct clk_regmap_mux_data * +clk_get_regmap_mux_data(struct clk_regmap *clk) +{ + return (struct clk_regmap_mux_data *)clk->data; +} + +extern const struct clk_ops clk_regmap_mux_ops; +extern const struct clk_ops clk_regmap_mux_ro_ops; + +#endif /* __CLK_REGMAP_H */ From patchwork Wed Jan 31 18:09:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126396 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp970191ljc; Wed, 31 Jan 2018 10:12:32 -0800 (PST) X-Google-Smtp-Source: AH8x226Hj5vXH3QPozmhKJL2HbnuGzKzUxxLEhy0rcdgGlBkJ1qsXeHSGudBTFKuR7/V9RU5H1Cp X-Received: by 2002:a17:902:930c:: with SMTP id bc12-v6mr29732255plb.328.1517422352095; Wed, 31 Jan 2018 10:12:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422352; cv=none; d=google.com; s=arc-20160816; b=iwqxlaUzmMu8YB54k30LSUa1MAIU4OIEq86iIrSLMSheHhLWjgrXqPPm5eFSjMpj6C hb023qTrk7ESAEvNba3qPYarUHdFYQ5QuNtAADoHvdhVtFoXgB+8UMhM6wxA9MjpYJyo GFTb12gok3r0j4q/zMSAp31yJDj+Sx98rTcPZYZ+ZYYxfpRmzDKBh6a4/HfItK9WmexB JArAIHrzWV1tHW6BNbw/wiw9vZugvyoLx/usvULUuPFdPmeW+7b3YVbK0D4EdJykVq3y PxXox8CxQjukAVnRfRHYd49KBNBQR9kIxft47/qA4eIxEtv08S4wzufEg1Hbsg8eRIiR O5sQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=5tFPnR2JI6hRww5brRTauIPjJ5l3Ls1DxeriWzUgg6A=; b=Ts4qBvvHDIaQWf0oYnFGlJ9MV9FpjyNqQl3jxZ+5BLX8iz1VI0sztUcn4zWj0G4Pqf TCeJJe6vqomDkWg/B1iFeZoiuAn5OU94HA+c2A3JCyGemg11PbdBHO3elfP6f16p9yox amxRhMs664mLXrvOIy+WhwcZqPUGU5J3S1hG5+UwGTJAxh9kkeCq3ntBhLJTiUVHmeqy 1V/6ZpjsrAyNw02hgAhwCRcV9JwQFMZoT2gVT7pgUZilPSDsUQxnT7RcjOLEYCzf00dH 2TFqyz4MvU1wcC02LtOdLum6eiZSRBVRd+d0KNP9pgDw0Z9pxqCncM+nNT9BuL14EXPR PsBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=kYtQAzta; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 1 + drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/gxbb-aoclk.c | 20 ++++++++++---------- drivers/clk/meson/gxbb-aoclk.h | 1 - 4 files changed, 12 insertions(+), 12 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index e97e85077da1..33d148e19066 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -20,6 +20,7 @@ config COMMON_CLK_GXBB bool depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER + select COMMON_CLK_REGMAP_MESON help Support for the clock controller on AmLogic S905 devices, aka gxbb. Say Y if you want peripherals and CPU frequency scaling to work. diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 11a50586666a..465086118d62 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -4,6 +4,6 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o -obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o +obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 6c161e0a8e59..9ec23ae9a219 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -62,10 +62,9 @@ #include #include #include +#include "clk-regmap.h" #include "gxbb-aoclk.h" -static DEFINE_SPINLOCK(gxbb_aoclk_lock); - struct gxbb_aoclk_reset_controller { struct reset_controller_dev reset; unsigned int *data; @@ -87,12 +86,14 @@ static const struct reset_control_ops gxbb_aoclk_reset_ops = { }; #define GXBB_AO_GATE(_name, _bit) \ -static struct aoclk_gate_regmap _name##_ao = { \ - .bit_idx = (_bit), \ - .lock = &gxbb_aoclk_lock, \ +static struct clk_regmap _name##_ao = { \ + .data = &(struct clk_regmap_gate_data) { \ + .offset = AO_RTI_GEN_CNTL_REG0, \ + .bit_idx = (_bit), \ + }, \ .hw.init = &(struct clk_init_data) { \ .name = #_name "_ao", \ - .ops = &meson_aoclk_gate_regmap_ops, \ + .ops = &clk_regmap_gate_ops, \ .parent_names = (const char *[]){ "clk81" }, \ .num_parents = 1, \ .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ @@ -107,7 +108,6 @@ GXBB_AO_GATE(uart2, 5); GXBB_AO_GATE(ir_blaster, 6); static struct aoclk_cec_32k cec_32k_ao = { - .lock = &gxbb_aoclk_lock, .hw.init = &(struct clk_init_data) { .name = "cec_32k_ao", .ops = &meson_aoclk_cec_32k_ops, @@ -126,7 +126,7 @@ static unsigned int gxbb_aoclk_reset[] = { [RESET_AO_IR_BLASTER] = 23, }; -static struct aoclk_gate_regmap *gxbb_aoclk_gate[] = { +static struct clk_regmap *gxbb_aoclk_gate[] = { [CLKID_AO_REMOTE] = &remote_ao, [CLKID_AO_I2C_MASTER] = &i2c_master_ao, [CLKID_AO_I2C_SLAVE] = &i2c_slave_ao, @@ -177,10 +177,10 @@ static int gxbb_aoclkc_probe(struct platform_device *pdev) * Populate regmap and register all clks */ for (clkid = 0; clkid < ARRAY_SIZE(gxbb_aoclk_gate); clkid++) { - gxbb_aoclk_gate[clkid]->regmap = regmap; + gxbb_aoclk_gate[clkid]->map = regmap; ret = devm_clk_hw_register(dev, - gxbb_aoclk_onecell_data.hws[clkid]); + gxbb_aoclk_onecell_data.hws[clkid]); if (ret) return ret; } diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h index e8604c8f7eee..127d58954cca 100644 --- a/drivers/clk/meson/gxbb-aoclk.h +++ b/drivers/clk/meson/gxbb-aoclk.h @@ -32,7 +32,6 @@ extern const struct clk_ops meson_aoclk_gate_regmap_ops; struct aoclk_cec_32k { struct clk_hw hw; struct regmap *regmap; - spinlock_t *lock; }; #define to_aoclk_cec_32k(_hw) container_of(_hw, struct aoclk_cec_32k, hw) From patchwork Wed Jan 31 18:09:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126387 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp968156ljc; Wed, 31 Jan 2018 10:10:08 -0800 (PST) X-Google-Smtp-Source: AH8x224LVxVG/OjISJx7HXmzt8Q4fU1R5qlVTjZQi5Hm3ziw/Y0y8eosQ6Usrh2Z3AtQiOL7U/SG X-Received: by 10.101.78.12 with SMTP id r12mr27301400pgt.33.1517422208659; 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It is no longer necessary so, remove it Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb-aoclk-regmap.c | 46 ----------------------------------- drivers/clk/meson/gxbb-aoclk.h | 10 -------- 2 files changed, 56 deletions(-) delete mode 100644 drivers/clk/meson/gxbb-aoclk-regmap.c -- 2.14.3 diff --git a/drivers/clk/meson/gxbb-aoclk-regmap.c b/drivers/clk/meson/gxbb-aoclk-regmap.c deleted file mode 100644 index 2515fbfa0467..000000000000 --- a/drivers/clk/meson/gxbb-aoclk-regmap.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2017 BayLibre, SAS. - * Author: Neil Armstrong - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include "gxbb-aoclk.h" - -static int aoclk_gate_regmap_enable(struct clk_hw *hw) -{ - struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw); - - return regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0, - BIT(gate->bit_idx), BIT(gate->bit_idx)); -} - -static void aoclk_gate_regmap_disable(struct clk_hw *hw) -{ - struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw); - - regmap_update_bits(gate->regmap, AO_RTI_GEN_CNTL_REG0, - BIT(gate->bit_idx), 0); -} - -static int aoclk_gate_regmap_is_enabled(struct clk_hw *hw) -{ - struct aoclk_gate_regmap *gate = to_aoclk_gate_regmap(hw); - unsigned int val; - int ret; - - ret = regmap_read(gate->regmap, AO_RTI_GEN_CNTL_REG0, &val); - if (ret) - return ret; - - return (val & BIT(gate->bit_idx)) != 0; -} - -const struct clk_ops meson_aoclk_gate_regmap_ops = { - .enable = aoclk_gate_regmap_enable, - .disable = aoclk_gate_regmap_disable, - .is_enabled = aoclk_gate_regmap_is_enabled, -}; diff --git a/drivers/clk/meson/gxbb-aoclk.h b/drivers/clk/meson/gxbb-aoclk.h index 127d58954cca..0be78383f257 100644 --- a/drivers/clk/meson/gxbb-aoclk.h +++ b/drivers/clk/meson/gxbb-aoclk.h @@ -17,16 +17,6 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 -struct aoclk_gate_regmap { - struct clk_hw hw; - unsigned bit_idx; - struct regmap *regmap; - spinlock_t *lock; -}; - -#define to_aoclk_gate_regmap(_hw) \ - container_of(_hw, struct aoclk_gate_regmap, hw) - extern const struct clk_ops meson_aoclk_gate_regmap_ops; struct aoclk_cec_32k { From patchwork Wed Jan 31 18:09:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126400 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp971411ljc; Wed, 31 Jan 2018 10:13:53 -0800 (PST) X-Google-Smtp-Source: AH8x2256McT5VnGUkhkY8qo9hrS3qL6FZYSredVjSVNfFQXtODA5LHuxTk82v5unVMaWTzaYuWrV X-Received: by 2002:a17:902:8b8a:: with SMTP id ay10-v6mr28849001plb.156.1517422433780; Wed, 31 Jan 2018 10:13:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422433; cv=none; d=google.com; s=arc-20160816; b=pFhr3TCdMwxng+i4A3EBN1TOyw4ZhAbLIPTz9OaRAQPWpjJXRsgPiI4U/mbk2DCzB4 7fZA6pkgkVaWFbCpeBl+pQojbwo336dg+3mKDnobwy4wQlCB+MhAICWgfMnMB+TImgBU 6weXNhysQl467M5rwYE8x2zcWqm5IFoHoB7xSaRHKduYB+xuLP4wzf7nfHcW+75/oscV 5Wsu5oLGoTkhhYXIG3QPgqEZUir64s3b0kRF4s1AGNaaGFi1ADIdZW8F0X2l45fEtKEh zefIKrWhcMqVPhL49y3ZEggmG3gP6IO+BRiKjynVFMLqWpVSDUeSmeKvXXMX7zYbeFqR epaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Xi+CQSEsVi0n3WmGIVsS7scJqSTrpWzaV8bGqwVRreg=; b=m3PbhhYJiutdZCTdTcZLUPMdwYyDlLpYyQwQSVPELgfiQEdlENGVnVUkPVbh5VbTVw cobjbmKBgNssx8lPpo2qE/NTOgpzLXthuRPtzyed1kW2T8NCZ/o0nL42GbaOV1/SR0E/ R8vdemTyzXCvR/ev8k2JyywFy01yA5T9/Lhibeshk6V+h0tZmT6Am2BRcGCUK6MRfeVQ IFtrwdt/SPsvGNbsqA8sxysjFkvNOo+UwP2IfheuLJTmTfLu96IMh+XihFzamGLXtPYI HzBNrlgLtnj5mR7JjLc5iDuG/Z82VM7LbnK2M9bCN7ifJDNRY8Mvnc32f+eLqI6UMsiH k0lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=AiQpxNPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The clock are still accessing their registers directly through iomem. Once all clocks handled by these controllers have been move to regmap, the regmap register will be removed and replaced with a syscon request. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 2 ++ drivers/clk/meson/axg.c | 15 ++++++++++++++- drivers/clk/meson/gxbb.c | 33 +++++++++++++++++++++++---------- drivers/clk/meson/meson8b.c | 14 +++++++++++++- 4 files changed, 52 insertions(+), 12 deletions(-) -- 2.14.3 Acked-by: Martin Blumenstingl diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 33d148e19066..9735335b17a9 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -11,6 +11,7 @@ config COMMON_CLK_MESON8B bool depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER + select REGMAP help Support for the clock controller on AmLogic S802 (Meson8), S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you @@ -29,6 +30,7 @@ config COMMON_CLK_AXG bool depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER + select REGMAP help Support for the clock controller on AmLogic A113D devices, aka axg. Say Y if you want peripherals and CPU frequency scaling to work. diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index f84927e76f88..669d0ed84ebc 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -11,10 +11,11 @@ #include #include +#include #include #include #include -#include +#include #include "clkc.h" #include "axg.h" @@ -791,12 +792,19 @@ static const struct of_device_id clkc_match_table[] = { {} }; +static const struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int axg_clkc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct clkc_data *clkc_data; struct resource *res; void __iomem *clk_base; + struct regmap *map; int ret, i; clkc_data = of_device_get_match_data(dev); @@ -807,12 +815,17 @@ static int axg_clkc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; + clk_base = devm_ioremap(dev, res->start, resource_size(res)); if (!clk_base) { dev_err(dev, "Unable to map clk base\n"); return -ENXIO; } + map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + /* Populate base address for PLLs */ for (i = 0; i < clkc_data->clk_plls_count; i++) clkc_data->clk_plls[i]->base = clk_base; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 6609024eee00..e3faf0a0fdb7 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -19,10 +19,11 @@ #include #include +#include #include #include #include -#include +#include #include "clkc.h" #include "gxbb.h" @@ -1937,10 +1938,18 @@ static const struct of_device_id clkc_match_table[] = { {}, }; +static const struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int gxbb_clkc_probe(struct platform_device *pdev) { const struct clkc_data *clkc_data; + struct resource *res; void __iomem *clk_base; + struct regmap *map; int ret, i; struct device *dev = &pdev->dev; @@ -1948,13 +1957,20 @@ static int gxbb_clkc_probe(struct platform_device *pdev) if (!clkc_data) return -EINVAL; - /* Generic clocks and PLLs */ - clk_base = of_iomap(dev->of_node, 0); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + clk_base = devm_ioremap(dev, res->start, resource_size(res)); if (!clk_base) { pr_err("%s: Unable to map clk base\n", __func__); return -ENXIO; } + map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + /* Populate base address for PLLs */ for (i = 0; i < clkc_data->clk_plls_count; i++) clkc_data->clk_plls[i]->base = clk_base; @@ -1991,17 +2007,14 @@ static int gxbb_clkc_probe(struct platform_device *pdev) ret = devm_clk_hw_register(dev, clkc_data->hw_onecell_data->hws[i]); - if (ret) - goto iounmap; + if (ret) { + dev_err(dev, "Clock registration failed\n"); + return ret; + } } - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkc_data->hw_onecell_data); - -iounmap: - iounmap(clk_base); - return ret; } static struct platform_driver gxbb_driver = { diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index db017c29a84c..0981e970de3d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -23,11 +23,12 @@ #include #include +#include #include #include #include #include -#include +#include #include "clkc.h" #include "meson8b.h" @@ -804,16 +805,27 @@ static const struct reset_control_ops meson8b_clk_reset_ops = { .deassert = meson8b_clk_reset_deassert, }; +static const struct regmap_config clkc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + static int meson8b_clkc_probe(struct platform_device *pdev) { int ret, i; struct clk_hw *parent_hw; struct clk *parent_clk; struct device *dev = &pdev->dev; + struct regmap *map; if (!clk_base) return -ENXIO; + map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + /* Populate base address for PLLs */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) meson8b_clk_plls[i]->base = clk_base; From patchwork Wed Jan 31 18:09:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126401 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp971614ljc; Wed, 31 Jan 2018 10:14:11 -0800 (PST) X-Google-Smtp-Source: AH8x2275BqI5jd5V6/PleYNbhRZCARCksZHtmhU51w6anaC3yKEo1IAHVjiNabkdx+Ua5PXgFtwP X-Received: by 2002:a17:902:780f:: with SMTP id p15-v6mr13888647pll.161.1517422450917; Wed, 31 Jan 2018 10:14:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422450; cv=none; d=google.com; s=arc-20160816; b=wIkBpBFz3bSLHkIDEea3+i14DoGBT45raAqimAMCF8QH7sGzxmfy4uiD3BtS9mCdH8 5lxP5YXFyoGS+FIl+61r5nVl3plCvqc/0BnKUHIFA6WHApl+AyPYRVeeQWTjxHuDnFdt P3ygGRmaDxCNd9v9NQh3Ibf47zyHLZg9+5+JkmtSySw1ZJavTNN0GbN0QjJtnCRx/vwJ sjj/PS0eubpj6hZP7Womk52akQsfW93fhAfqyRdbktDljW84AcnLMwYdHzNdO/1tpXLT gnH1a9JxkPd0VwnK2TuolDarNguvqrS8N/Ij2U5BjyyL88pFza0y7XXeOaRfxkw5wfEw wsZQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id y12-v6si2490297plr.581.2018.01.31.10.14.10; Wed, 31 Jan 2018 10:14:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=oLAl+5MW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753993AbeAaSNu (ORCPT + 27 others); Wed, 31 Jan 2018 13:13:50 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:34055 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753739AbeAaSKA (ORCPT ); Wed, 31 Jan 2018 13:10:00 -0500 Received: by mail-wr0-f193.google.com with SMTP id 36so16036610wrh.1 for ; Wed, 31 Jan 2018 10:10:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ojeTo+0wH/CSsj0SqJv/AZjQ9VNebNVvluY3HmAOab4=; b=oLAl+5MWcLNvDML4U5BbsP3jKrlAW4YVSPSPK/uCXQwwB77otmhMp8vkvit31kQLve tPlr9ZYWUykjWFp9VxDaR+zIMnisE3ycsRhA7ev5+PU++wWjR2QfA9EU8kHVY08535OI KIJhde7QHi3ZjwZJjcYuMX/xStUuAZaRfKViqZuOmE9oigSlkMy/K9/AN1kmqs3jMADn MMxKyTGNGDTxEMZIL15L8AhOYHJ1f78+FeLmoKQOxI6eXhjC22W/UXLpnkPDxbqmF6VB wt+qev/5BbuD/9U7IMOxdKiWmztPYbb16O1KtlencoJ/UX431EqeF5iL/rqX67OQ15Qs BodQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ojeTo+0wH/CSsj0SqJv/AZjQ9VNebNVvluY3HmAOab4=; b=qwzueN5XAD0QFOrxrrBkxAg804eZ8c9MoTL41C9xd3/rnUOWdVKe9eX5S3vK0AG5T4 gD0VrJ/ksnH62FaJKlaZvIwgtKxMPoWIY8BhrYdJs9F6Wd9ASowT0WKq5AwPP2Ivn/M+ SjdVLSSbMRqr+PsAIeemT12juG/72OcY1xR43uqyvZaWu7EMmqC/YLRfylrAE8Z75GHO ShtRsp1SAfQwpe36j2JvtEo42s0FcWa+Wxj7jpbcLN8p9EG7aeMjBbqVV32b27JhJ7MI XbOow9wmQhM9A39ozgnAl6ijM0UB/w8mzNvry2UqB6KDBsgPVvibgjG3NUIKszpbuBle Dzuw== X-Gm-Message-State: AKwxytdVvjbYgVNgbP3DdpXPkrJXwCNgi7z9CipI/EAFQjroOeH5O/aP e18769atOtVGHE6US558w7Co/Q== X-Received: by 10.223.185.29 with SMTP id k29mr12537279wrf.37.1517422199119; Wed, 31 Jan 2018 10:09:59 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:58 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/19] clk: meson: migrate gates to clk_regmap Date: Wed, 31 Jan 2018 19:09:35 +0100 Message-Id: <20180131180945.18025-10-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 4 +- drivers/clk/meson/axg.c | 72 ++++++------ drivers/clk/meson/clkc.h | 20 ++-- drivers/clk/meson/gxbb.c | 268 +++++++++++++++++++++++--------------------- drivers/clk/meson/meson8b.c | 39 +++---- 5 files changed, 208 insertions(+), 195 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 9735335b17a9..936afddae406 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -11,7 +11,7 @@ config COMMON_CLK_MESON8B bool depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select REGMAP + select COMMON_CLK_REGMAP_MESON help Support for the clock controller on AmLogic S802 (Meson8), S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you @@ -30,7 +30,7 @@ config COMMON_CLK_AXG bool depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select REGMAP + select COMMON_CLK_REGMAP_MESON help Support for the clock controller on AmLogic A113D devices, aka axg. Say Y if you want peripherals and CPU frequency scaling to work. diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 669d0ed84ebc..3b7c970907c1 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -447,13 +447,14 @@ static struct clk_divider axg_mpeg_clk_div = { }, }; -static struct clk_gate axg_clk81 = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +static struct clk_regmap axg_clk81 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPEG_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "clk81", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), @@ -501,13 +502,14 @@ static struct clk_divider axg_sd_emmc_b_clk0_div = { }, }; -static struct clk_gate axg_sd_emmc_b_clk0 = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .bit_idx = 23, - .lock = &meson_clk_lock, +static struct clk_regmap axg_sd_emmc_b_clk0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .bit_idx = 23, + }, .hw.init = &(struct clk_init_data){ .name = "sd_emmc_b_clk0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -544,13 +546,14 @@ static struct clk_divider axg_sd_emmc_c_clk0_div = { }, }; -static struct clk_gate axg_sd_emmc_c_clk0 = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +static struct clk_regmap axg_sd_emmc_c_clk0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_NAND_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "sd_emmc_c_clk0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -697,7 +700,19 @@ static struct meson_clk_mpll *const axg_clk_mplls[] = { &axg_mpll3, }; -static struct clk_gate *const axg_clk_gates[] = { +static struct clk_mux *const axg_clk_muxes[] = { + &axg_mpeg_clk_sel, + &axg_sd_emmc_b_clk0_sel, + &axg_sd_emmc_c_clk0_sel, +}; + +static struct clk_divider *const axg_clk_dividers[] = { + &axg_mpeg_clk_div, + &axg_sd_emmc_b_clk0_div, + &axg_sd_emmc_c_clk0_div, +}; + +static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, &axg_audio_locker, @@ -747,21 +762,7 @@ static struct clk_gate *const axg_clk_gates[] = { &axg_sd_emmc_c_clk0, }; -static struct clk_mux *const axg_clk_muxes[] = { - &axg_mpeg_clk_sel, - &axg_sd_emmc_b_clk0_sel, - &axg_sd_emmc_c_clk0_sel, -}; - -static struct clk_divider *const axg_clk_dividers[] = { - &axg_mpeg_clk_div, - &axg_sd_emmc_b_clk0_div, - &axg_sd_emmc_c_clk0_div, -}; - struct clkc_data { - struct clk_gate *const *clk_gates; - unsigned int clk_gates_count; struct meson_clk_mpll *const *clk_mplls; unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; @@ -774,8 +775,6 @@ struct clkc_data { }; static const struct clkc_data axg_clkc_data = { - .clk_gates = axg_clk_gates, - .clk_gates_count = ARRAY_SIZE(axg_clk_gates), .clk_mplls = axg_clk_mplls, .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls), .clk_plls = axg_clk_plls, @@ -834,11 +833,6 @@ static int axg_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_mplls_count; i++) clkc_data->clk_mplls[i]->base = clk_base; - /* Populate base address for gates */ - for (i = 0; i < clkc_data->clk_gates_count; i++) - clkc_data->clk_gates[i]->reg = clk_base + - (u64)clkc_data->clk_gates[i]->reg; - /* Populate base address for muxes */ for (i = 0; i < clkc_data->clk_muxes_count; i++) clkc_data->clk_muxes[i]->reg = clk_base + @@ -849,6 +843,10 @@ static int axg_clkc_probe(struct platform_device *pdev) clkc_data->clk_dividers[i]->reg = clk_base + (u64)clkc_data->clk_dividers[i]->reg; + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) + axg_clk_regmaps[i]->map = map; + for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { /* array might be sparse */ if (!clkc_data->hw_onecell_data->hws[i]) diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 07aaba26a857..aa2dfa0ff89f 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -18,6 +18,9 @@ #ifndef __CLKC_H #define __CLKC_H +#include +#include "clk-regmap.h" + #define PMASK(width) GENMASK(width - 1, 0) #define SETPMASK(width, shift) GENMASK(shift + width - 1, shift) #define CLRPMASK(width, shift) (~SETPMASK(width, shift)) @@ -134,16 +137,17 @@ struct meson_clk_audio_divider { }; #define MESON_GATE(_name, _reg, _bit) \ -struct clk_gate _name = { \ - .reg = (void __iomem *) _reg, \ - .bit_idx = (_bit), \ - .lock = &meson_clk_lock, \ - .hw.init = &(struct clk_init_data) { \ - .name = #_name, \ - .ops = &clk_gate_ops, \ +struct clk_regmap _name = { \ + .data = &(struct clk_regmap_gate_data){ \ + .offset = (_reg), \ + .bit_idx = (_bit), \ + }, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_regmap_gate_ops, \ .parent_names = (const char *[]){ "clk81" }, \ .num_parents = 1, \ - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ }, \ }; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e3faf0a0fdb7..ee1cd3785348 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -27,6 +27,7 @@ #include "clkc.h" #include "gxbb.h" +#include "clk-regmap.h" static DEFINE_SPINLOCK(meson_clk_lock); @@ -617,14 +618,15 @@ static struct clk_divider gxbb_mpeg_clk_div = { }, }; -/* the mother of dragons^W gates */ -static struct clk_gate gxbb_clk81 = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +/* the mother of dragons gates */ +static struct clk_regmap gxbb_clk81 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPEG_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "clk81", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), @@ -658,13 +660,14 @@ static struct clk_divider gxbb_sar_adc_clk_div = { }, }; -static struct clk_gate gxbb_sar_adc_clk = { - .reg = (void *)HHI_SAR_CLK_CNTL, - .bit_idx = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sar_adc_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SAR_CLK_CNTL, + .bit_idx = 8, + }, .hw.init = &(struct clk_init_data){ .name = "sar_adc_clk", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sar_adc_clk_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -716,13 +719,14 @@ static struct clk_divider gxbb_mali_0_div = { }, }; -static struct clk_gate gxbb_mali_0 = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .bit_idx = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MALI_CLK_CNTL, + .bit_idx = 8, + }, .hw.init = &(struct clk_init_data){ .name = "mali_0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mali_0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -763,13 +767,14 @@ static struct clk_divider gxbb_mali_1_div = { }, }; -static struct clk_gate gxbb_mali_1 = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .bit_idx = 24, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MALI_CLK_CNTL, + .bit_idx = 24, + }, .hw.init = &(struct clk_init_data){ .name = "mali_1", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mali_1_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -829,13 +834,14 @@ static struct meson_clk_audio_divider gxbb_cts_amclk_div = { }, }; -static struct clk_gate gxbb_cts_amclk = { - .reg = (void *) HHI_AUD_CLK_CNTL, - .bit_idx = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_cts_amclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_AUD_CLK_CNTL, + .bit_idx = 8, + }, .hw.init = &(struct clk_init_data){ .name = "cts_amclk", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "cts_amclk_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -873,13 +879,14 @@ static struct clk_divider gxbb_cts_mclk_i958_div = { }, }; -static struct clk_gate gxbb_cts_mclk_i958 = { - .reg = (void *)HHI_AUD_CLK_CNTL2, - .bit_idx = 24, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_cts_mclk_i958 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_AUD_CLK_CNTL2, + .bit_idx = 24, + }, .hw.init = &(struct clk_init_data){ .name = "cts_mclk_i958", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "cts_mclk_i958_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -918,13 +925,14 @@ static struct clk_divider gxbb_32k_clk_div = { }, }; -static struct clk_gate gxbb_32k_clk = { - .reg = (void *)HHI_32K_CLK_CNTL, - .bit_idx = 15, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_32k_clk = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_32K_CLK_CNTL, + .bit_idx = 15, + }, .hw.init = &(struct clk_init_data){ .name = "32k_clk", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "32k_clk_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -990,13 +998,14 @@ static struct clk_divider gxbb_sd_emmc_a_clk0_div = { }, }; -static struct clk_gate gxbb_sd_emmc_a_clk0 = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_a_clk0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "sd_emmc_a_clk0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1033,13 +1042,14 @@ static struct clk_divider gxbb_sd_emmc_b_clk0_div = { }, }; -static struct clk_gate gxbb_sd_emmc_b_clk0 = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .bit_idx = 23, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_b_clk0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .bit_idx = 23, + }, .hw.init = &(struct clk_init_data){ .name = "sd_emmc_b_clk0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1076,13 +1086,14 @@ static struct clk_divider gxbb_sd_emmc_c_clk0_div = { }, }; -static struct clk_gate gxbb_sd_emmc_c_clk0 = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_c_clk0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_NAND_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "sd_emmc_c_clk0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1129,13 +1140,14 @@ static struct clk_divider gxbb_vpu_0_div = { }, }; -static struct clk_gate gxbb_vpu_0 = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .bit_idx = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VPU_CLK_CNTL, + .bit_idx = 8, + }, .hw.init = &(struct clk_init_data) { .name = "vpu_0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "vpu_0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -1175,13 +1187,14 @@ static struct clk_divider gxbb_vpu_1_div = { }, }; -static struct clk_gate gxbb_vpu_1 = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .bit_idx = 24, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VPU_CLK_CNTL, + .bit_idx = 24, + }, .hw.init = &(struct clk_init_data) { .name = "vpu_1", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "vpu_1_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -1246,13 +1259,14 @@ static struct clk_divider gxbb_vapb_0_div = { }, }; -static struct clk_gate gxbb_vapb_0 = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .bit_idx = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VAPBCLK_CNTL, + .bit_idx = 8, + }, .hw.init = &(struct clk_init_data) { .name = "vapb_0", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "vapb_0_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -1292,13 +1306,14 @@ static struct clk_divider gxbb_vapb_1_div = { }, }; -static struct clk_gate gxbb_vapb_1 = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .bit_idx = 24, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VAPBCLK_CNTL, + .bit_idx = 24, + }, .hw.init = &(struct clk_init_data) { .name = "vapb_1", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "vapb_1_div" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -1323,13 +1338,14 @@ static struct clk_mux gxbb_vapb_sel = { }, }; -static struct clk_gate gxbb_vapb = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .bit_idx = 30, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_VAPBCLK_CNTL, + .bit_idx = 30, + }, .hw.init = &(struct clk_init_data) { .name = "vapb", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "vapb_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, @@ -1744,7 +1760,48 @@ static struct meson_clk_mpll *const gxbb_clk_mplls[] = { &gxbb_mpll2, }; -static struct clk_gate *const gxbb_clk_gates[] = { +static struct clk_mux *const gxbb_clk_muxes[] = { + &gxbb_mpeg_clk_sel, + &gxbb_sar_adc_clk_sel, + &gxbb_mali_0_sel, + &gxbb_mali_1_sel, + &gxbb_mali, + &gxbb_cts_amclk_sel, + &gxbb_cts_mclk_i958_sel, + &gxbb_cts_i958, + &gxbb_32k_clk_sel, + &gxbb_sd_emmc_a_clk0_sel, + &gxbb_sd_emmc_b_clk0_sel, + &gxbb_sd_emmc_c_clk0_sel, + &gxbb_vpu_0_sel, + &gxbb_vpu_1_sel, + &gxbb_vpu, + &gxbb_vapb_0_sel, + &gxbb_vapb_1_sel, + &gxbb_vapb_sel, +}; + +static struct clk_divider *const gxbb_clk_dividers[] = { + &gxbb_mpeg_clk_div, + &gxbb_sar_adc_clk_div, + &gxbb_mali_0_div, + &gxbb_mali_1_div, + &gxbb_cts_mclk_i958_div, + &gxbb_32k_clk_div, + &gxbb_sd_emmc_a_clk0_div, + &gxbb_sd_emmc_b_clk0_div, + &gxbb_sd_emmc_c_clk0_div, + &gxbb_vpu_0_div, + &gxbb_vpu_1_div, + &gxbb_vapb_0_div, + &gxbb_vapb_1_div, +}; + +static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { + &gxbb_cts_amclk_div, +}; + +static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_clk81, &gxbb_ddr, &gxbb_dos, @@ -1843,50 +1900,7 @@ static struct clk_gate *const gxbb_clk_gates[] = { &gxbb_vapb, }; -static struct clk_mux *const gxbb_clk_muxes[] = { - &gxbb_mpeg_clk_sel, - &gxbb_sar_adc_clk_sel, - &gxbb_mali_0_sel, - &gxbb_mali_1_sel, - &gxbb_mali, - &gxbb_cts_amclk_sel, - &gxbb_cts_mclk_i958_sel, - &gxbb_cts_i958, - &gxbb_32k_clk_sel, - &gxbb_sd_emmc_a_clk0_sel, - &gxbb_sd_emmc_b_clk0_sel, - &gxbb_sd_emmc_c_clk0_sel, - &gxbb_vpu_0_sel, - &gxbb_vpu_1_sel, - &gxbb_vpu, - &gxbb_vapb_0_sel, - &gxbb_vapb_1_sel, - &gxbb_vapb_sel, -}; - -static struct clk_divider *const gxbb_clk_dividers[] = { - &gxbb_mpeg_clk_div, - &gxbb_sar_adc_clk_div, - &gxbb_mali_0_div, - &gxbb_mali_1_div, - &gxbb_cts_mclk_i958_div, - &gxbb_32k_clk_div, - &gxbb_sd_emmc_a_clk0_div, - &gxbb_sd_emmc_b_clk0_div, - &gxbb_sd_emmc_c_clk0_div, - &gxbb_vpu_0_div, - &gxbb_vpu_1_div, - &gxbb_vapb_0_div, - &gxbb_vapb_1_div, -}; - -static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { - &gxbb_cts_amclk_div, -}; - struct clkc_data { - struct clk_gate *const *clk_gates; - unsigned int clk_gates_count; struct meson_clk_mpll *const *clk_mplls; unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; @@ -1897,12 +1911,12 @@ struct clkc_data { unsigned int clk_dividers_count; struct meson_clk_audio_divider *const *clk_audio_dividers; unsigned int clk_audio_dividers_count; + struct clk_regmap *const *clk_regmaps; + unsigned int clk_regmaps_count; struct clk_hw_onecell_data *hw_onecell_data; }; static const struct clkc_data gxbb_clkc_data = { - .clk_gates = gxbb_clk_gates, - .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), .clk_mplls = gxbb_clk_mplls, .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxbb_clk_plls, @@ -1917,8 +1931,6 @@ static const struct clkc_data gxbb_clkc_data = { }; static const struct clkc_data gxl_clkc_data = { - .clk_gates = gxbb_clk_gates, - .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates), .clk_mplls = gxbb_clk_mplls, .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxl_clk_plls, @@ -1979,11 +1991,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_mplls_count; i++) clkc_data->clk_mplls[i]->base = clk_base; - /* Populate base address for gates */ - for (i = 0; i < clkc_data->clk_gates_count; i++) - clkc_data->clk_gates[i]->reg = clk_base + - (u64)clkc_data->clk_gates[i]->reg; - /* Populate base address for muxes */ for (i = 0; i < clkc_data->clk_muxes_count; i++) clkc_data->clk_muxes[i]->reg = clk_base + @@ -1998,6 +2005,9 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; + /* Populate regmap for the common regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) + gx_clk_regmaps[i]->map = map; /* Register all clks */ for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 0981e970de3d..835dbb1d2c9d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -32,6 +32,7 @@ #include "clkc.h" #include "meson8b.h" +#include "clk-regmap.h" static DEFINE_SPINLOCK(meson_clk_lock); @@ -406,13 +407,14 @@ struct clk_divider meson8b_mpeg_clk_div = { }, }; -struct clk_gate meson8b_clk81 = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .bit_idx = 7, - .lock = &meson_clk_lock, +struct clk_regmap meson8b_clk81 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPEG_CLK_CNTL, + .bit_idx = 7, + }, .hw.init = &(struct clk_init_data){ .name = "clk81", - .ops = &clk_gate_ops, + .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), @@ -617,7 +619,15 @@ static struct meson_clk_mpll *const meson8b_clk_mplls[] = { &meson8b_mpll2, }; -static struct clk_gate *const meson8b_clk_gates[] = { +static struct clk_mux *const meson8b_clk_muxes[] = { + &meson8b_mpeg_clk_sel, +}; + +static struct clk_divider *const meson8b_clk_dividers[] = { + &meson8b_mpeg_clk_div, +}; + +static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, &meson8b_dos, @@ -698,14 +708,6 @@ static struct clk_gate *const meson8b_clk_gates[] = { &meson8b_ao_iface, }; -static struct clk_mux *const meson8b_clk_muxes[] = { - &meson8b_mpeg_clk_sel, -}; - -static struct clk_divider *const meson8b_clk_dividers[] = { - &meson8b_mpeg_clk_div, -}; - static const struct meson8b_clk_reset_line { u32 reg; u8 bit_idx; @@ -837,11 +839,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) /* Populate the base address for CPU clk */ meson8b_cpu_clk.base = clk_base; - /* Populate base address for gates */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) - meson8b_clk_gates[i]->reg = clk_base + - (u32)meson8b_clk_gates[i]->reg; - /* Populate base address for muxes */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++) meson8b_clk_muxes[i]->reg = clk_base + @@ -852,6 +849,10 @@ static int meson8b_clkc_probe(struct platform_device *pdev) meson8b_clk_dividers[i]->reg = clk_base + (u32)meson8b_clk_dividers[i]->reg; + /* Populate regmap for the regmap backed clocks */ + for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) + meson8b_clk_regmaps[i]->map = map; + /* * register all clks * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 From patchwork Wed Jan 31 18:09:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126399 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp970799ljc; Wed, 31 Jan 2018 10:13:13 -0800 (PST) X-Google-Smtp-Source: AH8x224Ma2L5+WeUX9ZyF7YoSAxvE+RZtVaQHqY0gaQrtIi/qrLviicKki4INpz49YHALSC3JY4G X-Received: by 2002:a17:902:824:: with SMTP id 33-v6mr27756083plk.258.1517422393500; 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Wed, 31 Jan 2018 10:10:00 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:59 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/19] clk: meson: migrate dividers to clk_regmap Date: Wed, 31 Jan 2018 19:09:36 +0100 Message-Id: <20180131180945.18025-11-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move meson8b, gxbb and axg clocks using clk_divider to clk_regmap Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 61 ++++++------- drivers/clk/meson/gxbb.c | 217 ++++++++++++++++++++++---------------------- drivers/clk/meson/meson8b.c | 23 ++--- 3 files changed, 142 insertions(+), 159 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 3b7c970907c1..60b822d8905c 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -433,14 +433,15 @@ static struct clk_mux axg_mpeg_clk_sel = { }, }; -static struct clk_divider axg_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap axg_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -487,15 +488,16 @@ static struct clk_mux axg_sd_emmc_b_clk0_sel = { }, }; -static struct clk_divider axg_sd_emmc_b_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap axg_sd_emmc_b_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 16, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -531,15 +533,16 @@ static struct clk_mux axg_sd_emmc_c_clk0_sel = { }, }; -static struct clk_divider axg_sd_emmc_c_clk0_div = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap axg_sd_emmc_c_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_NAND_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -706,12 +709,6 @@ static struct clk_mux *const axg_clk_muxes[] = { &axg_sd_emmc_c_clk0_sel, }; -static struct clk_divider *const axg_clk_dividers[] = { - &axg_mpeg_clk_div, - &axg_sd_emmc_b_clk0_div, - &axg_sd_emmc_c_clk0_div, -}; - static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, @@ -760,6 +757,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_ao_i2c, &axg_sd_emmc_b_clk0, &axg_sd_emmc_c_clk0, + &axg_mpeg_clk_div, + &axg_sd_emmc_b_clk0_div, + &axg_sd_emmc_c_clk0_div, }; struct clkc_data { @@ -769,8 +769,6 @@ struct clkc_data { unsigned int clk_plls_count; struct clk_mux *const *clk_muxes; unsigned int clk_muxes_count; - struct clk_divider *const *clk_dividers; - unsigned int clk_dividers_count; struct clk_hw_onecell_data *hw_onecell_data; }; @@ -781,8 +779,6 @@ static const struct clkc_data axg_clkc_data = { .clk_plls_count = ARRAY_SIZE(axg_clk_plls), .clk_muxes = axg_clk_muxes, .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes), - .clk_dividers = axg_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers), .hw_onecell_data = &axg_hw_onecell_data, }; @@ -838,11 +834,6 @@ static int axg_clkc_probe(struct platform_device *pdev) clkc_data->clk_muxes[i]->reg = clk_base + (u64)clkc_data->clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < clkc_data->clk_dividers_count; i++) - clkc_data->clk_dividers[i]->reg = clk_base + - (u64)clkc_data->clk_dividers[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ee1cd3785348..cdb20bf0682d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -604,14 +604,15 @@ static struct clk_mux gxbb_mpeg_clk_sel = { }, }; -static struct clk_divider gxbb_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), @@ -647,14 +648,15 @@ static struct clk_mux gxbb_sar_adc_clk_sel = { }, }; -static struct clk_divider gxbb_sar_adc_clk_div = { - .reg = (void *)HHI_SAR_CLK_CNTL, - .shift = 0, - .width = 8, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sar_adc_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SAR_CLK_CNTL, + .shift = 0, + .width = 8, + }, .hw.init = &(struct clk_init_data){ .name = "sar_adc_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sar_adc_clk_sel" }, .num_parents = 1, }, @@ -705,14 +707,15 @@ static struct clk_mux gxbb_mali_0_sel = { }, }; -static struct clk_divider gxbb_mali_0_div = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MALI_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mali_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mali_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -753,14 +756,15 @@ static struct clk_mux gxbb_mali_1_sel = { }, }; -static struct clk_divider gxbb_mali_1_div = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MALI_CLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mali_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mali_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_NO_REPARENT, @@ -864,15 +868,16 @@ static struct clk_mux gxbb_cts_mclk_i958_sel = { }, }; -static struct clk_divider gxbb_cts_mclk_i958_div = { - .reg = (void *)HHI_AUD_CLK_CNTL2, - .shift = 16, - .width = 8, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_cts_mclk_i958_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_AUD_CLK_CNTL2, + .shift = 16, + .width = 8, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "cts_mclk_i958_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -911,14 +916,15 @@ static struct clk_mux gxbb_cts_i958 = { }, }; -static struct clk_divider gxbb_32k_clk_div = { - .reg = (void *)HHI_32K_CLK_CNTL, - .shift = 0, - .width = 14, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_32k_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_32K_CLK_CNTL, + .shift = 0, + .width = 14, + }, .hw.init = &(struct clk_init_data){ .name = "32k_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "32k_clk_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, @@ -983,15 +989,16 @@ static struct clk_mux gxbb_sd_emmc_a_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_a_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_a_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_a_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1027,15 +1034,16 @@ static struct clk_mux gxbb_sd_emmc_b_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_b_clk0_div = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_b_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .shift = 16, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1071,15 +1079,16 @@ static struct clk_mux gxbb_sd_emmc_c_clk0_sel = { }, }; -static struct clk_divider gxbb_sd_emmc_c_clk0_div = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, - .flags = CLK_DIVIDER_ROUND_CLOSEST, +static struct clk_regmap gxbb_sd_emmc_c_clk0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_NAND_CLK_CNTL, + .shift = 0, + .width = 7, + .flags = CLK_DIVIDER_ROUND_CLOSEST, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1126,14 +1135,15 @@ static struct clk_mux gxbb_vpu_0_sel = { }, }; -static struct clk_divider gxbb_vpu_0_div = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VPU_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vpu_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1173,14 +1183,15 @@ static struct clk_mux gxbb_vpu_1_sel = { }, }; -static struct clk_divider gxbb_vpu_1_div = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VPU_CLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vpu_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1245,14 +1256,15 @@ static struct clk_mux gxbb_vapb_0_sel = { }, }; -static struct clk_divider gxbb_vapb_0_div = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_0_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VAPBCLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_0_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vapb_0_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1292,14 +1304,15 @@ static struct clk_mux gxbb_vapb_1_sel = { }, }; -static struct clk_divider gxbb_vapb_1_div = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .shift = 16, - .width = 7, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_1_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_VAPBCLK_CNTL, + .shift = 16, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_1_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "vapb_1_sel" }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1781,22 +1794,6 @@ static struct clk_mux *const gxbb_clk_muxes[] = { &gxbb_vapb_sel, }; -static struct clk_divider *const gxbb_clk_dividers[] = { - &gxbb_mpeg_clk_div, - &gxbb_sar_adc_clk_div, - &gxbb_mali_0_div, - &gxbb_mali_1_div, - &gxbb_cts_mclk_i958_div, - &gxbb_32k_clk_div, - &gxbb_sd_emmc_a_clk0_div, - &gxbb_sd_emmc_b_clk0_div, - &gxbb_sd_emmc_c_clk0_div, - &gxbb_vpu_0_div, - &gxbb_vpu_1_div, - &gxbb_vapb_0_div, - &gxbb_vapb_1_div, -}; - static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { &gxbb_cts_amclk_div, }; @@ -1898,6 +1895,19 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_vapb_0, &gxbb_vapb_1, &gxbb_vapb, + &gxbb_mpeg_clk_div, + &gxbb_sar_adc_clk_div, + &gxbb_mali_0_div, + &gxbb_mali_1_div, + &gxbb_cts_mclk_i958_div, + &gxbb_32k_clk_div, + &gxbb_sd_emmc_a_clk0_div, + &gxbb_sd_emmc_b_clk0_div, + &gxbb_sd_emmc_c_clk0_div, + &gxbb_vpu_0_div, + &gxbb_vpu_1_div, + &gxbb_vapb_0_div, + &gxbb_vapb_1_div, }; struct clkc_data { @@ -1907,8 +1917,6 @@ struct clkc_data { unsigned int clk_plls_count; struct clk_mux *const *clk_muxes; unsigned int clk_muxes_count; - struct clk_divider *const *clk_dividers; - unsigned int clk_dividers_count; struct meson_clk_audio_divider *const *clk_audio_dividers; unsigned int clk_audio_dividers_count; struct clk_regmap *const *clk_regmaps; @@ -1923,8 +1931,6 @@ static const struct clkc_data gxbb_clkc_data = { .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), .clk_muxes = gxbb_clk_muxes, .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), - .clk_dividers = gxbb_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxbb_hw_onecell_data, @@ -1937,8 +1943,6 @@ static const struct clkc_data gxl_clkc_data = { .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), .clk_muxes = gxbb_clk_muxes, .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), - .clk_dividers = gxbb_clk_dividers, - .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxl_hw_onecell_data, @@ -1996,11 +2000,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) clkc_data->clk_muxes[i]->reg = clk_base + (u64)clkc_data->clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < clkc_data->clk_dividers_count; i++) - clkc_data->clk_dividers[i]->reg = clk_base + - (u64)clkc_data->clk_dividers[i]->reg; - /* Populate base address for the audio dividers */ for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 835dbb1d2c9d..e9c5278072cd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -393,14 +393,15 @@ struct clk_mux meson8b_mpeg_clk_sel = { }, }; -struct clk_divider meson8b_mpeg_clk_div = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .shift = 0, - .width = 7, - .lock = &meson_clk_lock, +struct clk_regmap meson8b_mpeg_clk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_MPEG_CLK_CNTL, + .shift = 0, + .width = 7, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_div", - .ops = &clk_divider_ops, + .ops = &clk_regmap_divider_ops, .parent_names = (const char *[]){ "mpeg_clk_sel" }, .num_parents = 1, .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), @@ -623,10 +624,6 @@ static struct clk_mux *const meson8b_clk_muxes[] = { &meson8b_mpeg_clk_sel, }; -static struct clk_divider *const meson8b_clk_dividers[] = { - &meson8b_mpeg_clk_div, -}; - static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, @@ -706,6 +703,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_ao_ahb_sram, &meson8b_ao_ahb_bus, &meson8b_ao_iface, + &meson8b_mpeg_clk_div, }; static const struct meson8b_clk_reset_line { @@ -844,11 +842,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) meson8b_clk_muxes[i]->reg = clk_base + (u32)meson8b_clk_muxes[i]->reg; - /* Populate base address for dividers */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++) - meson8b_clk_dividers[i]->reg = clk_base + - (u32)meson8b_clk_dividers[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) meson8b_clk_regmaps[i]->map = map; From patchwork Wed Jan 31 18:09:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126398 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp970538ljc; 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Wed, 31 Jan 2018 10:10:01 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.10.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:10:00 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/19] clk: meson: migrate muxes to clk_regmap Date: Wed, 31 Jan 2018 19:09:37 +0100 Message-Id: <20180131180945.18025-12-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Move meson8b, gxbb and axg clocks using clk_mux to clk_regmap Also remove a few useless tables in the process Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 60 ++++----- drivers/clk/meson/gxbb.c | 312 +++++++++++++++++++++----------------------- drivers/clk/meson/meson8b.c | 27 ++-- 3 files changed, 184 insertions(+), 215 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 60b822d8905c..6ce413a9d0dd 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -418,16 +418,16 @@ static const char * const clk81_parent_names[] = { "fclk_div3", "fclk_div5" }; -static struct clk_mux axg_mpeg_clk_sel = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .mask = 0x7, - .shift = 12, - .flags = CLK_MUX_READ_ONLY, - .table = mux_table_clk81, - .lock = &meson_clk_lock, +static struct clk_regmap axg_mpeg_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MPEG_CLK_CNTL, + .mask = 0x7, + .shift = 12, + .table = mux_table_clk81, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_sel", - .ops = &clk_mux_ro_ops, + .ops = &clk_regmap_mux_ro_ops, .parent_names = clk81_parent_names, .num_parents = ARRAY_SIZE(clk81_parent_names), }, @@ -474,14 +474,15 @@ static const char * const axg_sd_emmc_clk0_parent_names[] = { }; /* SDcard clock */ -static struct clk_mux axg_sd_emmc_b_clk0_sel = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .mask = 0x7, - .shift = 25, - .lock = &meson_clk_lock, +static struct clk_regmap axg_sd_emmc_b_clk0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .mask = 0x7, + .shift = 25, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = axg_sd_emmc_clk0_parent_names, .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), .flags = CLK_SET_RATE_PARENT, @@ -519,14 +520,15 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = { }; /* EMMC/NAND clock */ -static struct clk_mux axg_sd_emmc_c_clk0_sel = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .mask = 0x7, - .shift = 9, - .lock = &meson_clk_lock, +static struct clk_regmap axg_sd_emmc_c_clk0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_NAND_CLK_CNTL, + .mask = 0x7, + .shift = 9, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = axg_sd_emmc_clk0_parent_names, .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), .flags = CLK_SET_RATE_PARENT, @@ -703,12 +705,6 @@ static struct meson_clk_mpll *const axg_clk_mplls[] = { &axg_mpll3, }; -static struct clk_mux *const axg_clk_muxes[] = { - &axg_mpeg_clk_sel, - &axg_sd_emmc_b_clk0_sel, - &axg_sd_emmc_c_clk0_sel, -}; - static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, @@ -760,6 +756,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_mpeg_clk_div, &axg_sd_emmc_b_clk0_div, &axg_sd_emmc_c_clk0_div, + &axg_mpeg_clk_sel, + &axg_sd_emmc_b_clk0_sel, + &axg_sd_emmc_c_clk0_sel, }; struct clkc_data { @@ -767,8 +766,6 @@ struct clkc_data { unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; unsigned int clk_plls_count; - struct clk_mux *const *clk_muxes; - unsigned int clk_muxes_count; struct clk_hw_onecell_data *hw_onecell_data; }; @@ -777,8 +774,6 @@ static const struct clkc_data axg_clkc_data = { .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls), .clk_plls = axg_clk_plls, .clk_plls_count = ARRAY_SIZE(axg_clk_plls), - .clk_muxes = axg_clk_muxes, - .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes), .hw_onecell_data = &axg_hw_onecell_data, }; @@ -829,11 +824,6 @@ static int axg_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_mplls_count; i++) clkc_data->clk_mplls[i]->base = clk_base; - /* Populate base address for muxes */ - for (i = 0; i < clkc_data->clk_muxes_count; i++) - clkc_data->clk_muxes[i]->reg = clk_base + - (u64)clkc_data->clk_muxes[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index cdb20bf0682d..d9f426265774 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -583,16 +583,16 @@ static const char * const clk81_parent_names[] = { "fclk_div3", "fclk_div5" }; -static struct clk_mux gxbb_mpeg_clk_sel = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .mask = 0x7, - .shift = 12, - .flags = CLK_MUX_READ_ONLY, - .table = mux_table_clk81, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mpeg_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MPEG_CLK_CNTL, + .mask = 0x7, + .shift = 12, + .table = mux_table_clk81, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_sel", - .ops = &clk_mux_ro_ops, + .ops = &clk_regmap_mux_ro_ops, /* * bits 14:12 selects from 8 possible parents: * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, @@ -634,14 +634,15 @@ static struct clk_regmap gxbb_clk81 = { }, }; -static struct clk_mux gxbb_sar_adc_clk_sel = { - .reg = (void *)HHI_SAR_CLK_CNTL, - .mask = 0x3, - .shift = 9, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sar_adc_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SAR_CLK_CNTL, + .mask = 0x3, + .shift = 9, + }, .hw.init = &(struct clk_init_data){ .name = "sar_adc_clk_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* NOTE: The datasheet doesn't list the parents for bit 10 */ .parent_names = (const char *[]){ "xtal", "clk81", }, .num_parents = 2, @@ -681,21 +682,20 @@ static struct clk_regmap gxbb_sar_adc_clk = { * muxed by a glitch-free switch. */ -static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7}; static const char * const gxbb_mali_0_1_parent_names[] = { "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3", "fclk_div5" }; -static struct clk_mux gxbb_mali_0_sel = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .mask = 0x7, - .shift = 9, - .table = mux_table_mali_0_1, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MALI_CLK_CNTL, + .mask = 0x7, + .shift = 9, + }, .hw.init = &(struct clk_init_data){ .name = "mali_0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 10:9 selects from 8 possible parents: * xtal, gp0_pll, mpll2, mpll1, fclk_div7, @@ -736,15 +736,15 @@ static struct clk_regmap gxbb_mali_0 = { }, }; -static struct clk_mux gxbb_mali_1_sel = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .mask = 0x7, - .shift = 25, - .table = mux_table_mali_0_1, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MALI_CLK_CNTL, + .mask = 0x7, + .shift = 25, + }, .hw.init = &(struct clk_init_data){ .name = "mali_1_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 10:9 selects from 8 possible parents: * xtal, gp0_pll, mpll2, mpll1, fclk_div7, @@ -785,36 +785,35 @@ static struct clk_regmap gxbb_mali_1 = { }, }; -static u32 mux_table_mali[] = {0, 1}; static const char * const gxbb_mali_parent_names[] = { "mali_0", "mali_1" }; -static struct clk_mux gxbb_mali = { - .reg = (void *)HHI_MALI_CLK_CNTL, - .mask = 1, - .shift = 31, - .table = mux_table_mali, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_mali = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MALI_CLK_CNTL, + .mask = 1, + .shift = 31, + }, .hw.init = &(struct clk_init_data){ .name = "mali", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = gxbb_mali_parent_names, .num_parents = 2, .flags = CLK_SET_RATE_NO_REPARENT, }, }; -static struct clk_mux gxbb_cts_amclk_sel = { - .reg = (void *) HHI_AUD_CLK_CNTL, - .mask = 0x3, - .shift = 9, - /* Default parent unknown (register reset value: 0) */ - .table = (u32[]){ 1, 2, 3 }, - .lock = &meson_clk_lock, - .hw.init = &(struct clk_init_data){ +static struct clk_regmap gxbb_cts_amclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_AUD_CLK_CNTL, + .mask = 0x3, + .shift = 9, + .table = (u32[]){ 1, 2, 3 }, + }, + .hw.init = &(struct clk_init_data){ .name = "cts_amclk_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, @@ -852,16 +851,16 @@ static struct clk_regmap gxbb_cts_amclk = { }, }; -static struct clk_mux gxbb_cts_mclk_i958_sel = { - .reg = (void *)HHI_AUD_CLK_CNTL2, - .mask = 0x3, - .shift = 25, - /* Default parent unknown (register reset value: 0) */ - .table = (u32[]){ 1, 2, 3 }, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_cts_mclk_i958_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_AUD_CLK_CNTL2, + .mask = 0x3, + .shift = 25, + .table = (u32[]){ 1, 2, 3 }, + }, .hw.init = &(struct clk_init_data) { .name = "cts_mclk_i958_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, @@ -898,14 +897,15 @@ static struct clk_regmap gxbb_cts_mclk_i958 = { }, }; -static struct clk_mux gxbb_cts_i958 = { - .reg = (void *)HHI_AUD_CLK_CNTL2, - .mask = 0x1, - .shift = 27, - .lock = &meson_clk_lock, - .hw.init = &(struct clk_init_data){ +static struct clk_regmap gxbb_cts_i958 = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_AUD_CLK_CNTL2, + .mask = 0x1, + .shift = 27, + }, + .hw.init = &(struct clk_init_data){ .name = "cts_i958", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, .num_parents = 2, /* @@ -949,14 +949,15 @@ static const char * const gxbb_32k_clk_parent_names[] = { "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5" }; -static struct clk_mux gxbb_32k_clk_sel = { - .reg = (void *)HHI_32K_CLK_CNTL, - .mask = 0x3, - .shift = 16, - .lock = &meson_clk_lock, - .hw.init = &(struct clk_init_data){ +static struct clk_regmap gxbb_32k_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_32K_CLK_CNTL, + .mask = 0x3, + .shift = 16, + }, + .hw.init = &(struct clk_init_data){ .name = "32k_clk_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = gxbb_32k_clk_parent_names, .num_parents = 4, .flags = CLK_SET_RATE_PARENT, @@ -975,14 +976,15 @@ static const char * const gxbb_sd_emmc_clk0_parent_names[] = { }; /* SDIO clock */ -static struct clk_mux gxbb_sd_emmc_a_clk0_sel = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .mask = 0x7, - .shift = 9, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .mask = 0x7, + .shift = 9, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_a_clk0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = gxbb_sd_emmc_clk0_parent_names, .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .flags = CLK_SET_RATE_PARENT, @@ -1020,14 +1022,15 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = { }; /* SDcard clock */ -static struct clk_mux gxbb_sd_emmc_b_clk0_sel = { - .reg = (void *)HHI_SD_EMMC_CLK_CNTL, - .mask = 0x7, - .shift = 25, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SD_EMMC_CLK_CNTL, + .mask = 0x7, + .shift = 25, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_b_clk0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = gxbb_sd_emmc_clk0_parent_names, .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .flags = CLK_SET_RATE_PARENT, @@ -1065,14 +1068,15 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = { }; /* EMMC/NAND clock */ -static struct clk_mux gxbb_sd_emmc_c_clk0_sel = { - .reg = (void *)HHI_NAND_CLK_CNTL, - .mask = 0x7, - .shift = 9, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_NAND_CLK_CNTL, + .mask = 0x7, + .shift = 9, + }, .hw.init = &(struct clk_init_data) { .name = "sd_emmc_c_clk0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, .parent_names = gxbb_sd_emmc_clk0_parent_names, .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), .flags = CLK_SET_RATE_PARENT, @@ -1111,20 +1115,19 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = { /* VPU Clock */ -static u32 mux_table_vpu[] = {0, 1, 2, 3}; static const char * const gxbb_vpu_parent_names[] = { "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" }; -static struct clk_mux gxbb_vpu_0_sel = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .mask = 0x3, - .shift = 9, - .lock = &meson_clk_lock, - .table = mux_table_vpu, +static struct clk_regmap gxbb_vpu_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VPU_CLK_CNTL, + .mask = 0x3, + .shift = 9, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 9:10 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, @@ -1164,15 +1167,15 @@ static struct clk_regmap gxbb_vpu_0 = { }, }; -static struct clk_mux gxbb_vpu_1_sel = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .mask = 0x3, - .shift = 25, - .lock = &meson_clk_lock, - .table = mux_table_vpu, +static struct clk_regmap gxbb_vpu_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VPU_CLK_CNTL, + .mask = 0x3, + .shift = 25, + }, .hw.init = &(struct clk_init_data){ .name = "vpu_1_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 25:26 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, @@ -1212,14 +1215,15 @@ static struct clk_regmap gxbb_vpu_1 = { }, }; -static struct clk_mux gxbb_vpu = { - .reg = (void *)HHI_VPU_CLK_CNTL, - .mask = 1, - .shift = 31, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vpu = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VPU_CLK_CNTL, + .mask = 1, + .shift = 31, + }, .hw.init = &(struct clk_init_data){ .name = "vpu", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bit 31 selects from 2 possible parents: * vpu_0 or vpu_1 @@ -1232,20 +1236,19 @@ static struct clk_mux gxbb_vpu = { /* VAPB Clock */ -static u32 mux_table_vapb[] = {0, 1, 2, 3}; static const char * const gxbb_vapb_parent_names[] = { "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" }; -static struct clk_mux gxbb_vapb_0_sel = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .mask = 0x3, - .shift = 9, - .lock = &meson_clk_lock, - .table = mux_table_vapb, +static struct clk_regmap gxbb_vapb_0_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VAPBCLK_CNTL, + .mask = 0x3, + .shift = 9, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_0_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 9:10 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, @@ -1285,15 +1288,15 @@ static struct clk_regmap gxbb_vapb_0 = { }, }; -static struct clk_mux gxbb_vapb_1_sel = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .mask = 0x3, - .shift = 25, - .lock = &meson_clk_lock, - .table = mux_table_vapb, +static struct clk_regmap gxbb_vapb_1_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VAPBCLK_CNTL, + .mask = 0x3, + .shift = 25, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_1_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bits 25:26 selects from 4 possible parents: * fclk_div4, fclk_div3, fclk_div5, fclk_div7, @@ -1333,14 +1336,15 @@ static struct clk_regmap gxbb_vapb_1 = { }, }; -static struct clk_mux gxbb_vapb_sel = { - .reg = (void *)HHI_VAPBCLK_CNTL, - .mask = 1, - .shift = 31, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_vapb_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VAPBCLK_CNTL, + .mask = 1, + .shift = 31, + }, .hw.init = &(struct clk_init_data){ .name = "vapb_sel", - .ops = &clk_mux_ops, + .ops = &clk_regmap_mux_ops, /* * bit 31 selects from 2 possible parents: * vapb_0 or vapb_1 @@ -1773,27 +1777,6 @@ static struct meson_clk_mpll *const gxbb_clk_mplls[] = { &gxbb_mpll2, }; -static struct clk_mux *const gxbb_clk_muxes[] = { - &gxbb_mpeg_clk_sel, - &gxbb_sar_adc_clk_sel, - &gxbb_mali_0_sel, - &gxbb_mali_1_sel, - &gxbb_mali, - &gxbb_cts_amclk_sel, - &gxbb_cts_mclk_i958_sel, - &gxbb_cts_i958, - &gxbb_32k_clk_sel, - &gxbb_sd_emmc_a_clk0_sel, - &gxbb_sd_emmc_b_clk0_sel, - &gxbb_sd_emmc_c_clk0_sel, - &gxbb_vpu_0_sel, - &gxbb_vpu_1_sel, - &gxbb_vpu, - &gxbb_vapb_0_sel, - &gxbb_vapb_1_sel, - &gxbb_vapb_sel, -}; - static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { &gxbb_cts_amclk_div, }; @@ -1908,6 +1891,24 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_vpu_1_div, &gxbb_vapb_0_div, &gxbb_vapb_1_div, + &gxbb_mpeg_clk_sel, + &gxbb_sar_adc_clk_sel, + &gxbb_mali_0_sel, + &gxbb_mali_1_sel, + &gxbb_mali, + &gxbb_cts_amclk_sel, + &gxbb_cts_mclk_i958_sel, + &gxbb_cts_i958, + &gxbb_32k_clk_sel, + &gxbb_sd_emmc_a_clk0_sel, + &gxbb_sd_emmc_b_clk0_sel, + &gxbb_sd_emmc_c_clk0_sel, + &gxbb_vpu_0_sel, + &gxbb_vpu_1_sel, + &gxbb_vpu, + &gxbb_vapb_0_sel, + &gxbb_vapb_1_sel, + &gxbb_vapb_sel, }; struct clkc_data { @@ -1915,12 +1916,8 @@ struct clkc_data { unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; unsigned int clk_plls_count; - struct clk_mux *const *clk_muxes; - unsigned int clk_muxes_count; struct meson_clk_audio_divider *const *clk_audio_dividers; unsigned int clk_audio_dividers_count; - struct clk_regmap *const *clk_regmaps; - unsigned int clk_regmaps_count; struct clk_hw_onecell_data *hw_onecell_data; }; @@ -1929,8 +1926,6 @@ static const struct clkc_data gxbb_clkc_data = { .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxbb_clk_plls, .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), - .clk_muxes = gxbb_clk_muxes, - .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxbb_hw_onecell_data, @@ -1941,8 +1936,6 @@ static const struct clkc_data gxl_clkc_data = { .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxl_clk_plls, .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), - .clk_muxes = gxbb_clk_muxes, - .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes), .clk_audio_dividers = gxbb_audio_dividers, .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxl_hw_onecell_data, @@ -1995,11 +1988,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_mplls_count; i++) clkc_data->clk_mplls[i]->base = clk_base; - /* Populate base address for muxes */ - for (i = 0; i < clkc_data->clk_muxes_count; i++) - clkc_data->clk_muxes[i]->reg = clk_base + - (u64)clkc_data->clk_muxes[i]->reg; - /* Populate base address for the audio dividers */ for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index e9c5278072cd..e643f7556f5e 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -370,17 +370,16 @@ static struct meson_clk_cpu meson8b_cpu_clk = { }; static u32 mux_table_clk81[] = { 6, 5, 7 }; - -struct clk_mux meson8b_mpeg_clk_sel = { - .reg = (void *)HHI_MPEG_CLK_CNTL, - .mask = 0x7, - .shift = 12, - .flags = CLK_MUX_READ_ONLY, - .table = mux_table_clk81, - .lock = &meson_clk_lock, +static struct clk_regmap meson8b_mpeg_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MPEG_CLK_CNTL, + .mask = 0x7, + .shift = 12, + .table = mux_table_clk81, + }, .hw.init = &(struct clk_init_data){ .name = "mpeg_clk_sel", - .ops = &clk_mux_ro_ops, + .ops = &clk_regmap_mux_ro_ops, /* * FIXME bits 14:12 selects from 8 possible parents: * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, @@ -620,10 +619,6 @@ static struct meson_clk_mpll *const meson8b_clk_mplls[] = { &meson8b_mpll2, }; -static struct clk_mux *const meson8b_clk_muxes[] = { - &meson8b_mpeg_clk_sel, -}; - static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, @@ -704,6 +699,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_ao_ahb_bus, &meson8b_ao_iface, &meson8b_mpeg_clk_div, + &meson8b_mpeg_clk_sel, }; static const struct meson8b_clk_reset_line { @@ -837,11 +833,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) /* Populate the base address for CPU clk */ meson8b_cpu_clk.base = clk_base; - /* Populate base address for muxes */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++) - meson8b_clk_muxes[i]->reg = clk_base + - (u32)meson8b_clk_muxes[i]->reg; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) meson8b_clk_regmaps[i]->map = map; From patchwork Wed Jan 31 18:09:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126397 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp970212ljc; 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Providing helpers to access these field with regmap helps keep drivers readable Signed-off-by: Jerome Brunet --- drivers/clk/meson/clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.14.3 diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index aa2dfa0ff89f..8edc25297422 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -38,6 +38,22 @@ struct parm { u8 width; }; +static inline unsigned int meson_parm_read(struct regmap *map, struct parm *p) +{ + unsigned int val; + + regmap_read(map, p->reg_off, &val); + return PARM_GET(p->width, p->shift, val); +} + +static inline void meson_parm_write(struct regmap *map, struct parm *p, + unsigned int val) +{ + regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift), + val << p->shift); +} + + struct pll_rate_table { unsigned long rate; u16 m; From patchwork Wed Jan 31 18:09:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126395 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp969548ljc; Wed, 31 Jan 2018 10:11:44 -0800 (PST) X-Google-Smtp-Source: AH8x224O28s/NU7qr7Rqt88BQzqcauTaSHrWkjf3gGtCeZQwQn1IGw4D4LTnv/lLaaulpYNiJk/v X-Received: by 2002:a17:902:241:: with SMTP id 59-v6mr29434878plc.280.1517422304573; Wed, 31 Jan 2018 10:11:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422304; cv=none; d=google.com; s=arc-20160816; b=Z2Afdasa52loNB6m98FbMXIWPxex3jkMMtxQQdTvOrUcBOhb3ya9LK9XkBsIFxpw/+ Iw6vVNADmeTUF18QtjzkMiIxvOwtxXZHM55GGbDe2f/93FO/2AvxZDkYdVHzNKIdSt6B i4EX/iyBU3DLcd/k7XkjiND2oQvhTxCG8y5V+97wPnnUDCHOOQKpx9II6IDSRTlV43+Z wTg89j0pqXjABNdGZzEc/s7LitO8onU72IlQ18v+cACNI6n28+1C+PcC7Jmkg0eB6Ad8 vzIEf9n0gjK4h00xNvfmrUYouOWH1VVY4vyfTsJALJ9A9a5aCHQ9YaMfEswS8fcL4o2Q f1Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pyDht8pbarcnE68yPMWsepHmNEw6eUeICUxp+1E6bfk=; b=JYQjdNBmVKQ/C4mavZxBZUCU9p3jh60e3X8Bbe9YSeoBKrsKByPpz5QzVJm2s5hG0j /Q1W2SxGUz5np8Wz23xNTVIFUqB8d3dRmFWIS1VeaWAqoigPzfChTe6S+BSleAyvtmT9 22UyatfJwjrf2aKRVceRLK18sfh/sEWcVES7tBc4fsURXRbE/oob0zLM0xR1mjnZ1Scf QyphJneO7b6jUqdfvDqdT48qaZSyli5+SZccQDzcHt6T+snsFjs3aY9cyeuhgP8SXvMq OI1B55yA78Fx3VhUWKpiYNmvp6H+Xq0l/WFTCoR/IEwNJtnKlNfe1e4LD3iZctqYDnC0 YRPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=J3H7B/LO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 31 Jan 2018 10:10:03 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.10.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:10:02 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/19] clk: meson: migrate mplls clocks to clk_regmap Date: Wed, 31 Jan 2018 19:09:39 +0100 Message-Id: <20180131180945.18025-14-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Rework meson mpll driver to use clk_regmap and move meson8b, gxbb and axg clocks using meson_clk_mpll to clk_regmap Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 245 +++++++++++++++++++++---------------------- drivers/clk/meson/clk-mpll.c | 102 +++++++----------- drivers/clk/meson/clkc.h | 4 +- drivers/clk/meson/gxbb.c | 161 ++++++++++++++-------------- drivers/clk/meson/meson8b.c | 155 ++++++++++++++------------- 5 files changed, 313 insertions(+), 354 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 6ce413a9d0dd..5c753be71b45 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -267,38 +267,40 @@ static struct clk_fixed_factor axg_fclk_div7 = { }, }; -static struct meson_clk_mpll axg_mpll0 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, +static struct clk_regmap axg_mpll0 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 14, + .width = 1, + }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 0, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .ssen = { - .reg_off = HHI_MPLL_CNTL, - .shift = 25, - .width = 1, - }, - .misc = { - .reg_off = HHI_PLL_TOP_MISC, - .shift = 0, - .width = 1, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll0", .ops = &meson_clk_mpll_ops, @@ -307,33 +309,35 @@ static struct meson_clk_mpll axg_mpll0 = { }, }; -static struct meson_clk_mpll axg_mpll1 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 0, - .width = 14, +static struct clk_regmap axg_mpll1 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 14, + .width = 1, + }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 1, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, - }, - .misc = { - .reg_off = HHI_PLL_TOP_MISC, - .shift = 1, - .width = 1, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll1", .ops = &meson_clk_mpll_ops, @@ -342,33 +346,35 @@ static struct meson_clk_mpll axg_mpll1 = { }, }; -static struct meson_clk_mpll axg_mpll2 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 15, - .width = 1, +static struct clk_regmap axg_mpll2 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 14, + .width = 1, + }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 2, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .n2 = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, - }, - .misc = { - .reg_off = HHI_PLL_TOP_MISC, - .shift = 2, - .width = 1, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll2", .ops = &meson_clk_mpll_ops, @@ -377,33 +383,35 @@ static struct meson_clk_mpll axg_mpll2 = { }, }; -static struct meson_clk_mpll axg_mpll3 = { - .sdm = { - .reg_off = HHI_MPLL3_CNTL0, - .shift = 12, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL3_CNTL0, - .shift = 11, - .width = 1, +static struct clk_regmap axg_mpll3 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 12, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 11, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 2, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL3_CNTL0, + .shift = 0, + .width = 1, + }, + .misc = { + .reg_off = HHI_PLL_TOP_MISC, + .shift = 3, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .n2 = { - .reg_off = HHI_MPLL3_CNTL0, - .shift = 2, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL3_CNTL0, - .shift = 0, - .width = 1, - }, - .misc = { - .reg_off = HHI_PLL_TOP_MISC, - .shift = 3, - .width = 1, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll3", .ops = &meson_clk_mpll_ops, @@ -698,13 +706,6 @@ static struct meson_clk_pll *const axg_clk_plls[] = { &axg_gp0_pll, }; -static struct meson_clk_mpll *const axg_clk_mplls[] = { - &axg_mpll0, - &axg_mpll1, - &axg_mpll2, - &axg_mpll3, -}; - static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, @@ -759,19 +760,19 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_mpeg_clk_sel, &axg_sd_emmc_b_clk0_sel, &axg_sd_emmc_c_clk0_sel, + &axg_mpll0, + &axg_mpll1, + &axg_mpll2, + &axg_mpll3, }; struct clkc_data { - struct meson_clk_mpll *const *clk_mplls; - unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; unsigned int clk_plls_count; struct clk_hw_onecell_data *hw_onecell_data; }; static const struct clkc_data axg_clkc_data = { - .clk_mplls = axg_clk_mplls, - .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls), .clk_plls = axg_clk_plls, .clk_plls_count = ARRAY_SIZE(axg_clk_plls), .hw_onecell_data = &axg_hw_onecell_data, @@ -820,10 +821,6 @@ static int axg_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_plls_count; i++) clkc_data->clk_plls[i]->base = clk_base; - /* Populate base address for MPLLs */ - for (i = 0; i < clkc_data->clk_mplls_count; i++) - clkc_data->clk_mplls[i]->base = clk_base; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 6d79d6daadc4..66998ff47635 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -68,11 +68,15 @@ #define N2_MIN 4 #define N2_MAX 511 -#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw) +static inline struct meson_clk_mpll_data * +meson_clk_mpll_data(struct clk_regmap *clk) +{ + return (struct meson_clk_mpll_data *)clk->data; +} static long rate_from_params(unsigned long parent_rate, - unsigned long sdm, - unsigned long n2) + unsigned int sdm, + unsigned int n2) { unsigned long divisor = (SDM_DEN * n2) + sdm; @@ -84,8 +88,8 @@ static long rate_from_params(unsigned long parent_rate, static void params_from_rate(unsigned long requested_rate, unsigned long parent_rate, - unsigned long *sdm, - unsigned long *n2) + unsigned int *sdm, + unsigned int *n2) { uint64_t div = parent_rate; unsigned long rem = do_div(div, requested_rate); @@ -105,31 +109,23 @@ static void params_from_rate(unsigned long requested_rate, static unsigned long mpll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw); - struct parm *p; - unsigned long reg, sdm, n2; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); + unsigned int sdm, n2; long rate; - p = &mpll->sdm; - reg = readl(mpll->base + p->reg_off); - sdm = PARM_GET(p->width, p->shift, reg); - - p = &mpll->n2; - reg = readl(mpll->base + p->reg_off); - n2 = PARM_GET(p->width, p->shift, reg); + sdm = meson_parm_read(clk->map, &mpll->sdm); + n2 = meson_parm_read(clk->map, &mpll->n2); rate = rate_from_params(parent_rate, sdm, n2); - if (rate < 0) - return 0; - - return rate; + return rate < 0 ? 0 : rate; } static long mpll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - unsigned long sdm, n2; + unsigned int sdm, n2; params_from_rate(rate, *parent_rate, &sdm, &n2); return rate_from_params(*parent_rate, sdm, n2); @@ -139,9 +135,9 @@ static int mpll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw); - struct parm *p; - unsigned long reg, sdm, n2; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); + unsigned int sdm, n2; unsigned long flags = 0; params_from_rate(rate, parent_rate, &sdm, &n2); @@ -151,34 +147,20 @@ static int mpll_set_rate(struct clk_hw *hw, else __acquire(mpll->lock); - p = &mpll->sdm; - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, sdm); - writel(reg, mpll->base + p->reg_off); - - p = &mpll->sdm_en; - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, 1); - writel(reg, mpll->base + p->reg_off); - - p = &mpll->ssen; - if (p->width != 0) { - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, 1); - writel(reg, mpll->base + p->reg_off); - } + /* Enable and set the fractional part */ + meson_parm_write(clk->map, &mpll->sdm, sdm); + meson_parm_write(clk->map, &mpll->sdm_en, 1); - p = &mpll->n2; - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, n2); - writel(reg, mpll->base + p->reg_off); + /* Set additional fractional part enable if required */ + if (MESON_PARM_APPLICABLE(&mpll->ssen)) + meson_parm_write(clk->map, &mpll->ssen, 1); - p = &mpll->misc; - if (p->width != 0) { - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, 1); - writel(reg, mpll->base + p->reg_off); - } + /* Set the integer divider part */ + meson_parm_write(clk->map, &mpll->n2, n2); + + /* Set the magic misc bit if required */ + if (MESON_PARM_APPLICABLE(&mpll->misc)) + meson_parm_write(clk->map, &mpll->misc, 1); if (mpll->lock) spin_unlock_irqrestore(mpll->lock, flags); @@ -190,9 +172,8 @@ static int mpll_set_rate(struct clk_hw *hw, static void mpll_enable_core(struct clk_hw *hw, int enable) { - struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw); - struct parm *p; - unsigned long reg; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); unsigned long flags = 0; if (mpll->lock) @@ -200,10 +181,7 @@ static void mpll_enable_core(struct clk_hw *hw, int enable) else __acquire(mpll->lock); - p = &mpll->en; - reg = readl(mpll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, enable ? 1 : 0); - writel(reg, mpll->base + p->reg_off); + meson_parm_write(clk->map, &mpll->en, enable ? 1 : 0); if (mpll->lock) spin_unlock_irqrestore(mpll->lock, flags); @@ -226,16 +204,10 @@ static void mpll_disable(struct clk_hw *hw) static int mpll_is_enabled(struct clk_hw *hw) { - struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw); - struct parm *p; - unsigned long reg; - int en; - - p = &mpll->en; - reg = readl(mpll->base + p->reg_off); - en = PARM_GET(p->width, p->shift, reg); + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); - return en; + return meson_parm_read(clk->map, &mpll->en); } const struct clk_ops meson_clk_mpll_ro_ops = { diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 8edc25297422..08a1ebfc65dc 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -132,9 +132,7 @@ struct meson_clk_cpu { int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event, void *data); -struct meson_clk_mpll { - struct clk_hw hw; - void __iomem *base; +struct meson_clk_mpll_data { struct parm sdm; struct parm sdm_en; struct parm n2; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index d9f426265774..d2724a7ce9e7 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -482,33 +482,35 @@ static struct clk_fixed_factor gxbb_fclk_div7 = { }, }; -static struct meson_clk_mpll gxbb_mpll0 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, - }, - .ssen = { - .reg_off = HHI_MPLL_CNTL, - .shift = 25, - .width = 1, +static struct clk_regmap gxbb_mpll0 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 14, + .width = 1, + }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll0", .ops = &meson_clk_mpll_ops, @@ -517,28 +519,30 @@ static struct meson_clk_mpll gxbb_mpll0 = { }, }; -static struct meson_clk_mpll gxbb_mpll1 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, +static struct clk_regmap gxbb_mpll1 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 14, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll1", .ops = &meson_clk_mpll_ops, @@ -547,28 +551,30 @@ static struct meson_clk_mpll gxbb_mpll1 = { }, }; -static struct meson_clk_mpll gxbb_mpll2 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, +static struct clk_regmap gxbb_mpll2 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 14, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll2", .ops = &meson_clk_mpll_ops, @@ -1771,12 +1777,6 @@ static struct meson_clk_pll *const gxl_clk_plls[] = { &gxl_gp0_pll, }; -static struct meson_clk_mpll *const gxbb_clk_mplls[] = { - &gxbb_mpll0, - &gxbb_mpll1, - &gxbb_mpll2, -}; - static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { &gxbb_cts_amclk_div, }; @@ -1909,11 +1909,12 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_vapb_0_sel, &gxbb_vapb_1_sel, &gxbb_vapb_sel, + &gxbb_mpll0, + &gxbb_mpll1, + &gxbb_mpll2, }; struct clkc_data { - struct meson_clk_mpll *const *clk_mplls; - unsigned int clk_mplls_count; struct meson_clk_pll *const *clk_plls; unsigned int clk_plls_count; struct meson_clk_audio_divider *const *clk_audio_dividers; @@ -1922,8 +1923,6 @@ struct clkc_data { }; static const struct clkc_data gxbb_clkc_data = { - .clk_mplls = gxbb_clk_mplls, - .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxbb_clk_plls, .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), .clk_audio_dividers = gxbb_audio_dividers, @@ -1932,8 +1931,6 @@ static const struct clkc_data gxbb_clkc_data = { }; static const struct clkc_data gxl_clkc_data = { - .clk_mplls = gxbb_clk_mplls, - .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls), .clk_plls = gxl_clk_plls, .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), .clk_audio_dividers = gxbb_audio_dividers, @@ -1984,10 +1981,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_plls_count; i++) clkc_data->clk_plls[i]->base = clk_base; - /* Populate base address for MPLLs */ - for (i = 0; i < clkc_data->clk_mplls_count; i++) - clkc_data->clk_mplls[i]->base = clk_base; - /* Populate base address for the audio dividers */ for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) clkc_data->clk_audio_dividers[i]->base = clk_base; diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index e643f7556f5e..4bb51c8f3102 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -257,33 +257,35 @@ static struct clk_fixed_factor meson8b_fclk_div7 = { }, }; -static struct meson_clk_mpll meson8b_mpll0 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, - }, - .ssen = { - .reg_off = HHI_MPLL_CNTL, - .shift = 25, - .width = 1, +static struct clk_regmap meson8b_mpll0 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL7, + .shift = 14, + .width = 1, + }, + .ssen = { + .reg_off = HHI_MPLL_CNTL, + .shift = 25, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll0", .ops = &meson_clk_mpll_ops, @@ -292,28 +294,30 @@ static struct meson_clk_mpll meson8b_mpll0 = { }, }; -static struct meson_clk_mpll meson8b_mpll1 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 16, - .width = 9, +static struct clk_regmap meson8b_mpll1 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL8, + .shift = 14, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll1", .ops = &meson_clk_mpll_ops, @@ -322,28 +326,30 @@ static struct meson_clk_mpll meson8b_mpll1 = { }, }; -static struct meson_clk_mpll meson8b_mpll2 = { - .sdm = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 0, - .width = 14, - }, - .sdm_en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 15, - .width = 1, - }, - .n2 = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 16, - .width = 9, - }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, +static struct clk_regmap meson8b_mpll2 = { + .data = &(struct meson_clk_mpll_data){ + .sdm = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 0, + .width = 14, + }, + .sdm_en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 15, + .width = 1, + }, + .n2 = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 16, + .width = 9, + }, + .en = { + .reg_off = HHI_MPLL_CNTL9, + .shift = 14, + .width = 1, + }, + .lock = &meson_clk_lock, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "mpll2", .ops = &meson_clk_mpll_ops, @@ -613,12 +619,6 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = { &meson8b_sys_pll, }; -static struct meson_clk_mpll *const meson8b_clk_mplls[] = { - &meson8b_mpll0, - &meson8b_mpll1, - &meson8b_mpll2, -}; - static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, @@ -700,6 +700,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_ao_iface, &meson8b_mpeg_clk_div, &meson8b_mpeg_clk_sel, + &meson8b_mpll0, + &meson8b_mpll1, + &meson8b_mpll2, }; static const struct meson8b_clk_reset_line { @@ -826,10 +829,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) meson8b_clk_plls[i]->base = clk_base; - /* Populate base address for MPLLs */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_mplls); i++) - meson8b_clk_mplls[i]->base = clk_base; - /* Populate the base address for CPU clk */ meson8b_cpu_clk.base = clk_base; From patchwork Wed Jan 31 18:09:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126394 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp969489ljc; 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Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-audio-divider.c | 63 +++++++++++------------------------ drivers/clk/meson/clkc.h | 5 +-- drivers/clk/meson/gxbb.c | 30 +++++------------ 3 files changed, 30 insertions(+), 68 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c index 6c07db06642d..f7ab5b1db342 100644 --- a/drivers/clk/meson/clk-audio-divider.c +++ b/drivers/clk/meson/clk-audio-divider.c @@ -28,8 +28,11 @@ #include #include "clkc.h" -#define to_meson_clk_audio_divider(_hw) container_of(_hw, \ - struct meson_clk_audio_divider, hw) +static inline struct meson_clk_audio_div_data * +meson_clk_audio_div_data(struct clk_regmap *clk) +{ + return (struct meson_clk_audio_div_data *)clk->data; +} static int _div_round(unsigned long parent_rate, unsigned long rate, unsigned long flags) @@ -45,15 +48,9 @@ static int _get_val(unsigned long parent_rate, unsigned long rate) return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; } -static int _valid_divider(struct clk_hw *hw, int divider) +static int _valid_divider(unsigned int width, int divider) { - struct meson_clk_audio_divider *adiv = - to_meson_clk_audio_divider(hw); - int max_divider; - u8 width; - - width = adiv->div.width; - max_divider = 1 << width; + int max_divider = 1 << width; return clamp(divider, 1, max_divider); } @@ -61,14 +58,11 @@ static int _valid_divider(struct clk_hw *hw, int divider) static unsigned long audio_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct meson_clk_audio_divider *adiv = - to_meson_clk_audio_divider(hw); - struct parm *p; - unsigned long reg, divider; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk); + unsigned long divider; - p = &adiv->div; - reg = readl(adiv->base + p->reg_off); - divider = PARM_GET(p->width, p->shift, reg) + 1; + divider = meson_parm_read(clk->map, &adiv->div); return DIV_ROUND_UP_ULL((u64)parent_rate, divider); } @@ -77,14 +71,14 @@ static long audio_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct meson_clk_audio_divider *adiv = - to_meson_clk_audio_divider(hw); + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk); unsigned long max_prate; int divider; if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { divider = _div_round(*parent_rate, rate, adiv->flags); - divider = _valid_divider(hw, divider); + divider = _valid_divider(adiv->div.width, divider); return DIV_ROUND_UP_ULL((u64)*parent_rate, divider); } @@ -93,7 +87,7 @@ static long audio_divider_round_rate(struct clk_hw *hw, /* Get the corresponding rounded down divider */ divider = max_prate / rate; - divider = _valid_divider(hw, divider); + divider = _valid_divider(adiv->div.width, divider); /* Get actual rate of the parent */ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), @@ -106,28 +100,11 @@ static int audio_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct meson_clk_audio_divider *adiv = - to_meson_clk_audio_divider(hw); - struct parm *p; - unsigned long reg, flags = 0; - int val; - - val = _get_val(parent_rate, rate); - - if (adiv->lock) - spin_lock_irqsave(adiv->lock, flags); - else - __acquire(adiv->lock); - - p = &adiv->div; - reg = readl(adiv->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, val); - writel(reg, adiv->base + p->reg_off); - - if (adiv->lock) - spin_unlock_irqrestore(adiv->lock, flags); - else - __release(adiv->lock); + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk); + int val = _get_val(parent_rate, rate); + + meson_parm_write(clk->map, &adiv->div, val); return 0; } diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 08a1ebfc65dc..a4a526cbca4c 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -142,12 +142,9 @@ struct meson_clk_mpll_data { spinlock_t *lock; }; -struct meson_clk_audio_divider { - struct clk_hw hw; - void __iomem *base; +struct meson_clk_audio_div_data { struct parm div; u8 flags; - spinlock_t *lock; }; #define MESON_GATE(_name, _reg, _bit) \ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index d2724a7ce9e7..196557f11608 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -826,14 +826,15 @@ static struct clk_regmap gxbb_cts_amclk_sel = { }, }; -static struct meson_clk_audio_divider gxbb_cts_amclk_div = { - .div = { - .reg_off = HHI_AUD_CLK_CNTL, - .shift = 0, - .width = 8, +static struct clk_regmap gxbb_cts_amclk_div = { + .data = &(struct meson_clk_audio_div_data){ + .div = { + .reg_off = HHI_AUD_CLK_CNTL, + .shift = 0, + .width = 8, + }, + .flags = CLK_DIVIDER_ROUND_CLOSEST, }, - .flags = CLK_DIVIDER_ROUND_CLOSEST, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "cts_amclk_div", .ops = &meson_clk_audio_divider_ops, @@ -1777,10 +1778,6 @@ static struct meson_clk_pll *const gxl_clk_plls[] = { &gxl_gp0_pll, }; -static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { - &gxbb_cts_amclk_div, -}; - static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_clk81, &gxbb_ddr, @@ -1912,29 +1909,24 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_mpll0, &gxbb_mpll1, &gxbb_mpll2, + &gxbb_cts_amclk_div, }; struct clkc_data { struct meson_clk_pll *const *clk_plls; unsigned int clk_plls_count; - struct meson_clk_audio_divider *const *clk_audio_dividers; - unsigned int clk_audio_dividers_count; struct clk_hw_onecell_data *hw_onecell_data; }; static const struct clkc_data gxbb_clkc_data = { .clk_plls = gxbb_clk_plls, .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), - .clk_audio_dividers = gxbb_audio_dividers, - .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxbb_hw_onecell_data, }; static const struct clkc_data gxl_clkc_data = { .clk_plls = gxl_clk_plls, .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), - .clk_audio_dividers = gxbb_audio_dividers, - .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers), .hw_onecell_data = &gxl_hw_onecell_data, }; @@ -1981,10 +1973,6 @@ static int gxbb_clkc_probe(struct platform_device *pdev) for (i = 0; i < clkc_data->clk_plls_count; i++) clkc_data->clk_plls[i]->base = clk_base; - /* Populate base address for the audio dividers */ - for (i = 0; i < clkc_data->clk_audio_dividers_count; i++) - clkc_data->clk_audio_dividers[i]->base = clk_base; - /* Populate regmap for the common regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) gx_clk_regmaps[i]->map = map; From patchwork Wed Jan 31 18:09:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126393 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp969256ljc; Wed, 31 Jan 2018 10:11:23 -0800 (PST) X-Google-Smtp-Source: AH8x224mZt8kEObNoTRa4HG1sdEsjPffDtOr398diNsAYuOHSor6d4p2gYm6nSm7HxkXJzsRNqFk X-Received: by 10.98.34.27 with SMTP id i27mr34057945pfi.43.1517422283404; Wed, 31 Jan 2018 10:11:23 -0800 (PST) ARC-Seal: i=1; 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This rework is not just about clk_regmap, there a serious clean-up of the driver code: * Add lock and reset field: Previously inferred from the n field. * Simplify the reset logic: Code seemed to apply reset differently but in fact it always the same -> assert reset, apply params, de-assert reset. The 2 lock checking loops have been kept for now, as they seem to be necessary. * Do the sequence of init register pokes only at .init() instead of in .set_rate(). Redoing the init on every set_rate() is not necessary Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 213 +++++++++++----------- drivers/clk/meson/clk-pll.c | 243 ++++++++++--------------- drivers/clk/meson/clkc.h | 36 +--- drivers/clk/meson/gxbb.c | 424 +++++++++++++++++++++++++------------------- drivers/clk/meson/meson8b.c | 149 +++++++++------- 5 files changed, 535 insertions(+), 530 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 5c753be71b45..df1f15bfd058 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -22,28 +22,39 @@ static DEFINE_SPINLOCK(meson_clk_lock); -static struct meson_clk_pll axg_fixed_pll = { - .m = { - .reg_off = HHI_MPLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_MPLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_MPLL_CNTL, - .shift = 16, - .width = 2, - }, - .frac = { - .reg_off = HHI_MPLL_CNTL2, - .shift = 0, - .width = 12, - }, - .lock = &meson_clk_lock, +static struct clk_regmap axg_fixed_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_MPLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_MPLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_MPLL_CNTL, + .shift = 16, + .width = 2, + }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, + .l = { + .reg_off = HHI_MPLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_MPLL_CNTL, + .shift = 29, + .width = 1, + }, + }, .hw.init = &(struct clk_init_data){ .name = "fixed_pll", .ops = &meson_clk_pll_ro_ops, @@ -52,23 +63,34 @@ static struct meson_clk_pll axg_fixed_pll = { }, }; -static struct meson_clk_pll axg_sys_pll = { - .m = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 10, - .width = 2, +static struct clk_regmap axg_sys_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 10, + .width = 2, + }, + .l = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 29, + .width = 1, + }, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "sys_pll", .ops = &meson_clk_pll_ro_ops, @@ -169,40 +191,47 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = { { /* sentinel */ }, }; -static struct pll_params_table axg_gp0_params_table[] = { - PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), - PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), - PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), - PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), - PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), - PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), +const struct reg_sequence axg_gp0_init_regs[] = { + { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, + { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, + { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, + { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, }; -static struct meson_clk_pll axg_gp0_pll = { - .m = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 16, - .width = 2, - }, - .params = { - .params_table = axg_gp0_params_table, - .params_count = ARRAY_SIZE(axg_gp0_params_table), - .no_init_reset = true, - .reset_lock_loop = true, - }, - .rate_table = axg_gp0_pll_rate_table, - .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table), - .lock = &meson_clk_lock, +static struct clk_regmap axg_gp0_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 29, + .width = 1, + }, + .table = axg_gp0_pll_rate_table, + .init_regs = axg_gp0_init_regs, + .init_count = ARRAY_SIZE(axg_gp0_init_regs), + .flags = CLK_MESON_PLL_LOCK_LOOP_RST, + }, .hw.init = &(struct clk_init_data){ .name = "gp0_pll", .ops = &meson_clk_pll_ops, @@ -698,14 +727,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { .num = NR_CLKS, }; -/* Convenience tables to populate base addresses in .probe */ - -static struct meson_clk_pll *const axg_clk_plls[] = { - &axg_fixed_pll, - &axg_sys_pll, - &axg_gp0_pll, -}; - +/* Convenience table to populate regmap in .probe */ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_clk81, &axg_ddr, @@ -764,22 +786,13 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_mpll1, &axg_mpll2, &axg_mpll3, -}; - -struct clkc_data { - struct meson_clk_pll *const *clk_plls; - unsigned int clk_plls_count; - struct clk_hw_onecell_data *hw_onecell_data; -}; - -static const struct clkc_data axg_clkc_data = { - .clk_plls = axg_clk_plls, - .clk_plls_count = ARRAY_SIZE(axg_clk_plls), - .hw_onecell_data = &axg_hw_onecell_data, + &axg_fixed_pll, + &axg_sys_pll, + &axg_gp0_pll, }; static const struct of_device_id clkc_match_table[] = { - { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data }, + { .compatible = "amlogic,axg-clkc" }, {} }; @@ -792,16 +805,11 @@ static const struct regmap_config clkc_regmap_config = { static int axg_clkc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - const struct clkc_data *clkc_data; struct resource *res; void __iomem *clk_base; struct regmap *map; int ret, i; - clkc_data = of_device_get_match_data(dev); - if (!clkc_data) - return -EINVAL; - /* Generic clocks and PLLs */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) @@ -817,21 +825,16 @@ static int axg_clkc_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - /* Populate base address for PLLs */ - for (i = 0; i < clkc_data->clk_plls_count; i++) - clkc_data->clk_plls[i]->base = clk_base; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; - for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { + for (i = 0; i < axg_hw_onecell_data.num; i++) { /* array might be sparse */ - if (!clkc_data->hw_onecell_data->hws[i]) + if (!axg_hw_onecell_data.hws[i]) continue; - ret = devm_clk_hw_register(dev, - clkc_data->hw_onecell_data->hws[i]); + ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]); if (ret) { dev_err(dev, "Clock registration failed\n"); return ret; @@ -839,7 +842,7 @@ static int axg_clkc_probe(struct platform_device *pdev) } return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, - clkc_data->hw_onecell_data); + &axg_hw_onecell_data); } static struct platform_driver axg_driver = { diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 218c769c6d50..f3d909719111 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -42,52 +42,36 @@ #include "clkc.h" -#define MESON_PLL_RESET BIT(29) -#define MESON_PLL_LOCK BIT(31) - -#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) +static inline struct meson_clk_pll_data * +meson_clk_pll_data(struct clk_regmap *clk) +{ + return (struct meson_clk_pll_data *)clk->data; +} static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { - struct meson_clk_pll *pll = to_meson_clk_pll(hw); - struct parm *p; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); u64 rate; u16 n, m, frac = 0, od, od2 = 0, od3 = 0; - u32 reg; - - p = &pll->n; - reg = readl(pll->base + p->reg_off); - n = PARM_GET(p->width, p->shift, reg); - p = &pll->m; - reg = readl(pll->base + p->reg_off); - m = PARM_GET(p->width, p->shift, reg); + n = meson_parm_read(clk->map, &pll->n); + m = meson_parm_read(clk->map, &pll->m); + od = meson_parm_read(clk->map, &pll->od); - p = &pll->od; - reg = readl(pll->base + p->reg_off); - od = PARM_GET(p->width, p->shift, reg); + if (MESON_PARM_APPLICABLE(&pll->od2)) + od2 = meson_parm_read(clk->map, &pll->od2); - p = &pll->od2; - if (p->width) { - reg = readl(pll->base + p->reg_off); - od2 = PARM_GET(p->width, p->shift, reg); - } - - p = &pll->od3; - if (p->width) { - reg = readl(pll->base + p->reg_off); - od3 = PARM_GET(p->width, p->shift, reg); - } + if (MESON_PARM_APPLICABLE(&pll->od3)) + od3 = meson_parm_read(clk->map, &pll->od3); rate = (u64)m * parent_rate; - p = &pll->frac; - if (p->width) { - reg = readl(pll->base + p->reg_off); - frac = PARM_GET(p->width, p->shift, reg); + if (MESON_PARM_APPLICABLE(&pll->frac)) { + frac = meson_parm_read(clk->map, &pll->frac); - rate += mul_u64_u32_shr(parent_rate, frac, p->width); + rate += mul_u64_u32_shr(parent_rate, frac, pll->frac.width); } return div_u64(rate, n) >> od >> od2 >> od3; @@ -96,177 +80,136 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - struct meson_clk_pll *pll = to_meson_clk_pll(hw); - const struct pll_rate_table *rate_table = pll->rate_table; - int i; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + const struct pll_rate_table *pllt; /* * if the table is missing, just return the current rate * since we don't have the other available frequencies */ - if (!rate_table) + if (!pll->table) return meson_clk_pll_recalc_rate(hw, *parent_rate); - for (i = 0; i < pll->rate_count; i++) { - if (rate <= rate_table[i].rate) - return rate_table[i].rate; + for (pllt = pll->table; pllt->rate; pllt++) { + if (rate <= pllt->rate) + return pllt->rate; } /* else return the smallest value */ - return rate_table[0].rate; + return pll->table[0].rate; } -static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_pll *pll, - unsigned long rate) +static const struct pll_rate_table * +meson_clk_get_pll_settings(const struct pll_rate_table *table, + unsigned long rate) { - const struct pll_rate_table *rate_table = pll->rate_table; - int i; + const struct pll_rate_table *pllt; - if (!rate_table) + if (!table) return NULL; - for (i = 0; i < pll->rate_count; i++) { - if (rate == rate_table[i].rate) - return &rate_table[i]; + for (pllt = table; pllt->rate; pllt++) { + if (rate == pllt->rate) + return pllt; } + return NULL; } -/* Specific wait loop for GXL/GXM GP0 PLL */ -static int meson_clk_pll_wait_lock_reset(struct meson_clk_pll *pll, - struct parm *p_n) +static int meson_clk_pll_wait_lock(struct clk_hw *hw) { - int delay = 100; - u32 reg; - - while (delay > 0) { - reg = readl(pll->base + p_n->reg_off); - writel(reg | MESON_PLL_RESET, pll->base + p_n->reg_off); - udelay(10); - writel(reg & ~MESON_PLL_RESET, pll->base + p_n->reg_off); - - /* This delay comes from AMLogic tree clk-gp0-gxl driver */ - mdelay(1); - - reg = readl(pll->base + p_n->reg_off); - if (reg & MESON_PLL_LOCK) + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + int delay = pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST ? + 100 : 24000000; + + do { + /* Specific wait loop for GXL/GXM GP0 PLL */ + if (pll->flags & CLK_MESON_PLL_LOCK_LOOP_RST) { + /* Procedure taken from the vendor kernel */ + meson_parm_write(clk->map, &pll->rst, 1); + udelay(10); + meson_parm_write(clk->map, &pll->rst, 0); + mdelay(1); + } + + /* Is the clock locked now ? */ + if (meson_parm_read(clk->map, &pll->l)) return 0; - delay--; - } - return -ETIMEDOUT; -} -static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll, - struct parm *p_n) -{ - int delay = 24000000; - u32 reg; - - while (delay > 0) { - reg = readl(pll->base + p_n->reg_off); - - if (reg & MESON_PLL_LOCK) - return 0; delay--; - } + } while (delay > 0); + return -ETIMEDOUT; } -static void meson_clk_pll_init_params(struct meson_clk_pll *pll) +static void meson_clk_pll_init(struct clk_hw *hw) { - int i; - - for (i = 0 ; i < pll->params.params_count ; ++i) - writel(pll->params.params_table[i].value, - pll->base + pll->params.params_table[i].reg_off); + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + + if (pll->init_count) { + meson_parm_write(clk->map, &pll->rst, 1); + regmap_multi_reg_write(clk->map, pll->init_regs, + pll->init_count); + meson_parm_write(clk->map, &pll->rst, 0); + } } static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { - struct meson_clk_pll *pll = to_meson_clk_pll(hw); - struct parm *p; - const struct pll_rate_table *rate_set; + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); + const struct pll_rate_table *pllt; unsigned long old_rate; - int ret = 0; - u32 reg; if (parent_rate == 0 || rate == 0) return -EINVAL; old_rate = rate; - rate_set = meson_clk_get_pll_settings(pll, rate); - if (!rate_set) + pllt = meson_clk_get_pll_settings(pll->table, rate); + if (!pllt) return -EINVAL; - /* Initialize the PLL in a clean state if specified */ - if (pll->params.params_count) - meson_clk_pll_init_params(pll); - - /* PLL reset */ - p = &pll->n; - reg = readl(pll->base + p->reg_off); - /* If no_init_reset is provided, avoid resetting at this point */ - if (!pll->params.no_init_reset) - writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); - - reg = PARM_SET(p->width, p->shift, reg, rate_set->n); - writel(reg, pll->base + p->reg_off); - - p = &pll->m; - reg = readl(pll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, rate_set->m); - writel(reg, pll->base + p->reg_off); - - p = &pll->od; - reg = readl(pll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, rate_set->od); - writel(reg, pll->base + p->reg_off); - - p = &pll->od2; - if (p->width) { - reg = readl(pll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, rate_set->od2); - writel(reg, pll->base + p->reg_off); - } + /* Put the pll in reset to write the params */ + meson_parm_write(clk->map, &pll->rst, 1); - p = &pll->od3; - if (p->width) { - reg = readl(pll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, rate_set->od3); - writel(reg, pll->base + p->reg_off); - } + meson_parm_write(clk->map, &pll->n, pllt->n); + meson_parm_write(clk->map, &pll->m, pllt->m); + meson_parm_write(clk->map, &pll->od, pllt->od); - p = &pll->frac; - if (p->width) { - reg = readl(pll->base + p->reg_off); - reg = PARM_SET(p->width, p->shift, reg, rate_set->frac); - writel(reg, pll->base + p->reg_off); - } + if (MESON_PARM_APPLICABLE(&pll->od2)) + meson_parm_write(clk->map, &pll->od2, pllt->od2); - p = &pll->n; - /* If clear_reset_for_lock is provided, remove the reset bit here */ - if (pll->params.clear_reset_for_lock) { - reg = readl(pll->base + p->reg_off); - writel(reg & ~MESON_PLL_RESET, pll->base + p->reg_off); - } + if (MESON_PARM_APPLICABLE(&pll->od3)) + meson_parm_write(clk->map, &pll->od3, pllt->od3); + + if (MESON_PARM_APPLICABLE(&pll->frac)) + meson_parm_write(clk->map, &pll->frac, pllt->frac); + + /* make sure the reset is cleared at this point */ + meson_parm_write(clk->map, &pll->rst, 0); - /* If reset_lock_loop, use a special loop including resetting */ - if (pll->params.reset_lock_loop) - ret = meson_clk_pll_wait_lock_reset(pll, p); - else - ret = meson_clk_pll_wait_lock(pll, p); - if (ret) { + if (meson_clk_pll_wait_lock(hw)) { pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", __func__, old_rate); + /* + * FIXME: Do we really need/want this HACK ? + * It looks unsafe. what happens if the clock gets into a + * broken state and we can't lock back on the old_rate ? Looks + * like an infinite recursion is possible + */ meson_clk_pll_set_rate(hw, old_rate, parent_rate); } - return ret; + return 0; } const struct clk_ops meson_clk_pll_ops = { + .init = meson_clk_pll_init, .recalc_rate = meson_clk_pll_recalc_rate, .round_rate = meson_clk_pll_round_rate, .set_rate = meson_clk_pll_set_rate, diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index a4a526cbca4c..f0d70eaffcf3 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -82,41 +82,21 @@ struct pll_rate_table { .frac = (_frac), \ } \ -struct pll_params_table { - unsigned int reg_off; - unsigned int value; -}; - -#define PLL_PARAM(_reg, _val) \ - { \ - .reg_off = (_reg), \ - .value = (_val), \ - } - -struct pll_setup_params { - struct pll_params_table *params_table; - unsigned int params_count; - /* Workaround for GP0, do not reset before configuring */ - bool no_init_reset; - /* Workaround for GP0, unreset right before checking for lock */ - bool clear_reset_for_lock; - /* Workaround for GXL GP0, reset in the lock checking loop */ - bool reset_lock_loop; -}; +#define CLK_MESON_PLL_LOCK_LOOP_RST BIT(0) -struct meson_clk_pll { - struct clk_hw hw; - void __iomem *base; +struct meson_clk_pll_data { struct parm m; struct parm n; struct parm frac; struct parm od; struct parm od2; struct parm od3; - const struct pll_setup_params params; - const struct pll_rate_table *rate_table; - unsigned int rate_count; - spinlock_t *lock; + struct parm l; + struct parm rst; + const struct reg_sequence *init_regs; + unsigned int init_count; + const struct pll_rate_table *table; + u8 flags; }; #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 196557f11608..49f5716ce8b6 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -188,28 +188,39 @@ static const struct pll_rate_table gxl_gp0_pll_rate_table[] = { { /* sentinel */ }, }; -static struct meson_clk_pll gxbb_fixed_pll = { - .m = { - .reg_off = HHI_MPLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_MPLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_MPLL_CNTL, - .shift = 16, - .width = 2, - }, - .frac = { - .reg_off = HHI_MPLL_CNTL2, - .shift = 0, - .width = 12, - }, - .lock = &meson_clk_lock, +static struct clk_regmap gxbb_fixed_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_MPLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_MPLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_MPLL_CNTL, + .shift = 16, + .width = 2, + }, + .frac = { + .reg_off = HHI_MPLL_CNTL2, + .shift = 0, + .width = 12, + }, + .l = { + .reg_off = HHI_MPLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_MPLL_CNTL, + .shift = 29, + .width = 1, + }, + }, .hw.init = &(struct clk_init_data){ .name = "fixed_pll", .ops = &meson_clk_pll_ro_ops, @@ -230,38 +241,49 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = { }, }; -static struct meson_clk_pll gxbb_hdmi_pll = { - .m = { - .reg_off = HHI_HDMI_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_HDMI_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .frac = { - .reg_off = HHI_HDMI_PLL_CNTL2, - .shift = 0, - .width = 12, - }, - .od = { - .reg_off = HHI_HDMI_PLL_CNTL2, - .shift = 16, - .width = 2, - }, - .od2 = { - .reg_off = HHI_HDMI_PLL_CNTL2, - .shift = 22, - .width = 2, - }, - .od3 = { - .reg_off = HHI_HDMI_PLL_CNTL2, - .shift = 18, - .width = 2, +static struct clk_regmap gxbb_hdmi_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .frac = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 0, + .width = 12, + }, + .od = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 16, + .width = 2, + }, + .od2 = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 22, + .width = 2, + }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL2, + .shift = 18, + .width = 2, + }, + .l = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 28, + .width = 1, + }, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll", .ops = &meson_clk_pll_ro_ops, @@ -271,43 +293,55 @@ static struct meson_clk_pll gxbb_hdmi_pll = { }, }; -static struct meson_clk_pll gxl_hdmi_pll = { - .m = { - .reg_off = HHI_HDMI_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_HDMI_PLL_CNTL, - .shift = 9, - .width = 5, +static struct clk_regmap gxl_hdmi_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .frac = { + /* + * On gxl, there is a register shift due to + * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, + * so we compute the register offset based on the PLL + * base to get it right + */ + .reg_off = HHI_HDMI_PLL_CNTL + 4, + .shift = 0, + .width = 12, + }, + .od = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 21, + .width = 2, + }, + .od2 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 23, + .width = 2, + }, + .od3 = { + .reg_off = HHI_HDMI_PLL_CNTL + 8, + .shift = 19, + .width = 2, + }, + .l = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_HDMI_PLL_CNTL, + .shift = 29, + .width = 1, + }, }, - .frac = { - /* - * On gxl, there is a register shift due to HHI_HDMI_PLL_CNTL1 - * which does not exist on gxbb, so we compute the register - * offset based on the PLL base to get it right - */ - .reg_off = HHI_HDMI_PLL_CNTL + 4, - .shift = 0, - .width = 12, - }, - .od = { - .reg_off = HHI_HDMI_PLL_CNTL + 8, - .shift = 21, - .width = 2, - }, - .od2 = { - .reg_off = HHI_HDMI_PLL_CNTL + 8, - .shift = 23, - .width = 2, - }, - .od3 = { - .reg_off = HHI_HDMI_PLL_CNTL + 8, - .shift = 19, - .width = 2, - }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "hdmi_pll", .ops = &meson_clk_pll_ro_ops, @@ -317,23 +351,34 @@ static struct meson_clk_pll gxl_hdmi_pll = { }, }; -static struct meson_clk_pll gxbb_sys_pll = { - .m = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 10, - .width = 2, +static struct clk_regmap gxbb_sys_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 10, + .width = 2, + }, + .l = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 29, + .width = 1, + }, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "sys_pll", .ops = &meson_clk_pll_ro_ops, @@ -343,38 +388,44 @@ static struct meson_clk_pll gxbb_sys_pll = { }, }; -struct pll_params_table gxbb_gp0_params_table[] = { - PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228), - PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000), - PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4), - PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d), +const struct reg_sequence gxbb_gp0_init_regs[] = { + { .reg = HHI_GP0_PLL_CNTL, .def = 0x6a000228 }, + { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 }, + { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 }, + { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d }, }; -static struct meson_clk_pll gxbb_gp0_pll = { - .m = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 16, - .width = 2, - }, - .params = { - .params_table = gxbb_gp0_params_table, - .params_count = ARRAY_SIZE(gxbb_gp0_params_table), - .no_init_reset = true, - .clear_reset_for_lock = true, +static struct clk_regmap gxbb_gp0_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 29, + .width = 1, + }, + .table = gxbb_gp0_pll_rate_table, + .init_regs = gxbb_gp0_init_regs, + .init_count = ARRAY_SIZE(gxbb_gp0_init_regs), }, - .rate_table = gxbb_gp0_pll_rate_table, - .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table), - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "gp0_pll", .ops = &meson_clk_pll_ops, @@ -384,40 +435,47 @@ static struct meson_clk_pll gxbb_gp0_pll = { }, }; -struct pll_params_table gxl_gp0_params_table[] = { - PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250), - PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000), - PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be), - PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288), - PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d), - PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000), +const struct reg_sequence gxl_gp0_init_regs[] = { + { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 }, + { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084a000 }, + { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be }, + { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 }, + { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d }, + { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 }, }; -static struct meson_clk_pll gxl_gp0_pll = { - .m = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_GP0_PLL_CNTL, - .shift = 16, - .width = 2, - }, - .params = { - .params_table = gxl_gp0_params_table, - .params_count = ARRAY_SIZE(gxl_gp0_params_table), - .no_init_reset = true, - .reset_lock_loop = true, +static struct clk_regmap gxl_gp0_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_GP0_PLL_CNTL, + .shift = 29, + .width = 1, + }, + .table = gxl_gp0_pll_rate_table, + .init_regs = gxl_gp0_init_regs, + .init_count = ARRAY_SIZE(gxl_gp0_init_regs), + .flags = CLK_MESON_PLL_LOCK_LOOP_RST, }, - .rate_table = gxl_gp0_pll_rate_table, - .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table), - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "gp0_pll", .ops = &meson_clk_pll_ops, @@ -1762,20 +1820,14 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { .num = NR_CLKS, }; -/* Convenience tables to populate base addresses in .probe */ - -static struct meson_clk_pll *const gxbb_clk_plls[] = { - &gxbb_fixed_pll, - &gxbb_hdmi_pll, - &gxbb_sys_pll, +static struct clk_regmap *const gxbb_clk_regmaps[] = { &gxbb_gp0_pll, + &gxbb_hdmi_pll, }; -static struct meson_clk_pll *const gxl_clk_plls[] = { - &gxbb_fixed_pll, - &gxl_hdmi_pll, - &gxbb_sys_pll, +static struct clk_regmap *const gxl_clk_regmaps[] = { &gxl_gp0_pll, + &gxl_hdmi_pll, }; static struct clk_regmap *const gx_clk_regmaps[] = { @@ -1910,23 +1962,25 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_mpll1, &gxbb_mpll2, &gxbb_cts_amclk_div, + &gxbb_fixed_pll, + &gxbb_sys_pll, }; struct clkc_data { - struct meson_clk_pll *const *clk_plls; - unsigned int clk_plls_count; + struct clk_regmap *const *regmap_clks; + unsigned int regmap_clks_count; struct clk_hw_onecell_data *hw_onecell_data; }; static const struct clkc_data gxbb_clkc_data = { - .clk_plls = gxbb_clk_plls, - .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls), + .regmap_clks = gxbb_clk_regmaps, + .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps), .hw_onecell_data = &gxbb_hw_onecell_data, }; static const struct clkc_data gxl_clkc_data = { - .clk_plls = gxl_clk_plls, - .clk_plls_count = ARRAY_SIZE(gxl_clk_plls), + .regmap_clks = gxl_clk_regmaps, + .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps), .hw_onecell_data = &gxl_hw_onecell_data, }; @@ -1969,14 +2023,14 @@ static int gxbb_clkc_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - /* Populate base address for PLLs */ - for (i = 0; i < clkc_data->clk_plls_count; i++) - clkc_data->clk_plls[i]->base = clk_base; - /* Populate regmap for the common regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++) gx_clk_regmaps[i]->map = map; + /* Populate regmap for soc specific clocks */ + for (i = 0; i < clkc_data->regmap_clks_count; i++) + clkc_data->regmap_clks[i]->map = map; + /* Register all clks */ for (i = 0; i < clkc_data->hw_onecell_data->num; i++) { /* array might be sparse */ diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 4bb51c8f3102..4fd8253c54bb 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -122,23 +122,34 @@ static struct clk_fixed_rate meson8b_xtal = { }, }; -static struct meson_clk_pll meson8b_fixed_pll = { - .m = { - .reg_off = HHI_MPLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_MPLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_MPLL_CNTL, - .shift = 16, - .width = 2, - }, - .lock = &meson_clk_lock, +static struct clk_regmap meson8b_fixed_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_MPLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_MPLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_MPLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_MPLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_MPLL_CNTL, + .shift = 29, + .width = 1, + }, + }, .hw.init = &(struct clk_init_data){ .name = "fixed_pll", .ops = &meson_clk_pll_ro_ops, @@ -148,23 +159,34 @@ static struct meson_clk_pll meson8b_fixed_pll = { }, }; -static struct meson_clk_pll meson8b_vid_pll = { - .m = { - .reg_off = HHI_VID_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_VID_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_VID_PLL_CNTL, - .shift = 16, - .width = 2, +static struct clk_regmap meson8b_vid_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_VID_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_VID_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_VID_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_VID_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_VID_PLL_CNTL, + .shift = 29, + .width = 1, + }, }, - .lock = &meson_clk_lock, .hw.init = &(struct clk_init_data){ .name = "vid_pll", .ops = &meson_clk_pll_ro_ops, @@ -174,25 +196,35 @@ static struct meson_clk_pll meson8b_vid_pll = { }, }; -static struct meson_clk_pll meson8b_sys_pll = { - .m = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 0, - .width = 9, - }, - .n = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 9, - .width = 5, - }, - .od = { - .reg_off = HHI_SYS_PLL_CNTL, - .shift = 16, - .width = 2, - }, - .rate_table = sys_pll_rate_table, - .rate_count = ARRAY_SIZE(sys_pll_rate_table), - .lock = &meson_clk_lock, +static struct clk_regmap meson8b_sys_pll = { + .data = &(struct meson_clk_pll_data){ + .m = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 9, + .width = 5, + }, + .od = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 16, + .width = 2, + }, + .l = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = HHI_SYS_PLL_CNTL, + .shift = 29, + .width = 1, + }, + .table = sys_pll_rate_table, + }, .hw.init = &(struct clk_init_data){ .name = "sys_pll", .ops = &meson_clk_pll_ops, @@ -613,12 +645,6 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { .num = CLK_NR_CLKS, }; -static struct meson_clk_pll *const meson8b_clk_plls[] = { - &meson8b_fixed_pll, - &meson8b_vid_pll, - &meson8b_sys_pll, -}; - static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_clk81, &meson8b_ddr, @@ -703,6 +729,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_mpll0, &meson8b_mpll1, &meson8b_mpll2, + &meson8b_fixed_pll, + &meson8b_vid_pll, + &meson8b_sys_pll, }; static const struct meson8b_clk_reset_line { @@ -825,10 +854,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - /* Populate base address for PLLs */ - for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) - meson8b_clk_plls[i]->base = clk_base; - /* Populate the base address for CPU clk */ meson8b_cpu_clk.base = clk_base; From patchwork Wed Jan 31 18:09:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126392 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp969002ljc; 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When the RW operation have been added, enable/disable ops have been mistakenly inserted in this driver. These ops are essentially a poor copy/paste of generic gate ops. This change remove the gate ops from the mpll driver and insert a generic gate clock on each mpll divider, simplifying the mpll driver and reducing code duplication. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 100 +++++++++++++++++++++++++++++++------------ drivers/clk/meson/axg.h | 6 ++- drivers/clk/meson/clk-mpll.c | 44 ------------------- drivers/clk/meson/clkc.h | 1 - drivers/clk/meson/gxbb.c | 75 +++++++++++++++++++++++--------- drivers/clk/meson/gxbb.h | 5 ++- drivers/clk/meson/meson8b.c | 75 +++++++++++++++++++++++--------- drivers/clk/meson/meson8b.h | 6 ++- 8 files changed, 194 insertions(+), 118 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index df1f15bfd058..ae1dd35246f5 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -296,7 +296,7 @@ static struct clk_fixed_factor axg_fclk_div7 = { }, }; -static struct clk_regmap axg_mpll0 = { +static struct clk_regmap axg_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL7, @@ -313,11 +313,6 @@ static struct clk_regmap axg_mpll0 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, - }, .ssen = { .reg_off = HHI_MPLL_CNTL, .shift = 25, @@ -331,14 +326,28 @@ static struct clk_regmap axg_mpll0 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll0", + .name = "mpll0_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap axg_mpll1 = { +static struct clk_regmap axg_mpll0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL7, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll0_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axg_mpll1_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL8, @@ -355,11 +364,6 @@ static struct clk_regmap axg_mpll1 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, - }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 1, @@ -368,14 +372,28 @@ static struct clk_regmap axg_mpll1 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll1", + .name = "mpll1_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap axg_mpll2 = { +static struct clk_regmap axg_mpll1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL8, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll1", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll1_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axg_mpll2_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL9, @@ -392,11 +410,6 @@ static struct clk_regmap axg_mpll2 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, - }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 2, @@ -405,14 +418,28 @@ static struct clk_regmap axg_mpll2 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll2", + .name = "mpll2_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap axg_mpll3 = { +static struct clk_regmap axg_mpll2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL9, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll2_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axg_mpll3_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL3_CNTL0, @@ -429,11 +456,6 @@ static struct clk_regmap axg_mpll3 = { .shift = 2, .width = 9, }, - .en = { - .reg_off = HHI_MPLL3_CNTL0, - .shift = 0, - .width = 1, - }, .misc = { .reg_off = HHI_PLL_TOP_MISC, .shift = 3, @@ -442,13 +464,27 @@ static struct clk_regmap axg_mpll3 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll3", + .name = "mpll3_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap axg_mpll3 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL3_CNTL0, + .bit_idx = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll3", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll3_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", @@ -722,6 +758,10 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw, [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw, [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw, + [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw, + [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -786,6 +826,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_mpll1, &axg_mpll2, &axg_mpll3, + &axg_mpll0_div, + &axg_mpll1_div, + &axg_mpll2_div, + &axg_mpll3_div, &axg_fixed_pll, &axg_sys_pll, &axg_gp0_pll, diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index ce0bafdb6b28..4c1502a8b8c9 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -117,8 +117,12 @@ #define CLKID_SD_EMMC_B_CLK0_DIV 62 #define CLKID_SD_EMMC_C_CLK0_SEL 63 #define CLKID_SD_EMMC_C_CLK0_DIV 64 +#define CLKID_MPLL0_DIV 65 +#define CLKID_MPLL1_DIV 66 +#define CLKID_MPLL2_DIV 67 +#define CLKID_MPLL3_DIV 68 -#define NR_CLKS 65 +#define NR_CLKS 69 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c index 66998ff47635..0df1227b65b3 100644 --- a/drivers/clk/meson/clk-mpll.c +++ b/drivers/clk/meson/clk-mpll.c @@ -170,57 +170,13 @@ static int mpll_set_rate(struct clk_hw *hw, return 0; } -static void mpll_enable_core(struct clk_hw *hw, int enable) -{ - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); - unsigned long flags = 0; - - if (mpll->lock) - spin_lock_irqsave(mpll->lock, flags); - else - __acquire(mpll->lock); - - meson_parm_write(clk->map, &mpll->en, enable ? 1 : 0); - - if (mpll->lock) - spin_unlock_irqrestore(mpll->lock, flags); - else - __release(mpll->lock); -} - - -static int mpll_enable(struct clk_hw *hw) -{ - mpll_enable_core(hw, 1); - - return 0; -} - -static void mpll_disable(struct clk_hw *hw) -{ - mpll_enable_core(hw, 0); -} - -static int mpll_is_enabled(struct clk_hw *hw) -{ - struct clk_regmap *clk = to_clk_regmap(hw); - struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); - - return meson_parm_read(clk->map, &mpll->en); -} - const struct clk_ops meson_clk_mpll_ro_ops = { .recalc_rate = mpll_recalc_rate, .round_rate = mpll_round_rate, - .is_enabled = mpll_is_enabled, }; const struct clk_ops meson_clk_mpll_ops = { .recalc_rate = mpll_recalc_rate, .round_rate = mpll_round_rate, .set_rate = mpll_set_rate, - .enable = mpll_enable, - .disable = mpll_disable, - .is_enabled = mpll_is_enabled, }; diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index f0d70eaffcf3..cc1a964cd4d7 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -116,7 +116,6 @@ struct meson_clk_mpll_data { struct parm sdm; struct parm sdm_en; struct parm n2; - struct parm en; struct parm ssen; struct parm misc; spinlock_t *lock; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 49f5716ce8b6..92403ab2daf5 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -540,7 +540,7 @@ static struct clk_fixed_factor gxbb_fclk_div7 = { }, }; -static struct clk_regmap gxbb_mpll0 = { +static struct clk_regmap gxbb_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL7, @@ -557,11 +557,6 @@ static struct clk_regmap gxbb_mpll0 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, - }, .ssen = { .reg_off = HHI_MPLL_CNTL, .shift = 25, @@ -570,14 +565,28 @@ static struct clk_regmap gxbb_mpll0 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll0", + .name = "mpll0_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap gxbb_mpll1 = { +static struct clk_regmap gxbb_mpll0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL7, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll0_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap gxbb_mpll1_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL8, @@ -594,22 +603,31 @@ static struct clk_regmap gxbb_mpll1 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, - }, .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll1", + .name = "mpll1_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap gxbb_mpll2 = { +static struct clk_regmap gxbb_mpll1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL8, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll1", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll1_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap gxbb_mpll2_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL9, @@ -626,21 +644,30 @@ static struct clk_regmap gxbb_mpll2 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, - }, .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll2", + .name = "mpll2_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap gxbb_mpll2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL9, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll2_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", @@ -1815,6 +1842,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = { [CLKID_VAPB_1] = &gxbb_vapb_1.hw, [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw, [CLKID_VAPB] = &gxbb_vapb.hw, + [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -1961,6 +1991,9 @@ static struct clk_regmap *const gx_clk_regmaps[] = { &gxbb_mpll0, &gxbb_mpll1, &gxbb_mpll2, + &gxbb_mpll0_div, + &gxbb_mpll1_div, + &gxbb_mpll2_div, &gxbb_cts_amclk_div, &gxbb_fixed_pll, &gxbb_sys_pll, diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 42573b28a137..a8e7b8884e95 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -195,8 +195,11 @@ #define CLKID_VAPB_0_DIV 134 #define CLKID_VAPB_1_DIV 137 #define CLKID_HDMI_PLL_PRE_MULT 141 +#define CLKID_MPLL0_DIV 142 +#define CLKID_MPLL1_DIV 143 +#define CLKID_MPLL2_DIV 144 -#define NR_CLKS 142 +#define NR_CLKS 145 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 4fd8253c54bb..625d953511be 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -289,7 +289,7 @@ static struct clk_fixed_factor meson8b_fclk_div7 = { }, }; -static struct clk_regmap meson8b_mpll0 = { +static struct clk_regmap meson8b_mpll0_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL7, @@ -306,11 +306,6 @@ static struct clk_regmap meson8b_mpll0 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL7, - .shift = 14, - .width = 1, - }, .ssen = { .reg_off = HHI_MPLL_CNTL, .shift = 25, @@ -319,14 +314,28 @@ static struct clk_regmap meson8b_mpll0 = { .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll0", + .name = "mpll0_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap meson8b_mpll1 = { +static struct clk_regmap meson8b_mpll0 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL7, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll0", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll0_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap meson8b_mpll1_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL8, @@ -343,22 +352,31 @@ static struct clk_regmap meson8b_mpll1 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL8, - .shift = 14, - .width = 1, - }, .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll1", + .name = "mpll1_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; -static struct clk_regmap meson8b_mpll2 = { +static struct clk_regmap meson8b_mpll1 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL8, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll1", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll1_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap meson8b_mpll2_div = { .data = &(struct meson_clk_mpll_data){ .sdm = { .reg_off = HHI_MPLL_CNTL9, @@ -375,21 +393,30 @@ static struct clk_regmap meson8b_mpll2 = { .shift = 16, .width = 9, }, - .en = { - .reg_off = HHI_MPLL_CNTL9, - .shift = 14, - .width = 1, - }, .lock = &meson_clk_lock, }, .hw.init = &(struct clk_init_data){ - .name = "mpll2", + .name = "mpll2_div", .ops = &meson_clk_mpll_ops, .parent_names = (const char *[]){ "fixed_pll" }, .num_parents = 1, }, }; +static struct clk_regmap meson8b_mpll2 = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_MPLL_CNTL9, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "mpll2", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "mpll2_div" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + /* * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL * post-dividers and should be modeled with their respective PLLs via the @@ -640,6 +667,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPLL0] = &meson8b_mpll0.hw, [CLKID_MPLL1] = &meson8b_mpll1.hw, [CLKID_MPLL2] = &meson8b_mpll2.hw, + [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, + [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, + [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -729,6 +759,9 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_mpll0, &meson8b_mpll1, &meson8b_mpll2, + &meson8b_mpll0_div, + &meson8b_mpll1_div, + &meson8b_mpll2_div, &meson8b_fixed_pll, &meson8b_vid_pll, &meson8b_sys_pll, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 2eaf8a52e7dd..f2780508edec 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -69,7 +69,11 @@ * will remain defined here. */ -#define CLK_NR_CLKS 96 +#define CLKID_MPLL0_DIV 96 +#define CLKID_MPLL1_DIV 97 +#define CLKID_MPLL2_DIV 98 + +#define CLK_NR_CLKS 99 /* * include the CLKID and RESETID that have From patchwork Wed Jan 31 18:09:43 2018 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id e17si1797231pgo.189.2018.01.31.10.10.24; Wed, 31 Jan 2018 10:10:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=z3UZZYxN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753905AbeAaSKW (ORCPT + 28 others); Wed, 31 Jan 2018 13:10:22 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:56224 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753856AbeAaSKJ (ORCPT ); Wed, 31 Jan 2018 13:10:09 -0500 Received: by mail-wm0-f68.google.com with SMTP id 143so821298wma.5 for ; Wed, 31 Jan 2018 10:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jV8eaynRYbjPynIV51n800Mpvh/AxpJOW3kh+L+upYM=; b=z3UZZYxNk2QiY/LKvr0gP8yPPiP8PwCTzpVX/tcxZp7vcy3KvoCNsztyBOgfttp5lm pe3beAMRizlTsk+OyWtTCdV5Jskdsr39ZlXXSjklEAClgK6avNCapuvLpMIBbT9i1KsO 7Cl+PiYhoU90/6g9MyOiBn6XjY6xpfk5gmunhfq10F227QCv0oeotuM0Capkm6gI62Lu nQHCkWpay4hexdCBSyR2/MKMHTgD4fWEODUw+mOPhEzhXYo0XnsWC4u9uHlqYKIweNCa BNgcYu5ElU5q2tXA2Vp8y38PoCV5OOCzljkcAD19i+O5gnOk+i5vBGY7s37X/I7EspVJ vO3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jV8eaynRYbjPynIV51n800Mpvh/AxpJOW3kh+L+upYM=; b=rdAuCF9RUFQjjErIuydzM2dmxLOSL2diKxlKJOqB4UUTJ9zcSRozAbB7jScKGoQYXV WH8TpmaSivmlDBQRW2MsJcQROsi7nHgD9u1VpOq6VTBQRBHalHuE2KDG0nFvc2mO7nBl i/uRDTVm6I6OOys0ViooKO9F+zbN+8CMQ6ngii9CJKYCVKzTYvFpZa8644MvhSSn2jj3 HQXUldV7s55oGtStKhVRROO/vj3hIZGhLbV4X9beS61AKCCdI9a1ejd7yPOcM4SyQ6Rc xSZQHyjIbHok9tlJ4Edw1LuLfg18WLSTlRl50kK/Yy1zyJvUUtWpCBTIB8Z9jPrqPfKg vVdg== X-Gm-Message-State: AKwxytffMrALnsnN7/PAhCNSpvE+00Idg8nFe/KCPSDF2YCIDrk/VC5k bkTVHugZQz39peHTyrSHJUtf9Q== X-Received: by 10.28.188.131 with SMTP id m125mr26696556wmf.39.1517422207672; Wed, 31 Jan 2018 10:10:07 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.10.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:10:07 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 17/19] clk: meson: rework meson8b cpu clock Date: Wed, 31 Jan 2018 19:09:43 +0100 Message-Id: <20180131180945.18025-18-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Instead of migrating meson cpu_clk to clk_regmap, like the other meson clock drivers, we take advantage of the massive rework to get rid of it completely, and solve (the first part) of the related FIXME notice. As pointed out in the code comments, the cpu_clk should be modeled with dividers and muxes it is made of, instead of one big composite clock. The other issue pointed out in the FIXME note, around cpu notifier, remains unsolved, until CCR comes up. AFAIK, the cpu_clk was not working correctly to enable dvfs on meson8b. This change being just a re-implementation, hopefully cleaner, of the cpu_clk, the problem remains unsolved as well. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson8b.c | 203 ++++++++++++++++++++++++++++++++++---------- drivers/clk/meson/meson8b.h | 7 +- 2 files changed, 163 insertions(+), 47 deletions(-) -- 2.14.3 Reviewed-by: Martin Blumenstingl diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 625d953511be..e6a6b7c9cfa9 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -99,20 +99,6 @@ static const struct pll_rate_table sys_pll_rate_table[] = { { /* sentinel */ }, }; -static const struct clk_div_table cpu_div_table[] = { - { .val = 1, .div = 1 }, - { .val = 2, .div = 2 }, - { .val = 3, .div = 3 }, - { .val = 2, .div = 4 }, - { .val = 3, .div = 6 }, - { .val = 4, .div = 8 }, - { .val = 5, .div = 10 }, - { .val = 6, .div = 12 }, - { .val = 7, .div = 14 }, - { .val = 8, .div = 16 }, - { /* sentinel */ }, -}; - static struct clk_fixed_rate meson8b_xtal = { .fixed_rate = 24000000, .hw.init = &(struct clk_init_data){ @@ -417,23 +403,6 @@ static struct clk_regmap meson8b_mpll2 = { }, }; -/* - * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL - * post-dividers and should be modeled with their respective PLLs via the - * forthcoming coordinated clock rates feature - */ -static struct meson_clk_cpu meson8b_cpu_clk = { - .reg_off = HHI_SYS_CPU_CLK_CNTL1, - .div_table = cpu_div_table, - .clk_nb.notifier_call = meson_clk_cpu_notifier_cb, - .hw.init = &(struct clk_init_data){ - .name = "cpu_clk", - .ops = &meson_clk_cpu_ops, - .parent_names = (const char *[]){ "sys_pll" }, - .num_parents = 1, - }, -}; - static u32 mux_table_clk81[] = { 6, 5, 7 }; static struct clk_regmap meson8b_mpeg_clk_sel = { .data = &(struct clk_regmap_mux_data){ @@ -486,6 +455,106 @@ struct clk_regmap meson8b_clk81 = { }, }; +struct clk_regmap meson8b_cpu_in_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 0, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_in_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "xtal", "sys_pll" }, + .num_parents = 2, + .flags = (CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT), + }, +}; + +static struct clk_fixed_factor meson8b_cpu_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "cpu_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_in_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "cpu_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_in_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static const struct clk_div_table cpu_div_table[] = { + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { .val = 4, .div = 8 }, + { .val = 5, .div = 10 }, + { .val = 6, .div = 12 }, + { .val = 7, .div = 14 }, + { .val = 8, .div = 16 }, + { /* sentinel */ }, +}; + +struct clk_regmap meson8b_cpu_div = { + .data = &(struct clk_regmap_div_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .shift = 20, + .width = 9, + .table = cpu_div_table, + .flags = CLK_DIVIDER_ALLOW_ZERO, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_div", + .ops = &clk_regmap_divider_ops, + .parent_names = (const char *[]){ "cpu_in_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +struct clk_regmap meson8b_cpu_out_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x3, + .shift = 2, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_out_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]) { "cpu_in_sel", "cpu_div2", + "cpu_div3", "cpu_div" }, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +struct clk_regmap meson8b_cpu_clk = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL0, + .mask = 0x1, + .shift = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "xtal", "cpu_out_sel" }, + .num_parents = 2, + .flags = (CLK_SET_RATE_PARENT | + CLK_SET_RATE_NO_REPARENT), + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); @@ -670,6 +739,11 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw, [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, + [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, + [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw, + [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, + [CLKID_CPU_DIV] = &meson8b_cpu_div.hw, + [CLKID_CPU_OUT_SEL] = &meson8b_cpu_out_sel.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -765,6 +839,49 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_fixed_pll, &meson8b_vid_pll, &meson8b_sys_pll, + &meson8b_cpu_in_sel, + &meson8b_cpu_div, + &meson8b_cpu_out_sel, + &meson8b_cpu_clk, +}; + +struct meson8b_nb_data { + struct notifier_block nb; + struct clk_hw_onecell_data *onecell_data; +}; + +int meson8b_clk_cpu_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct meson8b_nb_data *nb_data = + container_of(nb, struct meson8b_nb_data, nb); + struct clk_hw **hws = nb_data->onecell_data->hws; + + switch (event) { + case PRE_RATE_CHANGE: + clk_hw_reparent(hws[CLKID_CPUCLK], + hws[CLKID_XTAL]); + udelay(100); + clk_hw_reparent(hws[CLKID_CPU_IN_SEL], + hws[CLKID_PLL_SYS]); + break; + + case POST_RATE_CHANGE: + clk_hw_reparent(hws[CLKID_CPUCLK], + hws[CLKID_CPU_OUT_SEL]); + udelay(100); + break; + + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +static struct meson8b_nb_data cpu_nb_data = { + .nb.notifier_call = meson8b_clk_cpu_notifier_cb, + .onecell_data = &meson8b_hw_onecell_data, }; static const struct meson8b_clk_reset_line { @@ -875,8 +992,7 @@ static const struct regmap_config clkc_regmap_config = { static int meson8b_clkc_probe(struct platform_device *pdev) { int ret, i; - struct clk_hw *parent_hw; - struct clk *parent_clk; + struct clk *clk; struct device *dev = &pdev->dev; struct regmap *map; @@ -887,9 +1003,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (IS_ERR(map)) return PTR_ERR(map); - /* Populate the base address for CPU clk */ - meson8b_cpu_clk.base = clk_base; - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++) meson8b_clk_regmaps[i]->map = map; @@ -909,25 +1022,23 @@ static int meson8b_clkc_probe(struct platform_device *pdev) } /* - * Register CPU clk notifier + * Register sys clk notifier * - * FIXME this is wrong for a lot of reasons. First, the muxes should be - * struct clk_hw objects. Second, we shouldn't program the muxes in - * notifier handlers. The tricky programming sequence will be handled + * FIXME this is wrong, we shouldn't program the muxes in notifier + * handlers. The tricky programming sequence will be handled * by the forthcoming coordinated clock rates mechanism once that * feature is released. * - * Furthermore, looking up the parent this way is terrible. At some + * Furthermore, looking up the clk this way is terrible. At some * point we will stop allocating a default struct clk when registering * a new clk_hw, and this hack will no longer work. Releasing the ccr * feature before that time solves the problem :-) */ - parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw); - parent_clk = parent_hw->clk; - ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb); + clk = meson8b_hw_onecell_data.hws[CLKID_PLL_SYS]->clk; + ret = clk_notifier_register(clk, &cpu_nb_data.nb); if (ret) { - pr_err("%s: failed to register clock notifier for cpu_clk\n", - __func__); + dev_err(dev, + "failed to register clock notifier for cpu clock\n"); return ret; } diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index f2780508edec..0a764187f8f3 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -72,8 +72,13 @@ #define CLKID_MPLL0_DIV 96 #define CLKID_MPLL1_DIV 97 #define CLKID_MPLL2_DIV 98 +#define CLKID_CPU_IN_SEL 99 +#define CLKID_CPU_DIV2 100 +#define CLKID_CPU_DIV3 101 +#define CLKID_CPU_DIV 102 +#define CLKID_CPU_OUT_SEL 103 -#define CLK_NR_CLKS 99 +#define CLK_NR_CLKS 104 /* * include the CLKID and RESETID that have From patchwork Wed Jan 31 18:09:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126389 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp968375ljc; Wed, 31 Jan 2018 10:10:23 -0800 (PST) X-Google-Smtp-Source: AH8x2241HHiPfPD3CdbsUrgbQ65Ns/DW58M+jpgfBKp9Ixmrj9HcAOzagVblBOQQFEhPbSYH/nZN X-Received: by 10.99.113.11 with SMTP id m11mr27408986pgc.57.1517422223689; Wed, 31 Jan 2018 10:10:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422223; cv=none; d=google.com; s=arc-20160816; b=C8/NzkwNuFOac2lfOAsfWVgupz69eOTfo1usFhNV1VbwOqOcRBRU4YUWJmr67wXM1q ZnftXAb0+jSKV7JeaqDT49WKqtPKM5RdHPT8EntRo/gRoT8NW64Rr0FoLECeuSB4e5/q FALNDhyDddZa7l38XWOGs8qA5tGz39ftmsmCUs8+OyqvteLcXYPRE8eN+C8stIsnHrur ohaPQvCSqjVnaE76dG+kEqeuJK/pY0ukSHtOVeWd41nIB8fjbsbCFy1hBGIouaKL0bgD YpMVyofTIt3+NgYabcjDfxVViwOxj81lEogFGjbzyh+34XCaWknuQjRgYgEYEiDszIoZ 1lzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wm3w/lk9YDK3mvZ1ESPhbGn5UO2DL6FkULvElJ7gazc=; b=MeJ6DDmza273zsSGJAcL7jtlJoPI+RpVX/7cmoWLYxZ0Lj7ea0f7adsYSSsL8uxiyf moLvyEbHOnN6eb49MiI0ScwquvaG74y6zDR52U0YBpu7mzLWUkLh4cZsY2alGHFkDOBt CeFDNWScSiVv3LtHZDCA6yA1OkQ75QWGeext5nLeR5UF/dalFDUgZwR8RAwmBIRhlURV lhPgdXsgMzCt8rZ1ZYXj8arqbFA/gUomUgToinBPvY6QSyff9bbi2AqYpoN6sksDxKoc JqYlHEgDvt34On5Od4uISnVjIeIVsI1kfNWxLLyRi8yS+kdX8NfoJi06Mk0UYvVQQU79 Hfmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=z3PWLjJq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e17si1797231pgo.189.2018.01.31.10.10.23; Wed, 31 Jan 2018 10:10:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=z3PWLjJq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753884AbeAaSKU (ORCPT + 28 others); Wed, 31 Jan 2018 13:10:20 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:54627 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753870AbeAaSKK (ORCPT ); Wed, 31 Jan 2018 13:10:10 -0500 Received: by mail-wm0-f66.google.com with SMTP id i186so836315wmi.4 for ; Wed, 31 Jan 2018 10:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wm3w/lk9YDK3mvZ1ESPhbGn5UO2DL6FkULvElJ7gazc=; b=z3PWLjJqTapNkGl1CXr1T8L3pFXVetain5BsYExFvJtC++KLYjpRI3pG/UcKV131ie HBtXEtp4Y6xd7KyMZzzktR+gvmvssaOdmx16Eb4IgfLyEEn1WvN+6Ygv8PH2bcB+bZI2 hi5ZInLPtKTVTq8QZ7XtJY3NIAaBTfuLkqQC8P+MI1sM3WZKRROkNMKJ2xgwJ/Nb1ArO L4UbF8vPDYW9kEQN6Go9mnmta8Jx60i5KWApsKiif/s3t75jQzmtFVvGEJVCCTwQCo/y jrfS709BSyqU39DrYgaVB/svaqIUhYeyyY9OxyUVIk6fEHRWuu7AbG7XzP2NobnEsBx3 hX7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wm3w/lk9YDK3mvZ1ESPhbGn5UO2DL6FkULvElJ7gazc=; b=tmiv7EgACVOUTxnGlHAHVCBhgxI0EPllsYFAUDD9m5fe+vowHDFj1xf1kX0l794wgf N+nQ5CWcVOnCtV7jomVdBFTSOzWcyULvxRGGGj9PajDwl7j3vzlqBzrluFf20A2OSg6s IGB7y6aThi984BSjW+FBu4S6pc6f0m7G5WrlfSLwrZ+bJ+HI6qeeFgCcsdVc/K9MmyRi 38IjV+JoKSUSHZqkLHjA9rGBlemTXnAEv6uncKTbZ1bA3COyE4pzdtPl9NpXM9ItKrKc lVg0n4Y6JICg5GDv8sVLhXpQn1MWMPqUBuCW+JrFe+MYjBgDj+sUToqcfRV8/zYIOLcm 3KOw== X-Gm-Message-State: AKwxytf63POsljhGY1p8c/Vra14Y81iSXRwzHp/tfzEgzPGoZDHDVIf5 cPjZEnznP7bktVEoZ+XlWAVweQ== X-Received: by 10.28.109.10 with SMTP id i10mr26889339wmc.107.1517422208682; Wed, 31 Jan 2018 10:10:08 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.10.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:10:08 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 18/19] clk: meson: remove obsolete cpu_clk Date: Wed, 31 Jan 2018 19:09:44 +0100 Message-Id: <20180131180945.18025-19-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org meson8b cpu_clk has been replaced by a set of divider and mux clocks. meson_cpu_clk is no longer used and can be removed Signed-off-by: Jerome Brunet --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clk-cpu.c | 178 -------------------------------------------- drivers/clk/meson/clkc.h | 11 --- 3 files changed, 1 insertion(+), 190 deletions(-) delete mode 100644 drivers/clk/meson/clk-cpu.c -- 2.14.3 Acked-by: Martin Blumenstingl diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 465086118d62..ffee82e60b7a 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -2,7 +2,7 @@ # Makefile for Meson specific clk # -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o diff --git a/drivers/clk/meson/clk-cpu.c b/drivers/clk/meson/clk-cpu.c deleted file mode 100644 index f8b2b7efd016..000000000000 --- a/drivers/clk/meson/clk-cpu.c +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2015 Endless Mobile, Inc. - * Author: Carlo Caione - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see . - */ - -/* - * CPU clock path: - * - * +-[/N]-----|3| - * MUX2 +--[/3]-+----------|2| MUX1 - * [sys_pll]---|1| |--[/2]------------|1|-|1| - * | |---+------------------|0| | |----- [a5_clk] - * +--|0| | | - * [xtal]---+-------------------------------|0| - * - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define MESON_CPU_CLK_CNTL1 0x00 -#define MESON_CPU_CLK_CNTL 0x40 - -#define MESON_CPU_CLK_MUX1 BIT(7) -#define MESON_CPU_CLK_MUX2 BIT(0) - -#define MESON_N_WIDTH 9 -#define MESON_N_SHIFT 20 -#define MESON_SEL_WIDTH 2 -#define MESON_SEL_SHIFT 2 - -#include "clkc.h" - -#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw) -#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb) - -static long meson_clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); - - return divider_round_rate(hw, rate, prate, clk_cpu->div_table, - MESON_N_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); -} - -static int meson_clk_cpu_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); - unsigned int div, sel, N = 0; - u32 reg; - - div = DIV_ROUND_UP(parent_rate, rate); - - if (div <= 3) { - sel = div - 1; - } else { - sel = 3; - N = div / 2; - } - - reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); - reg = PARM_SET(MESON_N_WIDTH, MESON_N_SHIFT, reg, N); - writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); - - reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); - reg = PARM_SET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg, sel); - writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); - - return 0; -} - -static unsigned long meson_clk_cpu_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw); - unsigned int N, sel; - unsigned int div = 1; - u32 reg; - - reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); - N = PARM_GET(MESON_N_WIDTH, MESON_N_SHIFT, reg); - - reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); - sel = PARM_GET(MESON_SEL_WIDTH, MESON_SEL_SHIFT, reg); - - if (sel < 3) - div = sel + 1; - else - div = 2 * N; - - return parent_rate / div; -} - -/* FIXME MUX1 & MUX2 should be struct clk_hw objects */ -static int meson_clk_cpu_pre_rate_change(struct meson_clk_cpu *clk_cpu, - struct clk_notifier_data *ndata) -{ - u32 cpu_clk_cntl; - - /* switch MUX1 to xtal */ - cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off - + MESON_CPU_CLK_CNTL); - cpu_clk_cntl &= ~MESON_CPU_CLK_MUX1; - writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off - + MESON_CPU_CLK_CNTL); - udelay(100); - - /* switch MUX2 to sys-pll */ - cpu_clk_cntl |= MESON_CPU_CLK_MUX2; - writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off - + MESON_CPU_CLK_CNTL); - - return 0; -} - -/* FIXME MUX1 & MUX2 should be struct clk_hw objects */ -static int meson_clk_cpu_post_rate_change(struct meson_clk_cpu *clk_cpu, - struct clk_notifier_data *ndata) -{ - u32 cpu_clk_cntl; - - /* switch MUX1 to divisors' output */ - cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off - + MESON_CPU_CLK_CNTL); - cpu_clk_cntl |= MESON_CPU_CLK_MUX1; - writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off - + MESON_CPU_CLK_CNTL); - udelay(100); - - return 0; -} - -/* - * This clock notifier is called when the frequency of the of the parent - * PLL clock is to be changed. We use the xtal input as temporary parent - * while the PLL frequency is stabilized. - */ -int meson_clk_cpu_notifier_cb(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct clk_notifier_data *ndata = data; - struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_nb(nb); - int ret = 0; - - if (event == PRE_RATE_CHANGE) - ret = meson_clk_cpu_pre_rate_change(clk_cpu, ndata); - else if (event == POST_RATE_CHANGE) - ret = meson_clk_cpu_post_rate_change(clk_cpu, ndata); - - return notifier_from_errno(ret); -} - -const struct clk_ops meson_clk_cpu_ops = { - .recalc_rate = meson_clk_cpu_recalc_rate, - .round_rate = meson_clk_cpu_round_rate, - .set_rate = meson_clk_cpu_set_rate, -}; diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index cc1a964cd4d7..8d8fe608cff4 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -101,17 +101,6 @@ struct meson_clk_pll_data { #define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw) -struct meson_clk_cpu { - struct clk_hw hw; - void __iomem *base; - u16 reg_off; - struct notifier_block clk_nb; - const struct clk_div_table *div_table; -}; - -int meson_clk_cpu_notifier_cb(struct notifier_block *nb, unsigned long event, - void *data); - struct meson_clk_mpll_data { struct parm sdm; struct parm sdm_en; From patchwork Wed Jan 31 18:09:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 126391 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp968396ljc; Wed, 31 Jan 2018 10:10:25 -0800 (PST) X-Google-Smtp-Source: AH8x226COSGmStHgLPGA9nzoB1N4olG2o+fSE1gH2yEcoclPrC9Ye8bqgwJhDkuNEHrKDhu1Ft5e X-Received: by 10.98.103.209 with SMTP id t78mr34695572pfj.53.1517422225176; Wed, 31 Jan 2018 10:10:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517422225; cv=none; d=google.com; s=arc-20160816; b=etn3W2k+oXBoxlxsQhkrhGABUHjaPYcNgYgbI5JXYdsJZHQrV11CFWsO9aJ1F3jBV+ XpHzoVK0gaUNJBgjUigGoFTXVCiXbYCFMU0g1nOkDQLOOv7GBN+HirEViLv6clDHkf2x zwwd4BfpwVcplWvPk5aXXoonYFUfuj3TwGMwLsUZqCrJw9gfsrquzLEg9r08ksApHcZ4 uhOgOQa76Q09zTOhnBMf5mXQD6o0raA35fAgpMPE9fD8pyKclDMybvuzEKEK2NqD1X5X zNZiaU/Ss2sO78rhk0GVnJCrOP4+6qAWKXLiebxJzILpk8iOlbzTESQAu1nJHihUSxMs qQbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=pA/l753Clohi2etsvUOL73GFxfOVooDosfGEhU+JF1Q=; b=wKUdmIbfVjs593EkuGQ9CU2qeTKuDdQxoluh27AXRwTsBi4VWM4oZDBOlMJYJMRvyw ho2m8gh9AiuY4pX20tjeU6p4ATnxsbbz5S3wmTWkHjglDf2Jsy6fiZAiDkEJCNo+QQuH jy2adgnlEjh5J7WKoOsqwOBbPJESkDXJnJ7LLhfkh8HUe9ZIQXrTXq9p1S4Ra6W4k4Zo 7nMzMV2pQRPwaSYz3CwH7X4nZdil+Uq1rCc3OohIcqCaZWS/ZUtVYqvwl3jUj4miGwO6 2elc7jwyFjA40nWlQpZfvB7hbuKe4QV3wPcZcutu/lLR5GoOcBS163ePJ4h6jTrnqs4/ x6iA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=wUsKODBD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e17si1797231pgo.189.2018.01.31.10.10.24; Wed, 31 Jan 2018 10:10:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=wUsKODBD; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753919AbeAaSKY (ORCPT + 28 others); Wed, 31 Jan 2018 13:10:24 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:37780 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753881AbeAaSKL (ORCPT ); Wed, 31 Jan 2018 13:10:11 -0500 Received: by mail-wm0-f67.google.com with SMTP id v71so811031wmv.2 for ; Wed, 31 Jan 2018 10:10:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pA/l753Clohi2etsvUOL73GFxfOVooDosfGEhU+JF1Q=; b=wUsKODBDDAym+F+L07LWUDkDtvLkpAe+0FmD2nxqcrIUO3OX/MTYirHBnZKfqmLYR4 kPpKUQ8WOOpib2X3mfgHIdLF/giV6/Hsu3PwuGAv8lSHGaibyAHNwlqri00K6OZROp5v Arwtfe3KY+trwHR3nC7FH2U/kMPw+ud/R4BX4gdpz0Q7OV9ZCaTtSFM+uc6QZDrctb3A /W3t+HC4Obtv57dwef1tDhwyBBSbG9IrdaPmux9yvnx02tGonwXGxtuhRetRDSdrbJRl aVhUokpJdlOFWWJi3WTdwMVjyH+bQV4MSxlGNH/7vpGsrWpnzfVc6g0xqfJsquDDLVF0 5YQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pA/l753Clohi2etsvUOL73GFxfOVooDosfGEhU+JF1Q=; b=rVa63PQanIGVJYVLhAVdfcv6zcV+9DwauDhDIqNUrBKQfq6qvNozmNhr4NrzigGAZE xJT2suYvur1iLBZ3ivCgUuI6QYGXGB/k2TCX3Hnm3wmeeguD5NC2BKhbnteMi1OMTJfD PFXMcncxcYF8Zkb7OYqHQVDHy6p3bbxairVQA8OJ3wSqYYDTGOLu6ecTHY6U7oXzGVtK GfZ1XMOtzvEglORJoiK/J7DBIhFBaj9Z5wBYq5CWLaLIoMsVVIQblB3W/NaHeTKll5ua CYLcVEaG/EHkedRJiEgZUcmOcA9AKxWucnoVWEBgqStzD+6lV2QFSG+6LRfpgtjhyt0G 2qcQ== X-Gm-Message-State: AKwxytclzJse8cwrNmw8N0Ai1prtiTNHmapLol1zAGVpkrdkBWJ9S+gq XJIQBqkRkNFAlop0cQtO7jnvOA== X-Received: by 10.28.141.212 with SMTP id p203mr16147754wmd.39.1517422209679; Wed, 31 Jan 2018 10:10:09 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.10.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:10:09 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 19/19] clk: meson: use hhi syscon if available Date: Wed, 31 Jan 2018 19:09:45 +0100 Message-Id: <20180131180945.18025-20-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On gxbb and axg, try to get the hhi regmap from the parent DT node, which should be the HHI system controller once the necessary changes have been made in amlogic's DTs Until then, if getting regmap through the system controller fails, the clock controller will fall back to the old way, requesting memory region directly and then registering the regmap itself. This should allow a smooth transition to syscon Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 2 ++ drivers/clk/meson/axg.c | 43 ++++++++++++++++++++++++++++++------------- drivers/clk/meson/gxbb.c | 39 ++++++++++++++++++++++++++++----------- 3 files changed, 60 insertions(+), 24 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 936afddae406..d5cbec522aec 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -22,6 +22,7 @@ config COMMON_CLK_GXBB depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON help Support for the clock controller on AmLogic S905 devices, aka gxbb. Say Y if you want peripherals and CPU frequency scaling to work. @@ -31,6 +32,7 @@ config COMMON_CLK_AXG depends on COMMON_CLK_AMLOGIC select RESET_CONTROLLER select COMMON_CLK_REGMAP_MESON + select MFD_SYSCON help Support for the clock controller on AmLogic A113D devices, aka axg. Say Y if you want peripherals and CPU frequency scaling to work. diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index ae1dd35246f5..8c455f8c1d91 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -850,25 +851,41 @@ static int axg_clkc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct resource *res; - void __iomem *clk_base; + void __iomem *clk_base = NULL; struct regmap *map; int ret, i; - /* Generic clocks and PLLs */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + /* Get the hhi system controller node if available */ + map = syscon_node_to_regmap(of_get_parent(dev->of_node)); + if (IS_ERR(map)) { + dev_err(dev, + "failed to get HHI regmap - Trying obsolete regs\n"); + + /* + * FIXME: HHI registers should be accessed through + * the appropriate system controller. This is required because + * there is more than just clocks in this register space + * + * This fallback method is only provided temporarily until + * all the platform DTs are properly using the syscon node + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + + clk_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!clk_base) { + dev_err(dev, "Unable to map clk base\n"); + return -ENXIO; + } - clk_base = devm_ioremap(dev, res->start, resource_size(res)); - if (!clk_base) { - dev_err(dev, "Unable to map clk base\n"); - return -ENXIO; + map = devm_regmap_init_mmio(dev, clk_base, + &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); } - map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); - if (IS_ERR(map)) - return PTR_ERR(map); - /* Populate regmap for the regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++) axg_clk_regmaps[i]->map = map; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 92403ab2daf5..f9acd4015a1c 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -2042,19 +2043,35 @@ static int gxbb_clkc_probe(struct platform_device *pdev) if (!clkc_data) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -EINVAL; + /* Get the hhi system controller node if available */ + map = syscon_node_to_regmap(of_get_parent(dev->of_node)); + if (IS_ERR(map)) { + dev_err(dev, + "failed to get HHI regmap - Trying obsolete regs\n"); - clk_base = devm_ioremap(dev, res->start, resource_size(res)); - if (!clk_base) { - pr_err("%s: Unable to map clk base\n", __func__); - return -ENXIO; - } + /* + * FIXME: HHI registers should be accessed through + * the appropriate system controller. This is required because + * there is more than just clocks in this register space + * + * This fallback method is only provided temporarily until + * all the platform DTs are properly using the syscon node + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + clk_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!clk_base) { + dev_err(dev, "Unable to map clk base\n"); + return -ENXIO; + } - map = devm_regmap_init_mmio(dev, clk_base, &clkc_regmap_config); - if (IS_ERR(map)) - return PTR_ERR(map); + map = devm_regmap_init_mmio(dev, clk_base, + &clkc_regmap_config); + if (IS_ERR(map)) + return PTR_ERR(map); + } /* Populate regmap for the common regmap backed clocks */ for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)