From patchwork Tue Dec 8 00:46:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 339827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CC00C4361B for ; Tue, 8 Dec 2020 00:47:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B7C323A1C for ; Tue, 8 Dec 2020 00:47:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728801AbgLHArM (ORCPT ); Mon, 7 Dec 2020 19:47:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726231AbgLHArM (ORCPT ); Mon, 7 Dec 2020 19:47:12 -0500 Received: from mail-lf1-x141.google.com (mail-lf1-x141.google.com [IPv6:2a00:1450:4864:20::141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37B61C061285 for ; Mon, 7 Dec 2020 16:46:22 -0800 (PST) Received: by mail-lf1-x141.google.com with SMTP id u19so20757100lfr.7 for ; Mon, 07 Dec 2020 16:46:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iMeYx3PuOFeT/ou7cP6t4OiaQH+OiI6hASKT4SyHXP4=; b=plXKbgH1XkCLdCGGiX1O46e+mERn8lchrvrv9dK3Sr9L4mOghPw5HhQz4rIoKSTLnp HxU9mdDKOZAIxt8F1nNvYFP7AT+4aXhBMrJWGJl7UI79BKrx/UquQ83wkYpFx1fKuscP LAJ4vVdSc8BMznhZpiofqLHte19wz4EJ3Nzl9wDFDpLMW63gLVLuHTDCdq0wmmw857s2 ULxEEh1u3nZ5tkYQQas/vDC1g7AtbcNDQ/0RJ8BsJRBrKEYSC2ax65ka6DVZwopNdtyJ n3ZilaKXXuJxj4VsQBAsHp4fsrrOhBqMfF6MUhcl3CTkU9uEblsDfs4y8D9qCXbt8nxY jnCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iMeYx3PuOFeT/ou7cP6t4OiaQH+OiI6hASKT4SyHXP4=; b=bM0XEbKe5+lbXnt7fLmM6bSWL8xUBfMOTbecMcyA2ws98HHe8uNJF/xVGnW1xV0ax3 zwpdfmJQIL/XodX0YQHFcPdDk4MGmc9gaDwyTpzpXSs3QmwzAwaWjn2an3C7nshi+UL1 oxByg7EQJpx8D2+Y5icoTD2RVvDFikmJhYP2r6qEtuf9mwpDbGsVyilhCtXCqhV9hRhW Ou3EWhFzaG6M6QUPMlAxZRHpPa/zC05LyluJrPYv1zlSS6y8R3NSoeSxtJlP1Cfg0xfh NeBL2JJUmn6bN1/6qO+/8a1vk5SwnJG+CklYFA3UWYmkpytIkXveRFFFyFEnw+5OpUl3 ex7A== X-Gm-Message-State: AOAM5333Fv0vXx3HPptuQBQmMC7aAtpw4EGHlv0c5+lDiE/AcAWdBi5x RfurB00ixBhttt/TVAmd0qAoQg== X-Google-Smtp-Source: ABdhPJwbvUrdi5CDciG/D+wS0Nn+liIRxKlNfGmYY+fFeM4F89RLWMsV50NVfh/HO2J2V8kGqAafxw== X-Received: by 2002:a05:6512:3690:: with SMTP id d16mr10009389lfs.321.1607388380637; Mon, 07 Dec 2020 16:46:20 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.229.141]) by smtp.gmail.com with ESMTPSA id d3sm3028229lfj.206.2020.12.07.16.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:46:20 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: pci: qcom: Document ddrss_sf_tbu clock for sm8250 Date: Tue, 8 Dec 2020 03:46:11 +0300 Message-Id: <20201208004613.1472278-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201208004613.1472278-1-dmitry.baryshkov@linaro.org> References: <20201208004613.1472278-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Document this clock in devicetree bindings. Signed-off-by: Dmitry Baryshkov Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..c87806f76a43 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -142,6 +142,7 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock, required on sm8250 - "pipe" PIPE clock - resets: From patchwork Tue Dec 8 00:46:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 339681 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp3264557jai; Mon, 7 Dec 2020 16:48:47 -0800 (PST) X-Google-Smtp-Source: ABdhPJzRXcFqMVs4/KzA32NqRpDfQycUecLRSsQtHaYtZUbfWi5Hi5rAYT+q7ShqDLDVnRqLia7z X-Received: by 2002:a17:907:961b:: with SMTP id gb27mr20760585ejc.313.1607388526808; Mon, 07 Dec 2020 16:48:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607388526; cv=none; d=google.com; s=arc-20160816; b=wXioFTyrX8ZlLJmUCAUTnIxn5It/glN16DEgkB9phgNNPNhUanwDGO5mkdmmF+Ax3M IP8qbNZrOv2rztWClQIeK2b15EkXLxSZJoo4olPiZOEJx5w5ml+S5ZHsrTfhqH0priYR 4EKacagbZ1G9eenSsy0wfpW+IE6d52FyUMemyJ8Cua0d9nMPgs91hRkxiV52EIBpm7nq o0BiKM0LzdL6lpL/sCsjuUXeOvtfrmGaf/ec88XwSl73WwvvsyR3W3iWd2qfyPuaEinf gTvBpEXw00D3F6cNmpd/0FdsLXQAoeQ0hmEAdhdVQDbF/Mweq7k3hpVDSZK46WkdBT/d Ildg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NWy8EXHdxkf0XTbmE1PCRNTwXozVSEc9y+L8i0BKYwI=; b=c/6AfzhDrPJLfx+pPaPKIoqtJoz7UZp6lASTJirJkUWAxljZk7GLnIX2CJoPsLb37g UwRu93J+/o8QzRWcojnBy1TWrWSFspAUl/T9SYosbZ6duhk0di+gYo7bb1bmzLe+ItW9 1hx2igLC6N55WjtmYLZLK6RwWI1t+zDKrkCYN8zA8PHP7zMeFFSb0rMq8YTzc3vVoWMt i1p2qQyIXlesVaqr2RBOrRK48rQ/pbOGeL5895FoSYTfyV8q76TIpx+BU3DfMghwMzfc e5Rg2jUbQaaVtQTkqzfaDLtXfocptr9N+f8Ny+clFE5LKjXWaEM06OkX5xcpGZh809IP e0aQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kRfk733P; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 2.29.2 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e45a43148f56..67712ea48d5f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,9 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 6 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS + 1]; /* + 1 for sf_tbu */ struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1167,10 +1168,15 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, QCOM_PCIE_2_7_0_MAX_CLOCKS, res->clks); if (ret < 0) return ret; + /* Optional clock for SM8250 */ + res->clks[6].clk = devm_clk_get_optional(dev, "ddrss_sf_tbu"); + if (IS_ERR(res->clks[6].clk)) + return PTR_ERR(res->clks[6].clk); + res->pipe_clk = devm_clk_get(dev, "pipe"); return PTR_ERR_OR_ZERO(res->pipe_clk); } From patchwork Tue Dec 8 00:46:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 339826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD5D3C197BF for ; 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Mon, 07 Dec 2020 16:46:23 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.229.141]) by smtp.gmail.com with ESMTPSA id d3sm3028229lfj.206.2020.12.07.16.46.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 16:46:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Bjorn Helgaas , Rob Herring , Stanimir Varbanov , Lorenzo Pieralisi , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH 3/3] arm64: dts: qcom: sm8250: add ddrss_sf_tbu clock to PCIe device nodes Date: Tue, 8 Dec 2020 03:46:13 +0300 Message-Id: <20201208004613.1472278-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201208004613.1472278-1-dmitry.baryshkov@linaro.org> References: <20201208004613.1472278-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Add this clock to PCIe devices nodes. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index deed186b1a84..4a6e11e78b35 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1345,14 +1345,16 @@ pcie0: pci@1c00000 { <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", - "tbu"; + "tbu", + "ddrss_sf_tbu"; iommus = <&apps_smmu 0x1c00 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, @@ -1437,7 +1439,8 @@ pcie1: pci@1c08000 { <&gcc GCC_PCIE_1_SLV_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; clock-names = "pipe", "aux", "cfg", @@ -1445,7 +1448,8 @@ pcie1: pci@1c08000 { "bus_slave", "slave_q2a", "ref", - "tbu"; + "tbu", + "ddrss_sf_tbu"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; @@ -1535,7 +1539,8 @@ pcie2: pci@1c10000 { <&gcc GCC_PCIE_2_SLV_AXI_CLK>, <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_MDM_CLKREF_EN>, - <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; clock-names = "pipe", "aux", "cfg", @@ -1543,7 +1548,8 @@ pcie2: pci@1c10000 { "bus_slave", "slave_q2a", "ref", - "tbu"; + "tbu", + "ddrss_sf_tbu"; assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>;