From patchwork Mon Feb 5 01:55:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 126826 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1577980ljc; Sun, 4 Feb 2018 17:55:34 -0800 (PST) X-Google-Smtp-Source: AH8x224p4FieqqxNLHHLTTPh13d29RcAgDzt+QVnIaWtajehI6zfvbS8m8uhDkg5hkcvPrSZAfqc X-Received: by 2002:a17:902:6186:: with SMTP id u6-v6mr41300323plj.390.1517795734345; Sun, 04 Feb 2018 17:55:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517795734; cv=none; d=google.com; s=arc-20160816; b=EBygkSAbQf9nsuYThOEtHfh2YL9itAw9DrFwGPBQaDMgLsXcqVd6aVqUV01gEt9mCr 1i5W98kNjSX+SKyYE9DY8ymAjeuLdvDmzQhpV8jesWEbMQBtimyQGoD/DQ6tT3tYVrYn GKjDDro4cGg7UPB6ShOJbg25c2WYI0kEb6IQLh8138FA0EjDSethS/jstzcPvakORVnw luLcrTYoAwYPoYqhs7JPMO7MrRlkyixJmuNnw6SEvHnLBI8aH0Qsv9opnog7vV5V5V4s E1omx/YVj3fbSwujshKMTo5etntHmcIGtqZX1C8NsynroJMAL+GgfJU8d7k//7Howq0N Z4Gw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=/c7UHPdvuHHarbuFHweHQh7GsumlCKcH1uNxjBxInlY=; b=qwhGXOQtuDy26J9G6J76Mv2WwtKdRNgA/TnUzIBfIWxLsFg1hZ2XcSFJ/lZAumjWNn CaYlV70FGate2ZDdEpBLyUublFnCftgJEYQ+En8zERgRBk0WAsTj7YAi2nRqtDp57SDk CNMXFLw4OiBIgEz8PtOtuX0f0UPCsieo1PGtpZCMpGud1Dh30/jiw68qHhm9YPUJ0UDl zKQSPOA3xrUmUE23WIMpKmXmgIMK7uUzwTTp5g20OLcVfdQOlGHoJEBcw9MehVu37FqQ Qt+kYATXYgc1zEkZkfkhNm6pNlaJywJXBuWI0PzL3XWQN1p7X4UK40/1yIQ2mkb9rHQo SFGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Lyv7r6ez; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j8-v6si1543957plk.87.2018.02.04.17.55.33; Sun, 04 Feb 2018 17:55:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Lyv7r6ez; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752256AbeBEBzb (ORCPT + 6 others); Sun, 4 Feb 2018 20:55:31 -0500 Received: from mail-pl0-f68.google.com ([209.85.160.68]:46318 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751991AbeBEBza (ORCPT ); Sun, 4 Feb 2018 20:55:30 -0500 Received: by mail-pl0-f68.google.com with SMTP id 36so10757123ple.13 for ; Sun, 04 Feb 2018 17:55:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=2oqtYYjQkMeVa0mKCIAOyHHiirr83ipCUPsUzsfHOBA=; b=Lyv7r6ezmHXL/aaygqr/LhIwNv51EVNX8YM2umpQ3uY+nt66GiuTDZnUG8Y5MaBH5S /sc7VMw4jw/gGFV9exvcurfiB1OPTVXTxZJv7E7toDMTqmxSuVDVtCJvw0+i8G2gjjkT QJNuyGGGjC1IPiqikx9mbHVym9AbjrTf6jP34= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=2oqtYYjQkMeVa0mKCIAOyHHiirr83ipCUPsUzsfHOBA=; b=JX4tOSj2rOmIWMnOAYFi2VBZRzGJw+M2QdgxkiFWQKIs00x3vPalw0J8U44ay2sED/ w0LxYp4bPMncrtG5yVb2l9lnyvyPyAK+v6LAWp7Y2N0ywR4o4AEVrrdPC5V5Q2yfj2K5 9ThJQf7Yrg06PLnfO0pNCuQCWPJZG6FgzURao/kNf/7lQBCDdXFmGSLqZyb5Q5Lp/+kV 6N5nX+sy6X8+HXC5O9gj3fej0Toje+z4TBKQrlHxsDPaX6y4xzx/zc8NW9C9FA2FHIwF BOzjOvskRx1nPYcbiCitn4Mc8qzndfB5G1O10maCFkJ7K0I+i5cX6fkFVeQ96RFYFPMV yD9A== X-Gm-Message-State: AKwxytfp65wyRkvlujU7piCRBulyUbVCGX8zKb5W/mnV7b3kosGups7r S2wzqDt08la2HQvcRaqHu8fMIQ== X-Received: by 2002:a17:902:bc3:: with SMTP id 61-v6mr39720764plr.407.1517795730283; Sun, 04 Feb 2018 17:55:30 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id t69sm15734677pfa.180.2018.02.04.17.55.27 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 04 Feb 2018 17:55:29 -0800 (PST) From: Baolin Wang To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org, andy.shevchenko@gmail.com Subject: [PATCH v3 1/2] dt-bindings: gpio: Add Spreadtrum GPIO controller documentation Date: Mon, 5 Feb 2018 09:55:10 +0800 Message-Id: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517795460.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds the device tree bindings for the Spreadtrum GPIO controller. The gpios will be supported by the GPIO generic library. Signed-off-by: Baolin Wang --- Changes since v1: - No updates. --- .../devicetree/bindings/gpio/gpio-sprd.txt | 28 ++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-sprd.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/gpio/gpio-sprd.txt b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt new file mode 100644 index 0000000..eca97d4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-sprd.txt @@ -0,0 +1,28 @@ +Spreadtrum GPIO controller bindings + +The controller's registers are organized as sets of sixteen 16-bit +registers with each set controlling a bank of up to 16 pins. A single +interrupt is shared for all of the banks handled by the controller. + +Required properties: +- compatible: Should be "sprd,sc9860-gpio". +- reg: Define the base and range of the I/O address space containing +the GPIO controller registers. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be <2>. The first cell is the gpio number and +the second cell is used to specify optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be <2>. Specifies the number of cells needed +to encode interrupt source. +- interrupts: Should be the port interrupt shared by all the gpios. + +Example: + ap_gpio: gpio@40280000 { + compatible = "sprd,sc9860-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; From patchwork Mon Feb 5 01:55:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 126827 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1578105ljc; Sun, 4 Feb 2018 17:55:53 -0800 (PST) X-Google-Smtp-Source: AH8x226GgnggvsGU6X8puc78fRkLgWryh+K0GKbNRKRVMorNl2TX4DrC8gF7boClz4eZ4+mmEeXr X-Received: by 10.101.82.203 with SMTP id z11mr37640830pgp.164.1517795753460; Sun, 04 Feb 2018 17:55:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517795753; cv=none; d=google.com; s=arc-20160816; b=Sg5eeGoLiy2VAyILo8l7XdzsXudKt+E3iQNZkkHbZNKYCE8etbVyay90ZwqPnlBP0f v9pUZacZGL1Iqk9POcI0NM89F3phv4F+QoqTCHmFbRD4Mz2CkQXhMkKgBLa7D8bZjsH6 3MUFXwOWtcodqV3t4mhog9bJpPx/H1brO5a3FTFzNsz15plKIeFdHzFfRSnk6mzTm0m4 witperRVF/hxTWb8GZQV9M7TED7MKEYxd7HL50rt2lkcI4F5tXFRKTjzjbfVDopkIIve 41q0TQQNocSguOJM7dc+H6gDwfpGVgtK1qJ0/Vw3eSgCLpdiJIoCJB7LCnszTX2QD26b 6kwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=P4raTOWLr+ox+2K7KCjoFXynyzyFU3rgMWbCPTm7zgU=; b=YTb2cj5MGKWibaF2uFHIUvYYdJbvGsFUuD8vyES5Rny9gjO96r+10don8es4Zn3Pf4 oXzAmxPXiU5k324BAPO276UIa54kz7Xurex3UldjtF4MU87dLsH7lns5FVdlAulR2/MA sT9VvDAz4KU3rHH2/KKAv1FhBGooGyMMbaz4MDqX9O6DORVYGoF//h6BV3psMvfeYf3C vCmvi2/nOxWem8QpLKb/ZaY3rCX1But3REGhYUKlOmuRxjmvHuF+FmOY1d+ci85t5ffQ 0cDC77NoYeQS3HAYytTvVHmeGYojejyBq7/D2qwyp+lxDKgwl6sDV5DW2dK9naO19dxr h6Sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jraFDylr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r16si3232017pgn.732.2018.02.04.17.55.53; Sun, 04 Feb 2018 17:55:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jraFDylr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752495AbeBEBzo (ORCPT + 6 others); Sun, 4 Feb 2018 20:55:44 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:40792 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752299AbeBEBze (ORCPT ); Sun, 4 Feb 2018 20:55:34 -0500 Received: by mail-pl0-f65.google.com with SMTP id g18so10750448plo.7 for ; Sun, 04 Feb 2018 17:55:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=r4BIwQK6TToiKLprNlKAiY15w4sFyWf/usbI9wPbbag=; b=jraFDylrbpI9U66ZwXxpGiSwnP74SEwAlmy4wi4XbJHcQW952PpPnS3p0e6LzpsWCf TK7wQ0wGMOVxsM+ey4IwY7CAOxtZnau1GTaRiFnOoadS/KukFGc9vp2A1DKUGtoW2Im1 qCt6Yg+qyYuXsFHZN1u6t8Jaccu695mm8tvgY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=r4BIwQK6TToiKLprNlKAiY15w4sFyWf/usbI9wPbbag=; b=sCi9e5XpqhM3u5CwDAioDJ+nLVTDvTXrA2Pox7HB6qfml5FC0Mapk8jWjcO8UNcsVY KQycjyyDm0cqGyTzYuL0KAGRDgPv3Uc0Yyx42g1ydHJkKl0/5ZkzT1eTcsIY+SaYk3mL lLLxE48/7m9nuMACb+fWVMKxAD7PGDcAZ/ZlxA8PuAQgJFUZ2PeyCu7oddBXS9il9q0D n7cyMKqlAYcNKG5FzWOuK999ohbZaIuFovxHXw6WiYpudR/CRIZcVAzohgzkx6yFTS/U Ydl1VYfkXfwz8vYfGNCbDWsAveMenVxxJBHMK/HvGxvOepbYdLn4svzDu01/1X9XwQKd 7Gcw== X-Gm-Message-State: AKwxytfqGBzoyRitn1KLuZhKAk5p9EDBjmonBQih0MYC2sjXp4tfupx3 UyOF/xvn7weoDR2oPRUE/SKNCw== X-Received: by 2002:a17:902:15c5:: with SMTP id a5-v6mr42525497plh.277.1517795733332; Sun, 04 Feb 2018 17:55:33 -0800 (PST) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id t69sm15734677pfa.180.2018.02.04.17.55.30 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 04 Feb 2018 17:55:32 -0800 (PST) From: Baolin Wang To: linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, broonie@kernel.org, baolin.wang@linaro.org, andy.shevchenko@gmail.com Subject: [PATCH v3 2/2] gpio: Add GPIO driver for Spreadtrum SC9860 platform Date: Mon, 5 Feb 2018 09:55:11 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517795460.git.baolin.wang@linaro.org> References: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517795460.git.baolin.wang@linaro.org> In-Reply-To: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517795460.git.baolin.wang@linaro.org> References: <2834309f69a1ec37b84a33f153a3d0b90336bcc6.1517795460.git.baolin.wang@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Spreadtrum SC9860 platform GPIO controller contains 16 groups and each group contains 16 GPIOs. Each GPIO can set input/output and has the interrupt capability. Signed-off-by: Baolin Wang Reviewed-by: Andy Shevchenko --- Changes since v2: - Use devm_ioremap_resource() instead of devm_ioremap_nocache(). Changes since v1: - Change 'bool' to 'tristate'. - Add reviewed tag from Andy. --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-sprd.c | 290 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 298 insertions(+) create mode 100644 drivers/gpio/gpio-sprd.c -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d6a8e85..2ed1a88 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -404,6 +404,13 @@ config GPIO_SPEAR_SPICS help Say yes here to support ST SPEAr SPI Chip Select as GPIO device +config GPIO_SPRD + tristate "Spreadtrum GPIO support" + depends on ARCH_SPRD || COMPILE_TEST + select GPIOLIB_IRQCHIP + help + Say yes here to support Spreadtrum GPIO device. + config GPIO_STA2X11 bool "STA2x11/ConneXt GPIO support" depends on MFD_STA2X11 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4bc24fe..5b633a0 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -108,6 +108,7 @@ obj-$(CONFIG_GPIO_SCH) += gpio-sch.o obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o +obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o diff --git a/drivers/gpio/gpio-sprd.c b/drivers/gpio/gpio-sprd.c new file mode 100644 index 0000000..7c0f9f1 --- /dev/null +++ b/drivers/gpio/gpio-sprd.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Spreadtrum Communications Inc. + * Copyright (c) 2018 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* GPIO registers definition */ +#define SPRD_GPIO_DATA 0x0 +#define SPRD_GPIO_DMSK 0x4 +#define SPRD_GPIO_DIR 0x8 +#define SPRD_GPIO_IS 0xc +#define SPRD_GPIO_IBE 0x10 +#define SPRD_GPIO_IEV 0x14 +#define SPRD_GPIO_IE 0x18 +#define SPRD_GPIO_RIS 0x1c +#define SPRD_GPIO_MIS 0x20 +#define SPRD_GPIO_IC 0x24 +#define SPRD_GPIO_INEN 0x28 + +/* We have 16 groups GPIOs and each group contain 16 GPIOs */ +#define SPRD_GPIO_GROUP_NR 16 +#define SPRD_GPIO_NR 256 +#define SPRD_GPIO_GROUP_SIZE 0x80 +#define SPRD_GPIO_GROUP_MASK GENMASK(15, 0) +#define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_GROUP_NR - 1)) + +struct sprd_gpio { + struct gpio_chip chip; + void __iomem *base; + spinlock_t lock; + int irq; +}; + +static inline void __iomem *sprd_gpio_group_base(struct sprd_gpio *sprd_gpio, + unsigned int group) +{ + return sprd_gpio->base + SPRD_GPIO_GROUP_SIZE * group; +} + +static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, + unsigned int reg, unsigned int val) +{ + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + void __iomem *base = sprd_gpio_group_base(sprd_gpio, + offset / SPRD_GPIO_GROUP_NR); + u32 shift = SPRD_GPIO_BIT(offset); + unsigned long flags; + u32 orig, tmp; + + spin_lock_irqsave(&sprd_gpio->lock, flags); + orig = readl_relaxed(base + reg); + + tmp = (orig & ~BIT(shift)) | (val << shift); + writel_relaxed(tmp, base + reg); + spin_unlock_irqrestore(&sprd_gpio->lock, flags); +} + +static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, + unsigned int reg) +{ + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + void __iomem *base = sprd_gpio_group_base(sprd_gpio, + offset / SPRD_GPIO_GROUP_NR); + u32 value = readl_relaxed(base + reg) & SPRD_GPIO_GROUP_MASK; + u32 shift = SPRD_GPIO_BIT(offset); + + return !!(value & BIT(shift)); +} + +static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1); + return 0; +} + +static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0); +} + +static int sprd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1); + return 0; +} + +static int sprd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value); + return 0; +} + +static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA); +} + +static void sprd_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value); +} + +static void sprd_gpio_irq_mask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0); +} + +static void sprd_gpio_irq_ack(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1); +} + +static void sprd_gpio_irq_unmask(struct irq_data *data) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1); +} + +static int sprd_gpio_irq_set_type(struct irq_data *data, + unsigned int flow_type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + u32 offset = irqd_to_hwirq(data); + + switch (flow_type) { + case IRQ_TYPE_EDGE_RISING: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_EDGE_FALLING: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_EDGE_BOTH: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1); + irq_set_handler_locked(data, handle_edge_irq); + break; + case IRQ_TYPE_LEVEL_HIGH: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1); + irq_set_handler_locked(data, handle_level_irq); + break; + case IRQ_TYPE_LEVEL_LOW: + sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1); + sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0); + sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0); + irq_set_handler_locked(data, handle_level_irq); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void sprd_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *chip = irq_desc_get_handler_data(desc); + struct irq_chip *ic = irq_desc_get_chip(desc); + struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip); + u32 group, n, girq; + + chained_irq_enter(ic, desc); + + for (group = 0; group * SPRD_GPIO_GROUP_NR < chip->ngpio; group++) { + void __iomem *base = sprd_gpio_group_base(sprd_gpio, group); + unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) & + SPRD_GPIO_GROUP_MASK; + + for_each_set_bit(n, ®, SPRD_GPIO_GROUP_NR) { + girq = irq_find_mapping(chip->irq.domain, + group * SPRD_GPIO_GROUP_NR + n); + + generic_handle_irq(girq); + } + + } + chained_irq_exit(ic, desc); +} + +static struct irq_chip sprd_gpio_irqchip = { + .name = "sprd-gpio", + .irq_ack = sprd_gpio_irq_ack, + .irq_mask = sprd_gpio_irq_mask, + .irq_unmask = sprd_gpio_irq_unmask, + .irq_set_type = sprd_gpio_irq_set_type, + .flags = IRQCHIP_SKIP_SET_WAKE, +}; + +static int sprd_gpio_probe(struct platform_device *pdev) +{ + struct gpio_irq_chip *irq; + struct sprd_gpio *sprd_gpio; + struct resource *res; + int ret; + + sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL); + if (!sprd_gpio) + return -ENOMEM; + + sprd_gpio->irq = platform_get_irq(pdev, 0); + if (sprd_gpio->irq < 0) { + dev_err(&pdev->dev, "Failed to get GPIO interrupt.\n"); + return sprd_gpio->irq; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sprd_gpio->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sprd_gpio->base)) + return PTR_ERR(sprd_gpio->base); + + spin_lock_init(&sprd_gpio->lock); + + sprd_gpio->chip.label = dev_name(&pdev->dev); + sprd_gpio->chip.ngpio = SPRD_GPIO_NR; + sprd_gpio->chip.base = -1; + sprd_gpio->chip.parent = &pdev->dev; + sprd_gpio->chip.of_node = pdev->dev.of_node; + sprd_gpio->chip.request = sprd_gpio_request; + sprd_gpio->chip.free = sprd_gpio_free; + sprd_gpio->chip.get = sprd_gpio_get; + sprd_gpio->chip.set = sprd_gpio_set; + sprd_gpio->chip.direction_input = sprd_gpio_direction_input; + sprd_gpio->chip.direction_output = sprd_gpio_direction_output; + + irq = &sprd_gpio->chip.irq; + irq->chip = &sprd_gpio_irqchip; + irq->handler = handle_simple_irq; + irq->default_type = IRQ_TYPE_NONE; + irq->parent_handler = sprd_gpio_irq_handler; + irq->parent_handler_data = sprd_gpio; + irq->num_parents = 1; + irq->parents = &sprd_gpio->irq; + + ret = devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, sprd_gpio); + return 0; +} + +static const struct of_device_id sprd_gpio_of_match[] = { + { .compatible = "sprd,sc9860-gpio", }, + { /* end of list */ }, +}; +MODULE_DEVICE_TABLE(of, sprd_gpio_of_match); + +static struct platform_driver sprd_gpio_driver = { + .probe = sprd_gpio_probe, + .driver = { + .name = "sprd-gpio", + .of_match_table = sprd_gpio_of_match, + }, +}; + +module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe); + +MODULE_DESCRIPTION("Spreadtrum GPIO driver"); +MODULE_LICENSE("GPL v2");