From patchwork Fri Dec 11 22:15:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 342269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71CFFC433FE for ; Fri, 11 Dec 2020 23:10:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3086822D06 for ; Fri, 11 Dec 2020 23:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406774AbgLKWQu (ORCPT ); Fri, 11 Dec 2020 17:16:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2406765AbgLKWQY (ORCPT ); Fri, 11 Dec 2020 17:16:24 -0500 Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 031B8C061793 for ; Fri, 11 Dec 2020 14:15:44 -0800 (PST) Received: by mail-pl1-x643.google.com with SMTP id u4so5274379plr.12 for ; Fri, 11 Dec 2020 14:15:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eSXgvDLpVB7w74OUfv3cDJRgo0Ae+QBThzZ61gjo+zM=; b=RjZ/Yl0JAFwkfZgGfxUK6IM1WdZvS9NvWj2e7aH+rj+FX+LHVf5JZrhWKXJbGnGpeP tmUoJNEC3rB1oxmNbw52dkbdEvfZNA5zKbTD/+VmkdXldxrdyG4kRSbb2lPsxUWxGd61 zQ5OS9TS9SSwyvVOyG+79q7i4gO/e4fmrsrfM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eSXgvDLpVB7w74OUfv3cDJRgo0Ae+QBThzZ61gjo+zM=; b=TaCRWv8+qWxqYMn8xvKTn5r3GcGH/mgaEwOrtOF/AyqAb6rJ0tS6ouD5kUuX4xvS98 H1T1E5burR3SHX8KeCYre+zaDLJc+9ay8ZgZG25Y1pUsfKGBx93Ht/u+d7hUdvu7GuFa 1j8JjUg0s19LFg2TrqjzoZJ4jHZhg0KQgYb8Yi82q2xXuM1EiLgt3moqt3+GkVER94OT J+MovEQCzgnpKzLt5eAxgxfZjGyLbcN0d62r4RkuKkTwxWdcoOIMveQWDfYnY2EV/XbW t3Ku3DUrtAJaJVvXzDVdsuKL6CmVxQOI03EfG6V7peyM60hn9b25VjzlD5EStQ1+8tUM STQw== X-Gm-Message-State: AOAM5312gMaCEAUdMkD5R+0FE+wWIWz8Gxo1f2j6/mpSdaozk/Eeb3x1 3tWDN3VYN4H8KqsVGHGP+O5jZA== X-Google-Smtp-Source: ABdhPJyIv2Jehmt+dPfzYJ96qnWSdOKGFV7nzHGwAGIYg+MmYfmO6vSXyTlAjfuNOW3jvr2yWdLwgQ== X-Received: by 2002:a17:90a:f28f:: with SMTP id fs15mr15217771pjb.121.1607724943391; Fri, 11 Dec 2020 14:15:43 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:42b0:34ff:fe3d:58e6]) by smtp.gmail.com with ESMTPSA id s21sm11832981pgk.52.2020.12.11.14.15.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 14:15:42 -0800 (PST) From: Douglas Anderson To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Linus Walleij Cc: Bjorn Andersson , Rajendra Nayak , Maulik Shah , Stephen Boyd , linux-arm-msm@vger.kernel.org, Srinivas Ramana , Neeraj Upadhyay , linux-gpio@vger.kernel.org, Douglas Anderson , Andy Gross , Archana Sathyakumar , Lina Iyer , linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] irqchip: qcom-pdc: Fix phantom irq when changing between rising/falling Date: Fri, 11 Dec 2020 14:15:35 -0800 Message-Id: <20201211141514.v4.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid> X-Mailer: git-send-email 2.29.2.576.ga3fc446d84-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org We have a problem if we use gpio-keys and configure wakeups such that we only want one edge to wake us up. AKA: wakeup-event-action = ; wakeup-source; Specifically we end up with a phantom interrupt that blocks suspend if the line was already high and we want wakeups on rising edges (AKA we want the GPIO to go low and then high again before we wake up). The opposite is also problematic. Specifically, here's what's happening today: 1. Normally, gpio-keys configures to look for both edges. Due to the current workaround introduced in commit c3c0c2e18d94 ("pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180"), if the line was high we'd configure for falling edges. 2. At suspend time, we change to look for rising edges. 3. After qcom_pdc_gic_set_type() runs, we get a phantom interrupt. We can solve this by just clearing the phantom interrupt. NOTE: it is possible that this could cause problems for a client with very specific needs, but there's not much we can do with this hardware. As an example, let's say the interrupt signal is currently high and the client is looking for falling edges. The client now changes to look for rising edges. The client could possibly expect that if the line has a short pulse low (and back high) that it would always be detected. Specifically no matter when the pulse happened, it should either have tripped the (old) falling edge trigger or the (new) rising edge trigger. We will simply not trip it. We could narrow down the race a bit by polling our parent before changing types, but no matter what we do there will still be a period of time where we can't tell the difference between a real transition (or more than one transition) and the phantom. Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") Signed-off-by: Douglas Anderson Reviewed-by: Maulik Shah Tested-by: Maulik Shah Reviewed-by: Stephen Boyd Reviewed-by: Stephen Boyd Reviewed-by: Rajendra Nayak --- There are no dependencies between this patch and patch #2/#3. It can go in by itself. Patches are only grouped together in one series because they address similar issues. Maulik has got confirmation from hardware guys and understands the problem. This patch is ready to land. Changes in v4: - No changes, this patch on its own ready to land. Changes in v3: - Adjusted the comment as per Maulik. Changes in v2: - 0 => false - If irq_chip_set_type_parent() fails don't bother clearing. - Add Fixes tag. drivers/irqchip/qcom-pdc.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index bd39e9de6ecf..5dc63c20b67e 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -159,6 +159,8 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) { int pin_out = d->hwirq; enum pdc_irq_config_bits pdc_type; + enum pdc_irq_config_bits old_pdc_type; + int ret; if (pin_out == GPIO_NO_WAKE_IRQ) return 0; @@ -187,9 +189,26 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) return -EINVAL; } + old_pdc_type = pdc_reg_read(IRQ_i_CFG, pin_out); pdc_reg_write(IRQ_i_CFG, pin_out, pdc_type); - return irq_chip_set_type_parent(d, type); + ret = irq_chip_set_type_parent(d, type); + if (ret) + return ret; + + /* + * When we change types the PDC can give a phantom interrupt. + * Clear it. Specifically the phantom shows up when reconfiguring + * polarity of interrupt without changing the state of the signal + * but let's be consistent and clear it always. + * + * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the + * interrupt will be cleared before the rest of the system sees it. + */ + if (old_pdc_type != pdc_type) + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); + + return 0; } static struct irq_chip qcom_pdc_gic_chip = { From patchwork Fri Dec 11 22:15:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 342268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C573C4361B for ; Fri, 11 Dec 2020 23:12:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4F43622D06 for ; Fri, 11 Dec 2020 23:12:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406768AbgLKWRe (ORCPT ); Fri, 11 Dec 2020 17:17:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2406796AbgLKWRJ (ORCPT ); Fri, 11 Dec 2020 17:17:09 -0500 Received: from mail-pj1-x1042.google.com (mail-pj1-x1042.google.com [IPv6:2607:f8b0:4864:20::1042]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26C18C0613D3 for ; Fri, 11 Dec 2020 14:15:49 -0800 (PST) Received: by mail-pj1-x1042.google.com with SMTP id hk16so3075470pjb.4 for ; Fri, 11 Dec 2020 14:15:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y7sUikV/F7gNe5Jy42I6mRR8y7okTjvOyaqlUQve9s8=; b=EYiob21Rk2nzqjeDbvTDWyfCsA5lwPGIN4WkDcg9WvyrIj+NdQqgSUBvcFUeMIaojD Qreh8bkGQrrrOE40m5XF9N4P8r0PR6Cvk+j5LTDKEfe7GA9uwRzUwZFKxnBIpsgEP7l9 6SPjZnja/FHUJJmDxX+CKRlXiqeTiJFh4QCq4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y7sUikV/F7gNe5Jy42I6mRR8y7okTjvOyaqlUQve9s8=; b=FmJMp9gj6rNO+2I6ukLcBGDcf6fuJo0yAhbQqcuHq441vAu/D7+FNEmCdHPXVHSS1d 8aLYSiUpuKpTyS87T86pf2cV4/anbGWb3qmQAQcb29kYMGRsb6TbNsn8iIfz7EVjlZEs 5ING1HfVHP26mEb5ynIJGdQADf0YQseGeB/HFep9zff5g+si/jgxphGKtDtfAH/xxH/i +b57qHnt5IshzzEZkCv30M4d5rRotsR0zRB97uxTex2kcDjai5q3sjAQ4T4p9V1DgK7r gTqZrIUHN5G65JwAyEfI4wLgVDZb0suqSEZwEuqQfI6Hv2H+eQDoWF9ZZ3ZBZpYcKNy+ 6AgQ== X-Gm-Message-State: AOAM531tCqr3SUY6vfBF+UUNYxKF2Hcpdf3yq2UrU80GL4xEgn4oCbZa 392/cnxRNfkAbeWOTKYD0Ci6uw== X-Google-Smtp-Source: ABdhPJwQaEII/ZFOuv5w3ZNFYFqtSx7WMh6WT8IlI/wAmhJhldG2bz6rBTVow8GDJR+cKB3eYQkmrw== X-Received: by 2002:a17:902:5581:b029:da:a817:1753 with SMTP id g1-20020a1709025581b02900daa8171753mr12637716pli.76.1607724948477; Fri, 11 Dec 2020 14:15:48 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:42b0:34ff:fe3d:58e6]) by smtp.gmail.com with ESMTPSA id s21sm11832981pgk.52.2020.12.11.14.15.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Dec 2020 14:15:48 -0800 (PST) From: Douglas Anderson To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Linus Walleij Cc: Bjorn Andersson , Rajendra Nayak , Maulik Shah , Stephen Boyd , linux-arm-msm@vger.kernel.org, Srinivas Ramana , Neeraj Upadhyay , linux-gpio@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH v4 4/4] pinctrl: qcom: Clear possible pending parent irq when remuxing GPIOs Date: Fri, 11 Dec 2020 14:15:38 -0800 Message-Id: <20201211141514.v4.4.I771b6594b2a4d5b7fe7e12a991a6640f46386e8d@changeid> X-Mailer: git-send-email 2.29.2.576.ga3fc446d84-goog In-Reply-To: <20201211141514.v4.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid> References: <20201211141514.v4.1.I2702919afc253e2a451bebc3b701b462b2d22344@changeid> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org In commit 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback") we tried to make it so that the "enable" didn't clear pending interrupts for interrupts that were handled by our parent (the PDC). Unfortunately that regressed things. After that patch we found that sc7180-trogdor based devices could no longer enter suspend. Specifically in sc7180-trogdor.dtsi we configure the uart3 to have two pinctrl states, sleep and default, and mux between the two during runtime PM and system suspend (see geni_se_resources_{on,off}() for more details). The difference between the sleep and default state is that the RX pin is muxed to a GPIO during sleep and muxed to the UART otherwise. As per Qualcomm, when we mux the pin over to the UART function the PDC is still watching it / latching edges. These edges don't cause interrupts because the current code masks the interrupt unless we're entering suspend. However, as soon as we enter suspend we unmask the interrupt and it's counted as a wakeup. Let's deal with the problem like this: * When we mux away, we'll mask our parent. This isn't necessary in the above case since the parent already masked us, but it's a good idea in general. * When we mux back will clear any interrupts and unmask our parent if needed. Fixes: 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback") Signed-off-by: Douglas Anderson --- This patch depends on #2/#3 in the series, but not #1. #1 can land on its own and then #2/#3/#4 can land together even without #1. The only reason patch #1 and #2/#3/#4 are together in one series is because they address similar issues. I have done most of this patch testing on the Chrome OS 5.4 kernel tree (with many backports) but have sanity checked it on mainline. This patch definitely needs more testing / discussion, so please don't land without Qualcomm confirming that it looks OK in all the cases they are aware of. Changes in v4: - Totally rewrote again with my new understanding of the world. - Split non-PDC fix and PDC fix in two. Changes in v3: - Fixed bug in msm_gpio_direction_output() (s/oldval =/oldval = val =/) - Add back "if !skip_wake_irqs" test in msm_gpio_irq_enable() - For non-PDC, clear 1st interrupt in msm_gpio_irq_set_type() Changes in v2: - 0 => false - If skip_wake_irqs, don't need to clear normal intr. - Add comment about glitches in both output and input. drivers/pinctrl/qcom/pinctrl-msm.c | 42 +++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index f785646d1df7..37fa95c5805c 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -171,7 +171,12 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned group) { struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct gpio_chip *gc = &pctrl->chip; + unsigned int irq = irq_find_mapping(gc->irq.domain, group); + struct irq_data *d = irq_get_irq_data(irq); + unsigned int gpio_func = pctrl->soc->gpio_func; const struct msm_pingroup *g; + bool should_manage_parent; unsigned long flags; u32 val, mask; int i; @@ -187,6 +192,23 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, if (WARN_ON(i == g->nfuncs)) return -EINVAL; + /* + * If an GPIO interrupt is setup on this pin and those interrupts are + * handled by our parent we need special handling. Specifically the + * parent will still see the pin twiddle even when we're muxed away. + * + * If our GPIO was unmasked before muxing away from GPIO we need to + * mask our parent before switching so it doesn't see the twiddling. + * + * When we switch back we might need to clear any interrupts that were + * latched while were muxed away. + */ + should_manage_parent = d && d->parent_data && + test_bit(d->hwirq, pctrl->skip_wake_irqs); + + if (i != gpio_func && should_manage_parent && !irqd_irq_masked(d)) + irq_chip_mask_parent(d); + raw_spin_lock_irqsave(&pctrl->lock, flags); val = msm_readl_ctl(pctrl, g); @@ -196,6 +218,13 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, raw_spin_unlock_irqrestore(&pctrl->lock, flags); + if (i == gpio_func && should_manage_parent) { + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); + + if (!irqd_irq_masked(d)) + irq_chip_unmask_parent(d); + } + return 0; } @@ -1093,19 +1122,6 @@ static int msm_gpio_irq_reqres(struct irq_data *d) ret = -EINVAL; goto out; } - - /* - * Clear the interrupt that may be pending before we enable - * the line. - * This is especially a problem with the GPIOs routed to the - * PDC. These GPIOs are direct-connect interrupts to the GIC. - * Disabling the interrupt line at the PDC does not prevent - * the interrupt from being latched at the GIC. The state at - * GIC needs to be cleared before enabling. - */ - if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) - irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); - return 0; out: module_put(gc->owner);