From patchwork Tue Feb 6 15:04:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luis Machado X-Patchwork-Id: 127019 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3000197ljc; Tue, 6 Feb 2018 07:04:34 -0800 (PST) X-Google-Smtp-Source: AH8x227FE1DUOIWMKbU6UDtifSHbyqAkiSNB0i6cJbJQKyy4wsCbNVmjaVdoxCQUyu8ue0jMZlgb X-Received: by 10.98.207.6 with SMTP id b6mr2764335pfg.187.1517929474784; Tue, 06 Feb 2018 07:04:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517929474; cv=none; d=google.com; s=arc-20160816; b=l8J3SqThP6u59JhstinCNwK7PuUb9CuQ7umbVgaYD5AwjG3nSkhjBrN3sXNrYhGf2Z vDy3b09pHYGYr1iwkMdhqJtqyeV5FVLahde99IluKaxC+qVUB25udPPOCUs46lUwbzoE RzWmDBPf0y0DImYnSWrpMdgk6a95yVvmhQITTgUisye/qgtBJRZ/Ss+UFL9xHd4oVx8h qcS1JCwaPuBofyJai0glpEEjFrUwTEM4tDVfdwTdz8ZTAbW7w2zKRKhz4PqXwH54y5BX +dEYenTwNaJvP0Lf5BzB0ibTYvn+xBq0FI9Vr2d3UC1lAD+k+UuTCcinbD47BUehcPWb qVJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=ZQiaxMWET5v4XywqmZxhtXBVRSvT+o97KR6MQi1sSXQ=; b=Z3nuslFjwTilhbZ/PFkhL8FMB7xv5FcIWzId8hqevT+RH9NPzVpgOKbS9AmwEOtvJz Br+TWUdsha8aWzPP59Uo7bT/K+n29nTazYg1BvRsMaJrJcshZOlgNyyN71pPdlpZlvKW 54w+LQKIbe5++xOfCZBU4UKdjFK2N8SgBuVITUc7KdbZ3/AYr7jzAzt2Vwm/BbJNqEFE TX1qjHzA5QixeGWiH21xBH5Ak6VQpkkjuQukTZDKU+rfSzxPSbfRNO4y9XlS6a89x9GP kU67fuGMZqdTCLKG72ZSMZlrXCGpkCcqSVed8lhlsBaLcc4bm9URmvle0UUalKywsISn gLOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ZjvIvm+z; spf=pass (google.com: domain of gcc-patches-return-472671-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-472671-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id d10si1148728pge.248.2018.02.06.07.04.34 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Feb 2018 07:04:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-472671-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ZjvIvm+z; spf=pass (google.com: domain of gcc-patches-return-472671-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-472671-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=uD9nAeLblberwtr90WyyD944CJp+33vTU+XP4IOEyjkhl8DJV0uqJ 6Sp1uYNn7UKxbFi85cw1tMFKWo6qoUS1tmY1sD0Uv8ZAnJT06TEguEMZPkPol2rS FG8+j1oWrivVtyMPvh7Ko02E+OAXMY+BVsAJH14POld/pca+jrawxc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=lRIqJDqbAlN/c84kiyTVGiVuQPY=; b=ZjvIvm+zInGDIJeQ8TLD IYw8ifBVNxrngrNgRNfdo3qR7BRG18LFhw2c4rwqB6fap/nwHsuHSFdWNNljJngb KSHuAQwDNKKNDPz/LsVbnLPc6v5P87wZo5BUpzD2fhxF4qVRElvYStJdznLX0UPl wxxEEEL7aPuNH7CRcanOAfI= Received: (qmail 60051 invoked by alias); 6 Feb 2018 15:04:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 60011 invoked by uid 89); 6 Feb 2018 15:04:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-qt0-f174.google.com Received: from mail-qt0-f174.google.com (HELO mail-qt0-f174.google.com) (209.85.216.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Feb 2018 15:04:17 +0000 Received: by mail-qt0-f174.google.com with SMTP id d8so2666189qtm.0 for ; Tue, 06 Feb 2018 07:04:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZQiaxMWET5v4XywqmZxhtXBVRSvT+o97KR6MQi1sSXQ=; b=bl82+lGa/XbLFXtTnLmUiaJFLqnAV62P2suFBIU35sVrqv2TQoVS6Y/xXHj8qyoodx 6eV8Su6mXoHwA1frcHXZEdrhGgievjU+g67xpvJLZ49Y4wzhoJOnzaivEkJ5ZfDFLzTC gUKT7u19dW+uDd85TeUfJWsTQ2aZA+6Svks2hyE0/16it8285fjhg1nASPWqe23giYBH FXY/6lhxjQ12nDv360MXQlXYn26h0EtQH+iAw4tofXYtmkBUjix1oWHn/pGVZLEYTiqM hLwKpjkpjoXpSQ0zbxTwbLg3i+TYkcT/f6GNZE1ng0hgFZK7UahgCVADw4u+8EIJD218 Bjiw== X-Gm-Message-State: APf1xPBzh1ZlkvdWKbmNLOHtU54+oAqGvPFX7g0zTfgQywFXglD5D2Tt kQAz2BJjhXk8VWYsWdFDZGpXVra9O78= X-Received: by 10.200.57.132 with SMTP id v4mr4063562qte.128.1517929455343; Tue, 06 Feb 2018 07:04:15 -0800 (PST) Received: from localhost.localdomain ([177.180.105.91]) by smtp.gmail.com with ESMTPSA id g3sm5552228qkh.35.2018.02.06.07.04.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 06 Feb 2018 07:04:14 -0800 (PST) From: Luis Machado To: gcc-patches@gcc.gnu.org Cc: james.greenhalgh@arm.com, Richard.Earnshaw@arm.com, kyrylo.tkachov@foss.arm.com Subject: [PATCH, v2] Recognize a missed usage of a sbfiz instruction Date: Tue, 6 Feb 2018 13:04:00 -0200 Message-Id: <1517929440-7534-1-git-send-email-luis.machado@linaro.org> In-Reply-To: <5A747C58.8020501@foss.arm.com> References: <5A747C58.8020501@foss.arm.com> X-IsSubscribed: yes Thanks for the feedback Kyrill. I've adjusted the v2 patch based on your suggestions and re-tested the changes. Everything is still sane. Since this is ARM-specific and fairly specific, i wonder if it would be reasonable to consider it for inclusion at the current stage. Regards, Luis Changes in v2: - Added more restrictive predicates to operands 2, 3 and 4. - Removed pattern conditional. - Switched to long long for 64-bit signed integer for the testcase. --- A customer reported the following missed opportunities to combine a couple instructions into a sbfiz. int sbfiz32 (int x) { return x << 29 >> 10; } long long sbfiz64 (long long x) { return x << 58 >> 20; } This gets converted to the following pattern: (set (reg:SI 98) (ashift:SI (sign_extend:SI (reg:HI 0 x0 [ xD.3334 ])) (const_int 6 [0x6]))) Currently, gcc generates the following: sbfiz32: lsl x0, x0, 29 asr x0, x0, 10 ret sbfiz64: lsl x0, x0, 58 asr x0, x0, 20 ret It could generate this instead: sbfiz32: sbfiz w0, w0, 19, 3 ret sbfiz64:: sbfiz x0, x0, 38, 6 ret The unsigned versions already generate ubfiz for the same code, so the lack of a sbfiz pattern may have been an oversight. This particular sbfiz pattern shows up in both CPU2006 (~ 80 hits) and CPU2017 (~ 280 hits). It's not a lot, but seems beneficial in any case. No significant performance differences, probably due to the small number of occurrences. 2018-02-06 Luis Machado gcc/ * config/aarch64/aarch64.md (*ashift_extv_bfiz): New pattern. 2018-02-06 Luis Machado gcc/testsuite/ * gcc.target/aarch64/lsl_asr_sbfiz.c: New test. --- gcc/config/aarch64/aarch64.md | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c -- 2.7.4 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5a2a930..e8284ae 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4828,6 +4828,19 @@ [(set_attr "type" "bfx")] ) +;; Match sbfiz pattern in a shift left + shift right operation. + +(define_insn "*ashift_extv_bfiz" + [(set (match_operand:GPI 0 "register_operand" "=r") + (ashift:GPI (sign_extract:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "aarch64_simd_shift_imm_offset_" "n") + (match_operand 3 "aarch64_simd_shift_imm_" "n")) + (match_operand 4 "aarch64_simd_shift_imm_" "n")))] + "" + "sbfiz\\t%0, %1, %4, %2" + [(set_attr "type" "bfx")] +) + ;; When the bit position and width of the equivalent extraction add up to 32 ;; we can use a W-reg LSL instruction taking advantage of the implicit ;; zero-extension of the X-reg. diff --git a/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c b/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c new file mode 100644 index 0000000..106433d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/lsl_asr_sbfiz.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* Check that a LSL followed by an ASR can be combined into a single SBFIZ + instruction. */ + +/* Using W-reg */ + +int +sbfiz32 (int x) +{ + return x << 29 >> 10; +} + +/* Using X-reg */ + +long long +sbfiz64 (long long x) +{ + return x << 58 >> 20; +} + +/* { dg-final { scan-assembler "sbfiz\tw" } } */ +/* { dg-final { scan-assembler "sbfiz\tx" } } */