From patchwork Mon Dec 14 13:31:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Kleine-Budde X-Patchwork-Id: 343850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56063C2BB9A for ; Mon, 14 Dec 2020 13:37:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1267B206C1 for ; Mon, 14 Dec 2020 13:37:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439988AbgLNNg6 (ORCPT ); Mon, 14 Dec 2020 08:36:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2407976AbgLNNdS (ORCPT ); Mon, 14 Dec 2020 08:33:18 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2E79CC0617A6 for ; Mon, 14 Dec 2020 05:31:57 -0800 (PST) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=bjornoya.blackshift.org) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1konxD-0003Sd-Lm for netdev@vger.kernel.org; Mon, 14 Dec 2020 14:31:55 +0100 Received: from dspam.blackshift.org (localhost [127.0.0.1]) by bjornoya.blackshift.org (Postfix) with SMTP id 449EA5AD2B8 for ; Mon, 14 Dec 2020 13:31:50 +0000 (UTC) Received: from hardanger.blackshift.org (unknown [172.20.34.65]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by bjornoya.blackshift.org (Postfix) with ESMTPS id 5732D5AD28E; Mon, 14 Dec 2020 13:31:47 +0000 (UTC) Received: from blackshift.org (localhost [::1]) by hardanger.blackshift.org (OpenSMTPD) with ESMTP id a38b67d6; Mon, 14 Dec 2020 13:31:46 +0000 (UTC) From: Marc Kleine-Budde To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, linux-can@vger.kernel.org, kernel@pengutronix.de, Marc Kleine-Budde , Sean Nyekjaer , Dan Murphy Subject: [net-next 2/7] can: m_can: convert indention to kernel coding style Date: Mon, 14 Dec 2020 14:31:40 +0100 Message-Id: <20201214133145.442472-3-mkl@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201214133145.442472-1-mkl@pengutronix.de> References: <20201214133145.442472-1-mkl@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch converts the indention in the m_can driver to kernel coding style. Link: https://lore.kernel.org/r/20201212175518.139651-3-mkl@pengutronix.de Reviewed-by: Sean Nyekjaer Reviewed-by: Dan Murphy Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 88 +++++++++++++++++------------------ 1 file changed, 43 insertions(+), 45 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index ec209326c3d8..f9b24fb45a8c 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -39,7 +39,7 @@ enum m_can_reg { M_CAN_TOCV = 0x2c, M_CAN_ECR = 0x40, M_CAN_PSR = 0x44, -/* TDCR Register only available for version >=3.1.x */ + /* TDCR Register only available for version >=3.1.x */ M_CAN_TDCR = 0x48, M_CAN_IR = 0x50, M_CAN_IE = 0x54, @@ -335,7 +335,7 @@ static u32 m_can_fifo_read(struct m_can_classdev *cdev, u32 fgi, unsigned int offset) { u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE + - offset; + offset; return cdev->ops->read_fifo(cdev, addr_offset); } @@ -344,7 +344,7 @@ static void m_can_fifo_write(struct m_can_classdev *cdev, u32 fpi, unsigned int offset, u32 val) { u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE + - offset; + offset; cdev->ops->write_fifo(cdev, addr_offset, val); } @@ -358,14 +358,14 @@ static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev, static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset) { u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE + - offset; + offset; return cdev->ops->read_fifo(cdev, addr_offset); } static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev) { - return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); + return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF); } void m_can_config_endisable(struct m_can_classdev *cdev, bool enable) @@ -921,14 +921,13 @@ static void m_can_echo_tx_event(struct net_device *dev) m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); /* Get Tx Event fifo element count */ - txe_count = (m_can_txefs & TXEFS_EFFL_MASK) - >> TXEFS_EFFL_SHIFT; + txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT; /* Get and process all sent elements */ for (i = 0; i < txe_count; i++) { /* retrieve get index */ - fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) - >> TXEFS_EFGI_SHIFT; + fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >> + TXEFS_EFGI_SHIFT; /* get message marker */ msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) & @@ -1087,7 +1086,7 @@ static int m_can_set_bittiming(struct net_device *dev) * Transmitter Delay Compensation Section */ tdco = (cdev->can.clock.freq / 1000) * - ssp / dbt->bitrate; + ssp / dbt->bitrate; /* Max valid TDCO value is 127 */ if (tdco > 127) { @@ -1102,9 +1101,9 @@ static int m_can_set_bittiming(struct net_device *dev) } reg_btp |= (brp << DBTP_DBRP_SHIFT) | - (sjw << DBTP_DSJW_SHIFT) | - (tseg1 << DBTP_DTSEG1_SHIFT) | - (tseg2 << DBTP_DTSEG2_SHIFT); + (sjw << DBTP_DSJW_SHIFT) | + (tseg1 << DBTP_DTSEG1_SHIFT) | + (tseg2 << DBTP_DTSEG2_SHIFT); m_can_write(cdev, M_CAN_DBTP, reg_btp); } @@ -1137,7 +1136,7 @@ static void m_can_chip_config(struct net_device *dev) if (cdev->version == 30) { /* only support one Tx Buffer currently */ m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | - cdev->mcfg[MRAM_TXB].off); + cdev->mcfg[MRAM_TXB].off); } else { /* TX FIFO is used for newer IP Core versions */ m_can_write(cdev, M_CAN_TXBC, @@ -1151,7 +1150,7 @@ static void m_can_chip_config(struct net_device *dev) /* TX Event FIFO */ if (cdev->version == 30) { m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | - cdev->mcfg[MRAM_TXE].off); + cdev->mcfg[MRAM_TXE].off); } else { /* Full TX Event FIFO is used */ m_can_write(cdev, M_CAN_TXEFC, @@ -1163,27 +1162,27 @@ static void m_can_chip_config(struct net_device *dev) /* rx fifo configuration, blocking mode, fifo size 1 */ m_can_write(cdev, M_CAN_RXF0C, (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | - cdev->mcfg[MRAM_RXF0].off); + cdev->mcfg[MRAM_RXF0].off); m_can_write(cdev, M_CAN_RXF1C, (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | - cdev->mcfg[MRAM_RXF1].off); + cdev->mcfg[MRAM_RXF1].off); cccr = m_can_read(cdev, M_CAN_CCCR); test = m_can_read(cdev, M_CAN_TEST); test &= ~TEST_LBCK; if (cdev->version == 30) { - /* Version 3.0.x */ + /* Version 3.0.x */ cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | - (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | - (CCCR_CME_MASK << CCCR_CME_SHIFT)); + (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | + (CCCR_CME_MASK << CCCR_CME_SHIFT)); if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; } else { - /* Version 3.1.x or 3.2.x */ + /* Version 3.1.x or 3.2.x */ cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE | CCCR_NISO | CCCR_DAR); @@ -1352,10 +1351,10 @@ static int m_can_dev_setup(struct m_can_classdev *m_can_dev) /* Set M_CAN supported operations */ m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | - CAN_CTRLMODE_LISTENONLY | - CAN_CTRLMODE_BERR_REPORTING | - CAN_CTRLMODE_FD | - CAN_CTRLMODE_ONE_SHOT; + CAN_CTRLMODE_LISTENONLY | + CAN_CTRLMODE_BERR_REPORTING | + CAN_CTRLMODE_FD | + CAN_CTRLMODE_ONE_SHOT; /* Set properties depending on M_CAN version */ switch (m_can_dev->version) { @@ -1366,8 +1365,8 @@ static int m_can_dev_setup(struct m_can_classdev *m_can_dev) m_can_dev->bit_timing : &m_can_bittiming_const_30X; m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ? - m_can_dev->data_timing : - &m_can_data_bittiming_const_30X; + m_can_dev->data_timing : + &m_can_data_bittiming_const_30X; break; case 31: /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */ @@ -1376,8 +1375,8 @@ static int m_can_dev_setup(struct m_can_classdev *m_can_dev) m_can_dev->bit_timing : &m_can_bittiming_const_31X; m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ? - m_can_dev->data_timing : - &m_can_data_bittiming_const_31X; + m_can_dev->data_timing : + &m_can_data_bittiming_const_31X; break; case 32: case 33: @@ -1386,13 +1385,12 @@ static int m_can_dev_setup(struct m_can_classdev *m_can_dev) m_can_dev->bit_timing : &m_can_bittiming_const_31X; m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ? - m_can_dev->data_timing : - &m_can_data_bittiming_const_31X; + m_can_dev->data_timing : + &m_can_data_bittiming_const_31X; m_can_dev->can.ctrlmode_supported |= - (m_can_niso_supported(m_can_dev) - ? CAN_CTRLMODE_FD_NON_ISO - : 0); + (m_can_niso_supported(m_can_dev) ? + CAN_CTRLMODE_FD_NON_ISO : 0); break; default: dev_err(m_can_dev->dev, "Unsupported version number: %2d", @@ -1534,7 +1532,7 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) /* get put index for frame */ putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) - >> TXFQS_TFQPI_SHIFT); + >> TXFQS_TFQPI_SHIFT); /* Write ID Field to FIFO Element */ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); @@ -1581,7 +1579,7 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) static void m_can_tx_work_queue(struct work_struct *ws) { struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev, - tx_work); + tx_work); m_can_tx_handler(cdev); cdev->tx_skb = NULL; @@ -1705,26 +1703,26 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev, cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0]; cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1]; cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off + - cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; + cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE; cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2]; cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + - cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; + cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & - (RXFC_FS_MASK >> RXFC_FS_SHIFT); + (RXFC_FS_MASK >> RXFC_FS_SHIFT); cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + - cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; + cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & - (RXFC_FS_MASK >> RXFC_FS_SHIFT); + (RXFC_FS_MASK >> RXFC_FS_SHIFT); cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + - cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; + cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off + - cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; + cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE; cdev->mcfg[MRAM_TXE].num = mram_config_vals[6]; cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + - cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; + cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & - (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); + (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); dev_dbg(cdev->dev, "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", From patchwork Mon Dec 14 13:31:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Kleine-Budde X-Patchwork-Id: 343852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D2D5C2BB9A for ; Mon, 14 Dec 2020 13:34:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48DC6229C5 for ; Mon, 14 Dec 2020 13:34:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439721AbgLNNeA (ORCPT ); Mon, 14 Dec 2020 08:34:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2407995AbgLNNdg (ORCPT ); Mon, 14 Dec 2020 08:33:36 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA25CC061248 for ; Mon, 14 Dec 2020 05:31:58 -0800 (PST) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=bjornoya.blackshift.org) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1konxF-0003VA-Ay for netdev@vger.kernel.org; Mon, 14 Dec 2020 14:31:57 +0100 Received: from dspam.blackshift.org (localhost [127.0.0.1]) by bjornoya.blackshift.org (Postfix) with SMTP id 2AC565AD2CB for ; Mon, 14 Dec 2020 13:31:53 +0000 (UTC) Received: from hardanger.blackshift.org (unknown [172.20.34.65]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by bjornoya.blackshift.org (Postfix) with ESMTPS id D2FFE5AD295; Mon, 14 Dec 2020 13:31:47 +0000 (UTC) Received: from blackshift.org (localhost [::1]) by hardanger.blackshift.org (OpenSMTPD) with ESMTP id 5a0c37cc; Mon, 14 Dec 2020 13:31:46 +0000 (UTC) From: Marc Kleine-Budde To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, linux-can@vger.kernel.org, kernel@pengutronix.de, Marc Kleine-Budde , Sean Nyekjaer , Dan Murphy Subject: [net-next 6/7] can: m_can: let m_can_class_allocate_dev() allocate driver specific private data Date: Mon, 14 Dec 2020 14:31:44 +0100 Message-Id: <20201214133145.442472-7-mkl@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201214133145.442472-1-mkl@pengutronix.de> References: <20201214133145.442472-1-mkl@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This patch enhances m_can_class_allocate_dev() to allocate driver specific private data. The driver's private data struct must contain struct m_can_classdev as its first member followed by the remaining private data. Link: https://lore.kernel.org/r/20201212175518.139651-7-mkl@pengutronix.de Reviewed-by: Sean Nyekjaer Reviewed-by: Dan Murphy Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 5 +-- drivers/net/can/m_can/m_can.h | 4 +-- drivers/net/can/m_can/m_can_pci.c | 27 +++++++++------- drivers/net/can/m_can/m_can_platform.c | 26 ++++++++------- drivers/net/can/m_can/tcan4x5x.c | 44 +++++++++++++------------- 5 files changed, 56 insertions(+), 50 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index f258c81db0c3..cc7972a103dc 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1759,7 +1759,8 @@ int m_can_class_get_clocks(struct m_can_classdev *cdev) } EXPORT_SYMBOL_GPL(m_can_class_get_clocks); -struct m_can_classdev *m_can_class_allocate_dev(struct device *dev) +struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, + int sizeof_priv) { struct m_can_classdev *class_dev = NULL; u32 mram_config_vals[MRAM_CFG_LEN]; @@ -1782,7 +1783,7 @@ struct m_can_classdev *m_can_class_allocate_dev(struct device *dev) tx_fifo_size = mram_config_vals[7]; /* allocate the m_can device */ - net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size); + net_dev = alloc_candev(sizeof_priv, tx_fifo_size); if (!net_dev) { dev_err(dev, "Failed to allocate CAN device"); goto out; diff --git a/drivers/net/can/m_can/m_can.h b/drivers/net/can/m_can/m_can.h index 3994e20249f8..3fda84cef351 100644 --- a/drivers/net/can/m_can/m_can.h +++ b/drivers/net/can/m_can/m_can.h @@ -86,8 +86,6 @@ struct m_can_classdev { struct m_can_ops *ops; - void *device_data; - int version; u32 irqstatus; @@ -97,7 +95,7 @@ struct m_can_classdev { struct mram_cfg mcfg[MRAM_CFG_NUM]; }; -struct m_can_classdev *m_can_class_allocate_dev(struct device *dev); +struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv); void m_can_class_free_dev(struct net_device *net); int m_can_class_register(struct m_can_classdev *cdev); void m_can_class_unregister(struct m_can_classdev *cdev); diff --git a/drivers/net/can/m_can/m_can_pci.c b/drivers/net/can/m_can/m_can_pci.c index 04010ee0407c..ebfbef25e3f9 100644 --- a/drivers/net/can/m_can/m_can_pci.c +++ b/drivers/net/can/m_can/m_can_pci.c @@ -22,26 +22,33 @@ #define CTL_CSR_INT_CTL_OFFSET 0x508 struct m_can_pci_priv { + struct m_can_classdev cdev; + void __iomem *base; }; +static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev) +{ + return container_of(cdev, struct m_can_pci_priv, cdev); +} + static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg) { - struct m_can_pci_priv *priv = cdev->device_data; + struct m_can_pci_priv *priv = cdev_to_priv(cdev); return readl(priv->base + reg); } static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset) { - struct m_can_pci_priv *priv = cdev->device_data; + struct m_can_pci_priv *priv = cdev_to_priv(cdev); return readl(priv->base + offset); } static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) { - struct m_can_pci_priv *priv = cdev->device_data; + struct m_can_pci_priv *priv = cdev_to_priv(cdev); writel(val, priv->base + reg); @@ -50,7 +57,7 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val) { - struct m_can_pci_priv *priv = cdev->device_data; + struct m_can_pci_priv *priv = cdev_to_priv(cdev); writel(val, priv->base + offset); @@ -89,21 +96,19 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - priv = devm_kzalloc(&pci->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - mcan_class = m_can_class_allocate_dev(&pci->dev); + mcan_class = m_can_class_allocate_dev(&pci->dev, + sizeof(struct m_can_pci_priv)); if (!mcan_class) return -ENOMEM; + priv = cdev_to_priv(mcan_class); + priv->base = base; ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES); if (ret < 0) return ret; - mcan_class->device_data = priv; mcan_class->dev = &pci->dev; mcan_class->net->irq = pci_irq_vector(pci, 0); mcan_class->pm_clock_support = 1; @@ -135,7 +140,7 @@ static void m_can_pci_remove(struct pci_dev *pci) { struct net_device *dev = pci_get_drvdata(pci); struct m_can_classdev *mcan_class = netdev_priv(dev); - struct m_can_pci_priv *priv = mcan_class->device_data; + struct m_can_pci_priv *priv = cdev_to_priv(mcan_class); pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 36ef791da388..5758d25e42c8 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -10,27 +10,34 @@ #include "m_can.h" struct m_can_plat_priv { + struct m_can_classdev cdev; + void __iomem *base; void __iomem *mram_base; }; +static inline struct m_can_plat_priv *cdev_to_priv(struct m_can_classdev *cdev) +{ + return container_of(cdev, struct m_can_plat_priv, cdev); +} + static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg) { - struct m_can_plat_priv *priv = cdev->device_data; + struct m_can_plat_priv *priv = cdev_to_priv(cdev); return readl(priv->base + reg); } static u32 iomap_read_fifo(struct m_can_classdev *cdev, int offset) { - struct m_can_plat_priv *priv = cdev->device_data; + struct m_can_plat_priv *priv = cdev_to_priv(cdev); return readl(priv->mram_base + offset); } static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) { - struct m_can_plat_priv *priv = cdev->device_data; + struct m_can_plat_priv *priv = cdev_to_priv(cdev); writel(val, priv->base + reg); @@ -39,7 +46,7 @@ static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val) static int iomap_write_fifo(struct m_can_classdev *cdev, int offset, int val) { - struct m_can_plat_priv *priv = cdev->device_data; + struct m_can_plat_priv *priv = cdev_to_priv(cdev); writel(val, priv->mram_base + offset); @@ -62,17 +69,12 @@ static int m_can_plat_probe(struct platform_device *pdev) void __iomem *mram_addr; int irq, ret = 0; - mcan_class = m_can_class_allocate_dev(&pdev->dev); + mcan_class = m_can_class_allocate_dev(&pdev->dev, + sizeof(struct m_can_plat_priv)); if (!mcan_class) return -ENOMEM; - priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - ret = -ENOMEM; - goto probe_fail; - } - - mcan_class->device_data = priv; + priv = cdev_to_priv(mcan_class); ret = m_can_class_get_clocks(mcan_class); if (ret) diff --git a/drivers/net/can/m_can/tcan4x5x.c b/drivers/net/can/m_can/tcan4x5x.c index a0fecc3fb829..24c737c4fc44 100644 --- a/drivers/net/can/m_can/tcan4x5x.c +++ b/drivers/net/can/m_can/tcan4x5x.c @@ -114,17 +114,23 @@ #define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29)) struct tcan4x5x_priv { + struct m_can_classdev cdev; + struct regmap *regmap; struct spi_device *spi; - struct m_can_classdev *mcan_dev; - struct gpio_desc *reset_gpio; struct gpio_desc *device_wake_gpio; struct gpio_desc *device_state_gpio; struct regulator *power; }; +static inline struct tcan4x5x_priv *cdev_to_priv(struct m_can_classdev *cdev) +{ + return container_of(cdev, struct tcan4x5x_priv, cdev); + +} + static struct can_bittiming_const tcan4x5x_bittiming_const = { .name = DEVICE_NAME, .tseg1_min = 2, @@ -253,7 +259,7 @@ static struct regmap_bus tcan4x5x_bus = { static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) { - struct tcan4x5x_priv *priv = cdev->device_data; + struct tcan4x5x_priv *priv = cdev_to_priv(cdev); u32 val; regmap_read(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, &val); @@ -263,7 +269,7 @@ static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg) static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset) { - struct tcan4x5x_priv *priv = cdev->device_data; + struct tcan4x5x_priv *priv = cdev_to_priv(cdev); u32 val; regmap_read(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, &val); @@ -273,7 +279,7 @@ static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset) static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) { - struct tcan4x5x_priv *priv = cdev->device_data; + struct tcan4x5x_priv *priv = cdev_to_priv(cdev); return regmap_write(priv->regmap, TCAN4X5X_MCAN_OFFSET + reg, val); } @@ -281,7 +287,7 @@ static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val) static int tcan4x5x_write_fifo(struct m_can_classdev *cdev, int addr_offset, int val) { - struct tcan4x5x_priv *priv = cdev->device_data; + struct tcan4x5x_priv *priv = cdev_to_priv(cdev); return regmap_write(priv->regmap, TCAN4X5X_MRAM_START + addr_offset, val); } @@ -300,7 +306,7 @@ static int tcan4x5x_power_enable(struct regulator *reg, int enable) static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev, int reg, int val) { - struct tcan4x5x_priv *priv = cdev->device_data; + struct tcan4x5x_priv *priv = cdev_to_priv(cdev); return regmap_write(priv->regmap, reg, val); } @@ -330,7 +336,7 @@ static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev) static int tcan4x5x_init(struct m_can_classdev *cdev) { - struct tcan4x5x_priv *tcan4x5x = cdev->device_data; + struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); int ret; tcan4x5x_check_wake(tcan4x5x); @@ -357,7 +363,7 @@ static int tcan4x5x_init(struct m_can_classdev *cdev) static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) { - struct tcan4x5x_priv *tcan4x5x = cdev->device_data; + struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, TCAN4X5X_DISABLE_WAKE_MSK, 0x00); @@ -365,7 +371,7 @@ static int tcan4x5x_disable_wake(struct m_can_classdev *cdev) static int tcan4x5x_disable_state(struct m_can_classdev *cdev) { - struct tcan4x5x_priv *tcan4x5x = cdev->device_data; + struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); return regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG, TCAN4X5X_DISABLE_INH_MSK, 0x01); @@ -373,7 +379,7 @@ static int tcan4x5x_disable_state(struct m_can_classdev *cdev) static int tcan4x5x_get_gpios(struct m_can_classdev *cdev) { - struct tcan4x5x_priv *tcan4x5x = cdev->device_data; + struct tcan4x5x_priv *tcan4x5x = cdev_to_priv(cdev); int ret; tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake", @@ -427,15 +433,12 @@ static int tcan4x5x_can_probe(struct spi_device *spi) struct m_can_classdev *mcan_class; int freq, ret; - mcan_class = m_can_class_allocate_dev(&spi->dev); + mcan_class = m_can_class_allocate_dev(&spi->dev, + sizeof(struct tcan4x5x_priv)); if (!mcan_class) return -ENOMEM; - priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); - if (!priv) { - ret = -ENOMEM; - goto out_m_can_class_free_dev; - } + priv = cdev_to_priv(mcan_class); priv->power = devm_regulator_get_optional(&spi->dev, "vsup"); if (PTR_ERR(priv->power) == -EPROBE_DEFER) { @@ -445,8 +448,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi) priv->power = NULL; } - mcan_class->device_data = priv; - m_can_class_get_clocks(mcan_class); if (IS_ERR(mcan_class->cclk)) { dev_err(&spi->dev, "no CAN clock source defined\n"); @@ -462,7 +463,6 @@ static int tcan4x5x_can_probe(struct spi_device *spi) } priv->spi = spi; - priv->mcan_dev = mcan_class; mcan_class->pm_clock_support = 0; mcan_class->can.clock.freq = freq; @@ -518,11 +518,11 @@ static int tcan4x5x_can_remove(struct spi_device *spi) { struct tcan4x5x_priv *priv = spi_get_drvdata(spi); - m_can_class_unregister(priv->mcan_dev); + m_can_class_unregister(&priv->cdev); tcan4x5x_power_enable(priv->power, 0); - m_can_class_free_dev(priv->mcan_dev->net); + m_can_class_free_dev(priv->cdev.net); return 0; } From patchwork Mon Dec 14 13:31:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Kleine-Budde X-Patchwork-Id: 343851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10C52C2BB48 for ; Mon, 14 Dec 2020 13:36:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B681122795 for ; Mon, 14 Dec 2020 13:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2439590AbgLNNf0 (ORCPT ); Mon, 14 Dec 2020 08:35:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2407982AbgLNNdg (ORCPT ); Mon, 14 Dec 2020 08:33:36 -0500 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9053C0611C5 for ; Mon, 14 Dec 2020 05:31:58 -0800 (PST) Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=bjornoya.blackshift.org) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1konxF-0003VZ-DT for netdev@vger.kernel.org; Mon, 14 Dec 2020 14:31:57 +0100 Received: from dspam.blackshift.org (localhost [127.0.0.1]) by bjornoya.blackshift.org (Postfix) with SMTP id 923EC5AD2D1 for ; Mon, 14 Dec 2020 13:31:54 +0000 (UTC) Received: from hardanger.blackshift.org (unknown [172.20.34.65]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by bjornoya.blackshift.org (Postfix) with ESMTPS id 015525AD298; Mon, 14 Dec 2020 13:31:47 +0000 (UTC) Received: from blackshift.org (localhost [::1]) by hardanger.blackshift.org (OpenSMTPD) with ESMTP id 0a1d330d; Mon, 14 Dec 2020 13:31:46 +0000 (UTC) From: Marc Kleine-Budde To: netdev@vger.kernel.org Cc: davem@davemloft.net, kuba@kernel.org, linux-can@vger.kernel.org, kernel@pengutronix.de, Marc Kleine-Budde , Sean Nyekjaer , Dan Murphy Subject: [net-next 7/7] can: m_can: use struct m_can_classdev as drvdata Date: Mon, 14 Dec 2020 14:31:45 +0100 Message-Id: <20201214133145.442472-8-mkl@pengutronix.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201214133145.442472-1-mkl@pengutronix.de> References: <20201214133145.442472-1-mkl@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: mkl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The m_can driver's suspend and resume functions (m_can_class_suspend() and m_can_class_resume()) make use of dev_get_drvdata() and assume that the drvdata is a pointer to the struct net_device. With upcoming conversion of the tcan4x5x driver to pm_runtime this assumption is no longer valid. As the suspend and resume functions actually need a struct m_can_classdev pointer, change the m_can_platform and the m_can_pci driver to hold a pointer to struct m_can_classdev instead, as the tcan4x5x driver already does. Link: https://lore.kernel.org/r/20201212175518.139651-8-mkl@pengutronix.de Reviewed-by: Sean Nyekjaer Reviewed-by: Dan Murphy Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 8 ++++---- drivers/net/can/m_can/m_can_pci.c | 5 ++--- drivers/net/can/m_can/m_can_platform.c | 14 +++++++------- 3 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index cc7972a103dc..2c9f12401276 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1859,8 +1859,8 @@ EXPORT_SYMBOL_GPL(m_can_class_unregister); int m_can_class_suspend(struct device *dev) { - struct net_device *ndev = dev_get_drvdata(dev); - struct m_can_classdev *cdev = netdev_priv(ndev); + struct m_can_classdev *cdev = dev_get_drvdata(dev); + struct net_device *ndev = cdev->net; if (netif_running(ndev)) { netif_stop_queue(ndev); @@ -1879,8 +1879,8 @@ EXPORT_SYMBOL_GPL(m_can_class_suspend); int m_can_class_resume(struct device *dev) { - struct net_device *ndev = dev_get_drvdata(dev); - struct m_can_classdev *cdev = netdev_priv(ndev); + struct m_can_classdev *cdev = dev_get_drvdata(dev); + struct net_device *ndev = cdev->net; pinctrl_pm_select_default_state(dev); diff --git a/drivers/net/can/m_can/m_can_pci.c b/drivers/net/can/m_can/m_can_pci.c index ebfbef25e3f9..128808605c3f 100644 --- a/drivers/net/can/m_can/m_can_pci.c +++ b/drivers/net/can/m_can/m_can_pci.c @@ -115,7 +115,7 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) mcan_class->can.clock.freq = id->driver_data; mcan_class->ops = &m_can_pci_ops; - pci_set_drvdata(pci, mcan_class->net); + pci_set_drvdata(pci, mcan_class); ret = m_can_class_register(mcan_class); if (ret) @@ -138,8 +138,7 @@ static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) static void m_can_pci_remove(struct pci_dev *pci) { - struct net_device *dev = pci_get_drvdata(pci); - struct m_can_classdev *mcan_class = netdev_priv(dev); + struct m_can_classdev *mcan_class = pci_get_drvdata(pci); struct m_can_pci_priv *priv = cdev_to_priv(mcan_class); pm_runtime_forbid(&pci->dev); diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c index 5758d25e42c8..599de0e08cd7 100644 --- a/drivers/net/can/m_can/m_can_platform.c +++ b/drivers/net/can/m_can/m_can_platform.c @@ -113,7 +113,7 @@ static int m_can_plat_probe(struct platform_device *pdev) mcan_class->is_peripheral = false; - platform_set_drvdata(pdev, mcan_class->net); + platform_set_drvdata(pdev, mcan_class); m_can_init_ram(mcan_class); @@ -143,8 +143,8 @@ static __maybe_unused int m_can_resume(struct device *dev) static int m_can_plat_remove(struct platform_device *pdev) { - struct net_device *dev = platform_get_drvdata(pdev); - struct m_can_classdev *mcan_class = netdev_priv(dev); + struct m_can_plat_priv *priv = platform_get_drvdata(pdev); + struct m_can_classdev *mcan_class = &priv->cdev; m_can_class_unregister(mcan_class); @@ -155,8 +155,8 @@ static int m_can_plat_remove(struct platform_device *pdev) static int __maybe_unused m_can_runtime_suspend(struct device *dev) { - struct net_device *ndev = dev_get_drvdata(dev); - struct m_can_classdev *mcan_class = netdev_priv(ndev); + struct m_can_plat_priv *priv = dev_get_drvdata(dev); + struct m_can_classdev *mcan_class = &priv->cdev; clk_disable_unprepare(mcan_class->cclk); clk_disable_unprepare(mcan_class->hclk); @@ -166,8 +166,8 @@ static int __maybe_unused m_can_runtime_suspend(struct device *dev) static int __maybe_unused m_can_runtime_resume(struct device *dev) { - struct net_device *ndev = dev_get_drvdata(dev); - struct m_can_classdev *mcan_class = netdev_priv(ndev); + struct m_can_plat_priv *priv = dev_get_drvdata(dev); + struct m_can_classdev *mcan_class = &priv->cdev; int err; err = clk_prepare_enable(mcan_class->hclk);