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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 01/32] include/exec/helper-head.h: support f16 in helper calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org, Peter Crosthwaite Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to explicitly pass float16 to helpers rather than assuming uint32_t and dealing with the result. Of course they will be passed in i32 sized registers by default. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- include/exec/helper-head.h | 3 +++ 1 file changed, 3 insertions(+) -- 2.15.1 diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index e1fd08f2ba..15b6a68de3 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 #define dh_alias_ptr ptr @@ -38,6 +39,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_f16 float16 #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 #define dh_ctype_ptr void * @@ -94,6 +96,7 @@ #define dh_is_signed_s32 1 #define dh_is_signed_i64 0 #define dh_is_signed_s64 1 +#define dh_is_signed_f16 0 #define dh_is_signed_f32 0 #define dh_is_signed_f64 0 #define dh_is_signed_tl 0 From patchwork Thu Feb 8 17:31:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127693 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1712459ljc; Thu, 8 Feb 2018 09:42:56 -0800 (PST) X-Google-Smtp-Source: AH8x224C3cHjgtaEMU5OqtPi7oHCFg7CSUQE6OstMVWBZvQtAInSYJInbzzeRz42jr2+Abyg0ROe X-Received: by 10.37.172.96 with SMTP id r32mr1103443ybd.454.1518111776321; Thu, 08 Feb 2018 09:42:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518111776; cv=none; d=google.com; s=arc-20160816; b=oOxHCMJMlavDAIa9E0wgbUnh9Ax2E+jaH4bHT27o7GsHyb+8bZks3ZdjIkrUve9fbl F5H3QRazQYe4J7MH1b+7b0VPPVFpoPTG4bbqnc3evRiqvpX8d7PI2Ay9TONR2iW0wvcF Nh+L5xXAxnqU3GzF3aDxFypY7izGaNzJf0UumGgoJgcf5Wj/eoB8UrD/G+0PifbvhZz/ Y6OQy00SuQo3+8/E+mBng1WNAvWYK389b2XksoCjMOaS9QWFTxhd78L9WNexaU0zdysf l8FIFoegyQ9hxMOYGPV+dYZlKhWtxHTi5l6chi6qjVgj7xCUsNRvYRz82ZdCHuWIG6s6 GB5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=5FcM++eRyZVbmGXeJhC+0CkujVOg7r55axUt+Od4YVI=; b=lpw3ixZfZmG9BqBbCi1hWy1HM+wi8s/tMcZqava+kU0kBdVWFUAiygIdI+VH/aG6rY 9/F0oOJa/ccA6byIhf0QnYEq6w4aQT/i2r0xx1Tvw6y6/NXQD0fJ1SaQhkt+uhHhZ4Tu I0Fmaa18JpB/xsqukwH7G1rGGfLRVrzQcV5oyFKBk0dcO9KdwXGcev9IC/Ssh/r03bjn vUalTT1a1GEC6R3aDFJGP4T+Wxk1FicT2epPxTNAoVpMjig8WzTamzuLGJ9rZU/eivg3 B0NLYQnEPGQtoHzoTGtf4qyY/omHPiunLbgt91X8oHcKuE/zdpHvgQxzDT9aXb84DG4L mRQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g6TpQYVc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 02/32] target/arm/cpu64: introduce ARM_V8_FP16 feature bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) -- 2.15.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c7c922d79b..c793250186 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1339,6 +1339,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_SVE, /* has Scalable Vector Extension */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 670c07ab6e..973614dfc6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } From patchwork Thu Feb 8 17:31:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127692 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1711707ljc; Thu, 8 Feb 2018 09:42:01 -0800 (PST) X-Google-Smtp-Source: AH8x2246n1I5/3g1DKayxwBZxGnY1iLHCBYkTTgbWt2fhw7lHuQxhKEfM9ok1Sydvcfmb3Eiczz8 X-Received: by 10.37.185.195 with SMTP id y3mr1123663ybj.7.1518111721485; Thu, 08 Feb 2018 09:42:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518111721; cv=none; d=google.com; s=arc-20160816; b=m/c1cjQbTqlm+Pin1uWOC7bb9DUYeSb+qJkwXX3M0BSko6aq2xlxGxfhEYtDknYxNr E5wtpUaMp5yPz6DdaQWV6X72twkI+i6lfXpVNuQ9uY2Zt52+iuK9TjKpXePoB75uygi4 voptyUR7EoKDtJ6pTfKdSlTzyVubXj0Qf3ZXuzAlIFimrNqdxdvM6wxy2usjNfnOHJ7y CuyIozPrycX50tidNDHaioHHzuALCmCNQaJoxg0Fv7222e3jUOyvNoZjptg1nHETJijl OQbgGbdkzxjBTLLijlWhPIq1T//eSQh5cql+GNeX/YAMShNf9pIKSxtTIUqBDWYgx+qQ KEfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xy+BqTsxwQYHxuAigXd/mT01GPZdBWUZ1Bw2X5bjo58=; b=koRoG4pQuQIrTvY9CgvsSkd4gKhMftnYIV0+fXkKDiEFq1fnuLvu3LuXlyLOZihkOR HGXm6WgwJqEudc8HfvQIDKTvAXbpNaGFdfdqoaY8GmNQjZzEsfEq1y/Z2rEWcU2J+OQR yLTKebUf3IRTJU/FOzKFbQGvgfG0LGI97hX+qOBAvy4ZAC0PDh69nAKJdM6AUbMhLAyB DRtTF8u2kbUBspM+tHfL1jHmdR+wWKfIQRT54B30l450FQImF+2BulSxr2uhhwymW9a4 HacbTp4qhlJJFtIS6yifkjMQKeF5p9aORCzht9/RxIVVYzBiWMfwkJVPhmPR7bwV6FqR tVOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IqGcBGWu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v2 03/32] target/arm/cpu64: allow fp16 to be disabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While for CONFIG_USER_ONLY it is policy for the "cpu" to be the most capable is can be this does cause problems. For example legacy RISU runs would fail as there are a bunch of implemented instructions which would have caused failures that now trigger actual calculations. Signed-off-by: Alex Bennée --- target/arm/cpu64.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 973614dfc6..0dc4debd9c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -275,6 +275,26 @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) } } +#ifdef CONFIG_USER_ONLY +static bool aarch64_cpu_get_fp16(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + return arm_feature(&cpu->env, ARM_FEATURE_V8_FP16); +} + +static void aarch64_cpu_set_fp16(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (value == false) { + unset_feature(&cpu->env, ARM_FEATURE_V8_FP16); + } else { + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + } +} +#endif + static void aarch64_cpu_initfn(Object *obj) { object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64, @@ -283,6 +303,13 @@ static void aarch64_cpu_initfn(Object *obj) "Set on/off to enable/disable aarch64 " "execution state ", NULL); +#ifdef CONFIG_USER_ONLY + object_property_add_bool(obj, "fp16", aarch64_cpu_get_fp16, + aarch64_cpu_set_fp16, NULL); + object_property_set_description(obj, "fp16", + "Set on/off to enable/disable FP16 extensions ", + NULL); +#endif } static void aarch64_cpu_finalizefn(Object *obj) From patchwork Thu Feb 8 17:31:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127698 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1717806ljc; Thu, 8 Feb 2018 09:49:21 -0800 (PST) X-Google-Smtp-Source: AH8x224S3X+9jrLLAEZtO9Xb2q2E3INix3D2UK6hBkDX//PW/06rvROW7aSi4ITw57TvZq7ZTHru X-Received: by 10.37.128.65 with SMTP id a1mr18461ybn.86.1518112161553; Thu, 08 Feb 2018 09:49:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112161; cv=none; d=google.com; s=arc-20160816; b=H/RMizHWk9+oe+9RhUECgnhnAPVnD97FJCsnc4WdhpOAUMwd79uYPYzbKSeVjZ8mPj OxqW9xwxVnzSH17YqecLPqZ69Oawr+UFnln+UkBlCN0PYjPXBYGJnqgLXoIQVFJMS3l5 L0z9M75J75i+hzEPBfk1wAoDqSTF5KY9Yzo7EZ8quRm7Nwm2cu4ES8fGX6llJPeEA5kZ at9F8jyclN/BLqC9hypMpE9hmp5e+AKijnuXj3ZFQQ0RpalkPtzgV92ORdr2FttuvAhI j+sC0dnCeM108CxRKCOaSd/cUDRB6cJAK4bgOQDdFASjLBJLs3xvb4qStEI12qgt2T1x H4+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=EsR2R0f03CvTKrIkus5/9uYgewPBltPoiGfpRXEhMig=; b=nXn8XGEsehs9ai6Al2ogHMwFeXs83M7ImI2y/hMedjQ1i8LPePeqhQdTZm4c8n1EHJ Cm4CGofMtAgfEHtylh2hkfieAJOQVjNWUaSML2XTaAoMpQTdxT22ZiSt6bqjVT/b510d pT40FRL7FEWibiThPQi8ya+fFvHtHTbUJ1pTYn9rZVblc3+NRJdXTIcZK9dTrYZyjflE vazNXbeADHs8M8U8WLSMijDcvF4GdXtKj8pXlDPL5PoOxL0BXZXmmvRZAjYjtm6iSaVn Vcndny9lrj1ruEj3Corhyou7mimrGd+9y5gPhkHgWoH0rpmXiX09k33IsaN4ncNGrRVZ 5ukg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YJtZIyTU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v2 04/32] target/arm/cpu.h: update comment for half-precision values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) -- 2.15.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c793250186..f976969011 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -486,6 +486,7 @@ typedef struct CPUARMState { * Qn = regs[2n+1]:regs[2n] * Dn = regs[2n] * Sn = regs[2n] bits 31..0 + * Hn = regs[2n] bits 15..0 for even n, and bits 31..16 for odd n * This corresponds to the architecturally defined mapping between * the two execution states, and means we do not need to explicitly * map these registers when changing states. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 05/32] target/arm/cpu.h: add additional float_status flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 22 +++++++++++++------ target/arm/helper.c | 12 +++++++++-- target/arm/translate-a64.c | 53 +++++++++++++++++++++++++--------------------- 3 files changed, 55 insertions(+), 32 deletions(-) -- 2.15.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f976969011..97c9352a0f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -501,19 +501,29 @@ typedef struct CPUARMState { /* scratch space when Tn are not sufficient. */ uint32_t scratch[8]; - /* fp_status is the "normal" fp status. standard_fp_status retains - * values corresponding to the ARM "Standard FPSCR Value", ie - * default-NaN, flush-to-zero, round-to-nearest and is used by - * any operations (generally Neon) which the architecture defines - * as controlled by the standard FPSCR value rather than the FPSCR. + /* There are a number of distinct float control structures: + * + * fp_status: is the "normal" fp status. + * fp_status_fp16: used for half-precision calculations + * standard_fp_status : the ARM "Standard FPSCR Value" + * + * Half-precision operations are governed by a separate + * flush-to-zero control bit in FPSCR:FZ16. We pass a separate + * status structure to control this. + * + * The "Standard FPSCR", ie default-NaN, flush-to-zero, + * round-to-nearest and is used by any operations (generally + * Neon) which the architecture defines as controlled by the + * standard FPSCR value rather than the FPSCR. * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the two fp statuses. This relies on the + * OR of the flags in the three fp statuses. This relies on the * only thing which needs to read the exception flags being * an explicit FPSCR read. */ float_status fp_status; + float_status fp_status_f16; float_status standard_fp_status; } vfp; uint64_t exclusive_addr; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4ef99882c4..1cc3d43a9f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10692,6 +10692,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_stride << 20); i = get_float_exception_flags(&env->vfp.fp_status); i |= get_float_exception_flags(&env->vfp.standard_fp_status); + i |= get_float_exception_flags(&env->vfp.fp_status_f16); fpscr |= vfp_exceptbits_from_host(i); return fpscr; } @@ -10750,15 +10751,22 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) } set_float_rounding_mode(i, &env->vfp.fp_status); } - if (changed & (1 << 24)) { + if (changed & (1 << 19)) { /* FPCR:FZ16 */ + set_flush_to_zero((val & (1 << 19)) != 0, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero((val & (1 << 19)) != 0, + &env->vfp.fp_status_f16); + } + if (changed & (1 << 24)) { /* FPCR:FZ */ set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); } - if (changed & (1 << 25)) + if (changed & (1 << 25)) { /* FPCR:DN */ set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); + } i = vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(i, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index eed64c73e5..1afa669e6e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -604,16 +604,21 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) tcg_temp_free_i64(tmp); } -static TCGv_ptr get_fpstatus_ptr(void) +static TCGv_ptr get_fpstatus_ptr(bool is_f16) { TCGv_ptr statusptr = tcg_temp_new_ptr(); int offset; - /* In A64 all instructions (both FP and Neon) use the FPCR; - * there is no equivalent of the A32 Neon "standard FPSCR value" - * and all operations use vfp.fp_status. + /* In A64 all instructions (both FP and Neon) use the FPCR; there + * is no equivalent of the A32 Neon "standard FPSCR value". + * However half-precision operations operate under a different + * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. */ - offset = offsetof(CPUARMState, vfp.fp_status); + if (is_f16) { + offset = offsetof(CPUARMState, vfp.fp_status_f16); + } else { + offset = offsetof(CPUARMState, vfp.fp_status); + } tcg_gen_addi_ptr(statusptr, cpu_env, offset); return statusptr; } @@ -4335,7 +4340,7 @@ static void handle_fp_compare(DisasContext *s, bool is_double, bool cmp_with_zero, bool signal_all_nans) { TCGv_i64 tcg_flags = tcg_temp_new_i64(); - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); if (is_double) { TCGv_i64 tcg_vn, tcg_vm; @@ -4510,7 +4515,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) TCGv_i32 tcg_op; TCGv_i32 tcg_res; - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); tcg_op = read_fp_sreg(s, rn); tcg_res = tcg_temp_new_i32(); @@ -4566,7 +4571,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) TCGv_i64 tcg_op; TCGv_i64 tcg_res; - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); tcg_op = read_fp_dreg(s, rn); tcg_res = tcg_temp_new_i64(); @@ -4749,7 +4754,7 @@ static void handle_fp_2src_single(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i32(); - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -4802,7 +4807,7 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i64(); - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -4888,7 +4893,7 @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, { TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res = tcg_temp_new_i32(); - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -4926,7 +4931,7 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, { TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res = tcg_temp_new_i64(); - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -5067,7 +5072,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift; - tcg_fpstatus = get_fpstatus_ptr(); + tcg_fpstatus = get_fpstatus_ptr(false); tcg_shift = tcg_const_i32(64 - scale); @@ -5779,7 +5784,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); assert(esize == 32); assert(elements == 4); @@ -6314,7 +6319,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) } size = extract32(size, 0, 1) ? 3 : 2; - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); break; default: unallocated_encoding(s); @@ -6824,7 +6829,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, int fracbits, int size) { bool is_double = size == 3 ? true : false; - TCGv_ptr tcg_fpst = get_fpstatus_ptr(); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); TCGv_i32 tcg_shift = tcg_const_i32(fracbits); TCGv_i64 tcg_int = tcg_temp_new_i64(); TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); @@ -6942,7 +6947,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus = get_fpstatus_ptr(); + tcg_fpstatus = get_fpstatus_ptr(false); tcg_shift = tcg_const_i32(fracbits); if (is_double) { @@ -7271,7 +7276,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements, int fpopcode, int rd, int rn, int rm) { int pass; - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); for (pass = 0; pass < elements; pass++) { if (size) { @@ -7738,7 +7743,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, return; } - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(); @@ -7847,7 +7852,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, int size, int rn, int rd) { bool is_double = (size == 3); - TCGv_ptr fpst = get_fpstatus_ptr(); + TCGv_ptr fpst = get_fpstatus_ptr(false); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(); @@ -8258,7 +8263,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) if (is_fcvt) { tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); - tcg_fpstatus = get_fpstatus_ptr(); + tcg_fpstatus = get_fpstatus_ptr(false); } else { tcg_rmode = NULL; tcg_fpstatus = NULL; @@ -9187,7 +9192,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, /* Floating point operations need fpst */ if (opcode >= 0x58) { - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); } else { fpst = NULL; } @@ -10245,7 +10250,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } if (need_fpstatus) { - tcg_fpstatus = get_fpstatus_ptr(); + tcg_fpstatus = get_fpstatus_ptr(false); } else { tcg_fpstatus = NULL; } @@ -10612,7 +10617,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - fpst = get_fpstatus_ptr(); + fpst = get_fpstatus_ptr(false); } else { fpst = NULL; } From patchwork Thu Feb 8 17:31:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127689 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1707538ljc; Thu, 8 Feb 2018 09:36:41 -0800 (PST) X-Google-Smtp-Source: AH8x2273lYIytyRvAx6C2kz/+OjrQzyfqdmSyFBBLN2DxUkhtHu+Rsav445DcdBaWRceV7Z7pW2K X-Received: by 10.37.224.87 with SMTP id x84mr1088531ybg.419.1518111400918; Thu, 08 Feb 2018 09:36:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518111400; cv=none; d=google.com; s=arc-20160816; b=iooy6z4ARUcY5zley1igptGmtzGRnh1VZ+19U0aCWfF+WgKZFeeqYHgAQV4HKeE5tR 08PS5SM7kw+vhNumvExNgyht+ppieoYG443DHLiQiSk4LGNBVOMAS1biSZu/5juqSFic cszRaxBIvbWvZ4tBew+woy3q+ICbjR8MJPK4GTOf3Q1O/VgAUtHN+BUQR7g/b0HrHISA txLI4xGArLUVZD903VtDphdRqvsv2RKwhFJoOntM3DdhIUq5fG2HE58w4lMS5RUmduXg 38w0AaUgkXdhB2mtVClOKnrT0P8NoKp/s56KAMxtWOsDtW3W6SXXDC+0ua6xl/HjhXGV LoeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=ml/xvzIbPv19eJLYkntnj7Z+EVoNUja0LWh7WSz6jhY=; b=NycOjHRhVXwV4Vk+1R5OTFBWaE3y1wK54Xz87OZBTkzZIRPt0lsZu4rNAR0bclTFkI fZBxH6t/Kq9KfOlKoNQo7oC1ErlkprzzsITEFsGDs1XrOYyULkHyQzMzQ36Nn1JX9bev ckJhQwgi/F/T4Q+N8o3Keh3zDx1Bw49NYmOCObuCq/J+M+QzYkv+C+orJfSFU8zSfWTZ f/M0azGPFsU9tEwR4LXTe/lixdNaQNVjN0HTRVrjFXk1rTHA+tMYjlW/+Tdi+GqAgdmp N84z2bk0pfpyWAh7jcPrKwCiM00teM1D6ilUolX80fLiHVLzBG0wc4QswUbrD40mL+5R xsZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GGSFp8/H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 06/32] target/arm/helper: pass explicit fpst to set_rmode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As the rounding mode is now split between FP16 and the rest of floating point we need to be explicit when tweaking it. Instead of passing the CPU env we now pass the appropriate fpst pointer directly. Signed-off-by: Alex Bennée --- target/arm/helper.c | 4 ++-- target/arm/helper.h | 2 +- target/arm/translate-a64.c | 26 +++++++++++++------------- target/arm/translate.c | 12 ++++++------ 4 files changed, 22 insertions(+), 22 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 1cc3d43a9f..72522c125c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10974,9 +10974,9 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) /* Set the current fp rounding mode and return the old one. * The argument is a softfloat float_round_ value. */ -uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env) +uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp) { - float_status *fp_status = &env->vfp.fp_status; + float_status *fp_status = fpstp; uint32_t prev_rmode = get_float_rounding_mode(fp_status); set_float_rounding_mode(rmode, fp_status); diff --git a/target/arm/helper.h b/target/arm/helper.h index 5dec2e6262..40dcd74cfd 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -167,7 +167,7 @@ DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) -DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, env) +DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) DEF_HELPER_2(vfp_fcvt_f16_to_f32, f32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1afa669e6e..531ac5999c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4540,10 +4540,10 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) { TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tcg_res, tcg_op, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -4596,10 +4596,10 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) { TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tcg_res, tcg_op, fpst); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); break; } @@ -5126,7 +5126,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); if (is_double) { TCGv_i64 tcg_double = read_fp_dreg(s, rn); @@ -5173,7 +5173,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, tcg_temp_free_i32(tcg_single); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); if (!sf) { @@ -6946,8 +6946,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, assert(!(is_scalar && is_q)); tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus = get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_shift = tcg_const_i32(fracbits); if (is_double) { @@ -6993,7 +6993,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_shift); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } @@ -8262,8 +8262,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) if (is_fcvt) { tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); tcg_fpstatus = get_fpstatus_ptr(false); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode = NULL; tcg_fpstatus = NULL; @@ -8328,7 +8328,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) } if (is_fcvt) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(tcg_fpstatus); } @@ -10249,14 +10249,14 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) return; } - if (need_fpstatus) { + if (need_fpstatus || need_rmode) { tcg_fpstatus = get_fpstatus_ptr(false); } else { tcg_fpstatus = NULL; } if (need_rmode) { tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); } else { tcg_rmode = NULL; } @@ -10485,7 +10485,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } if (need_rmode) { - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); } if (need_fpstatus) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 55826b7e5a..9aee67f067 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3144,7 +3144,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, TCGv_i32 tcg_rmode; tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { TCGv_i64 tcg_op; @@ -3168,7 +3168,7 @@ static int handle_vrint(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_res); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(fpst); @@ -3185,7 +3185,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, tcg_shift = tcg_const_i32(0); tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding)); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { TCGv_i64 tcg_double, tcg_res; @@ -3223,7 +3223,7 @@ static int handle_vcvt(uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp, tcg_temp_free_i32(tcg_single); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_i32(tcg_shift); @@ -3893,13 +3893,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) TCGv_ptr fpst = get_fpstatus_ptr(0); TCGv_i32 tcg_rmode; tcg_rmode = tcg_const_i32(float_round_to_zero); - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); if (dp) { gen_helper_rintd(cpu_F0d, cpu_F0d, fpst); } else { gen_helper_rints(cpu_F0s, cpu_F0s, fpst); } - gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_ptr(fpst); break; From patchwork Thu Feb 8 17:31:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127694 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1713181ljc; Thu, 8 Feb 2018 09:43:46 -0800 (PST) X-Google-Smtp-Source: AH8x225sm3HrOKWRNgL4TUIPkqo5VBOom7qBLaJX8l2m7qPJID3+5iU5JDEMLgWUDRI2S6vMgiRz X-Received: by 10.37.232.15 with SMTP id k15mr1179138ybd.47.1518111826058; Thu, 08 Feb 2018 09:43:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518111826; cv=none; d=google.com; s=arc-20160816; b=Zo5kAuAtCoKShKhuUnsnxcmlmjnCl8FnUYbo3goSZYH2aPK8sl9tJZID3G8CWzAXzQ lrFCNDBQ3a/ZPr7e1U6pDOzu8bBZHMebAy0EDH0KSr84uFO4m0JBEMCnPMaVOTPKtb4E Qd0aPQ7Co6hG+sFInf8vtrbt+BgQmjArhgR6uOSDFDQMQIkZ6B+TnkaaJQ993Qos5RD8 cW/vzgYvvpqr6TPOQ/lRNEr5QYdKmaBzdGaEi+MO8KjV3oiTSX7Gyelp0T/3MW4PUDXZ 6aZj10cm0AfmkqfJUbb6irbl/AQ8pMnfwye42J1jM/Hs/LF44MOhyFAnFvOOJQuhl3uo V5eQ== ARC-Message-Signature: i=1; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 07/32] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This implements the half-precision variants of the across vector reduction operations. This involves a re-factor of the reduction code which more closely matches the ARM ARM order (and handles 8 element reductions). Signed-off-by: Alex Bennée -- v1 - dropped the advsimd_2a stuff v2 - fixed up checkpatch --- target/arm/helper-a64.c | 18 ++++++ target/arm/helper-a64.h | 4 ++ target/arm/translate-a64.c | 144 ++++++++++++++++++++++++++++----------------- 3 files changed, 111 insertions(+), 55 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 10e08bdc1f..fddd5d242b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -572,3 +572,21 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, { return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC()); } + +/* + * AdvSIMD half-precision + */ + +#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) + +#define ADVSIMD_HALFOP(name) \ +float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ +{ \ + float_status *fpst = fpstp; \ + return float16_ ## name(a, b, fpst); \ +} + +ADVSIMD_HALFOP(min) +ADVSIMD_HALFOP(max) +ADVSIMD_HALFOP(minnum) +ADVSIMD_HALFOP(maxnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 85d86741db..b69a557241 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -48,3 +48,7 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 531ac5999c..f778886abc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5650,26 +5650,75 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_resh); } -static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2, - int opc, bool is_min, TCGv_ptr fpst) -{ - /* Helper function for disas_simd_across_lanes: do a single precision - * min/max operation on the specified two inputs, - * and return the result in tcg_elt1. - */ - if (opc == 0xc) { - if (is_min) { - gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } +/* + * do_reduction_op helper + * + * This mirrors the Reduce() pseudocode in the ARM ARM. It is + * important for correct NaN propagation that we do these + * operations in exactly the order specified by the pseudocode. + * + * This is a recursive function, TCG temps should be freed by the + * calling function once it is done with the values. + */ +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn, + int esize, int size, int vmap, TCGv_ptr fpst) +{ + if (esize == size) { + int element; + TCGMemOp msize = esize == 16 ? MO_16 : MO_32; + TCGv_i32 tcg_elem; + + /* We should have one register left here */ + assert(ctpop8(vmap) == 1); + element = ctz32(vmap); + assert(element < 8); + + tcg_elem = tcg_temp_new_i32(); + read_vec_element_i32(s, tcg_elem, rn, element, msize); + return tcg_elem; } else { - assert(opc == 0xf); - if (is_min) { - gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst); - } else { - gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst); + int bits = size / 2; + int shift = ctpop8(vmap) / 2; + int vmap_lo = (vmap >> shift) & vmap; + int vmap_hi = (vmap & ~vmap_lo); + TCGv_i32 tcg_hi, tcg_lo, tcg_res; + + tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst); + tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst); + tcg_res = tcg_temp_new_i32(); + + switch (fpopcode) { + case 0x0c: /* fmaxnmv half-precision */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x0f: /* fmaxv half-precision */ + gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1c: /* fminnmv half-precision */ + gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x1f: /* fminv half-precision */ + gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2c: /* fmaxnmv */ + gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x2f: /* fmaxv */ + gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3c: /* fminnmv */ + gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst); + break; + case 0x3f: /* fminv */ + gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst); + break; + default: + g_assert_not_reached(); } + + tcg_temp_free_i32(tcg_hi); + tcg_temp_free_i32(tcg_lo); + return tcg_res; } } @@ -5711,16 +5760,21 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) break; case 0xc: /* FMAXNMV, FMINNMV */ case 0xf: /* FMAXV, FMINV */ - if (!is_u || !is_q || extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - /* Bit 1 of size field encodes min vs max, and actual size is always - * 32 bits: adjust the size variable so following code can rely on it + /* Bit 1 of size field encodes min vs max and the actual size + * depends on the encoding of the U bit. If not set (and FP16 + * enabled) then we do half-precision float instead of single + * precision. */ is_min = extract32(size, 1, 1); is_fp = true; - size = 2; + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + size = 1; + } else if (!is_u || !is_q || extract32(size, 0, 1)) { + unallocated_encoding(s); + return; + } else { + size = 2; + } break; default: unallocated_encoding(s); @@ -5777,38 +5831,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) } } else { - /* Floating point ops which work on 32 bit (single) intermediates. + /* Floating point vector reduction ops which work across 32 + * bit (single) or 16 bit (half-precision) intermediates. * Note that correct NaN propagation requires that we do these * operations in exactly the order specified by the pseudocode. */ - TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); - TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); - TCGv_ptr fpst = get_fpstatus_ptr(false); - - assert(esize == 32); - assert(elements == 4); - - read_vec_element(s, tcg_elt, rn, 0, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt); - read_vec_element(s, tcg_elt, rn, 1, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - read_vec_element(s, tcg_elt, rn, 2, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt); - read_vec_element(s, tcg_elt, rn, 3, MO_32); - tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt); - - do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst); - - do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst); - - tcg_gen_extu_i32_i64(tcg_res, tcg_elt1); - tcg_temp_free_i32(tcg_elt1); - tcg_temp_free_i32(tcg_elt2); - tcg_temp_free_i32(tcg_elt3); + TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16); + int fpopcode = opcode | is_min << 4 | is_u << 5; + int vmap = (1 << elements) - 1; + TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize, + (is_q ? 128 : 64), vmap, fpst); + tcg_gen_extu_i32_i64(tcg_res, tcg_res32); + tcg_temp_free_i32(tcg_res32); tcg_temp_free_ptr(fpst); } @@ -5930,7 +5964,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn, { int size = ctz32(imm5); int esize = 8 << size; - int elements = (is_q ? 128 : 64)/esize; + int elements = (is_q ? 128 : 64) / esize; int i = 0; if (size > 3 || ((size == 3) && !is_q)) { From patchwork Thu Feb 8 17:31:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127695 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1714108ljc; Thu, 8 Feb 2018 09:44:51 -0800 (PST) X-Google-Smtp-Source: AH8x224s7rzmMwWlJZnh8LdDY++qY0DPcJ1gpCu5SBNj0o6ANipoCS/VdmfairvRlYCUHwFYfC4e X-Received: by 10.13.243.3 with SMTP id c3mr1177036ywf.336.1518111891582; Thu, 08 Feb 2018 09:44:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518111891; cv=none; d=google.com; s=arc-20160816; b=taUTTCBh273yVMB+Hb70eRhQQBvIARkRsXVB4YPWRnJanyIpHv2ary1H4QopZ8KXNt 0PNOhKOQpI/JXRJXc+zuN0npUH/h5i2+fVtr/dgQWvhl78KLbcH0EWjCAHYKuIlBJZ7H fl3/WvNz98vJDJ8QNJIWgEZ6Q9diqKRASatYZfT20FdZso7XiJMRO/b2vYXtyu1FYHTI ba6Snb5xXqrdc+dAAzQEaNC3Bcuu226fiQoN0JFEkKOWaD6zLiUHefoDab5YaAG+J5uz KxN+/uTTvSbWhe8U+/G77AzUZ9HRoann2P502hIADp8DT3i792g1YI9fXf5PNwWdCp4P meqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=x9Q2KKQTJwkBoKeX/kIza6UViZCasN3eUcXN2Atlxd8=; b=WClhUxkp77h8tB9vzg2l9lQmmSToCkzWhucfnzSQ+Q/24B/CNy8zYcEm37NExayCkx 30QXlgLiMSWMphhDOTIK2fL/6+dTrmBL//IcV5JiZz14t1DBl2n5ifmElxmcdBtQisNB 3gtZWJ4FYOc6Xdbseda1aOhJGyryHo8FbrUhlzeit7vicJmUK9fqGdBKUYN7rZabAyy3 P4aSMSbFGDKFgHcGpipEOWU/EZE8dkEb6Aif6WjDwPSZ9+hvGeB1hfmHQ7n5CLnC/4Mz /fXWlINHfjg87x25dMjGu4P0DFr5XB/KH+xVvdnzoMSYVjX2izXrjAsX+Rz344hM1AVv QBUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZNPrKDOM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 08/32] arm/translate-a64: handle_3same_64 comment fix X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do implement all the opcodes. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f778886abc..2dd958c0e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7220,8 +7220,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, /* Handle 64x64->64 opcodes which are shared between the scalar * and vector 3-same groups. We cover every opcode where size == 3 * is valid in either the three-reg-same (integer, not pairwise) - * or scalar-three-reg-same groups. (Some opcodes are not yet - * implemented.) + * or scalar-three-reg-same groups. */ TCGCond cond; From patchwork Thu Feb 8 17:31:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127708 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1729689ljc; Thu, 8 Feb 2018 10:03:21 -0800 (PST) X-Google-Smtp-Source: AH8x226WX8S68ZehR0/0S9DsJyKbMMZ/UQL+vviUonV0vuYg0dw+kSTDQbzGTEWJOULO0q3fTAgu X-Received: by 10.37.99.194 with SMTP id x185mr7571ybb.471.1518113001758; Thu, 08 Feb 2018 10:03:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518113001; cv=none; d=google.com; s=arc-20160816; b=nzhZH/77UlY91na8Xiqm02hBeQHwGretziqtHykuZxp10d1YrhEsxhBkzYDAD/O+Gk dqNbWV18Kc97HACUsDBrM8OGqBkQtUsJ/mDMXQSHoyqk73DznSXqJTr+GRWpgfnrQzIk nm5PKDzrlt/zryxQ08GFFJnNmsK4pTwh66VJ4t/ezGMbDl7t+MaHg0LLRIPYGsz0qUXs meI8++/N0vlKO3O7a5+myUgWmSTDpVTK6qbt/mNrSXTEsimpRxW6iD2h63LgtkAD32yu sxBtbnW2iIe+RKAL4I/dD5G66c7vrO7YAaubvufn60FdWv1bwLos4o70H8D8T2m43zn8 +8nA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=BVeImd1OiYsSaUNnIN2vG509/0i0QwAcJu2NtStwtTo=; b=X0q94GrELDBBoWmpBkPb4v8zYlJpp5f94X5B8xVUKPwOcKpnYV+IadAOfpiIGaQHsU bgOFWP2/jHpgG3RVpGP+Y43MxCDRHF5RDc3DnXljTjEYUR0l9B9K/P0haN9msjQaf1UM SLZXXihYRsqZGInUOxds2qvHHCD2mnCKlzgT1qJGwyR8CMnpiurNqV7RfXuBl2WYPuYj zgaafu1P0oWAEXzVcIvuIxz8FscFe7s/Y9afLRUxwTD5c3a4E6G7fxWxF6PFJqOtDaC6 DEhrQrpFvi6JfRFEQyQCgS9vEzDQ0vTqqoMGYTevgbZWhcdd3AUuxchvkYSqM9rn+7Wh i22A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NxSZaYMX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id k6si86528ywl.208.2018.02.08.10.03.21 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Feb 2018 10:03:21 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NxSZaYMX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57993 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejqXZ-0005ZH-4y for patch@linaro.org; Thu, 08 Feb 2018 13:03:21 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54300) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ejq3R-0003OH-8I for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ejq3O-0006iG-Ra for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:13 -0500 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:52929) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ejq3O-0006h7-JW for qemu-devel@nongnu.org; Thu, 08 Feb 2018 12:32:10 -0500 Received: by mail-wm0-x242.google.com with SMTP id g1so10887196wmg.2 for ; Thu, 08 Feb 2018 09:32:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BVeImd1OiYsSaUNnIN2vG509/0i0QwAcJu2NtStwtTo=; b=NxSZaYMXe7rCiWKDXY5IgI80aahpZZd7xcUaEWyu1sgrvHS3oZuSq86jSUJa5DJs6w 11P3Pm5P8aqkJc2xDsoQyqNz8pRGVHW9yYXyH/8Nex/lagNfLrNiGusZBRzerDCtxiZ3 UkdydtPq1SWL7qfZw1oQgWG3irGSUc31GPt1A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BVeImd1OiYsSaUNnIN2vG509/0i0QwAcJu2NtStwtTo=; b=bptYzq8MRS4UK6F4KgBQhr8P3t+p+tK/t85ZMZhePBtq0DlJB5SQ38ZMYcMSHP9jXj VP8YJLU9LHY5d69dl+IjVy14s2sRLPpYkZygZXNu9YY9oMsqrNeup4hqRNML0C5zga1A aKM0kQb9+5mwGet7D2WAmiIae4qVLv4LjCU0Z8NB7eLKrGV2U4Hf1Svt82o8B9KDNcBA HIWIkKP4gHnvldgDNt/g12/JvULTKbyzCmjqo4leXrbvfNSkTxJxLq3y8bohGbFGn4VL x6bGXL+yQhpxugOgV+NuZlD8O3GLSwUxmAD+lpzcWNAdc4DjriO2caZ8Zo5/5BZQQ54+ teKA== X-Gm-Message-State: APf1xPDeRcPKAyBiCjWSgIcef6PlguqMiYGPqa4XMb9NIDO0/UrT6ubl oBQXuhsU99M05gTf7/fnMg6pxw== X-Received: by 10.28.124.4 with SMTP id x4mr42055wmc.84.1518111129453; Thu, 08 Feb 2018 09:32:09 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b133sm452066wmh.4.2018.02.08.09.32.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 09:32:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 67DB13E0C29; Thu, 8 Feb 2018 17:31:58 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Thu, 8 Feb 2018 17:31:34 +0000 Message-Id: <20180208173157.24705-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208173157.24705-1-alex.bennee@linaro.org> References: <20180208173157.24705-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 09/32] arm/translate-a64: initial decode for simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the initial decode skeleton for the Advanced SIMD three same instruction group. The fprintf is purely to aid debugging as the additional instructions are added. It will be removed once the group is complete. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2dd958c0e7..5392f83794 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9794,6 +9794,82 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn) } } +/* + * Advanced SIMD three same (ARMv8.2 FP16 variants) + * + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +---+---+---+-----------+---------+------+-----+--------+---+------+------+ + * + * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE + * (register), FACGE, FABD, FCMGT (register) and FACGT. + * + */ +static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int opcode, fpopcode; + int is_q, u, a, rm, rn, rd; + int datasize, elements; + int pass; + TCGv_ptr fpst; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + /* For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + opcode = extract32(insn, 11, 3); + u = extract32(insn, 29, 1); + a = extract32(insn, 23, 1); + is_q = extract32(insn, 30, 1); + rm = extract32(insn, 16, 5); + rn = extract32(insn, 5, 5); + rd = extract32(insn, 0, 5); + + fpopcode = opcode | (a << 3) | (u << 4); + datasize = is_q ? 128 : 64; + elements = datasize / 16; + + fpst = get_fpstatus_ptr(true); + + for (pass = 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 = tcg_temp_new_i32(); + TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } + + tcg_temp_free_ptr(fpst); + + if (!is_q) { + /* non-quad vector op */ + clear_vec_high(s, rd); + } + +} + static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q, int size, int rn, int rd) { @@ -11199,6 +11275,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x4e280800, 0xff3e0c00, disas_crypto_aes }, { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, + { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Thu Feb 8 17:31:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127700 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1720378ljc; Thu, 8 Feb 2018 09:52:50 -0800 (PST) X-Google-Smtp-Source: AH8x2270Sym50Pd2UIZCpf6l27SDzea6RTVs42BS6dJr2TNypUCjZ26+DgAMype5JkVctVkXRFP5 X-Received: by 10.129.98.11 with SMTP id w11mr1180618ywb.381.1518112370495; Thu, 08 Feb 2018 09:52:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112370; cv=none; d=google.com; s=arc-20160816; b=jBxs7POVssNxWb88JYF4vqdWwoqCEHIsLaGOghqwjXU30bzKrsQPJnrC/Z/bO3G4Ww guJ/nYbVIgGmu6wVI1pxc0ST48QFyFW60Ka4NdfZqYtrB3k7kjqWNywp9LogDEUq9dLE rOyWqqmdD1ccfBDUdGheZypWsU59n0RZGQsVwVZwoUb5XO9Cs1PYkd9ccYQtM4dkJKgB lcMG7L+R7kM8IXDh39qkrR5fUlv/ktmCmQloBTb5VRDz0euEs5PWLKEid5IJdNMQFSG4 H3tXPLbN3FThmRV9Xo4vWtOMT6SYJIIv+PQtpqa4ilRnGHIHHVQc7kCuf70SaKEqrHiX 2NTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=8VX9dcj5SDXqsy9Xk2a6HEzG2IT5aonwQLMSFdmdXWM=; b=zti2QADSh0obtcame8tInGtYLKHZ2wrxHhCvBvcVtZcOg86fUNYUJhTeiuBoMYMVsF /6FdHUj+Em7skzC1sHQL0aHRGDhj19rLzjSwb4gooHbQBy/c3S9qw1eW4UC6YOj0HJg0 hBKe85a5HtcQMjVNi9GqBlWNCTKLWMaIoREB8nqZ06BsHhNNtavoYNhdWDfjlFYaHWbz pBiv02TfdUfgvE8HwHY+BxWaR9Abk1rh/wVb+xSoHa6jcmAnKK4H46x53vlOuXhBBp56 B80VhPcY5p+4hk6od5TUM1Vmol2ZcXPhclh/rh5ZN8bjIi2+/S8zPiqatw6ivrRQrBpP xA8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Q6yZ7ueR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 10/32] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The fprintf is only there for debugging as the skeleton is added to, it will be removed once the skeleton is complete. Signed-off-by: Alex Bennée --- v2 - add absh helper - fix checkpatch violation --- target/arm/helper-a64.c | 9 +++++++++ target/arm/helper-a64.h | 5 +++++ target/arm/translate-a64.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index fddd5d242b..25e45121af 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -579,6 +579,11 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, #define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix)) +float16 ADVSIMD_HELPER(abs, h) (float16 a) +{ + return float16_abs(a); +} + #define ADVSIMD_HALFOP(name) \ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ { \ @@ -586,6 +591,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \ return float16_ ## name(a, b, fpst); \ } +ADVSIMD_HALFOP(add) +ADVSIMD_HALFOP(sub) +ADVSIMD_HALFOP(mul) +ADVSIMD_HALFOP(div) ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b69a557241..5cbabcc27a 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -48,6 +48,11 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_1(advsimd_absh, f16, f16) +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5392f83794..93d71d8b2c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9849,6 +9849,34 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); switch (fpopcode) { + case 0x0: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xa: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xe: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x13: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x17: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + gen_helper_advsimd_absh(tcg_res, tcg_res); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc); 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 11/32] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++ target/arm/helper-a64.h | 5 +++++ target/arm/translate-a64.c | 15 ++++++++++++++ 3 files changed, 69 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 25e45121af..78eeda31d1 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -599,3 +599,52 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* + * Floating point comparisons produce an integer result. Softfloat + * routines return float_relation types which we convert to the 0/-1 + * Neon requires. + */ + +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 + +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare_quiet(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater || + compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + int compare = float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater || + compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + int compare = float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 5cbabcc27a..e701644ae7 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -57,3 +57,8 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 93d71d8b2c..14572f26e1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9855,6 +9855,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9870,6 +9873,12 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x17: /* FDIV */ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9877,6 +9886,12 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); gen_helper_advsimd_absh(tcg_res, tcg_res); break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 12/32] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 24 ++++++++++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 15 +++++++++++++++ 3 files changed, 41 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 78eeda31d1..bdfcac111f 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -600,6 +600,30 @@ ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) +/* Data processing - scalar floating-point and advanced SIMD */ +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + if ((float16_is_zero(a) && float16_is_infinity(b)) || + (float16_is_infinity(a) && float16_is_zero(b))) { + /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ + return make_float16((1U << 14) | + ((float16_val(a) ^ float16_val(b)) & (1U << 15))); + } + return float16_mul(a, b, fpst); +} + +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) +{ + float_status *fpst = fpstp; + return float16_muladd(a, b, c, 0, fpst); +} + /* * Floating point comparisons produce an integer result. Softfloat * routines return float_relation types which we convert to the 0/-1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index e701644ae7..7900299efd 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -57,6 +57,8 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 14572f26e1..3eec52eb34 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9852,9 +9852,17 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x0: /* FMAXNM */ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x1: /* FMLA */ + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x3: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x4: /* FCMEQ */ gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9864,6 +9872,13 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x8: /* FMINNM */ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x9: /* FMLS */ + /* As usual for ARM, separate negation for fused multiply-add */ + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0xa: /* FSUB */ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); break; From patchwork Thu Feb 8 17:31:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127707 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1728580ljc; Thu, 8 Feb 2018 10:02:19 -0800 (PST) X-Google-Smtp-Source: AH8x2272uDEOA+Eg0OqCYlrB4+Zrb90kJ3K2ZvRV/nUH7XoEzPwbjmd4KBZ5jOMgWpIhV0wei2y8 X-Received: by 10.129.89.136 with SMTP id n130mr49678ywb.120.1518112939075; Thu, 08 Feb 2018 10:02:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112939; cv=none; d=google.com; s=arc-20160816; b=NlrYY9CeA/Y/WLEiTaKh3V+ea8THMWYACJSsJafB4mc6Q/Fqq7pkDOQa6jqpcYL2tY 3lT/lJUMkufY6qs8LIV8YuC10SQu5cFMspStX+kqfAN1T66bwwdZkw7I7mp1iJ8CqaoP ozOhE1JvMEXkB8e2Vlcdpci2PIP5NOi+yX2ZhwNsv0VhHKARx1T777+pEEgvjpT7MAYi mvY66EbST07Rl2PL4DzbyErTMZEI9E39DbYwLjzDbrzU3Nj0uHRpJVN7KJHNx5mj0o4N jhtKHIj9gM6ChV2AM1uMGl46/R2ij5wPkxldYeIjph7DJL0SbyRKFIrsMRfe+RRbF0gG s01w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=pAq6OsJvcEL7YIM5ZKCSeNXORnbygdjHwbQD2LUH//E=; b=hgSfso8zRrlEN+fogXtZmfr87c00RNJS3qX5cUtJiaDwsCGXXVWJ4BzaFOrtvZsh5m wjTOJZmSv82XNb5ekV0PjmlInynVuj32pX1DLLZQ29w/vx+UFe1IqLKzQiVKRmc5OCIx WMapBY5K8Y20ZMPfpmIsFugAw9XJHhtIzfZ5cajYKzxj/WLLfTWJwOGWaUr0kKmaq/vk O42eb6ufAGZUdOx4xa2LOPCkA6edPquXUevY2Gip6tBPvF6jSI0WpkpKcqOjxh1oknvf x7WEcpRSidiXw3rQljiBN1A9StTIL+ovyDDUsBuSG6qetghFLkUiGWScvKryu/RE7Hpp a1Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a+K8mHID; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 13/32] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 42 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index bdfcac111f..6358b42472 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -192,6 +192,10 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) * versions, these do a fully fused multiply-add or * multiply-add-and-halve. */ +#define float16_two make_float16(0x4000) +#define float16_three make_float16(0x4200) +#define float16_one_point_five make_float16(0x3e00) + #define float32_two make_float32(0x40000000) #define float32_three make_float32(0x40400000) #define float32_one_point_five make_float32(0x3fc00000) @@ -200,6 +204,21 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) #define float64_three make_float64(0x4008000000000000ULL) #define float64_one_point_five make_float64(0x3FF8000000000000ULL) +float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + a = float16_chs(a); + if ((float16_is_infinity(a) && float16_is_zero(b)) || + (float16_is_infinity(b) && float16_is_zero(a))) { + return float16_two; + } + return float16_muladd(a, b, float16_two, 0, fpst); +} + float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp) { float_status *fpst = fpstp; @@ -230,6 +249,21 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp) return float64_muladd(a, b, float64_two, 0, fpst); } +float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + a = float16_chs(a); + if ((float16_is_infinity(a) && float16_is_zero(b)) || + (float16_is_infinity(b) && float16_is_zero(a))) { + return float16_one_point_five; + } + return float16_muladd(a, b, float16_three, float_muladd_halve_result, fpst); +} + float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp) { float_status *fpst = fpstp; diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7900299efd..d347f473d4 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -29,8 +29,10 @@ DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) +DEF_HELPER_FLAGS_3(recpsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) +DEF_HELPER_FLAGS_3(rsqrtsf_f16, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_1(neon_addlp_s8, TCG_CALL_NO_RWG_SE, i64, i64) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3eec52eb34..06fbf9df24 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9869,6 +9869,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x7: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x8: /* FMINNM */ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -9885,6 +9888,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0xe: /* FMIN */ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0xf: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); break; From patchwork Thu Feb 8 17:31:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127722 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1762174ljc; Thu, 8 Feb 2018 10:43:43 -0800 (PST) X-Google-Smtp-Source: AH8x225/ecjHrCDjZA4TVeqE3q+RDqgd/37mMBruhTOtFOftJa5/udAYM9VJ66dDFqFcF7c5XrAe X-Received: by 10.37.92.196 with SMTP id q187mr28199ybb.80.1518115423688; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 14/32] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 208 +++++++++++++++++++++++++++++---------------- 1 file changed, 133 insertions(+), 75 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 06fbf9df24..3a2be1e016 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -9813,6 +9813,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) int datasize, elements; int pass; TCGv_ptr fpst; + bool pairwise = false; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); @@ -9838,91 +9839,148 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) datasize = is_q ? 128 : 64; elements = datasize / 16; + switch (fpopcode) { + case 0x10: /* FMAXNMP */ + case 0x12: /* FADDP */ + case 0x16: /* FMAXP */ + case 0x18: /* FMINNMP */ + case 0x1e: /* FMINP */ + pairwise = true; + break; + } + fpst = get_fpstatus_ptr(true); - for (pass = 0; pass < elements; pass++) { + if (pairwise) { + int maxpass = is_q ? 8 : 4; TCGv_i32 tcg_op1 = tcg_temp_new_i32(); TCGv_i32 tcg_op2 = tcg_temp_new_i32(); - TCGv_i32 tcg_res = tcg_temp_new_i32(); + TCGv_i32 tcg_res[8]; - read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); - read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + for (pass = 0; pass < maxpass; pass++) { + int passreg = pass < (maxpass / 2) ? rn : rm; + int passelt = (pass << 1) & (maxpass - 1); - switch (fpopcode) { - case 0x0: /* FMAXNM */ - gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_16); - gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, - fpst); - break; - case 0x2: /* FADD */ - gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x3: /* FMULX */ - gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x4: /* FCMEQ */ - gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x6: /* FMAX */ - gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x7: /* FRECPS */ - gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x8: /* FMINNM */ - gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x9: /* FMLS */ - /* As usual for ARM, separate negation for fused multiply-add */ - tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); - read_vec_element_i32(s, tcg_res, rd, pass, MO_16); - gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, - fpst); - break; - case 0xa: /* FSUB */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xe: /* FMIN */ - gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xf: /* FRSQRTS */ - gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x13: /* FMUL */ - gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x14: /* FCMGE */ - gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x15: /* FACGE */ - gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x17: /* FDIV */ - gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1a: /* FABD */ - gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); - gen_helper_advsimd_absh(tcg_res, tcg_res); - break; - case 0x1c: /* FCMGT */ - gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x1d: /* FACGT */ - gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); - break; - default: - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", - __func__, insn, fpopcode, s->pc); - g_assert_not_reached(); + read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16); + read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16); + tcg_res[pass] = tcg_temp_new_i32(); + + switch (fpopcode) { + case 0x10: /* FMAXNMP */ + gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2, + fpst); + break; + case 0x12: /* FADDP */ + gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst); + break; + case 0x16: /* FMAXP */ + gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst); + break; + case 0x18: /* FMINNMP */ + gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2, + fpst); + break; + case 0x1e: /* FMINP */ + gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + } + + for (pass = 0; pass < maxpass; pass++) { + write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16); + tcg_temp_free_i32(tcg_res[pass]); } - write_vec_element_i32(s, tcg_res, rd, pass, MO_16); - tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_op1); tcg_temp_free_i32(tcg_op2); + + } else { + for (pass = 0; pass < elements; pass++) { + TCGv_i32 tcg_op1 = tcg_temp_new_i32(); + TCGv_i32 tcg_op2 = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, pass, MO_16); + read_vec_element_i32(s, tcg_op2, rm, pass, MO_16); + + switch (fpopcode) { + case 0x0: /* FMAXNM */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1: /* FMLA */ + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; + case 0x2: /* FADD */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x3: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x6: /* FMAX */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x7: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x8: /* FMINNM */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x9: /* FMLS */ + /* As usual for ARM, separate negation for fused multiply-add */ + tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000); + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; + case 0xa: /* FSUB */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xe: /* FMIN */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x13: /* FMUL */ + gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x17: /* FDIV */ + gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + gen_helper_advsimd_absh(tcg_res, tcg_res); + break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + } } tcg_temp_free_ptr(fpst); From patchwork Thu Feb 8 17:31:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127718 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1746102ljc; Thu, 8 Feb 2018 10:23:11 -0800 (PST) X-Google-Smtp-Source: AH8x224YRrAMuNhK82pvuINqguyPoFxDcSTWG4Zmmvq4Q1RXaI17kkRGrLtOaRoDvu5+ZCmheBCY X-Received: by 10.129.80.8 with SMTP id e8mr108890ywb.304.1518114191339; Thu, 08 Feb 2018 10:23:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518114191; cv=none; d=google.com; s=arc-20160816; b=YuLHlTKSrB8D3SH9PCr/M4QCiIDsfCaGEcJwZFX/klW9avEmkMXXvT0/f/HLL1C9IN 5tTljaJn1zc1tBGrKtr9oTRTZOSka+v6A5Zq/A9/gXustoDNAZPH701RXCfr7b0kx3SV tOUrojS00WjRbmMzuH9EKtHHt5qQY4P62Y1NuwcpgL1aa5vqniZNoB2Fhs4D9+ntkGyZ fRhv96K/b1dkTzj0T3r31FglOyz/nr27kd6zZr0jIDcH/te/OOSQL0EZPGNlbUh1KKs7 bwmrb83qlqm23K2JhZwsgp9qjEGd3mOotA994FfJpPsCSfyDDzBE5zyjXyHDXU+qFkvD fkNA== ARC-Message-Signature: i=1; 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 15/32] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The helpers use the new re-factored muladd support in SoftFloat for the float16 work. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 69 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 54 insertions(+), 15 deletions(-) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3a2be1e016..83a1fa3116 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10804,7 +10804,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } /* fall through */ case 0x9: /* FMUL, FMULX */ - if (!extract32(size, 1, 1)) { + if (size == 1 || (size < 2 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))) { unallocated_encoding(s); return; } @@ -10816,18 +10816,30 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - /* low bit of size indicates single/double */ - size = extract32(size, 0, 1) ? 3 : 2; - if (size == 2) { + /* convert insn encoded size to TCGMemOp size */ + switch (size) { + case 0: /* half-precision */ + size = MO_16; + index = h << 2 | l << 1 | m; + break; + case 2: /* single precision */ + size = MO_32; index = h << 1 | l; - } else { + rm |= (m << 4); + break; + case 3: /* double precision */ + size = MO_64; if (l || !is_q) { unallocated_encoding(s); return; } index = h; + rm |= (m << 4); + break; + default: + g_assert_not_reached(); + break; } - rm |= (m << 4); } else { switch (size) { case 1: @@ -10953,18 +10965,45 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) break; } case 0x5: /* FMLS */ - /* As usual for ARM, separate negation for fused multiply-add */ - gen_helper_vfp_negs(tcg_op, tcg_op); - /* fall through */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, MO_32); - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : MO_32); + switch (size) { + case 1: + if (opcode == 0x5) { + /* As usual for ARM, separate negation for fused multiply-add */ + tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); + } + gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + break; + case 2: + if (opcode == 0x5) { + /* As usual for ARM, separate negation for fused multiply-add */ + tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); + } + gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + break; + default: + g_assert_not_reached(); + } break; case 0x9: /* FMUL, FMULX */ - if (u) { - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); - } else { - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + switch (size) { + case 1: + if (u) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst); + } else { + g_assert_not_reached(); + } + break; + case 2: + if (u) { + gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst); + } else { + gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst); + } + break; + default: + g_assert_not_reached(); } break; case 0xc: /* SQDMULH */ From patchwork Thu Feb 8 17:31:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127721 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1757904ljc; Thu, 8 Feb 2018 10:37:55 -0800 (PST) X-Google-Smtp-Source: AH8x226treV5hpgFl7fGImV0Qj3EWBQcfHcZFH5UzZwGh6oTdxhSwtAJq6dXpDVho8L6q3V18vBx X-Received: by 10.13.211.130 with SMTP id v124mr139810ywd.476.1518115075228; Thu, 08 Feb 2018 10:37:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518115075; cv=none; d=google.com; s=arc-20160816; b=l3sBMhWrhIqEzAgp9SP7iirudgTj8OnQNadUfHTB84+WjEGX0B8PhuVSvpDuTLQHUJ ENJ1FySrRexhCwDYhq6p8FX28U6qiT6BDIWDC9r7o+jophjLI6oDSPK2XOC2abL4wxtY rp9OSJsQoo3WbPfNKsEgoRI3EEo0Fd02JCY8kWAEekxQPjnbcswbHFfHfJJvSXnkdpCO 4jhvMfw+E+xayoA7VyHbZYHrZwSzyJJf4EGdVNcpzqFz+JKBzT7XfawgnHbfetlt+BLg nBx1OQvVbtxhNH2rTTcpqQl/RY1TYKEYKlKmNq3fK6pM3m8aYEYcjnAnCxlBG1eTY1eN gz3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+gbSDJCRdq+Zc9wfQZR5pTpDA9vK2kya6rCVU185sfM=; b=KZm2fPGZX4J3OKKWpNHDucDu1VRLyut7xlzbiwiRVnRPI8fUZgXwEURZFBUaj7WD69 YT/6s07GIRAbd9YfL6/mLwxR50RJcHDPmwHXPk2oLjDFr4roVk85jTinlEE/TbSRKa3i njAimqKg3CA8mUGUcIP3EgjsDXMqS1j4iF6S1A0PuFVsP5v8hX2veqneblq60W5Ff4ap z0xu1J+WquZWck3aDDJFnPWU21Neg5u+q9GS1EBqLJhw3O9Qa4l5F1q2GwiE6TzETvKh gD+dWUaKwzPbiMY+97xAub+A/ifOvgCWkhytoas6R5lLlFOhTMUmptDfrjWOrSr2K+mA RnDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CcC03tSR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 16/32] arm/translate-a64: add FP16 x2 ops for simd_indexed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A bunch of the vectorised bitwise operations just operate on larger chunks at a time. We can do the same for the new half-precision operations by introducing some TWOHALFOP helpers which work on each half of a pair of half-precision operations at once. Hopefully all this hoop jumping will get simpler once we have generically vectorised helpers here. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/helper-a64.c | 46 +++++++++++++++++++++++++++++++++++++++++++++- target/arm/helper-a64.h | 10 ++++++++++ target/arm/translate-a64.c | 36 +++++++++++++++++++++++++++++------- 3 files changed, 84 insertions(+), 8 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 6358b42472..8f0f59ea31 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -634,8 +634,32 @@ ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) +#define ADVSIMD_TWOHALFOP(name) \ +uint32_t ADVSIMD_HELPER(name, 2h)(uint32_t two_a, uint32_t two_b, void *fpstp) \ +{ \ + float16 a1, a2, b1, b2; \ + uint32_t r1, r2; \ + float_status *fpst = fpstp; \ + a1 = extract32(two_a, 0, 16); \ + a2 = extract32(two_a, 16, 16); \ + b1 = extract32(two_b, 0, 16); \ + b2 = extract32(two_b, 16, 16); \ + r1 = float16_ ## name(a1, b1, fpst); \ + r2 = float16_ ## name(a2, b2, fpst); \ + return deposit32(r1, 16, 16, r2); \ +} + +ADVSIMD_TWOHALFOP(add) +ADVSIMD_TWOHALFOP(sub) +ADVSIMD_TWOHALFOP(mul) +ADVSIMD_TWOHALFOP(div) +ADVSIMD_TWOHALFOP(min) +ADVSIMD_TWOHALFOP(max) +ADVSIMD_TWOHALFOP(minnum) +ADVSIMD_TWOHALFOP(maxnum) + /* Data processing - scalar floating-point and advanced SIMD */ -float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +static float16 float16_mulx(float16 a, float16 b, void *fpstp) { float_status *fpst = fpstp; @@ -651,6 +675,9 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) return float16_mul(a, b, fpst); } +ADVSIMD_HALFOP(mulx) +ADVSIMD_TWOHALFOP(mulx) + /* fused multiply-accumulate */ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) { @@ -658,6 +685,23 @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) return float16_muladd(a, b, c, 0, fpst); } +uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b, + uint32_t two_c, void *fpstp) +{ + float_status *fpst = fpstp; + float16 a1, a2, b1, b2, c1, c2; + uint32_t r1, r2; + a1 = extract32(two_a, 0, 16); + a2 = extract32(two_a, 16, 16); + b1 = extract32(two_b, 0, 16); + b2 = extract32(two_b, 16, 16); + c1 = extract32(two_c, 0, 16); + c2 = extract32(two_c, 16, 16); + r1 = float16_muladd(a1, b1, c1, 0, fpst); + r2 = float16_muladd(a2, b2, c2, 0, fpst); + return deposit32(r1, 16, 16, r2); +} + /* * Floating point comparisons produce an integer result. Softfloat * routines return float_relation types which we convert to the 0/-1 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index d347f473d4..d2dd46d07b 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -61,6 +61,16 @@ DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_add2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_sub2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_mul2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_div2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_max2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_min2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_maxnum2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_minnum2h, i32, i32, i32, ptr) +DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr) +DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr) DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 83a1fa3116..f01bab801c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10966,21 +10966,31 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } case 0x5: /* FMLS */ case 0x1: /* FMLA */ - read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : MO_32); + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); switch (size) { case 1: if (opcode == 0x5) { - /* As usual for ARM, separate negation for fused multiply-add */ + /* As usual for ARM, separate negation for fused + * multiply-add. */ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000); } - gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + if (is_scalar) { + gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx, + tcg_res, fpst); + } else { + gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx, + tcg_res, fpst); + } break; case 2: if (opcode == 0x5) { - /* As usual for ARM, separate negation for fused multiply-add */ + /* As usual for ARM, separate negation for fused + * multiply-add. */ tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000); } - gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst); + gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, + tcg_res, fpst); break; default: g_assert_not_reached(); @@ -10990,9 +11000,21 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) switch (size) { case 1: if (u) { - gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst); + if (is_scalar) { + gen_helper_advsimd_mulxh(tcg_res, tcg_op, + tcg_idx, fpst); + } else { + gen_helper_advsimd_mulx2h(tcg_res, tcg_op, + tcg_idx, fpst); + } } else { - g_assert_not_reached(); + if (is_scalar) { + gen_helper_advsimd_mulh(tcg_res, tcg_op, + tcg_idx, fpst); + } else { + gen_helper_advsimd_mul2h(tcg_res, tcg_op, + tcg_idx, fpst); + } } break; case 2: From patchwork Thu Feb 8 17:31:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127705 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1726102ljc; Thu, 8 Feb 2018 10:00:30 -0800 (PST) X-Google-Smtp-Source: AH8x224SNN8PLFPwR14/DfO1f477SuwUL/Iw6whUo8EJ9RnsM9yUehSXJrIMh5+KErcTrTfSFdMW X-Received: by 10.129.138.1 with SMTP id a1mr32143ywg.272.1518112830338; Thu, 08 Feb 2018 10:00:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112830; cv=none; d=google.com; s=arc-20160816; b=iwqoR1hDN2jV1tQ+TGmx7ImJkwGKq6Z+w7O8vpATpIoiAJyp1+njcJRZNRuJUmlJ8Z PFVKoPuY/kLhbvvEsf974lG0ErpI0UjFEdHJlcX2wjziCFKVKXmDsTUladGW1eW/h1Vj NmU4S4dYICPsq7lmAx/HqmsgfBGlv4biL6TILRNoVQsiAV0MI7sfgDJ370lJ8TJ2b4qP Y6WZsrwrdaazZA/Ygs1cX0ZYITDaRYuJQzuLb/7KfUsZToT/YtQNWpQJMLy5iHTeJ2bf rk+vBte/FkbYkRwu6aUeIiIu0l/ciGKlzf9dyKYKXigdDHoIRHzW3tFI2Qkbev0BfsNa iJDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=snCIeuHwZ2Iy8TQFZjGXmC1sKFnr41Jq+ozWnLy6cyY=; b=oF8FiajnlJ1wNnIZ0DQQZpx81mzf4+NRt2SjzOuCZ0rxjgWp+ewcewJS42x0Z5mBg7 DEeMXRrO0aAOU2TEm2hqfQea+DbFWSKkxF86gb0X+NX73LV2hlW2AaBh9ScPjlUJA5/5 /uiKs+uKyynIxmnt3MVC3lfkZqDJziZpU/PMpHnPYl+Sn+NTa9UdcNWiaO0m3USht1JT 2WoE0JiFVvDPtJmpq0eA3Qr20tXgIc3jECJIsdtocJbNN6MFUzK5wVkRM7YXItHsGdG1 qcjcBoiY3hIqlE7TRKYWPhfwvid8Rt0e2g+gJtat47q7pM7VXEPspdJ5UAl52CDLuTEf zrPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XdqQv03O; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v2 17/32] arm/translate-a64: initial decode for simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This actually covers two different sections of the encoding table: Advanced SIMD scalar two-register miscellaneous FP16 Advanced SIMD two-register miscellaneous (FP16) The difference between the two is covered by a combination of Q (bit 30) and S (bit 28). Notably the FRINTx instructions are only available in the vector form. This is just the decode skeleton which will be filled out by later patches. Signed-off-by: Alex Bennée --- v2 - checkpatch cleanups --- target/arm/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f01bab801c..f939ca4d40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10724,6 +10724,45 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } } +/* AdvSIMD [scalar] two register miscellaneous (FP16) + * + * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 + * +---+---+---+---+--------+---+-------------+--------+-----+------+------+ + * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | + * +---+---+---+---+--------+---+-------------+--------+-----+------+------+ + * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 + * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 + * + * ???While the group is listed with bit 28 always set to 1 this is not + * always the case.???? + * + * This actually covers two groups, + */ +static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) +{ + int fpop, opcode, a; + + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + opcode = extract32(insn, 12, 4); + a = extract32(insn, 23, 1); + fpop = deposit32(opcode, 5, 1, a); + + switch (fpop) { + default: + fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); + g_assert_not_reached(); + } + +} + /* AdvSIMD scalar x indexed element * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+ @@ -11459,6 +11498,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha }, { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, + { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, { 0x00000000, 0x00000000, NULL } }; @@ -11472,6 +11512,8 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn) if (fn) { fn(s, insn); } else { + /* fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n", */ + /* __func__, insn, s->pc); */ unallocated_encoding(s); } } From patchwork Thu Feb 8 17:31:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127713 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1739738ljc; Thu, 8 Feb 2018 10:15:19 -0800 (PST) X-Google-Smtp-Source: AH8x226fSMbwuOqO0CclEWv66tSJvK7tL1txwc7sg6xNAzbNd+bLmllBFGPginak/lEZx0N2Djmf X-Received: by 10.129.109.133 with SMTP id i127mr74521ywc.444.1518113719727; Thu, 08 Feb 2018 10:15:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518113719; cv=none; d=google.com; s=arc-20160816; b=aR388GNSq9araxwReBHZjxIWiFJfYgJgA8umPfH2d5u/MoO+5VwT7mClXjzYzXkiHn pZLgb0LbwIh5Sz/C/JZsSSiEONfFjnt3g+P8S7D8KZSHfeYZqgf+1bFOZbI1+IRPhZJ9 z9vE0FR5YPG/Qjq9ABB4qWt2seQiBa2dYlYCBkDFnb4mTHzrTn4GrV540vJzhmZ/kzrg iRdlfttv075aRX1wcy0qJVWZOoyGZXrq41LHpEFTZPXnNzit0kk7Pn5rZCzNtdtfE5KX dEwdEoIhcGxK7u9ZSSU5r8qwWAJ3EI7RCPemevaPZmPf1hY8Fk6WT32oz9pctPuxqoU9 4ygA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=99cgG/GpcQFnGgmSDCkovT54aRp3JoFpCezaCSLAdy4=; b=vqVYs+Pbfgw9c+4AJxsUcbKsj6kpvwfS/6mr7v3LLa3MLfPUMze6jGYLTLlfyNvJ53 WmgAcEAjLU3YYchV/tR8GsUswEAJtx5yskp4EmHTCd0fBLH+phd7+fqkPf4dnMKiRUg2 Iq8hpsatq6GRRKtcFFD4U0jQkaCtNBhIskUnZM86h+8T02gVEWxrRhPJmPaVIJEVw8Ed ELTIkiw4MTgnVnQ7Aw6t13tm8xLyaASeb5tNP/tFBSCmRweh1HYLZWx2XlYVNSBAZVxH ZhxfPFcX5xSB8Ne7bsajR7sYpQI/RE27pWqr+rHEDEdXNMefy6j2DR0PnxsBVD+2dcn3 AB3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TkOGfeb9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This adds the full range of half-precision floating point to integral instructions. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 22 ++++++++ target/arm/helper-a64.h | 2 + target/arm/translate-a64.c | 136 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 148 insertions(+), 12 deletions(-) -- 2.15.1 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 8f0f59ea31..919b073635 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -750,3 +750,25 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) int compare = float16_compare(f0, f1, fpst); return ADVSIMD_CMPRES(compare == float_relation_greater); } + +/* round to integral */ +float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status) +{ + return float16_round_to_int(x, fp_status); +} + +float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) +{ + int old_flags = get_float_exception_flags(fp_status), new_flags; + float16 ret; + + ret = float16_round_to_int(x, fp_status); + + /* Suppress any inexact exceptions the conversion produced */ + if (!(old_flags & float_flag_inexact)) { + new_flags = get_float_exception_flags(fp_status); + set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status); + } + + return ret; +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index d2dd46d07b..b583bc0dd8 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -76,3 +76,5 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) +DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f939ca4d40..a0506f094f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10727,40 +10727,152 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) /* AdvSIMD [scalar] two register miscellaneous (FP16) * * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0 - * +---+---+---+---+--------+---+-------------+--------+-----+------+------+ + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd | - * +---+---+---+---+--------+---+-------------+--------+-----+------+------+ + * +---+---+---+---+---------+---+-------------+--------+-----+------+------+ * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800 * - * ???While the group is listed with bit 28 always set to 1 this is not - * always the case.???? - * - * This actually covers two groups, + * This actually covers two groups where scalar access is governed by + * bit 28. A bunch of the instructions (float to integral) only exist + * in the vector form and are un-allocated for the scalar decode. Also + * in the scalar decode Q is always 1. */ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) { - int fpop, opcode, a; + int fpop, opcode, a, u; + int rn, rd; + bool is_q; + bool is_scalar; + bool only_in_vector = false; + + int pass; + TCGv_i32 tcg_rmode = NULL; + TCGv_ptr tcg_fpstatus = NULL; + bool need_rmode = false; + int rmode; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { unallocated_encoding(s); return; } - if (!fp_access_check(s)) { - return; - } - - opcode = extract32(insn, 12, 4); + opcode = extract32(insn, 12, 5); a = extract32(insn, 23, 1); + u = extract32(insn, 29, 1); + is_scalar = extract32(insn, 28, 1); + is_q = extract32(insn, 30, 1); + fpop = deposit32(opcode, 5, 1, a); + fpop = deposit32(fpop, 6, 1, u); switch (fpop) { + case 0x18: /* FRINTN */ + need_rmode = true; + only_in_vector = true; + rmode = FPROUNDING_TIEEVEN; + break; + case 0x19: /* FRINTM */ + need_rmode = true; + only_in_vector = true; + rmode = FPROUNDING_NEGINF; + break; + case 0x38: /* FRINTP */ + need_rmode = true; + only_in_vector = true; + rmode = FPROUNDING_POSINF; + break; + case 0x39: /* FRINTZ */ + need_rmode = true; + only_in_vector = true; + rmode = FPROUNDING_ZERO; + break; + case 0x58: /* FRINTA */ + need_rmode = true; + only_in_vector = true; + rmode = FPROUNDING_TIEAWAY; + break; + case 0x59: /* FRINTX */ + case 0x79: /* FRINTI */ + only_in_vector = true; + /* current rounding mode */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); } + + /* Check additional constraints for the scalar encoding */ + if (is_scalar) { + if (!is_q) { + unallocated_encoding(s); + return; + } + /* FRINTxx is only in the vector form */ + if (only_in_vector && is_scalar) { + unallocated_encoding(s); + return; + } + } + + if (!fp_access_check(s)) { + return; + } + + if (need_fpst || need_rmode) { + tcg_fpstatus = get_fpstatus_ptr(true); + } + + if (need_rmode) { + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + } + + if (is_scalar) { + /* no operations yet */ + } else { + for (pass = 0; pass < (is_q ? 8 : 4); pass++) { + TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, pass, MO_16); + + switch (fpop) { + case 0x18: /* FRINTN */ + case 0x19: /* FRINTM */ + case 0x38: /* FRINTP */ + case 0x39: /* FRINTZ */ + case 0x58: /* FRINTA */ + case 0x79: /* FRINTI */ + gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x59: /* FRINTX */ + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + write_vec_element_i32(s, tcg_res, rd, pass, MO_16); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); + } + + if (!is_q) { + clear_vec_high(s, rd); + } + } + + if (tcg_rmode) { + gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); + tcg_temp_free_i32(tcg_rmode); + } + + if (tcg_fpstatus) { + tcg_temp_free_ptr(tcg_fpstatus); + } } /* AdvSIMD scalar x indexed element From patchwork Thu Feb 8 17:31:44 2018 Content-Type: text/plain; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 19/32] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This covers all the floating point convert operations. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 32 +++++++++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/translate-a64.c | 85 +++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 118 insertions(+), 1 deletion(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 919b073635..76f3289e37 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -772,3 +772,35 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status) return ret; } + +/* + * Half-precision floating point conversion functions + * + * There are a multitude of conversion functions with various + * different rounding modes. This is dealt with by the calling code + * setting the mode appropriately before calling the helper. + */ + +uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp) +{ + float_status *fpst = fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_int16(a, fpst); +} + +uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) +{ + float_status *fpst = fpstp; + + /* Invalid if we are passed a NaN */ + if (float16_is_any_nan(a)) { + float_raise(float_flag_invalid, fpst); + return 0; + } + return float16_to_uint16(a, fpst); +} diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index b583bc0dd8..453753f4e7 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -78,3 +78,5 @@ DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) +DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) +DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a0506f094f..0049111e6d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10797,6 +10797,46 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) only_in_vector = true; /* current rounding mode */ break; + case 0x1a: /* FCVTNS */ + need_rmode = true; + rmode = FPROUNDING_TIEEVEN; + break; + case 0x1b: /* FCVTMS */ + need_rmode = true; + rmode = FPROUNDING_NEGINF; + break; + case 0x1c: /* FCVTAS */ + need_rmode = true; + rmode = FPROUNDING_TIEAWAY; + break; + case 0x3a: /* FCVTPS */ + need_rmode = true; + rmode = FPROUNDING_POSINF; + break; + case 0x3b: /* FCVTZS */ + need_rmode = true; + rmode = FPROUNDING_ZERO; + break; + case 0x5a: /* FCVTNU */ + need_rmode = true; + rmode = FPROUNDING_TIEEVEN; + break; + case 0x5b: /* FCVTMU */ + need_rmode = true; + rmode = FPROUNDING_NEGINF; + break; + case 0x5c: /* FCVTAU */ + need_rmode = true; + rmode = FPROUNDING_TIEAWAY; + break; + case 0x7a: /* FCVTPU */ + need_rmode = true; + rmode = FPROUNDING_POSINF; + break; + case 0x7b: /* FCVTZU */ + need_rmode = true; + rmode = FPROUNDING_ZERO; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -10830,7 +10870,36 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) } if (is_scalar) { - /* no operations yet */ + TCGv_i32 tcg_op = tcg_temp_new_i32(); + TCGv_i32 tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, 0, MO_16); + + switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); + break; + default: + g_assert_not_reached(); + } + + /* limit any sign extension going on */ + tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); + write_fp_sreg(s, rd, tcg_res); + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op); } else { for (pass = 0; pass < (is_q ? 8 : 4); pass++) { TCGv_i32 tcg_op = tcg_temp_new_i32(); @@ -10839,6 +10908,20 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) read_vec_element_i32(s, tcg_op, rn, pass, MO_16); switch (fpop) { + case 0x1a: /* FCVTNS */ + case 0x1b: /* FCVTMS */ + case 0x1c: /* FCVTAS */ + case 0x3a: /* FCVTPS */ + case 0x3b: /* FCVTZS */ + gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); + break; + case 0x5a: /* FCVTNU */ + case 0x5b: /* FCVTMU */ + case 0x5c: /* FCVTAU */ + case 0x7a: /* FCVTPU */ + case 0x7b: /* FCVTZU */ + gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ From patchwork Thu Feb 8 17:31:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127699 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1719438ljc; Thu, 8 Feb 2018 09:51:36 -0800 (PST) X-Google-Smtp-Source: AH8x224NUKVzfbOSuvVhi+gJW1WG0gJ/9NTTqW1oIgEk6ke0dP6882Jtzw4MnuuP1+O8WxpqDFdX X-Received: by 10.13.246.129 with SMTP id g123mr18317ywf.124.1518112296494; Thu, 08 Feb 2018 09:51:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112296; cv=none; d=google.com; s=arc-20160816; b=gw0tdXE2OQ1a2MG8bk4ErI8oWbsHdcrxULN7NlcZzGD1RIohMLx4wq1HLZDhaZWmUm 2dP7qWIf4CnRyi2HFjiAVUo3ggn8OeYGsVLiybDDzK+5EpJsndJtZKiAfsvKQUNHqM8t QMwvyfsg+ayoxses5Bj7PoWc+vvFedxMvy2lIeN5sMsdVh2KIdrqbg3JB51uqlxeyD/k rhIrgNijeuh7UzSjEIV4Ss84PmmAVgDhFn3vN6EmxQjegPr6F/mLw1Jj1zT5cyNn5vAt Nu0PBie8p//HJ0ySAEtHLvsBlZwtN7UiHjM4fCGKsGiHQwS4QZ/J+zozCXAME6XWW1ov 5Dzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Q/okEeKREVL648D8mDlu0pgAbVXU0Y4U06Kl8Fp5ohs=; b=yMT+ZjoK2LDGH0zbH0M0QlRLkoX+9SP1LSqKjIXPBc1jkZkm/2GcDGg7lYYqDWQl6o E5/b7m3ODIP5U5z9KirI3Xu8VFhIQX8Y7hWPoGsqWmtwcfz0DecWnz2NeANG6EcTKJZU VeXixEGJPI8wzVuT7BCk3JWqDAT+oFlVG+Mgk4iC/JensMEEWR3ZEOLcqNvU6LqO/W55 Q63zUm70FDIU6bMh5ytyNGlEZ3LUExVewOYV0nDjXv1qX3YoAm312ksmG6lbgz7ea56c RyW5W+p5Cj8l4QO+xAVm77SCP+Xfb+YUuKJI18LjBDff8SoYdqXEAjKdqmr32h0x2iki /7Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a6HocgPz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 20/32] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I re-use the existing handle_2misc_fcmp_zero handler and tweak it slightly to deal with the half-precision case. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0049111e6d..0efe9ae2fc 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7769,14 +7769,14 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, bool is_scalar, bool is_u, bool is_q, int size, int rn, int rd) { - bool is_double = (size == 3); + bool is_double = (size == MO_64); TCGv_ptr fpst; if (!fp_access_check(s)) { return; } - fpst = get_fpstatus_ptr(false); + fpst = get_fpstatus_ptr(size == MO_16); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(); @@ -7828,6 +7828,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, TCGv_i32 tcg_res = tcg_temp_new_i32(); NeonGenTwoSingleOPFn *genfn; bool swap = false; + bool hp = (size == MO_16 ? true : false); int pass, maxpasses; switch (opcode) { @@ -7835,16 +7836,16 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, swap = true; /* fall through */ case 0x2c: /* FCMGT (zero) */ - genfn = gen_helper_neon_cgt_f32; + genfn = hp ? gen_helper_advsimd_cgt_f16 : gen_helper_neon_cgt_f32; break; case 0x2d: /* FCMEQ (zero) */ - genfn = gen_helper_neon_ceq_f32; + genfn = hp ? gen_helper_advsimd_ceq_f16 : gen_helper_neon_ceq_f32; break; case 0x6d: /* FCMLE (zero) */ swap = true; /* fall through */ case 0x6c: /* FCMGE (zero) */ - genfn = gen_helper_neon_cge_f32; + genfn = hp ? gen_helper_advsimd_cge_f16 : gen_helper_neon_cge_f32; break; default: g_assert_not_reached(); @@ -7853,11 +7854,11 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, if (is_scalar) { maxpasses = 1; } else { - maxpasses = is_q ? 4 : 2; + maxpasses = hp ? (is_q ? 8 : 4) : (is_q ? 4 : 2); } for (pass = 0; pass < maxpasses; pass++) { - read_vec_element_i32(s, tcg_op, rn, pass, MO_32); + read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32); if (swap) { genfn(tcg_res, tcg_zero, tcg_op, fpst); } else { @@ -7866,7 +7867,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, if (is_scalar) { write_fp_sreg(s, rd, tcg_res); } else { - write_vec_element_i32(s, tcg_res, rd, pass, MO_32); + write_vec_element_i32(s, tcg_res, rd, pass, hp ? MO_16 : MO_32); } } tcg_temp_free_i32(tcg_res); @@ -10766,7 +10767,19 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) fpop = deposit32(opcode, 5, 1, a); fpop = deposit32(fpop, 6, 1, u); + rd = extract32(insn, 0, 5); + rn = extract32(insn, 5, 5); + switch (fpop) { + break; + case 0x2c: /* FCMGT (zero) */ + case 0x2d: /* FCMEQ (zero) */ + case 0x2e: /* FCMLT (zero) */ + case 0x6c: /* FCMGE (zero) */ + case 0x6d: /* FCMLE (zero) */ + handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); + return; + break; case 0x18: /* FRINTN */ need_rmode = true; only_in_vector = true; From patchwork Thu Feb 8 17:31:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127715 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1740762ljc; Thu, 8 Feb 2018 10:16:38 -0800 (PST) X-Google-Smtp-Source: AH8x227V3wBDkumcv5DZfflLdPKkfzdyo2d1JGcIkeDiMhAdpwG/mAE/2KK+WtHXiNavOLA/V1iD X-Received: by 10.37.136.12 with SMTP id c12mr69757ybl.175.1518113797909; Thu, 08 Feb 2018 10:16:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518113797; cv=none; d=google.com; s=arc-20160816; b=iRjbI7mYSdn1D292wXVIo63V3DCjMC0SaRDgPHyrlU611UhxPvBhrr1spFeK+ZAY6U dVfR2vk1CSpQkw1gbApSWOQdNmUMsmSkG0WQ833IOAX/sRE9RyFLV8CX7sTKSZqnmvwZ kV2lxf/wC6X/80/TqiK/0blvFlPcOC0f3ynENmMDcNfCwAETCKms0S0lyI0wZvYe/xl4 Bu1XgXK+Dcr8L8YBuMC1XFZu6tcPBEAw08ZKhRMzDjDevyeykpegHbHUkatgqUjdl4Aw yy5Fzc0FPba+Aq5e59+K2GrLTtGE5R6D5YU6D1lQYm9DbqFDVT8MPsH6RUt0SukFH7bf 5y2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0OgJyoO8L3UXs/fohml3rn6pIJLet0AbBMYfSYMBQeg=; b=lgwMpncTCzjIuxfkLjt9dQk9usCPFa9F3VwoV/88ExXMdPE3PlPaUpPA1D81XrVWN6 nKsLE1ArUKM/ZKleUfeyzGIn6FkPjusCXqGO0JcjN9AVG30u3XI9J562vbtOqyvA/0vl OgGKSwfeSfBTLTUVYnL9TvJwn1TfU1078VkP5pepX8uto+cviOsevacnbd9ES8xGmP4f GbrC9BONR+OxUIOZBJxi6I1ZQOwNWlYAWI9vytml2T1EYmuraUPU0wrH9jRo5SD8oof6 DYRX/ndsIDItt5oByyNxo15uqgL449QInTk0XFXLdLikJXsLO/wGFxLXYh1Yhji4uevW +r3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aQbRtpvK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 21/32] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I've re-factored the handle_simd_intfp_conv helper to properly handle half-precision as well as call plain conversion helpers when we are not doing fixed point conversion. Signed-off-by: Alex Bennée --- target/arm/helper.c | 4 ++ target/arm/helper.h | 10 ++++ target/arm/translate-a64.c | 121 +++++++++++++++++++++++++++++++++++---------- 3 files changed, 108 insertions(+), 27 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 72522c125c..d2ef3a0f00 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10883,8 +10883,10 @@ CONV_ITOF(vfp_##name##to##p, fsz, sign) \ CONV_FTOI(vfp_to##name##p, fsz, sign, ) \ CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero) +FLOAT_CONVS(si, h, 16, ) FLOAT_CONVS(si, s, 32, ) FLOAT_CONVS(si, d, 64, ) +FLOAT_CONVS(ui, h, 16, u) FLOAT_CONVS(ui, s, 32, u) FLOAT_CONVS(ui, d, 64, u) @@ -10967,6 +10969,8 @@ VFP_CONV_FIX_A64(sq, s, 32, 64, int64) VFP_CONV_FIX(uh, s, 32, 32, uint16) VFP_CONV_FIX(ul, s, 32, 32, uint32) VFP_CONV_FIX_A64(uq, s, 32, 64, uint64) +VFP_CONV_FIX_A64(sl, h, 16, 32, int32) +VFP_CONV_FIX_A64(ul, h, 16, 32, uint32) #undef VFP_CONV_FIX #undef VFP_CONV_FIX_FLOAT #undef VFP_CONV_FLOAT_FIX_ROUND diff --git a/target/arm/helper.h b/target/arm/helper.h index 40dcd74cfd..fcdb2b1520 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -120,17 +120,23 @@ DEF_HELPER_3(vfp_cmped, void, f64, f64, env) DEF_HELPER_2(vfp_fcvtds, f64, f32, env) DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) +DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) DEF_HELPER_2(vfp_uitos, f32, i32, ptr) DEF_HELPER_2(vfp_uitod, f64, i32, ptr) +DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) DEF_HELPER_2(vfp_sitos, f32, i32, ptr) DEF_HELPER_2(vfp_sitod, f64, i32, ptr) +DEF_HELPER_2(vfp_touih, i32, f16, ptr) DEF_HELPER_2(vfp_touis, i32, f32, ptr) DEF_HELPER_2(vfp_touid, i32, f64, ptr) +DEF_HELPER_2(vfp_touizh, i32, f16, ptr) DEF_HELPER_2(vfp_touizs, i32, f32, ptr) DEF_HELPER_2(vfp_touizd, i32, f64, ptr) +DEF_HELPER_2(vfp_tosih, i32, f16, ptr) DEF_HELPER_2(vfp_tosis, i32, f32, ptr) DEF_HELPER_2(vfp_tosid, i32, f64, ptr) +DEF_HELPER_2(vfp_tosizh, i32, f16, ptr) DEF_HELPER_2(vfp_tosizs, i32, f32, ptr) DEF_HELPER_2(vfp_tosizd, i32, f64, ptr) @@ -142,6 +148,8 @@ DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) @@ -166,6 +174,8 @@ DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0efe9ae2fc..5baf0261ff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6862,23 +6862,28 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, int elements, int is_signed, int fracbits, int size) { - bool is_double = size == 3 ? true : false; - TCGv_ptr tcg_fpst = get_fpstatus_ptr(false); - TCGv_i32 tcg_shift = tcg_const_i32(fracbits); - TCGv_i64 tcg_int = tcg_temp_new_i64(); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16); + TCGv_i32 tcg_shift = NULL; + TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); int pass; - for (pass = 0; pass < elements; pass++) { - read_vec_element(s, tcg_int, rn, pass, mop); + if (fracbits || size == MO_64) { + tcg_shift = tcg_const_i32(fracbits); + } + + if (size == MO_64) { + TCGv_i64 tcg_int64 = tcg_temp_new_i64(); + TCGv_i64 tcg_double = tcg_temp_new_i64(); + + for (pass = 0; pass < elements; pass++) { + read_vec_element(s, tcg_int64, rn, pass, mop); - if (is_double) { - TCGv_i64 tcg_double = tcg_temp_new_i64(); if (is_signed) { - gen_helper_vfp_sqtod(tcg_double, tcg_int, + gen_helper_vfp_sqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } else { - gen_helper_vfp_uqtod(tcg_double, tcg_int, + gen_helper_vfp_uqtod(tcg_double, tcg_int64, tcg_shift, tcg_fpst); } if (elements == 1) { @@ -6886,32 +6891,77 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, } else { write_vec_element(s, tcg_double, rd, pass, MO_64); } - tcg_temp_free_i64(tcg_double); - } else { - TCGv_i32 tcg_single = tcg_temp_new_i32(); - if (is_signed) { - gen_helper_vfp_sqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); - } else { - gen_helper_vfp_uqtos(tcg_single, tcg_int, - tcg_shift, tcg_fpst); + } + + tcg_temp_free_i64(tcg_int64); + tcg_temp_free_i64(tcg_double); + + } else { + TCGv_i32 tcg_int32 = tcg_temp_new_i32(); + TCGv_i32 tcg_float = tcg_temp_new_i32(); + + for (pass = 0; pass < elements; pass++) { + read_vec_element_i32(s, tcg_int32, rn, pass, mop); + + switch (size) { + case MO_32: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultos(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst); + } else { + gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst); + } + } + break; + case MO_16: + if (fracbits) { + if (is_signed) { + gen_helper_vfp_sltoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } else { + gen_helper_vfp_ultoh(tcg_float, tcg_int32, + tcg_shift, tcg_fpst); + } + } else { + if (is_signed) { + gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst); + } else { + gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst); + } + } + break; + default: + g_assert_not_reached(); } + if (elements == 1) { - write_fp_sreg(s, rd, tcg_single); + write_fp_sreg(s, rd, tcg_float); } else { - write_vec_element_i32(s, tcg_single, rd, pass, MO_32); + write_vec_element_i32(s, tcg_float, rd, pass, size); } - tcg_temp_free_i32(tcg_single); } - } - if (!is_double && elements == 2) { - clear_vec_high(s, rd); + tcg_temp_free_i32(tcg_int32); + tcg_temp_free_i32(tcg_float); + + if ((size == MO_32 && elements == 2) || + (size == MO_16 && elements == 4)) { + clear_vec_high(s, rd); + } } - tcg_temp_free_i64(tcg_int); tcg_temp_free_ptr(tcg_fpst); - tcg_temp_free_i32(tcg_shift); + if (tcg_shift) { + tcg_temp_free_i32(tcg_shift); + } } /* UCVTF/SCVTF - Integer to FP conversion */ @@ -10771,6 +10821,23 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) rn = extract32(insn, 5, 5); switch (fpop) { + case 0x1d: /* SCVTF */ + case 0x5d: /* UCVTF */ + { + int elements; + + if (is_scalar) { + elements = 1; + } else { + elements = (is_q ? 8 : 4); + } + + if (!fp_access_check(s)) { + return; + } + handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16); + return; + } break; case 0x2c: /* FCMGT (zero) */ case 0x2d: /* FCMEQ (zero) */ From patchwork Thu Feb 8 17:31:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127706 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1726109ljc; Thu, 8 Feb 2018 10:00:30 -0800 (PST) X-Google-Smtp-Source: AH8x224g8eArr29FQEHC+ngwBhmguZYprrqieuMnzbyFwl51lgc7j7K4LCQzz55v+M5NHMqIErig X-Received: by 10.37.64.194 with SMTP id n185mr28183yba.390.1518112830801; Thu, 08 Feb 2018 10:00:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112830; cv=none; d=google.com; s=arc-20160816; b=qlpS3zZ24IgMvlyvEor1A7yQIwnt7HLG1YFcVaZhjxMz4LPkJdT4As2oIN5ln+LQfE OobmKwIRavZ1k2fr+80Bw5ujDl4mK0czCQqHUgcJFHqGDyb2ne297oMCbVLxKWPzx8hs ESp4ysGsCAmgEBoHfNlu5A21EhvH0c2kvwW8wscUbk3JWWBFXg8+ASlIUNngoyd0MIVY A8qu7GGQn+Rswz29/6tumpfzl9eFjfIkQEueoFz+rZa7MgpST0TXqljI61VmyhfTDwW8 QEiqMhQ4+3S6hd/QwSZivft6sSJKPBZrjbm6zrCgCyq2Uj8dJfu5Ro7Or9HhyoYFUcHF PpKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lQlk313lEATGSOT2+WhMICU81WFdJyyDHn5jbHGR/vs=; b=tV7xZucUL5PrVR9Z8iBbErLOo+5bP5ksYrT7CyfjETHxj8HNFcjfnMCgwBdt0Lfm09 wu0eWdJcDe8oiqeryg4kahipps8up8Ou0lzkbYkc7yxzQVR7kRMHk7UzKXRPuLhHchcl Eeih0jizwOdj+j7b5KfJcvUdrClopUaGrRt0XcWkoaQnLYdloJ3Vhk9Gg5OpSIsMrYYG l1cw9bMG4qE75VslMYYxPEdQ2xEWu9NXJ2PhVluiDDRzxyq753EzN8ASel0DMPvV1cIe x4UL0htTmQoUJviUehQFacth6fiEfvcRTZZujJCqdZVPA8G9fLgUVH5KsWISAfLen1wY Lglg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HJrcxOaY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As these operations doesn't use the fpstatus pointer we can be smarter about allocating it. The negh can also be done with a bitwise xor rather than calling a helper. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5baf0261ff..da3c7bfa85 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10801,6 +10801,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) TCGv_i32 tcg_rmode = NULL; TCGv_ptr tcg_fpstatus = NULL; bool need_rmode = false; + bool need_fpst = true; int rmode; if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { @@ -10917,6 +10918,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) need_rmode = true; rmode = FPROUNDING_ZERO; break; + case 0x2f: /* FABS */ + case 0x6f: /* FNEG */ + need_fpst = false; + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -10970,6 +10975,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } @@ -11013,6 +11021,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x59: /* FRINTX */ gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x2f: /* FABS */ + gen_helper_advsimd_absh(tcg_res, tcg_op); + break; + case 0x6f: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; default: g_assert_not_reached(); } From patchwork Thu Feb 8 17:31:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127710 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1733554ljc; Thu, 8 Feb 2018 10:07:48 -0800 (PST) X-Google-Smtp-Source: AH8x226sDZGbxO4qqAcemgHCIOmsFixrSQlZ1lTmDfF2wI+2a3vqbcBHtnHQkw01GiV5tjDOUlHm X-Received: by 10.129.112.69 with SMTP id l66mr59649ywc.322.1518113268892; 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Thu, 08 Feb 2018 09:40:33 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 198sm478638wmo.36.2018.02.08.09.40.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 09:40:29 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 745AD3E0AC0; Thu, 8 Feb 2018 17:31:59 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-arm@nongnu.org Date: Thu, 8 Feb 2018 17:31:48 +0000 Message-Id: <20180208173157.24705-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180208173157.24705-1-alex.bennee@linaro.org> References: <20180208173157.24705-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" It looks like the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Bennée --- target/arm/helper.c | 225 ++++++++++++++++++++++++++++++---------------------- target/arm/helper.h | 1 + 2 files changed, 129 insertions(+), 97 deletions(-) -- 2.15.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index d2ef3a0f00..6cfab94c38 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11104,80 +11104,75 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env) * int->float conversions at run-time. */ #define float64_256 make_float64(0x4070000000000000LL) #define float64_512 make_float64(0x4080000000000000LL) +#define float16_maxnorm make_float16(0x7bff) #define float32_maxnorm make_float32(0x7f7fffff) #define float64_maxnorm make_float64(0x7fefffffffffffffLL) /* Reciprocal functions * * The algorithm that must be used to calculate the estimate - * is specified by the ARM ARM, see FPRecipEstimate() + * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate */ -static float64 recip_estimate(float64 a, float_status *real_fp_status) -{ - /* These calculations mustn't set any fp exception flags, - * so we use a local copy of the fp_status. - */ - float_status dummy_status = *real_fp_status; - float_status *s = &dummy_status; - /* q = (int)(a * 512.0) */ - float64 q = float64_mul(float64_512, a, s); - int64_t q_int = float64_to_int64_round_to_zero(q, s); - - /* r = 1.0 / (((double)q + 0.5) / 512.0) */ - q = int64_to_float64(q_int, s); - q = float64_add(q, float64_half, s); - q = float64_div(q, float64_512, s); - q = float64_div(float64_one, q, s); - - /* s = (int)(256.0 * r + 0.5) */ - q = float64_mul(q, float64_256, s); - q = float64_add(q, float64_half, s); - q_int = float64_to_int64_round_to_zero(q, s); +/* See RecipEstimate() + * + * input is a 9 bit fixed point number + * input range 256 .. 511 for a number from 0.5 <= x < 1.0. + * result range 256 .. 511 for a number from 1.0 to 511/256. + */ - /* return (double)s / 256.0 */ - return float64_div(int64_to_float64(q_int, s), float64_256, s); +static int recip_estimate(int input) +{ + int a, b, r; + assert(256 <= input && input < 512); + a = (input * 2) + 1; + b = (1 << 19) / a; + r = (b + 1) >> 1; + assert(256 <= r && r < 512); + return r; } -/* Common wrapper to call recip_estimate */ -static float64 call_recip_estimate(float64 num, int off, float_status *fpst) +/* + * Common wrapper to call recip_estimate + * + * The parameters are exponent and 64 bit fraction (without implicit + * bit) where the binary point is nominally at bit 52. Returns a + * float64 which can then be rounded to the appropriate size by the + * callee. + */ + +static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac) { - uint64_t val64 = float64_val(num); - uint64_t frac = extract64(val64, 0, 52); - int64_t exp = extract64(val64, 52, 11); - uint64_t sbit; - float64 scaled, estimate; + uint32_t scaled, estimate; + uint64_t result_frac; + int result_exp; - /* Generate the scaled number for the estimate function */ - if (exp == 0) { + /* Handle sub-normals */ + if (*exp == 0) { if (extract64(frac, 51, 1) == 0) { - exp = -1; - frac = extract64(frac, 0, 50) << 2; + *exp = -1; + frac <<= 2; } else { - frac = extract64(frac, 0, 51) << 1; + frac <<= 1; } } - /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */ - scaled = make_float64((0x3feULL << 52) - | extract64(frac, 44, 8) << 44); - - estimate = recip_estimate(scaled, fpst); + /* scaled = UInt('1':fraction<51:44>) */ + scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); + estimate = recip_estimate(scaled); - /* Build new result */ - val64 = float64_val(estimate); - sbit = 0x8000000000000000ULL & val64; - exp = off - exp; - frac = extract64(val64, 0, 52); - - if (exp == 0) { - frac = 1ULL << 51 | extract64(frac, 1, 51); - } else if (exp == -1) { - frac = 1ULL << 50 | extract64(frac, 2, 50); - exp = 0; + result_exp = exp_off - *exp; + result_frac = deposit64(0, 44, 8, estimate); + if (result_exp == 0) { + result_frac = deposit64(result_frac >> 1, 51, 1, 1); + } else if (result_exp == -1) { + result_frac = deposit64(result_frac >> 2, 50, 2, 1); + result_exp = 0; } - return make_float64(sbit | (exp << 52) | frac); + *exp = result_exp; + + return result_frac; } static bool round_to_inf(float_status *fpst, bool sign_bit) @@ -11196,18 +11191,64 @@ static bool round_to_inf(float_status *fpst, bool sign_bit) g_assert_not_reached(); } +float16 HELPER(recpe_f16)(float16 input, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f16 = float16_squash_input_denormal(input, fpst); + uint32_t f16_val = float16_val(f16); + uint32_t f16_sign = float16_is_neg(f16); + int f16_exp = extract32(f16_val, 10, 5); + uint32_t f16_frac = extract32(f16_val, 0, 10); + uint64_t f64_frac; + + if (float16_is_any_nan(f16)) { + float16 nan = f16; + if (float16_is_signaling_nan(f16, fpst)) { + float_raise(float_flag_invalid, fpst); + nan = float16_maybe_silence_nan(f16, fpst); + } + if (fpst->default_nan_mode) { + nan = float16_default_nan(fpst); + } + return nan; + } else if (float16_is_infinity(f16)) { + return float16_set_sign(float16_zero, float16_is_neg(f16)); + } else if (float16_is_zero(f16)) { + float_raise(float_flag_divbyzero, fpst); + return float16_set_sign(float16_infinity, float16_is_neg(f16)); + } else if (float16_abs(f16) < (1 << 8)) { + /* Abs(value) < 2.0^-14 */ + float_raise(float_flag_overflow | float_flag_inexact, fpst); + if (round_to_inf(fpst, f16_sign)) { + return float16_set_sign(float16_infinity, f16_sign); + } else { + return float16_set_sign(float16_maxnorm, f16_sign); + } + /* FP16 has it's own flag FZ16 flag which is in a separate fpst*/ + } else if (f16_exp >= 14 && fpst->flush_to_zero) { + float_raise(float_flag_underflow, fpst); + return float16_set_sign(float16_zero, float16_is_neg(f16)); + } + + f64_frac = call_recip_estimate(&f16_exp, 29, + ((uint64_t) f16_frac) << (52 - 10)); + + /* result = sign : result_exp<4:0> : fraction<51:42> */ + f16_val = deposit32(0, 15, 1, f16_sign); + f16_val = deposit32(f16_val, 10, 5, f16_exp); + f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10)); + return make_float16(f16_val); +} + float32 HELPER(recpe_f32)(float32 input, void *fpstp) { float_status *fpst = fpstp; float32 f32 = float32_squash_input_denormal(input, fpst); uint32_t f32_val = float32_val(f32); - uint32_t f32_sbit = 0x80000000ULL & f32_val; - int32_t f32_exp = extract32(f32_val, 23, 8); + bool f32_sign = float32_is_neg(f32); + int f32_exp = extract32(f32_val, 23, 8); uint32_t f32_frac = extract32(f32_val, 0, 23); - float64 f64, r64; - uint64_t r64_val; - int64_t r64_exp; - uint64_t r64_frac; + uint64_t f64_frac; if (float32_is_any_nan(f32)) { float32 nan = f32; @@ -11224,30 +11265,27 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) } else if (float32_is_zero(f32)) { float_raise(float_flag_divbyzero, fpst); return float32_set_sign(float32_infinity, float32_is_neg(f32)); - } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) { + } else if (float32_abs(f32) < (1ULL << 21)) { /* Abs(value) < 2.0^-128 */ float_raise(float_flag_overflow | float_flag_inexact, fpst); - if (round_to_inf(fpst, f32_sbit)) { - return float32_set_sign(float32_infinity, float32_is_neg(f32)); + if (round_to_inf(fpst, f32_sign)) { + return float32_set_sign(float32_infinity, f32_sign); } else { - return float32_set_sign(float32_maxnorm, float32_is_neg(f32)); + return float32_set_sign(float32_maxnorm, f32_sign); } } else if (f32_exp >= 253 && fpst->flush_to_zero) { float_raise(float_flag_underflow, fpst); return float32_set_sign(float32_zero, float32_is_neg(f32)); } + f64_frac = call_recip_estimate(&f32_exp, 253, + ((uint64_t) f32_frac) << (52 - 23)); - f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29); - r64 = call_recip_estimate(f64, 253, fpst); - r64_val = float64_val(r64); - r64_exp = extract64(r64_val, 52, 11); - r64_frac = extract64(r64_val, 0, 52); - - /* result = sign : result_exp<7:0> : fraction<51:29>; */ - return make_float32(f32_sbit | - (r64_exp & 0xff) << 23 | - extract64(r64_frac, 29, 24)); + /* result = sign : result_exp<7:0> : fraction<51:29> */ + f32_val = deposit32(0, 31, 1, f32_sign); + f32_val = deposit32(f32_val, 23, 8, f32_exp); + f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23)); + return make_float32(f32_val); } float64 HELPER(recpe_f64)(float64 input, void *fpstp) @@ -11255,12 +11293,9 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) float_status *fpst = fpstp; float64 f64 = float64_squash_input_denormal(input, fpst); uint64_t f64_val = float64_val(f64); - uint64_t f64_sbit = 0x8000000000000000ULL & f64_val; - int64_t f64_exp = extract64(f64_val, 52, 11); - float64 r64; - uint64_t r64_val; - int64_t r64_exp; - uint64_t r64_frac; + bool f64_sign = float64_is_neg(f64); + int f64_exp = extract64(f64_val, 52, 11); + uint64_t f64_frac = extract64(f64_val, 0, 52); /* Deal with any special cases */ if (float64_is_any_nan(f64)) { @@ -11281,25 +11316,23 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) { /* Abs(value) < 2.0^-1024 */ float_raise(float_flag_overflow | float_flag_inexact, fpst); - if (round_to_inf(fpst, f64_sbit)) { - return float64_set_sign(float64_infinity, float64_is_neg(f64)); + if (round_to_inf(fpst, f64_sign)) { + return float64_set_sign(float64_infinity, f64_sign); } else { - return float64_set_sign(float64_maxnorm, float64_is_neg(f64)); + return float64_set_sign(float64_maxnorm, f64_sign); } } else if (f64_exp >= 2045 && fpst->flush_to_zero) { float_raise(float_flag_underflow, fpst); return float64_set_sign(float64_zero, float64_is_neg(f64)); } - r64 = call_recip_estimate(f64, 2045, fpst); - r64_val = float64_val(r64); - r64_exp = extract64(r64_val, 52, 11); - r64_frac = extract64(r64_val, 0, 52); + f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac); - /* result = sign : result_exp<10:0> : fraction<51:0> */ - return make_float64(f64_sbit | - ((r64_exp & 0x7ff) << 52) | - r64_frac); + /* result = sign : result_exp<10:0> : fraction<51:0>; */ + f64_val = deposit64(0, 63, 1, f64_sign); + f64_val = deposit64(f64_val, 52, 11, f64_exp); + f64_val = deposit64(f64_val, 0, 52, f64_frac); + return make_float64(f64_val); } /* The algorithm that must be used to calculate the estimate @@ -11488,19 +11521,17 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) { - float_status *s = fpstp; - float64 f64; + /* float_status *s = fpstp; */ + int input, estimate; if ((a & 0x80000000) == 0) { return 0xffffffff; } - f64 = make_float64((0x3feULL << 52) - | ((int64_t)(a & 0x7fffffff) << 21)); - - f64 = recip_estimate(f64, s); + input = extract32(a, 23, 9); + estimate = recip_estimate(input); - return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); + return deposit32(0, (32 - 9), 9, estimate); } uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) diff --git a/target/arm/helper.h b/target/arm/helper.h index fcdb2b1520..e962b5392b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -192,6 +192,7 @@ DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) DEF_HELPER_3(recps_f32, f32, f32, f32, env) DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) From patchwork Thu Feb 8 17:31:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127709 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1733430ljc; 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v2 24/32] arm/translate-a64: add FP16 FRECPE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we have added f16 during the re-factoring we can simply call the helper. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index da3c7bfa85..4ad5e97f56 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10848,6 +10848,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; break; + case 0x3d: /* FRECPE */ + break; case 0x18: /* FRINTN */ need_rmode = true; only_in_vector = true; @@ -10968,6 +10970,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ @@ -11003,6 +11008,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ From patchwork Thu Feb 8 17:31:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127712 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1736592ljc; Thu, 8 Feb 2018 10:11:22 -0800 (PST) X-Google-Smtp-Source: AH8x224MI5IDtcnNi11LEo9pjoAQ/4MGYJ8W7JKRClGXyMJ9/dcj4UPN9UdeBjP0j4eaLKhRFMQu X-Received: by 10.129.209.11 with SMTP id w11mr30393ywi.475.1518113482710; Thu, 08 Feb 2018 10:11:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518113482; cv=none; d=google.com; s=arc-20160816; b=jaCNrlOHxhXYUvmISDNwK6yjJN+c9s+xKyzaQBsOo4WYAoCRd21fKX8iu2gRgPJIVY l2rmNsJf7naXWRisGgwGxrBbPVyRBG1gfde5tklA8c0oTx3xoC5zouBjtFtBEk2wzPGD 9YP8Wqq3P6BsQ7oJdyQr5YnirKXiz88cGde7RbZloTkrMeZkaDWKXr82ttdMzNOnR/md ubyD/wsuDYHW90dsSYR+VxdsNUN8XsNu1emwUIK5VpVAZCm4jRiif9VUTobDAo/vgz9y 4DXaW4PRgdWYKDqD883k8BamBSsF2Vu8Fb+nw9TDYoXCpUiOP1aVQdnjNLlj7q7L2WoL 8qOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=AOidBiav4IDSlHHH+8V/Klfwlu/r9S5JV5LA2I5xQHw=; b=BQBhSdgNucLlP4+0zvM9tlO2PnQ86GEw1jyRO9SMBI+Y5fqWIHpkx4LVSc6cWTm43P 9a9H5m5kVPmxPodsAtCiqorZwXlvDB0JsoR2ZJcrLJMalI9GQd/Ta2gjz6W42je2zk2c vKmvncV5JMMLqRk8VspzXe8zOZyl6ZVrPscEHyc5Yywcdl8iZ1TuAd8TF5AX530g3Hwi tf3Up8BCzJeo8FAi5Ei+c8q8WQXzar00iRVaG3LzGPu1y8j66AFb1XlWZHEVoVbtcW4z sXy/CyhCIyiNJjQqf4Y+Ck+AAvMrLE8FZVadUY3JTlt7NZq5RFVawN3yzlBRaxezhxt8 BaYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MB+qdDHY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We go with the localised helper. Signed-off-by: Alex Bennée --- target/arm/helper-a64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 4 ++++ 3 files changed, 34 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 76f3289e37..38cdc13b3e 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -356,6 +356,35 @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a) } /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ +float16 HELPER(frecpx_f16)(float16 a, void *fpstp) +{ + float_status *fpst = fpstp; + uint16_t val16, sbit; + int16_t exp; + + if (float16_is_any_nan(a)) { + float16 nan = a; + if (float16_is_signaling_nan(a, fpst)) { + float_raise(float_flag_invalid, fpst); + nan = float16_maybe_silence_nan(a, fpst); + } + if (fpst->default_nan_mode) { + nan = float16_default_nan(fpst); + } + return nan; + } + + val16 = float16_val(a); + sbit = 0x8000 & val16; + exp = extract32(val16, 10, 5); + + if (exp == 0) { + return make_float16(deposit32(sbit, 10, 5, 0x1e)); + } else { + return make_float16(deposit32(sbit, 10, 5, ~exp)); + } +} + float32 HELPER(frecpx_f32)(float32 a, void *fpstp) { float_status *fpst = fpstp; diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 453753f4e7..d8a55142b5 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -41,6 +41,7 @@ DEF_HELPER_FLAGS_1(neon_addlp_s16, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(neon_addlp_u16, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_2(frecpx_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frecpx_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4ad5e97f56..b6cd4dd8f2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10849,6 +10849,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) return; break; case 0x3d: /* FRECPE */ + case 0x3f: /* FRECPX */ break; case 0x18: /* FRINTN */ need_rmode = true; @@ -10973,6 +10974,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3d: /* FRECPE */ gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3f: /* FRECPX */ + gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ From patchwork Thu Feb 8 17:31:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127703 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1724488ljc; Thu, 8 Feb 2018 09:58:31 -0800 (PST) X-Google-Smtp-Source: AH8x225UZcQf7bLMMp2SUGgo+9jCD7tYZGtlmqU9Pxab5t8tSvXuTBHPaZ3/YY8Tvo8kXenBhVhW X-Received: by 10.37.29.9 with SMTP id d9mr960ybd.277.1518112711391; Thu, 08 Feb 2018 09:58:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112711; cv=none; d=google.com; s=arc-20160816; b=yusE7BkguPGEnZxJ9g1Q03IpccNXK5NKc69XsQwFTQcvhOZvq6wHOWpVkBg57HBqa2 mxFvl7pn2nzkQq1iQQ7LNY2XqmOlvqMjUGMWwLjF42L4j+nLGWiasbXjj4A6LRDLB4NR 04Uuq2KVWuorFvy6JhJI7sx1b9xRMxJ979R9G2U6/gRoHB8+hdUcihp/99YMkr1m+ofr ttwaR2lF+fpen3FzAai3ybfC1hZEkpaTbsQRWJw93B79bopnv0PZJ6bWJsVi65ogsGC8 o2D7uVBkqhMG6btWZbb1I2YMIWjW3Oz0wujO9eUthRIpYd6Xfik+oowzG3lI8N2V0nW0 cm5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Zy4Ft/IrAMI0aOg/zaIL2BU3SA6ZNZ5xx47jSNKWl88=; b=PStyVRzcyKy8x3ENdiRwfxtQQ0IucmLsaUrP4tz3TVP14k79XXjsalqrMZYLYeFlVz keitaj+KzN3NBGZb4BhfG6wL1hQzu33fZzu9iMAhXqWVACY4bc7+hVzfEQugSeD+u73r IiL29MqfVee9NPmq/hmjPsFh/2zud8yZE0ZdQhYkuOlYTbEP692ddVNNDgdIpZqgkNir Cdbk12dN4GSNAhpDKTIad7EYSPM0tLmqVM4F9m/5Xx2NPnEyTY4yLzbiv7/seOH7iK2R laE/oWsuApgk+8pAkqjH4gql9/rWMk0cNBujMw7jbIgkO/dm/93+bqayGibdxF6h4yCq 0/7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fbwcw4D5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 26/32] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- v2 remove superfluous helpers --- target/arm/helper-a64.c | 13 +++++++++++++ target/arm/helper-a64.h | 1 + target/arm/translate-a64.c | 5 +++++ 3 files changed, 19 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 38cdc13b3e..7952a6bfff 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -833,3 +833,16 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp) } return float16_to_uint16(a, fpst); } + +/* + * Square Root and Reciprocal square root + */ + +float16 HELPER(sqrt_f16)(float16 a, void *fpstp) +{ + float_status *s = fpstp; + + return float16_sqrt(a, s); +} + + diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index d8a55142b5..905125bab1 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -81,3 +81,4 @@ DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr) DEF_HELPER_2(advsimd_rinth, f16, f16, ptr) DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr) DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr) +DEF_HELPER_2(sqrt_f16, f16, f16, ptr) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b6cd4dd8f2..587d072d27 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10925,6 +10925,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7f: /* FSQRT (vector) */ + break; default: fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); g_assert_not_reached(); @@ -11039,6 +11041,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7f: /* FSQRT */ + gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } From patchwork Thu Feb 8 17:31:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127716 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1744688ljc; Thu, 8 Feb 2018 10:21:23 -0800 (PST) X-Google-Smtp-Source: AH8x227DO28NCPABrqfO70OmY79dHBhOOZwDAT0y3m6cWbGVdxZQeQ7kInA+sONZkhSuH0F/YNGN X-Received: by 10.37.135.67 with SMTP id e3mr29558ybn.366.1518114083698; Thu, 08 Feb 2018 10:21:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518114083; cv=none; d=google.com; s=arc-20160816; b=LKWeJpUK9mNEK5pLAV4JFRtWn7JuyosA+sGgjZfzXAJgOA6KwaEaeWeFEQHOFB8mqt aZxwn6VfINZiRSSomwVPfjTcqLUSqUyI5ZlAFQd9dREXR65VY5I4i599b474vzQQyhnf 6iIoVY+WFV+kbtOZ4YcX8uKsu+Z2Fsbvq4mtOUG5sAGoEue7O01QmdQmYyAf7Qib1k3L o48En8kSN/7KUpmMYir+tVQeOoXKhW+wbBvt+ryU0Np/ttEMuPqmyKDjckr6eQrX/wNc O0cl5Zdgt5xrwurWaztGp2/MQvkqYW1K79fMLeqzuzY6BMEj6drSbgp6Xdhx2sGXPZqb 2R+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=D8FoXSNAwRlEQmyYMc9PdW2O5l2HiITaU2krhWhxHNk=; b=oHJ+c5yTtTuFmkkBvN0CNptUXWxOuTdctYkFCFICDnVuVGyXbDQuzqhwdCFOlMatKW ciz4mszHZbiMOA+otFdrGSXhPzerO17RDKkCxzbny5mjdM9YH6XjNkUaxexoll1Hb3uR Go6dr2DQC6ilhJAp9aUfYhr8K7mwa1nsx1wKhOvcVCrG0qjK1MCVgWqE3oYCNicAQah0 Vnn+CTAo+o+FY5QnxghLt3LZR8kwFJi5yGHFCczrmc3RFBnBkj0HMmVcQ0fTbG9e48p1 +9cxQMKsWpigxyr+wmkYNNSmA5HsGiBHHG3IjiAzZrBTp4Z3mULnGnQA1AA6tmaK2MDd ZCOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NHMUU6CB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Much like recpe the ARM ARM has simplified the pseudo code for the calculation which is done on a fixed point 9 bit integer maths. So while adding f16 we can also clean this up to be a little less heavy on the floating point and just return the fractional part and leave the calle's to do the final packing of the result. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/helper.c | 221 ++++++++++++++++++++++++---------------------------- target/arm/helper.h | 1 + 2 files changed, 104 insertions(+), 118 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/helper.c b/target/arm/helper.c index 6cfab94c38..a16cc1b36b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11338,56 +11338,97 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) /* The algorithm that must be used to calculate the estimate * is specified by the ARM ARM. */ -static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status) -{ - /* These calculations mustn't set any fp exception flags, - * so we use a local copy of the fp_status. - */ - float_status dummy_status = *real_fp_status; - float_status *s = &dummy_status; - float64 q; - int64_t q_int; - - if (float64_lt(a, float64_half, s)) { - /* range 0.25 <= a < 0.5 */ - - /* a in units of 1/512 rounded down */ - /* q0 = (int)(a * 512.0); */ - q = float64_mul(float64_512, a, s); - q_int = float64_to_int64_round_to_zero(q, s); - - /* reciprocal root r */ - /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */ - q = int64_to_float64(q_int, s); - q = float64_add(q, float64_half, s); - q = float64_div(q, float64_512, s); - q = float64_sqrt(q, s); - q = float64_div(float64_one, q, s); + +static int do_recip_sqrt_estimate(int a) +{ + int b, estimate; + + assert(128 <= a && a < 512); + if (a < 256) { + a = a * 2 + 1; } else { - /* range 0.5 <= a < 1.0 */ + a = (a >> 1) << 1; + a = (a + 1) * 2; + } + b = 512; + while (a * (b + 1) * (b + 1) < (1 << 28)) { + b += 1; + } + estimate = (b + 1) / 2; + assert(256 <= estimate && estimate < 512); + + return estimate; +} + - /* a in units of 1/256 rounded down */ - /* q1 = (int)(a * 256.0); */ - q = float64_mul(float64_256, a, s); - int64_t q_int = float64_to_int64_round_to_zero(q, s); +static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac) +{ + int estimate; + uint32_t scaled; - /* reciprocal root r */ - /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */ - q = int64_to_float64(q_int, s); - q = float64_add(q, float64_half, s); - q = float64_div(q, float64_256, s); - q = float64_sqrt(q, s); - q = float64_div(float64_one, q, s); + if (*exp == 0) { + while (extract64(frac, 51, 1) == 0) { + frac = frac << 1; + *exp -= 1; + } + frac = extract64(frac, 0, 51) << 1; } - /* r in units of 1/256 rounded to nearest */ - /* s = (int)(256.0 * r + 0.5); */ - q = float64_mul(q, float64_256,s ); - q = float64_add(q, float64_half, s); - q_int = float64_to_int64_round_to_zero(q, s); + if (*exp & 1) { + /* scaled = UInt('01':fraction<51:45>) */ + scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7)); + } else { + /* scaled = UInt('1':fraction<51:44>) */ + scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8)); + } + estimate = do_recip_sqrt_estimate(scaled); - /* return (double)s / 256.0;*/ - return float64_div(int64_to_float64(q_int, s), float64_256, s); + *exp = (exp_off - *exp) / 2; + return extract64(estimate, 0, 8) << 44; +} + +float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) +{ + float_status *s = fpstp; + float16 f16 = float16_squash_input_denormal(input, s); + uint16_t val = float16_val(f16); + bool f16_sign = float16_is_neg(f16); + int f16_exp = extract32(val, 10, 5); + uint16_t f16_frac = extract32(val, 0, 10); + uint64_t f64_frac; + + if (float16_is_any_nan(f16)) { + float16 nan = f16; + if (float16_is_signaling_nan(f16, s)) { + float_raise(float_flag_invalid, s); + nan = float16_maybe_silence_nan(f16, s); + } + if (s->default_nan_mode) { + nan = float16_default_nan(s); + } + return nan; + } else if (float16_is_zero(f16)) { + float_raise(float_flag_divbyzero, s); + return float16_set_sign(float16_infinity, f16_sign); + } else if (f16_sign) { + float_raise(float_flag_invalid, s); + return float16_default_nan(s); + } else if (float16_is_infinity(f16)) { + return float16_zero; + } + + /* Scale and normalize to a double-precision value between 0.25 and 1.0, + * preserving the parity of the exponent. */ + + f64_frac = ((uint64_t) f16_frac) << (52 - 10); + + f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac); + + /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */ + val = deposit32(0, 15, 1, f16_sign); + val = deposit32(val, 10, 5, f16_exp); + val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float16(val); } float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) @@ -11395,13 +11436,10 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) float_status *s = fpstp; float32 f32 = float32_squash_input_denormal(input, s); uint32_t val = float32_val(f32); - uint32_t f32_sbit = 0x80000000 & val; - int32_t f32_exp = extract32(val, 23, 8); + uint32_t f32_sign = float32_is_neg(f32); + int f32_exp = extract32(val, 23, 8); uint32_t f32_frac = extract32(val, 0, 23); uint64_t f64_frac; - uint64_t val64; - int result_exp; - float64 f64; if (float32_is_any_nan(f32)) { float32 nan = f32; @@ -11427,32 +11465,13 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) * preserving the parity of the exponent. */ f64_frac = ((uint64_t) f32_frac) << 29; - if (f32_exp == 0) { - while (extract64(f64_frac, 51, 1) == 0) { - f64_frac = f64_frac << 1; - f32_exp = f32_exp-1; - } - f64_frac = extract64(f64_frac, 0, 51) << 1; - } - - if (extract64(f32_exp, 0, 1) == 0) { - f64 = make_float64(((uint64_t) f32_sbit) << 32 - | (0x3feULL << 52) - | f64_frac); - } else { - f64 = make_float64(((uint64_t) f32_sbit) << 32 - | (0x3fdULL << 52) - | f64_frac); - } - result_exp = (380 - f32_exp) / 2; + f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac); - f64 = recip_sqrt_estimate(f64, s); - - val64 = float64_val(f64); - - val = ((result_exp & 0xff) << 23) - | ((val64 >> 29) & 0x7fffff); + /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */ + val = deposit32(0, 31, 1, f32_sign); + val = deposit32(val, 23, 8, f32_exp); + val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8)); return make_float32(val); } @@ -11461,11 +11480,9 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) float_status *s = fpstp; float64 f64 = float64_squash_input_denormal(input, s); uint64_t val = float64_val(f64); - uint64_t f64_sbit = 0x8000000000000000ULL & val; - int64_t f64_exp = extract64(val, 52, 11); + bool f64_sign = float64_is_neg(f64); + int f64_exp = extract64(val, 52, 11); uint64_t f64_frac = extract64(val, 0, 52); - int64_t result_exp; - uint64_t result_frac; if (float64_is_any_nan(f64)) { float64 nan = f64; @@ -11487,36 +11504,13 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) return float64_zero; } - /* Scale and normalize to a double-precision value between 0.25 and 1.0, - * preserving the parity of the exponent. */ - - if (f64_exp == 0) { - while (extract64(f64_frac, 51, 1) == 0) { - f64_frac = f64_frac << 1; - f64_exp = f64_exp - 1; - } - f64_frac = extract64(f64_frac, 0, 51) << 1; - } + f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac); - if (extract64(f64_exp, 0, 1) == 0) { - f64 = make_float64(f64_sbit - | (0x3feULL << 52) - | f64_frac); - } else { - f64 = make_float64(f64_sbit - | (0x3fdULL << 52) - | f64_frac); - } - - result_exp = (3068 - f64_exp) / 2; - - f64 = recip_sqrt_estimate(f64, s); - - result_frac = extract64(float64_val(f64), 0, 52); - - return make_float64(f64_sbit | - ((result_exp & 0x7ff) << 52) | - result_frac); + /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */ + val = deposit64(0, 61, 1, f64_sign); + val = deposit64(val, 52, 11, f64_exp); + val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8)); + return make_float64(val); } uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) @@ -11536,24 +11530,15 @@ uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp) uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp) { - float_status *fpst = fpstp; - float64 f64; + int estimate; if ((a & 0xc0000000) == 0) { return 0xffffffff; } - if (a & 0x80000000) { - f64 = make_float64((0x3feULL << 52) - | ((uint64_t)(a & 0x7fffffff) << 21)); - } else { /* bits 31-30 == '01' */ - f64 = make_float64((0x3fdULL << 52) - | ((uint64_t)(a & 0x3fffffff) << 22)); - } - - f64 = recip_sqrt_estimate(f64, fpst); + estimate = do_recip_sqrt_estimate(extract32(a, 23, 9)); - return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff); + return deposit32(0, 23, 9, estimate); } /* VFPv4 fused multiply-accumulate */ diff --git a/target/arm/helper.h b/target/arm/helper.h index e962b5392b..9b01006ea6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -195,6 +195,7 @@ DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(recpe_u32, i32, i32, ptr) From patchwork Thu Feb 8 17:31:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127720 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1754564ljc; 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X-Received-From: 2a00:1450:400c:c09::243 Subject: [Qemu-devel] [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 587d072d27..fa21299061 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10925,6 +10925,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7d: /* FRSQRTE */ case 0x7f: /* FSQRT (vector) */ break; default: @@ -10989,6 +10990,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -11041,6 +11045,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x7f: /* FSQRT */ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); break; From patchwork Thu Feb 8 17:31:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127719 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1751162ljc; Thu, 8 Feb 2018 10:29:55 -0800 (PST) X-Google-Smtp-Source: AH8x225N7O0dMpt5NAWQ7U1mtAVo1fDAQzqmaHIhA2jrgw83oeVrzQNYIxJfkHiPtILZJxCuA8i3 X-Received: by 10.37.73.194 with SMTP id w185mr16347yba.427.1518114595502; Thu, 08 Feb 2018 10:29:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518114595; cv=none; d=google.com; s=arc-20160816; b=ouox9j3TVLsuqJO2bvjgOgYFQ7/7ue8rnyHdEcH2rMT99X4BTjzNJj4fx+X+6OkIui k4PkcnV/hq0QqtZ7N8kTZ48FHvXcL/kchvf3QQdSVAA49uImPToxd8/k6POv7tfIzBJH yFvwv0+sarotWeK+7x0URb/NV8VRsQd5XW/z16hcFwzP2LnvMWcTJTsUcZ/jFDGuPJgQ 06N4NMG+XxuSCyZKPuUwQdgNiHHbXCW8fntTW88XjqD3t0o4N8AeYAYXKvwpOz1OIYlC ssoD32hzLCLznymPTlCrMVFNrfxW37sZnXO+Rou7+pkk63nwgmNC0SsA1Nu4lNhkoeZ3 ZNLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6ruzjgKhgbGahv2tciRTBdbawFZedjHFVJrsITdlH2Q=; b=KzU1FEFJCiiaW9HtKDAho7vRMSl7jTba7/uCCls//omUVnivRwUlLcGVv80aPRu7ZX xqoTZejD+AurAKRrFZmUwHJbWbgTVarnbCVzEIwEBAEQ7TDK3GXp1mTLjNjb4bvBHiuq 2lMMe0mXe5ix3JvF4Vg14IfhJ0ZOejY6V7hvHan4904SvQK7xbwi24BXvime1koW/5Zz wD2WNOggNoBi67O+GhI2QQABfvEkSmQO4cXIBNxjVjVoKttWuG54iL3qsv8R2WJZJ00G yiA0DMAquNLle3kqyUAKYhITH0kP/MMtfpOvytMjZeiOAk3SLeMx244qIYmjcdECqlkS ugvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hbTzsOOh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only one half-precision instruction has been added to this group. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 10 deletions(-) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fa21299061..b209f57d55 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6160,6 +6160,8 @@ static void disas_simd_copy(DisasContext *s, uint32_t insn) * MVNI - move inverted (shifted) imm into register * ORR - bitwise OR of (shifted) imm with register * BIC - bitwise clear of (shifted) imm with register + * With ARMv8.2 we also have: + * FMOV half-precision */ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) { @@ -6176,8 +6178,11 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) int i; if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) { - unallocated_encoding(s); - return; + /* Check for FMOV (vector, immediate) - half-precision */ + if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) { + unallocated_encoding(s); + return; + } } if (!fp_access_check(s)) { @@ -6235,19 +6240,42 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn) imm |= 0x4000000000000000ULL; } } else { - imm = (abcdefgh & 0x3f) << 19; - if (abcdefgh & 0x80) { - imm |= 0x80000000; - } - if (abcdefgh & 0x40) { - imm |= 0x3e000000; + if (o2) { + /* FMOV (vector, immediate) - half-precision + * + * We don't need fancy immediate expansion, just: + * imm16 = imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,2): + * imm8<5:0>:Zeros(6); + */ + uint32_t imm8_5_0 = extract32(abcdefgh, 0, 6); + uint32_t imm8_6 = extract32(abcdefgh, 6, 1); + uint32_t imm8_7 = extract32(abcdefgh, 7, 1); + uint32_t imm8_6_rep = imm8_6 << 1 | imm8_6; + uint32_t imm8_6_not = ~imm8_6; + imm = deposit64(imm, 6, 6, imm8_5_0); + imm = deposit64(imm, 12, 2, imm8_6_rep); + imm = deposit64(imm, 14, 1, imm8_6_not); + imm = deposit64(imm, 15, 1, imm8_7); + /* now duplicate across the lanes */ + imm = bitfield_replicate(imm, 16); } else { - imm |= 0x40000000; + imm = (abcdefgh & 0x3f) << 19; + if (abcdefgh & 0x80) { + imm |= 0x80000000; + } + if (abcdefgh & 0x40) { + imm |= 0x3e000000; + } else { + imm |= 0x40000000; + } + imm |= (imm << 32); } - imm |= (imm << 32); } } break; + default: + fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); + g_assert_not_reached(); } if (cmode_3_1 != 7 && is_neg) { From patchwork Thu Feb 8 17:31:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127717 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1745672ljc; Thu, 8 Feb 2018 10:22:39 -0800 (PST) X-Google-Smtp-Source: AH8x224W6aN+P/9QUbwdVIgWVFCtvqmRPyem6pAgXLnm/FONxBSKgpzDpH632HmUl5V+aazwkI+Z X-Received: by 10.13.231.132 with SMTP id q126mr103652ywe.350.1518114159864; Thu, 08 Feb 2018 10:22:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518114159; cv=none; d=google.com; s=arc-20160816; b=tCrWaePOCv7Q/lTGs2oL+GRCeKXfxx/pDJ22IfGWAVV6nejBBbPpOFQXcVnvFkqkNa k20I3PBllNvVu1R/tRPa4fC0Yi1clAjY3AGYPUxPjbzffxddvHDD75ekmAMvIdTp1Doa j4Dg693JEVsdYs4CA+mvCZwRZ2+gxawaKdm+0c0Z8DjZ01niWEeVxHe0AHyzkb5650ri Wtf3qUsNU40WmWLhpTrAKiyxNerwzYhFPTvFCYNJYp1WLsrzFGCoRuVM7ttwC4bXpmus RU2ZF9mhDaahsksw2l3qIPF+IDtURa5XtEmaUQytfBWMaHJTZ1CphrcbJ15VeeCmmbLg uOXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0yDgimKm+CMDSWw8AX2+mTG+YAEGaWfAwu4YC6X2mjo=; b=fqNADe/fMJaHV/8wTDpalQ/Xzcd7HNUHI8OlS9hfY6J+MObXehWRXzYH3gYGjbUDVt qlIv+w9TFmtBlYUJs9l1KvnoOT0h5q1AD+mqW/Yn9hoYTNzUV4Tk/3J0qHYDbLXMvtVW 1wU+F+R+pqLtIbcHt+fJvHDImYf8B8m9Im+5aez9VQyXau/AdEqxAOF6Fr7ipXxNgh22 iFR81ADLbGCSfom1GJuwv9K2vKKvn1tQZ7oL1pA3ObWQ3XjS5cX/fKMflxop+3dHs6Yz bPyAxUIAmTDuq6xLH47CC4F794Oy/8/beDSiT7r8xRMzRTtsNsX5na5zwssM46GrCTND N0Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jEq8+5ol; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I only needed to do a little light re-factoring to support the half-precision helpers. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 80 +++++++++++++++++++++++++++++++--------------- 1 file changed, 54 insertions(+), 26 deletions(-) -- 2.15.1 Reviewed-by: Richard Henderson diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b209f57d55..b094399fb4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6371,24 +6371,30 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) case 0xf: /* FMAXP */ case 0x2c: /* FMINNMP */ case 0x2f: /* FMINP */ - /* FP op, size[0] is 32 or 64 bit */ + /* FP op, size[0] is 32 or 64 bit*/ if (!u) { - unallocated_encoding(s); - return; + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } else { + size = MO_16; + } + } else { + size = extract32(size, 0, 1) ? MO_64 : MO_32; } + if (!fp_access_check(s)) { return; } - size = extract32(size, 0, 1) ? 3 : 2; - fpst = get_fpstatus_ptr(false); + fpst = get_fpstatus_ptr(size == MO_16); break; default: unallocated_encoding(s); return; } - if (size == 3) { + if (size == MO_64) { TCGv_i64 tcg_op1 = tcg_temp_new_i64(); TCGv_i64 tcg_op2 = tcg_temp_new_i64(); TCGv_i64 tcg_res = tcg_temp_new_i64(); @@ -6429,27 +6435,49 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) TCGv_i32 tcg_op2 = tcg_temp_new_i32(); TCGv_i32 tcg_res = tcg_temp_new_i32(); - read_vec_element_i32(s, tcg_op1, rn, 0, MO_32); - read_vec_element_i32(s, tcg_op2, rn, 1, MO_32); + read_vec_element_i32(s, tcg_op1, rn, 0, size); + read_vec_element_i32(s, tcg_op2, rn, 1, size); - switch (opcode) { - case 0xc: /* FMAXNMP */ - gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xd: /* FADDP */ - gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0xf: /* FMAXP */ - gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2c: /* FMINNMP */ - gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); - break; - case 0x2f: /* FMINP */ - gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); - break; - default: - g_assert_not_reached(); + if (size == MO_16) { + switch (opcode) { + case 0xc: /* FMAXNMP */ + gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xd: /* FADDP */ + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FMAXP */ + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2c: /* FMINNMP */ + gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2f: /* FMINP */ + gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + } else { + switch (opcode) { + case 0xc: /* FMAXNMP */ + gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xd: /* FADDP */ + gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0xf: /* FMAXP */ + gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2c: /* FMINNMP */ + gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x2f: /* FMINP */ + gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } } write_fp_sreg(s, rd, tcg_res); From patchwork Thu Feb 8 17:31:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127701 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1722115ljc; Thu, 8 Feb 2018 09:55:08 -0800 (PST) X-Google-Smtp-Source: AH8x224i1LwBEssrsH2pEd9SZ0TBQC1lAPRZhI7sK43EsZqnObbrAc+8GAlE3MFkI60mFjKXgUb5 X-Received: by 10.129.87.141 with SMTP id l135mr1199104ywb.227.1518112508689; Thu, 08 Feb 2018 09:55:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518112508; cv=none; d=google.com; s=arc-20160816; b=M3fbvH742mgyf1O3XHML4rxZmuV0Pp9OVz5PqD93GpRVp7ryY+aivv0J5x3yPfUyHd jOtK7rHuGrHGC36Xgr2HOdWmacVHEWOzIIqJR7t8HmWsVpRQOPwTr7tUyf1kYlMTiqYh 0NvEQiuvbvjC5GBDHrc5tmn+klHCekntsy2c99Dv1nfAn4WJQ0QXAoqDEWLrOgoRLkok zuCvCw9dtBdS34lzxVzOfF8AVbHbjyDF2D0D+0o0XzqA/sXnsQ+oP3eWAWkNWZuufQGj ZLCjCCI96UIskBbeWz7JJC2+euAa6yhcUc2zv55+BguHGT6MI65D5xz1S4cO0+AJ8+zS dAlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=A695mZwIBbNF52PJP9rrQV0ErRNrUTdLHUaTuKmPooE=; b=KTMSwFjTOuX0BC3fl3JV5kmnTaBnxZ1l65HD6UnjEjsKKeiI2kpIZBwH2tf/7BSS3n UhNiDWCYQ+m4mMrZBq3c3kzIoeqLNUdXKtZFXPV1QrZYqGpKCh2RFotx/EEWvc+cMx7Z ToocyJhKyyCpM0tJ6iSmHbyLkscAmnfJeZNa3OMbD3A7L39OKnAein1SgiDJ+BYr+CO4 dPEJyLvWPoyprNFiNx0j+X15e0HHlqDaX2aQNMBZ36D+9c8Bx7l+S96KEQDz4AQH702G kwVhGNvWOjdLTYpPwXYWrgyglRPix86RrYWcWSrCVAPHeA4cfnNMUXYtPon9n+uwaIc8 WUmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JWS4BS9W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 31/32] arm/translate-a64: implement simd_scalar_three_reg_same_fp16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This covers the encoding group: Advanced SIMD scalar three same FP16 As all the helpers are already there it is simply a case of calling the existing helpers in the scalar context. Signed-off-by: Alex Bennée --- v2 - checkpatch fixes --- target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b094399fb4..92adf43a89 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7764,6 +7764,99 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_rd); } +/* AdvSIMD scalar three same FP16 + * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0 + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd | + * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+ + * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400 + * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400 + */ +static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s, uint32_t insn) +{ + int rd = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + int opcode = extract32(insn, 11, 3); + int rm = extract32(insn, 16, 5); + bool u = extract32(insn, 29, 1); + bool a = extract32(insn, 23, 1); + int fpopcode = opcode | (a << 3) | (u << 4); + TCGv_ptr fpst; + TCGv_i32 tcg_op1; + TCGv_i32 tcg_op2; + TCGv_i32 tcg_res; + + switch (fpopcode) { + case 0x03: /* FMULX */ + case 0x04: /* FCMEQ (reg) */ + case 0x07: /* FRECPS */ + case 0x0f: /* FRSQRTS */ + case 0x14: /* FCMGE (reg) */ + case 0x15: /* FACGE */ + case 0x1a: /* FABD */ + case 0x1c: /* FCMGT (reg) */ + case 0x1d: /* FACGT */ + break; + default: + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + fpst = get_fpstatus_ptr(true); + + tcg_op1 = tcg_temp_new_i32(); + tcg_op2 = tcg_temp_new_i32(); + tcg_res = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); + read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); + + switch (fpopcode) { + case 0x03: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x04: /* FCMEQ (reg) */ + gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x07: /* FRECPS */ + gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x0f: /* FRSQRTS */ + gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x14: /* FCMGE (reg) */ + gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1a: /* FABD */ + gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst); + gen_helper_advsimd_absh(tcg_res, tcg_res); + break; + case 0x1c: /* FCMGT (reg) */ + gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); + break; + default: + g_assert_not_reached(); + } + + write_fp_sreg(s, rd, tcg_res); + + + tcg_temp_free_i32(tcg_res); + tcg_temp_free_i32(tcg_op1); + tcg_temp_free_i32(tcg_op2); + tcg_temp_free_ptr(fpst); +} + static void handle_2misc_64(DisasContext *s, int opcode, bool u, TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus) @@ -9991,6 +10084,8 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst); break; default: + fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", + __func__, insn, fpopcode, s->pc); g_assert_not_reached(); } } @@ -11868,6 +11963,7 @@ static const AArch64DecodeTable data_proc_simd[] = { { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha }, { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 }, { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 }, + { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 }, { 0x00000000, 0x00000000, NULL } }; From patchwork Thu Feb 8 17:31:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 127714 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1740190ljc; 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 32/32] arm/translate-a64: add all single op FP16 to handle_fp_1src_half X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This includes FMOV, FABS, FNEG, FSQRT and FRINT[NPMZAXI]. We re-use existing helpers to achieve this. Signed-off-by: Alex Bennée --- target/arm/translate-a64.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) -- 2.15.1 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 92adf43a89..265bfb14d0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -4508,6 +4508,66 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn) tcg_temp_free_i64(t_true); } +/* Floating-point data-processing (1 source) - half precision */ +static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) +{ + TCGv_ptr fpst = NULL; + TCGv_i32 tcg_op; + TCGv_i32 tcg_res; + + tcg_op = read_fp_sreg(s, rn); + tcg_res = tcg_temp_new_i32(); + + switch (opcode) { + case 0x0: /* FMOV */ + tcg_gen_mov_i32(tcg_res, tcg_op); + break; + case 0x1: /* FABS */ + gen_helper_advsimd_absh(tcg_res, tcg_op); + break; + case 0x2: /* FNEG */ + tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); + break; + case 0x3: /* FSQRT */ + gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env); + break; + case 0x8: /* FRINTN */ + case 0x9: /* FRINTP */ + case 0xa: /* FRINTM */ + case 0xb: /* FRINTZ */ + case 0xc: /* FRINTA */ + { + TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); + fpst = get_fpstatus_ptr(true); + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); + + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); + tcg_temp_free_i32(tcg_rmode); + break; + } + case 0xe: /* FRINTX */ + fpst = get_fpstatus_ptr(true); + gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst); + break; + case 0xf: /* FRINTI */ + fpst = get_fpstatus_ptr(true); + gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); + break; + default: + abort(); + } + + write_fp_sreg(s, rd, tcg_res); + + if (fpst) { + tcg_temp_free_ptr(fpst); + } + tcg_temp_free_i32(tcg_op); + tcg_temp_free_i32(tcg_res); +} + /* Floating-point data-processing (1 source) - single precision */ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) { @@ -4734,6 +4794,18 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn) handle_fp_1src_double(s, opcode, rd, rn); break; + case 2: + if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { + unallocated_encoding(s); + return; + } + + if (!fp_access_check(s)) { + return; + } + + handle_fp_1src_half(s, opcode, rd, rn); + break; default: unallocated_encoding(s); }