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[192.237.175.120]) by mx.google.com with ESMTPS id j131si1703992ioj.178.2018.02.09.06.42.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Qcp+dlqi; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qA-0007xv-2a; Fri, 09 Feb 2018 14:39:50 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9q8-0007xL-L3 for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:39:48 +0000 X-Inumbo-ID: 0232fc81-0da7-11e8-ba59-bc764e045a96 Received: from mail-wm0-x244.google.com (unknown [2a00:1450:400c:c09::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 0232fc81-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:19 +0100 (CET) Received: by mail-wm0-x244.google.com with SMTP id g1so15780079wmg.2 for ; Fri, 09 Feb 2018 06:39:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=JR90OvA5Y35pIOwyAsJPQRVknZUmkLMt+2kQXOSFWnQ=; b=Qcp+dlqisw7DxjuPA9rBtR7BQqzK2Oe3MvtN3+xfuUiZydJ5Em0jZ12kORo0aX/guB 7TQrHtdCWGpHDgUl6Mb7zlm6/yfJivsun3W7qnCsn6YEwbaJ9hnV2FtHy0EwkcDm3FTO eku6TpWSLo61e6o9KvbqqbK0/K2X3jb5un9nM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=JR90OvA5Y35pIOwyAsJPQRVknZUmkLMt+2kQXOSFWnQ=; b=NFxGDntKaETadkeoVle5wcC7lH2+6Sdak9DDufz8ICchUrGneCsP9DhJOd6M/SrhFj lN8fX1Zcs/14Zn3cxmmC0MpLZ8PPbrgxB4weokHbAPwLORUHVRXOEp7WX7LL+0mZ+cJ5 z0V/Aka3ztEY/IPQ7lDVr0dzLvdEWHFSjFf60VOEb0lltY3fEUpCDG0jV7+6v1zsQbQ2 kWXEesunikNIRGTsdS1D5wjgoHFDF/uYO6JvyyuEndX+KK0hVt7raR1kOpM2pkZReBIU tP8IEZyNcDkJFehZe5QqThuXWqdUN47OncMtNinLEPJYpqpcd2Hw8NujVZ8bUaexNbEj WRWA== X-Gm-Message-State: APf1xPBZObcyaGROFjjV/EUmIjQN5IAUoC3sIF2b4FuwtKKLlPdwzbXr luWBlr7xpLmufqdX6RmOqlZLEA== X-Received: by 10.28.156.67 with SMTP id f64mr2396574wme.11.1518187186030; Fri, 09 Feb 2018 06:39:46 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:45 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:49 +0000 Message-Id: <20180209143937.28866-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 01/49] tools: ARM: vGICv3: avoid inserting optional DT properties X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When creating a GICv3 devicetree node, we currently insert the redistributor-stride and #redistributor-regions properties, with fixed values which are actually the architected ones. But those properties are optional and only needed to cover for broken platforms, where the values differ from the architected one. This will never be the case for the constructed DomU memory map. So we drop those properties altogether and provide a clean and architected GICv3 DT node for DomUs. Signed-off-by: Andre Przywara --- tools/libxl/libxl_arm.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 3e46554301..b5bba3cd33 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -524,14 +524,6 @@ static int make_gicv3_node(libxl__gc *gc, void *fdt) res = fdt_property(fdt, "interrupt-controller", NULL, 0); if (res) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - GUEST_GICV3_RDIST_STRIDE); - if (res) return res; - - res = fdt_property_cell(fdt, "#redistributor-regions", - GUEST_GICV3_RDIST_REGIONS); - if (res) return res; - res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, 2, gicd_base, gicd_size, From patchwork Fri Feb 9 14:38:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127842 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679865ljc; Fri, 9 Feb 2018 06:42:14 -0800 (PST) X-Google-Smtp-Source: AH8x225xfHo3kCiujzr0pUKnLxek8ts6NnJArqLre/ayPXf51UnGOdDVb27hwbeHBcdHtRwDLeh6 X-Received: by 10.36.60.203 with SMTP id m194mr3546666ita.96.1518187334517; Fri, 09 Feb 2018 06:42:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187334; cv=none; d=google.com; s=arc-20160816; b=wnCik303ArihfaQd6VvX/CzPWwpcZvoCOu6pqF6WLvfQptLWqjFxFWBFgRPAy4zLSz NrYy5jOM21ps4N9hebESjPOArCbUd/Oz1/tKYkKFbuk8iLD4JHV/GA8+lFxyYCbqYBgo +etEyXadct9mUPKvIpsMUd5nJNdWRr3wsuIjWqhpwB9rnRpz4b9OQyPc5/TDHCxV4YpD BtTqD0RMG5UHcXLgBJBX2aOEeyb7Bhzaqi4l6g7UraVDJMGCsuHGPha0adCvCV9eqmgt F0jQ2+ueS5lRRijwKoPpj5H+TdrkW/m09VSuR/YwGkmeeENSZdUacMPMAdmZ+wX66kgC Be0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=0Bh1Ou+BqLzJfG9BhedCs2upSrtdceAY0SMiYvaECWE=; b=Jc/SEJF1A/xDTo7K8hoZmIALJ+AMHG95r7pjuZYCiZbeiQh1Kj6z7DlumFPWu4zAb1 T7ON1OYR6RM57v2EsOC25eKvFWn4mVzmEgGOHyUSmmP2xtplsiadcLXJwBSLmvOM8Hwm YQ7FEWhna8BIqVTjqhNLNA/wGb2d/S8k/MmeGAXAN4nFy8XtDbYJmWUokG05nzNDNMzn uhwqoBuqQwsoVcGREPn7Al2Qsc0ZttMofZbVFuNAdBug1p+KYLDPdbLG8fzx/Qpt8I2F PehQC4dFdEdY8Ag+r+D4zbeodjBBTfVe9OL+PHcT1hiWOqjO74lMDtwShm6EHfxTLsnB cWWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O3II11vP; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:46 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:50 +0000 Message-Id: <20180209143937.28866-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 02/49] ARM: vGICv3: drop GUEST_GICV3_RDIST_REGIONS symbol X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Architecturally there is only one GICv3 redistributor region. Drop the symbol which suggested that was a delibarate choice for Xen guests, instead hard code the "1" in the appropriate places, along with a comment to explain the reasons. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic-v3.c | 17 ++++++++++++----- xen/include/public/arch-arm.h | 1 - 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 2ad8a6be62..12338c6b21 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1632,8 +1632,18 @@ static int vgic_v3_vcpu_init(struct vcpu *v) static inline unsigned int vgic_v3_rdist_count(struct domain *d) { - return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : - GUEST_GICV3_RDIST_REGIONS; + /* + * Architecturally there is only one GICv3 redistributor region. + * The GICv3 DT binding provisions for multiple regions, since there are + * platforms out there which break this architectural assumption. + * ACPI does not support this workaround at all. + * For Dom0 we have to live with the MMIO layout the hardware provides, + * so we have to copy the multiple regions - as the first region may not + * provide enough space to hold all redistributors we need. + * However DomU get a constructed memory map, so we can go with + * the architected single redistributor region. + */ + return is_hardware_domain(d) ? vgic_v3_hw.nr_rdist_regions : 1; } static int vgic_v3_domain_init(struct domain *d) @@ -1692,9 +1702,6 @@ static int vgic_v3_domain_init(struct domain *d) { d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE; - /* XXX: Only one Re-distributor region mapped for the guest */ - BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1); - d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; /* The first redistributor should contain enough space for all CPUs */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 05fd11ca38..ca79ab6284 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -402,7 +402,6 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) #define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000) -#define GUEST_GICV3_RDIST_REGIONS 1 #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) From patchwork Fri Feb 9 14:38:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127825 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679648ljc; Fri, 9 Feb 2018 06:42:02 -0800 (PST) X-Google-Smtp-Source: AH8x226SQBJXHrAaXYSaHGRu1gj6dWUqRYe880fILl3MhTYL3pVnQjJKiUvD74Xlmcdoek6nD0lo X-Received: by 10.36.69.78 with SMTP id y75mr4018106ita.9.1518187321978; Fri, 09 Feb 2018 06:42:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187321; cv=none; d=google.com; s=arc-20160816; b=O+VHV08D8ihQnhzZFh26STdpmgQX5pScuMwcev8TyTPaCb/2PErRg6/lhn8GnJOEqS CzzR6wr4CGWRhsHvEDXp1BYe4TUFZYE4KJJSVvS5Teivmw7lsyExA8S37BOznaSwU2Cy Wgt9/XkaoxZR9cOZ549Tdp3QaqflnGBOb/FmBqdBTyOjMZlhspqy4IG5N3koQy+C1oSx tl5/G1o7wyS+SytwVQu5S81foy4vXBj22Sf0Xoa/P3aihSm0B9HyGVyBtuqvDI4RDJCj lW6AIfF171glli3BpW4En0Jhq/CUqmLrjjh2RT6s2CZB4j6s9KshmMhkEp/XgPbjEwyo V/Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=UDZzCQLMa1X7QD69Tn3Kexc3mxmNehkzPnKAyd1nGFY=; b=igcrWGoUlsznly0ZUmKNA07q7EPvFNOZKsp2nkjYnRHEsQEIFaqooX/huw0dMcCwDi x72qXwBuRP/LIbE5HANDAlCoPQBAe3T9NWdAmTAQbyj+D53qqNin4wjuN8ife5Cc91hl fQp/okKX/9B0ToAo9m9jVhmKJW2s2yIlG58vAue9FHuwWtJT+q5wh5ov7zHmSoboCVHi MOUi+dI5PAswAXPuMcbuG2CaHy2D2s8PYcgu/Orl5RLC6ljIKAEvgffWvihhX43cdjOQ W5mKpviiaYo5UoPEhjR33V5SrmzGC+8XMr158NW0JN2kiOx8eFwOvj+vpi+YLG2kRkDU z8vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gwxczGNG; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:47 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:51 +0000 Message-Id: <20180209143937.28866-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 03/49] ARM: GICv3: use hardware GICv3 redistributor regions for Dom0 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The code to generate the DT node or MADT table for Dom0 reaches into the domain's VGIC structure to learn the number of redistributor regions and their base addresses. Since those values are copied from the hardware, we can as well use those hardware values directly when setting up the hardware domain. This avoids the hardware GIC code to reference vGIC data structures, making this variable VGIC internal. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 25c30bb9ea..bdca77417c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1167,8 +1167,7 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "#redistributor-regions", - d->arch.vgic.nr_regions); + res = fdt_property_cell(fdt, "#redistributor-regions", gicv3.rdist_count); if ( res ) return res; @@ -1178,7 +1177,7 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, * CPU interface and virtual cpu interfaces accessesed as System registers * So cells are created only for Distributor and rdist regions */ - new_len = new_len * (d->arch.vgic.nr_regions + 1); + new_len = new_len * (gicv3.rdist_count + 1); hw_reg = dt_get_property(gic, "reg", &len); if ( !hw_reg ) @@ -1406,13 +1405,13 @@ static int gicv3_make_hwdom_madt(const struct domain *d, u32 offset) /* Add Generic Redistributor */ size = sizeof(struct acpi_madt_generic_redistributor); - for ( i = 0; i < d->arch.vgic.nr_regions; i++ ) + for ( i = 0; i < gicv3.rdist_count; i++ ) { gicr = (struct acpi_madt_generic_redistributor *)(base_ptr + table_len); gicr->header.type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; gicr->header.length = size; - gicr->base_address = d->arch.vgic.rdist_regions[i].base; - gicr->length = d->arch.vgic.rdist_regions[i].size; + gicr->base_address = gicv3.rdist_regions[i].base; + gicr->length = gicv3.rdist_regions[i].size; table_len += size; } @@ -1425,8 +1424,7 @@ static unsigned long gicv3_get_hwdom_extra_madt_size(const struct domain *d) { unsigned long size; - size = sizeof(struct acpi_madt_generic_redistributor) - * d->arch.vgic.nr_regions; + size = sizeof(struct acpi_madt_generic_redistributor) * gicv3.rdist_count; size += sizeof(struct acpi_madt_generic_translator) * vgic_v3_its_count(d); From patchwork Fri Feb 9 14:38:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127834 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679775ljc; Fri, 9 Feb 2018 06:42:08 -0800 (PST) X-Google-Smtp-Source: AH8x227Ba0GLJfJilA2mrNOMWYPNUlNpY1cK5c5SYnHWDfbbfPNQ8rIGsJGroGT4sfFBG7TUL7Iz X-Received: by 10.36.181.87 with SMTP id j23mr3578706iti.48.1518187328217; Fri, 09 Feb 2018 06:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187328; cv=none; d=google.com; s=arc-20160816; b=KjHQkUJl5TeP+Wg2DbLCKPSAyyNqYoWGCHP6egka4Gz1g63uH4S/Uow/JrGMlJj8/0 b360Yb7mq5S0iN+gqcFSJ2OnbS0BgfzDJP99CK6NJMe8/zZxYh9nvt2noLEVy6EedglT gVj3jTUiShr5fyUg5R5rSYfnbDeCawaL7C/bbyKXsAiDrXthZ9lzLw3g2+vOY4JOxDt9 UQODLVscYrN/Q35NNrLbENsK18KV6Er4Z++R9kK+j40booBcu+fyqSwwPM9wi/5i8Z3Q 0odeF4PNOXmJ0F9+Con+dsfnYXcf2oni5euXnCnYKxRAm+2wEB3oSMGmOAsGhCZt8YHg ZUHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=88/pCnDcmau1jhFL5DHzpvjman9fqioQ6iisHGHOoww=; b=Wlz1Y0Jp07ZWaTGR6SbPk7jlEyaFjoQvZsnUzvpw7c+2hYy3N3WKAZsuw1zIRgfXu4 OkaNWx76DGCR2CTo3Sttsnj2NrawsXw7pWqHVXPQvV2wz/ZRytErG/WwSHwHmw/JxhDz UqoJ9g3R7IrZsThn20xhz7D7f38urkDuFek42Y3+HdNl4oKVtgqQaboAHKmr/1psEEYN gJ5a0mmhiVet2k80bcN2vIKpTXdvm90pUeBDn8tmPILbI5DX1cpedO2u5d72u+q3QoHw Dwt58jqx/2Oyt+Px0Zge4ok0hhvvyISDlWqbbsd7QPucStX9mexrnEa3MYcqZkTqRXni mJLg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VPWlYlT+; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:48 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:52 +0000 Message-Id: <20180209143937.28866-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 04/49] ARM: GICv3: simplify GICv3 redistributor stride handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Instead of hard coding the architected redistributor stride into the code, lets use a clear #define to the two values for GICv3 and GICv4 and clarify the algorithm to determine the needed stride value. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 18 ++++++++++-------- xen/include/asm-arm/gic_v3_defs.h | 5 +++++ 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bdca77417c..7837d93dc1 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -690,6 +690,15 @@ static int __init gicv3_populate_rdist(void) do { typer = readq_relaxed(ptr + GICR_TYPER); + /* Set the architectural redist size if not overridden by DT. */ + if ( !gicv3.rdist_stride ) + { + if ( typer & GICR_TYPER_VLPIS ) + gicv3.rdist_stride = GICV4_GICR_SIZE; + else + gicv3.rdist_stride = GICV3_GICR_SIZE; + } + if ( (typer >> 32) == aff ) { this_cpu(rbase) = ptr; @@ -732,14 +741,7 @@ static int __init gicv3_populate_rdist(void) if ( gicv3.rdist_regions[i].single_rdist ) break; - if ( gicv3.rdist_stride ) - ptr += gicv3.rdist_stride; - else - { - ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ - if ( typer & GICR_TYPER_VLPIS ) - ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ - } + ptr += gicv3.rdist_stride; } while ( !(typer & GICR_TYPER_LAST) ); } diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index 65c9dc47cf..412e41afed 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -18,6 +18,8 @@ #ifndef __ASM_ARM_GIC_V3_DEFS_H__ #define __ASM_ARM_GIC_V3_DEFS_H__ +#include + /* * Additional registers defined in GIC v3. * Common GICD registers are defined in gic.h @@ -68,6 +70,9 @@ #define GICV3_GICD_IIDR_VAL 0x34c #define GICV3_GICR_IIDR_VAL GICV3_GICD_IIDR_VAL +#define GICV3_GICR_SIZE (2 * SZ_64K) +#define GICV4_GICR_SIZE (4 * SZ_64K) + #define GICR_CTLR (0x0000) #define GICR_IIDR (0x0004) #define GICR_TYPER (0x0008) From patchwork Fri Feb 9 14:38:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127851 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679987ljc; Fri, 9 Feb 2018 06:42:22 -0800 (PST) X-Google-Smtp-Source: AH8x224dMaNPsTPgUaGiCgwbsKaA0WJswK6h9u9GvbcIGzYYp8MgRMgQedykErYZJ1orqOmamQWS X-Received: by 10.107.176.14 with SMTP id z14mr3141491ioe.8.1518187342394; Fri, 09 Feb 2018 06:42:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187342; cv=none; d=google.com; s=arc-20160816; b=q0POHpwBvKvdbmN/jdfUXkEbzaRfOkx/CXh5tUfRJoOUkbNs4S3JDuYA+KUCaA/3ns JJDwHGs3kcmDE2XqudvAeHqxUvHs4wi0nmd3vOJ1iS7p+Z9mQsr47ZzgjCj2goDxXG51 n1r0oCrj3SDFO6wM9KqVF7QlZ4kBE6zS1tD6zmyWbbJjunMX5o1GDMb2i22RoRKYmSsL UaN+m5kvw3dkFNB+4/byVtgeCNulEVycKlvglESuHHCBbOI/4T2UrWixKRcIhr+6UoAQ 53O/Vrn3oP2rjdFfjEs2XmvtQO8J1/66149Pts9IWEgU/Vpx2CU5+KJOP5YMc9tQ/39N 6iDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=at4BE4HMA7Q8dthVhqOWQuBF7b2V3/YertPfsPvVzKo=; b=RquEay1ECeH9h6+2JuvuQdYOoh2a0s2Yx1Olkv65sA1vhoLJfKLZhMp1vSOSgCDEpV 5MM0H6eINwoAf/H3h3xOrMVSHvcLnzIWvsyY6lD7Rp7A7CDiBXIqM+deGH0KUa5neV4U s5+ivK06HTwE37NhaWhnH0M6fVXEJeoeGrYbtiC2S13UOfrDeuqP/JZt9+8wFz2hDISV 4nPcNbFny6wWLXgEoDcQ6mY9htUNVAT0gF54lGhs2X/3yaBrQuM/bt930bDKE/HWRgBc 5v7bIJXYUzGa9E7E6USbao+YxhP3nRRL7MiHu/67DPj9eRT3fbAw+fKAdh1mvda3Sdh8 A4dQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Uign/kH9; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:49 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:53 +0000 Message-Id: <20180209143937.28866-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 05/49] ARM: vGICv3: always use architected redist stride X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The redistributor-stride property in a GICv3 DT node is only there to cover broken platforms where this value deviates from the architected one. Since we emulate the GICv3 distributor even for Dom0, we don't need to copy the broken behaviour. All the special handling for Dom0s using GICv3 is just for using the hardware's memory map, which is unaffected by the redistributor stride - it can never be smaller than the architected two pages. Remove the redistributor-stride property from Dom0's DT node and also remove the code that tried to reuse the hardware value for Dom0's GICv3 emulation. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 5 ----- xen/arch/arm/vgic-v3.c | 14 ++++++-------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 7837d93dc1..02c85e4c0c 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1164,11 +1164,6 @@ static int gicv3_make_hwdom_dt_node(const struct domain *d, if ( res ) return res; - res = fdt_property_cell(fdt, "redistributor-stride", - d->arch.vgic.rdist_stride); - if ( res ) - return res; - res = fdt_property_cell(fdt, "#redistributor-regions", gicv3.rdist_count); if ( res ) return res; diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index 12338c6b21..e45bbc6dcf 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1024,10 +1024,9 @@ static struct vcpu *get_vcpu_from_rdist(struct domain *d, paddr_t gpa, uint32_t *offset) { struct vcpu *v; - uint32_t stride = d->arch.vgic.rdist_stride; unsigned int vcpu_id; - vcpu_id = region->first_cpu + ((gpa - region->base) / stride); + vcpu_id = region->first_cpu + ((gpa - region->base) / GICV3_GICR_SIZE); if ( unlikely(vcpu_id >= d->max_vcpus) ) return NULL; @@ -1586,7 +1585,6 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Convenient alias */ struct domain *d = v->domain; - uint32_t rdist_stride = d->arch.vgic.rdist_stride; /* * Find the region where the re-distributor lives. For this purpose, @@ -1602,11 +1600,11 @@ static int vgic_v3_vcpu_init(struct vcpu *v) /* Get the base address of the redistributor */ rdist_base = region->base; - rdist_base += (v->vcpu_id - region->first_cpu) * rdist_stride; + rdist_base += (v->vcpu_id - region->first_cpu) * GICV3_GICR_SIZE; /* Check if a valid region was found for the re-distributor */ if ( (rdist_base < region->base) || - ((rdist_base + rdist_stride) > (region->base + region->size)) ) + ((rdist_base + GICV3_GICR_SIZE) > (region->base + region->size)) ) { dprintk(XENLOG_ERR, "d%u: Unable to find a re-distributor for VCPU %u\n", @@ -1622,7 +1620,7 @@ static int vgic_v3_vcpu_init(struct vcpu *v) * VGIC_V3_RDIST_LAST flags. * Note that we are assuming max_vcpus will never change. */ - last_cpu = (region->size / rdist_stride) + region->first_cpu - 1; + last_cpu = (region->size / GICV3_GICR_SIZE) + region->first_cpu - 1; if ( v->vcpu_id == last_cpu || (v->vcpu_id == (d->max_vcpus - 1)) ) v->arch.vgic.flags |= VGIC_V3_RDIST_LAST; @@ -1693,7 +1691,7 @@ static int vgic_v3_domain_init(struct domain *d) /* Set the first CPU handled by this region */ d->arch.vgic.rdist_regions[i].first_cpu = first_cpu; - first_cpu += size / d->arch.vgic.rdist_stride; + first_cpu += size / GICV3_GICR_SIZE; } d->arch.vgic.intid_bits = vgic_v3_hw.intid_bits; @@ -1705,7 +1703,7 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; /* The first redistributor should contain enough space for all CPUs */ - BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GUEST_GICV3_RDIST_STRIDE) < MAX_VIRT_CPUS); + BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE; d->arch.vgic.rdist_regions[0].first_cpu = 0; From patchwork Fri Feb 9 14:38:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127828 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679694ljc; Fri, 9 Feb 2018 06:42:04 -0800 (PST) X-Google-Smtp-Source: AH8x226iMNF9iu7h1up0iaXULjdv2QQ2EEJXwU4GN5zD5BSV/KAqQMfxsXRJv+w711qNsuXCbB0B X-Received: by 10.36.222.134 with SMTP id d128mr3854037itg.150.1518187324435; Fri, 09 Feb 2018 06:42:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187324; cv=none; d=google.com; s=arc-20160816; b=s0XKizY7x5UOk5isfkCc3JnzIR1YO1QT1YxG+CFVzCkGFkm79HgR0h/y5IXRk2XKUo Hf5OjIu5ViH6kAETDl5okbS4Iyy2k7FN0x23sLw37jn2DO3y+l0iF9jQuJVboWrulNEU fX9EL5d2bcqYS6NSv05zWpQbP1/sQc9XoFcLX6evz3Iw6MJh4FriDcPHO/KmC9UeqYBQ beFG2IcxQYqlTEPwU/NczGTtZrgqrDBPsZer5iW1WacgCQIJYJLn1g4ujESEm97QgB3E BGN3D/iVPzM6gyte6Zts01zHkn+ANlqq2neUtFNshVrolLHZZHId8n5szHEOM2uw7Hsu 0CtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=JRw0t5jSxsomgYXDPVMqXw5JBxIGFdzWQhPs4dgL4P8=; b=B8vLkcAF+OXqsw+Y6rt5l6J/oXx1K2IAssSBsUts+EehGgfFYdCbWjkjOM2nG+0qkb a0D1Q167TR2R32LEgg2tyOmHuSDnDpqYBTzbpq8SIMbbXlBfddPRy/a3humzyAXA2PSx LOBH+1vBWLIDRsSdK5VrBR82rgw2DnZtlw2bew8RJUPFV5U36Th3WPkp32vAiyEudi9Q 08XRyH+jAOPYek8NNIzEor0NG1g8MfTAnSlfMhHVWnSav6nX1yZJF5b6Lry3X4MAO5ky LnXZ4LxeXmDmJ8IsX8Wd2JQEkUmPRTkRRoI/I6ujsI8kO7uoh4Y0MXz7ZdeHMmHAJlLW 9dcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DeQW6+a3; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:51 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:54 +0000 Message-Id: <20180209143937.28866-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 06/49] ARM: vGICv3: remove rdist_stride from VGIC structure X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The last patch removed the usage of the hardware's redistributor-stride value from our (Dom0) GICv3 emulation. This means we no longer need to store this value in the VGIC data structure. Remove that variable and every code snippet that handled that, instead simply always use the architected value. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v3.c | 3 +-- xen/arch/arm/vgic-v3.c | 14 -------------- xen/include/asm-arm/domain.h | 1 - xen/include/asm-arm/vgic.h | 1 - xen/include/public/arch-arm.h | 2 -- 5 files changed, 1 insertion(+), 20 deletions(-) diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 02c85e4c0c..ea14ab4028 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1682,8 +1682,7 @@ static int __init gicv3_init(void) reg = readl_relaxed(GICD + GICD_TYPER); intid_bits = GICD_TYPE_ID_BITS(reg); - vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, - gicv3.rdist_stride, intid_bits); + vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions, intid_bits); gicv3_init_v2(); spin_lock_init(&gicv3.lock); diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index e45bbc6dcf..9b1b62744c 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -58,21 +58,18 @@ static struct { /* Re-distributor regions */ unsigned int nr_rdist_regions; const struct rdist_region *regions; - uint32_t rdist_stride; /* Re-distributor stride */ unsigned int intid_bits; /* Number of interrupt ID bits */ } vgic_v3_hw; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits) { vgic_v3_hw.enabled = true; vgic_v3_hw.dbase = dbase; vgic_v3_hw.nr_rdist_regions = nr_rdist_regions; vgic_v3_hw.regions = regions; - vgic_v3_hw.rdist_stride = rdist_stride; vgic_v3_hw.intid_bits = intid_bits; } @@ -1672,15 +1669,6 @@ static int vgic_v3_domain_init(struct domain *d) d->arch.vgic.dbase = vgic_v3_hw.dbase; - d->arch.vgic.rdist_stride = vgic_v3_hw.rdist_stride; - /* - * If the stride is not set, the default stride for GICv3 is 2 * 64K: - * - first 64k page for Control and Physical LPIs - * - second 64k page for Control and Generation of SGIs - */ - if ( !d->arch.vgic.rdist_stride ) - d->arch.vgic.rdist_stride = 2 * SZ_64K; - for ( i = 0; i < vgic_v3_hw.nr_rdist_regions; i++ ) { paddr_t size = vgic_v3_hw.regions[i].size; @@ -1700,8 +1688,6 @@ static int vgic_v3_domain_init(struct domain *d) { d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE; - d->arch.vgic.rdist_stride = GUEST_GICV3_RDIST_STRIDE; - /* The first redistributor should contain enough space for all CPUs */ BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) < MAX_VIRT_CPUS); d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE; diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 4fe189b1c3..3eda7196ff 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -108,7 +108,6 @@ struct arch_domain unsigned int first_cpu; /* First CPU handled */ } *rdist_regions; int nr_regions; /* Number of rdist regions */ - uint32_t rdist_stride; /* Re-Distributor stride */ unsigned long int nr_lpis; uint64_t rdist_propbase; struct rb_root its_devices; /* Devices mapped to an ITS */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 6ea9f140a7..d61b54867b 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -261,7 +261,6 @@ struct rdist_region; void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, const struct rdist_region *regions, - uint32_t rdist_stride, unsigned int intid_bits); #endif diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index ca79ab6284..3bca165fbf 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -401,8 +401,6 @@ typedef uint64_t xen_callback_t; #define GUEST_GICV3_GICD_BASE xen_mk_ullong(0x03001000) #define GUEST_GICV3_GICD_SIZE xen_mk_ullong(0x00010000) -#define GUEST_GICV3_RDIST_STRIDE xen_mk_ullong(0x00020000) - #define GUEST_GICV3_GICR0_BASE xen_mk_ullong(0x03020000) /* vCPU0..127 */ #define GUEST_GICV3_GICR0_SIZE xen_mk_ullong(0x01000000) From patchwork Fri Feb 9 14:38:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127827 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679685ljc; Fri, 9 Feb 2018 06:42:04 -0800 (PST) X-Google-Smtp-Source: AH8x2240kieYh/yeFB3u5+RZf2UMnu2Wg1PhvFpL8qEoH/ABNCnb2fUgQKmiYWspzlXYyBhv6dE2 X-Received: by 10.107.141.147 with SMTP id p141mr3206746iod.79.1518187324109; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:52 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:55 +0000 Message-Id: <20180209143937.28866-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 07/49] ARM: VGIC: move gic_remove_from_lr_pending() prototype X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The prototype for gic_remove_from_lr_pending() is the last function in gic.h which references a VGIC data structure. Move it over to vgic.h, so that we can remove the inclusion of vgic.h from gic.h. We add it to asm/domain.h instead, where it is actually needed. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/include/asm-arm/domain.h | 1 + xen/include/asm-arm/gic.h | 2 -- xen/include/asm-arm/vgic.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 3eda7196ff..1dd9683d25 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 497f195bc1..1d382b0ade 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -156,7 +156,6 @@ #ifndef __ASSEMBLY__ #include #include -#include #define DT_COMPAT_GIC_CORTEX_A15 "arm,cortex-a15-gic" @@ -245,7 +244,6 @@ extern void init_maintenance_interrupt(void); extern void gic_raise_guest_irq(struct vcpu *v, unsigned int irq, unsigned int priority); extern void gic_raise_inflight_irq(struct vcpu *v, unsigned int virtual_irq); -extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); /* Accept an interrupt from the GIC and dispatch its handler */ extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq); diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index d61b54867b..d03298e12c 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -205,6 +205,7 @@ extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq); extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); +extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); extern void vgic_init_pending_irq(struct pending_irq *p, unsigned int virq); extern struct pending_irq *irq_to_pending(struct vcpu *v, unsigned int irq); From patchwork Fri Feb 9 14:38:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127832 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679729ljc; Fri, 9 Feb 2018 06:42:06 -0800 (PST) X-Google-Smtp-Source: AH8x224DDSolLgYIEIrsQj6GQYTbGRi0mHL7kiLgTt//p+y+4pIeAyVrOAsN+iJM7ghPpPFDRhbw X-Received: by 10.36.239.130 with SMTP id i124mr3753691ith.27.1518187326669; Fri, 09 Feb 2018 06:42:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187326; cv=none; d=google.com; s=arc-20160816; b=q6D2vtnLeDa2niDpGjt98WSmK1Ew+kNyFTTr0T3AXApiRccyVT6mQDk41dXE0oDa+k J/1TfC8vR68iOTo/ahiWTMcPdCrKVwdp+KbICIjUq9Bi+kdhEyPGPPgAUMR93zn1w5xp PF5YBBLaSuRZW+j+RdNIq73i1FI/JJZ6LPm8aHTyc54k5tcEqyDuclC1HOV0uJzdDVd9 qe+VwrJ34edja9/t+yoJtot9lxR+UYA6LWcyh2rtxBtt/LqlcYY1amXKdzHzkFAyKHvx XokBqdCfliqIv7gnC7kSvoA6thXRtevc9+0DWJUkQ9MEvTnvwfX7z7eb9e30FVFZ9eaR izAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=/gEd8uW/E6HdpLQpYd/lQHuGPYBcS3bv4cMEQ6V/aCk=; b=llFwItX5uN8JKFfzuwjtkOpjVf697ANbD/OE4+VHgL9u9yQy4LMqUfxoZJJQIkO0LE AHi0VPI5J+IwqDUtzJ+wU26E9jvFRBpWyQ0CNhOAUX+O4UaHF7dJKAUdZPEHKeOG+sS+ 3v1VZh+EXSnoARTCkwKyJXH70Aj7ah77SiDhoR7IlBd2ZnhiwiSCK7ADh6wtqpHc2B9q PeMAkq2XeAQ6wr9MIWV81iDLmikDAW1XhNzOoEvB9fKq6dwdplfXzjGpJFHlQjLUNeXv zQY++4OwMrUQh0xCh/44eBxciimd/F6HOkthg9oDWLX4Uhf4mAuLLkjLv8alxQwOkkGG OnLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Nn+1/VoR; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:53 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:56 +0000 Message-Id: <20180209143937.28866-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 08/49] ARM: VGIC: move max_vcpus VGIC limit to struct arch_domain X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The VGIC model used for a domain (GICv2 or GICv3) determines the maximum number of VCPUs for that guest, as GICv2 can only handle 8 processors. In the moment we carry this per-VGIC-model limit in the vgic_ops, alongside the model specific functions. That makes some sense, but exposes some current VGIC implementation details to generic Xen code. Add a new arch specific field in our domain structure to hold this vcpu limit, and initialize it when we set the ops. This allows us to plug in the new VGIC later without also needing to carry some ops structure. Signed-off-by: Andre Przywara --- xen/arch/arm/domain.c | 5 ++--- xen/arch/arm/vgic.c | 3 ++- xen/include/asm-arm/domain.h | 1 + 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index a010443bfd..9ad4cd0a6e 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -975,11 +975,10 @@ unsigned int domain_max_vcpus(const struct domain *d) * allocation when the vgic_ops haven't been initialised yet, * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null. */ - if ( !d->arch.vgic.handler ) + if ( !d->arch.max_vcpus ) return MAX_VIRT_CPUS; else - return min_t(unsigned int, MAX_VIRT_CPUS, - d->arch.vgic.handler->max_vcpus); + return d->arch.max_vcpus; } /* diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 9921769b15..5f47aa84a9 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -166,7 +166,8 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis) void register_vgic_ops(struct domain *d, const struct vgic_ops *ops) { - d->arch.vgic.handler = ops; + d->arch.vgic.handler = ops; + d->arch.max_vcpus = ops->max_vcpus; } void domain_vgic_free(struct domain *d) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 1dd9683d25..2fef32eaee 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -149,6 +149,7 @@ struct arch_domain #ifdef CONFIG_SBSA_VUART_CONSOLE struct vpl011 vpl011; #endif + unsigned int max_vcpus; } __cacheline_aligned; From patchwork Fri Feb 9 14:38:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127853 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680073ljc; Fri, 9 Feb 2018 06:42:30 -0800 (PST) X-Google-Smtp-Source: AH8x225O3sSUQnlrbNXVnRYb8KWKlBmhN2Wrd7wZSsVuUZmRjddI72UzcmcCsopb+xZCh9p4gyka X-Received: by 10.107.17.37 with SMTP id z37mr3036209ioi.282.1518187349888; Fri, 09 Feb 2018 06:42:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187349; cv=none; d=google.com; s=arc-20160816; b=KgPlSltFw1lBQRTt41rFLrffCtPumquXOF+pnrKV1g0zBX6KcnhmJC0tS+aVGyvaqc itZhtLkwJzICS1/y6+IkCyaxIzDB/9NEc1RXtgSvG5v8fltKI/sj9uF+ee0vxSf5uP/w HexuwWL6wewlle5TpEucRxhzxhpS6k3qsvoMSBiqkvhHCq2U/mZBjdhc7zclBd4hXVFz 0qavBruJkBmw2lTNOGfq56C2FtH+9vSD2z2A5ua9NHp8/FXGf/PS6PZ6zkSs10cIk4DQ tGdW59pxh6YqL9SZdpeJugFCdHonpaEjER0oX1GWnp3rbtzMijWgiUVGpxHwybxGekac jwXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=i3tgaSk5H9uhAf7OqYvM0iT35hxQNU8ZM2fWFPmuQLw=; b=jgd6pB9UX4NoGbec/pi4oWH7cKN9nobPiBpqFZxiBJ3gsnsEoywkTDBh0s0kau2nh2 sgcKvghTJHRHt1LoK87RUK6HQS3LICQs8eX/+xxmNZmQAHiu0whKzD+BtzCeDsqyt7OG iSgeL1HBOXXr5nXcgHrMz0m4eeMCwxWnI2QML8dBDpxPqTLKWCC7Ni8E5DSOQYgc1iYr nZ3ObmC2/YDdjFXJkzuseNLU34gNZOIXlzlHBvoKjBXUB0S28X3pyYqC1ci9g8BPITU1 9mDb0PneRaKuCF11JbwHGM7bCM5gbzClM4AS4go4SHIlbryWR0UxMSpvKBR9h5iA8aD4 fiYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Tx9GrF7h; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:54 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:57 +0000 Message-Id: <20180209143937.28866-10-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 09/49] ARM: VGIC: change to level-IRQ compatible IRQ injection interface X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment vgic_vcpu_inject_irq() is the interface for Xen internal code and virtual devices to inject IRQs into a guest. This interface has two shortcomings: 1) It requires a VCPU pointer, which we may not know (and don't need!) for shared interrupts. A second function (vgic_vcpu_inject_spi()), was there to work around this issue. 2) This interface only really supports edge triggered IRQs, which is what the Xen VGIC emulates only anyway. However this needs to and will change, so we need to add the desired level (high or low) to the interface. This replaces the existing injection call (taking a VCPU and and IRQ parameter) with a new one, taking domain, VCPU, IRQ and level parameters. The VCPU can be NULL in case we don't know and don't care. We change all call sites to use this new interface. This still doesn't give us the missing level IRQ handling, but at least prepares the callers to do the right thing later automatically. Signed-off-by: Andre Przywara --- xen/arch/arm/domain.c | 4 ++-- xen/arch/arm/gic-v3-lpi.c | 2 +- xen/arch/arm/irq.c | 2 +- xen/arch/arm/time.c | 2 +- xen/arch/arm/vgic.c | 43 +++++++++++++++++++++++++------------------ xen/arch/arm/vpl011.c | 2 +- xen/arch/arm/vtimer.c | 4 ++-- xen/include/asm-arm/vgic.h | 4 ++-- 8 files changed, 35 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 9ad4cd0a6e..e76cfdfe83 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -952,14 +952,14 @@ void vcpu_mark_events_pending(struct vcpu *v) if ( already_pending ) return; - vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, * ignoring the CPSR register, *after* calling SCHEDOP_block to - * avoid races with vgic_vcpu_inject_irq. + * avoid races with vgic_inject_irq. */ void vcpu_block_unless_event_pending(struct vcpu *v) { diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c index 84582157b8..efd5cd62fb 100644 --- a/xen/arch/arm/gic-v3-lpi.c +++ b/xen/arch/arm/gic-v3-lpi.c @@ -153,7 +153,7 @@ void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq) if ( vcpu_id >= d->max_vcpus ) return; - vgic_vcpu_inject_irq(d->vcpu[vcpu_id], virq); + vgic_inject_irq(d, d->vcpu[vcpu_id], virq, true); } /* diff --git a/xen/arch/arm/irq.c b/xen/arch/arm/irq.c index 29af10e82c..aa4e832cae 100644 --- a/xen/arch/arm/irq.c +++ b/xen/arch/arm/irq.c @@ -225,7 +225,7 @@ void do_IRQ(struct cpu_user_regs *regs, unsigned int irq, int is_fiq) * The irq cannot be a PPI, we only support delivery of SPIs to * guests. */ - vgic_vcpu_inject_spi(info->d, info->virq); + vgic_inject_irq(info->d, NULL, info->virq, true); goto out_no_end; } diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 36f640f0c1..c11fcfeadd 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -260,7 +260,7 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) current->arch.virt_timer.ctl = READ_SYSREG32(CNTV_CTL_EL0); WRITE_SYSREG32(current->arch.virt_timer.ctl | CNTx_CTL_MASK, CNTV_CTL_EL0); - vgic_vcpu_inject_irq(current, current->arch.virt_timer.irq); + vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq, true); } /* diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 5f47aa84a9..2fc6e19625 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -285,7 +285,7 @@ bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq) vgic_remove_irq_from_queues(old, p); irq_set_affinity(p->desc, cpumask_of(new->processor)); spin_unlock_irqrestore(&old->arch.vgic.lock, flags); - vgic_vcpu_inject_irq(new, irq); + vgic_inject_irq(new->domain, new, irq, true); return true; } /* if the IRQ is in a GICH_LR register, set GIC_IRQ_GUEST_MIGRATING @@ -444,7 +444,7 @@ bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, sgir, target->list); continue; } - vgic_vcpu_inject_irq(d->vcpu[vcpuid], virq); + vgic_inject_irq(d, d->vcpu[vcpuid], virq, true); } break; case SGI_TARGET_OTHERS: @@ -453,12 +453,12 @@ bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, { if ( i != current->vcpu_id && d->vcpu[i] != NULL && is_vcpu_online(d->vcpu[i]) ) - vgic_vcpu_inject_irq(d->vcpu[i], virq); + vgic_inject_irq(d, d->vcpu[i], virq, true); } break; case SGI_TARGET_SELF: perfc_incr(vgic_sgi_self); - vgic_vcpu_inject_irq(d->vcpu[current->vcpu_id], virq); + vgic_inject_irq(d, current, virq, true); break; default: gprintk(XENLOG_WARNING, @@ -518,13 +518,29 @@ void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p) gic_remove_from_lr_pending(v, p); } -void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) +int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level) { uint8_t priority; struct pending_irq *iter, *n; unsigned long flags; bool running; + /* + * For edge triggered interrupts we always ignore a "falling edge". + * For level triggered interrupts we shouldn't, but do anyways. + */ + if ( !level ) + return 0; + + if ( !v ) + { + /* The IRQ needs to be an SPI if no vCPU is specified. */ + ASSERT(virq >= 32 && virq <= vgic_num_irqs(d)); + + v = vgic_get_target_vcpu(d->vcpu[0], virq); + }; + spin_lock_irqsave(&v->arch.vgic.lock, flags); n = irq_to_pending(v, virq); @@ -532,14 +548,14 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq) if ( unlikely(!n) ) { spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return; + return 0; } /* vcpu offline */ if ( test_bit(_VPF_down, &v->pause_flags) ) { spin_unlock_irqrestore(&v->arch.vgic.lock, flags); - return; + return 0; } set_bit(GIC_IRQ_GUEST_QUEUED, &n->status); @@ -576,22 +592,13 @@ out: perfc_incr(vgic_cross_cpu_intr_inject); smp_send_event_check_mask(cpumask_of(v->processor)); } -} - -void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq) -{ - struct vcpu *v; - /* the IRQ needs to be an SPI */ - ASSERT(virq >= 32 && virq <= vgic_num_irqs(d)); - - v = vgic_get_target_vcpu(d->vcpu[0], virq); - vgic_vcpu_inject_irq(v, virq); + return 0; } void arch_evtchn_inject(struct vcpu *v) { - vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq); + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } bool vgic_evtchn_irq_pending(struct vcpu *v) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 7788c2fc32..5dcf4bec18 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -68,7 +68,7 @@ static void vpl011_update_interrupt_status(struct domain *d) * status bit has been set since the last time. */ if ( uartmis & ~vpl011->shadow_uartmis ) - vgic_vcpu_inject_spi(d, GUEST_VPL011_SPI); + vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); vpl011->shadow_uartmis = uartmis; } diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index f52a723a5f..8164f6c7f1 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -46,7 +46,7 @@ static void phys_timer_expired(void *data) if ( !(t->ctl & CNTx_CTL_MASK) ) { perfc_incr(vtimer_phys_inject); - vgic_vcpu_inject_irq(t->v, t->irq); + vgic_inject_irq(t->v->domain, t->v, t->irq, true); } else perfc_incr(vtimer_phys_masked); @@ -56,7 +56,7 @@ static void virt_timer_expired(void *data) { struct vtimer *t = data; t->ctl |= CNTx_CTL_MASK; - vgic_vcpu_inject_irq(t->v, t->irq); + vgic_inject_irq(t->v->domain, t->v, t->irq, true); perfc_incr(vtimer_virt_inject); } diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index d03298e12c..b75fdeb068 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -202,8 +202,8 @@ extern int domain_vgic_init(struct domain *d, unsigned int nr_spis); extern void domain_vgic_free(struct domain *d); extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); -extern void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int virq); -extern void vgic_vcpu_inject_spi(struct domain *d, unsigned int virq); +extern int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); From patchwork Fri Feb 9 14:38:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127838 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679813ljc; Fri, 9 Feb 2018 06:42:10 -0800 (PST) X-Google-Smtp-Source: AH8x225dp7YFIgUfs7HpSyU06ljM5j7fdC/L+pPqwDaSEx7BU6yIpVIfKoHok182tZRV5jkm+Cpa X-Received: by 10.107.170.234 with SMTP id g103mr3382191ioj.240.1518187330011; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:55 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:58 +0000 Message-Id: <20180209143937.28866-11-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 10/49] ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently we describe the VGIC specific fields in an structure *embedded* in struct arch_domain and struct arch_vcpu. These members there are however related to the current VGIC implementation, and will be substantially different in the future. To allow coexistence of two implementations, move the definition of these embedded structures into vgic.h, and just use the opaque type in the arch specific structures. This allows easy switching between different implementations later. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/include/asm-arm/domain.h | 85 +----------------------------------------- xen/include/asm-arm/vgic.h | 88 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+), 83 deletions(-) diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 2fef32eaee..968ffb0c81 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -74,57 +74,7 @@ struct arch_domain uint64_t offset; } virt_timer_base; - struct { - /* Version of the vGIC */ - enum gic_version version; - /* GIC HW version specific vGIC driver handler */ - const struct vgic_ops *handler; - /* - * Covers access to other members of this struct _except_ for - * shared_irqs where each member contains its own locking. - * - * If both class of lock is required then this lock must be - * taken first. If multiple rank locks are required (including - * the per-vcpu private_irqs rank) then they must be taken in - * rank order. - */ - spinlock_t lock; - uint32_t ctlr; - int nr_spis; /* Number of SPIs */ - unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ - struct vgic_irq_rank *shared_irqs; - /* - * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in - * struct arch_vcpu. - */ - struct pending_irq *pending_irqs; - /* Base address for guest GIC */ - paddr_t dbase; /* Distributor base address */ -#ifdef CONFIG_HAS_GICV3 - /* GIC V3 addressing */ - /* List of contiguous occupied by the redistributors */ - struct vgic_rdist_region { - paddr_t base; /* Base address */ - paddr_t size; /* Size */ - unsigned int first_cpu; /* First CPU handled */ - } *rdist_regions; - int nr_regions; /* Number of rdist regions */ - unsigned long int nr_lpis; - uint64_t rdist_propbase; - struct rb_root its_devices; /* Devices mapped to an ITS */ - spinlock_t its_devices_lock; /* Protects the its_devices tree */ - struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */ - rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */ - struct list_head vits_list; /* List of virtual ITSes */ - unsigned int intid_bits; - /* - * TODO: if there are more bool's being added below, consider - * a flags variable instead. - */ - bool rdists_enabled; /* Is any redistributor enabled? */ - bool has_its; -#endif - } vgic; + struct vgic_dist vgic; struct vuart { #define VUART_BUF_SIZE 128 @@ -248,38 +198,7 @@ struct arch_vcpu union gic_state_data gic; uint64_t lr_mask; - struct { - /* - * SGIs and PPIs are per-VCPU, SPIs are domain global and in - * struct arch_domain. - */ - struct pending_irq pending_irqs[32]; - struct vgic_irq_rank *private_irqs; - - /* This list is ordered by IRQ priority and it is used to keep - * track of the IRQs that the VGIC injected into the guest. - * Depending on the availability of LR registers, the IRQs might - * actually be in an LR, and therefore injected into the guest, - * or queued in gic.lr_pending. - * As soon as an IRQ is EOI'd by the guest and removed from the - * corresponding LR it is also removed from this list. */ - struct list_head inflight_irqs; - /* lr_pending is used to queue IRQs (struct pending_irq) that the - * vgic tried to inject in the guest (calling gic_set_guest_irq) but - * no LRs were available at the time. - * As soon as an LR is freed we remove the first IRQ from this - * list and write it to the LR register. - * lr_pending is a subset of vgic.inflight_irqs. */ - struct list_head lr_pending; - spinlock_t lock; - - /* GICv3: redistributor base and flags for this vCPU */ - paddr_t rdist_base; - uint64_t rdist_pendbase; -#define VGIC_V3_RDIST_LAST (1 << 0) /* last vCPU of the rdist */ -#define VGIC_V3_LPIS_ENABLED (1 << 1) - uint8_t flags; - } vgic; + struct vgic_cpu vgic; /* Timer registers */ uint32_t cntkctl; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index b75fdeb068..4e1c37f091 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -19,6 +19,9 @@ #define __ASM_ARM_VGIC_H__ #include +#include +#include +#include #include #include @@ -123,6 +126,91 @@ struct vgic_irq_rank { uint8_t vcpu[32]; }; +struct vgic_dist { + /* Version of the vGIC */ + enum gic_version version; + /* GIC HW version specific vGIC driver handler */ + const struct vgic_ops *handler; + /* + * Covers access to other members of this struct _except_ for + * shared_irqs where each member contains its own locking. + * + * If both class of lock is required then this lock must be + * taken first. If multiple rank locks are required (including + * the per-vcpu private_irqs rank) then they must be taken in + * rank order. + */ + spinlock_t lock; + uint32_t ctlr; + int nr_spis; /* Number of SPIs */ + unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ + struct vgic_irq_rank *shared_irqs; + /* + * SPIs are domain global, SGIs and PPIs are per-VCPU and stored in + * struct arch_vcpu. + */ + struct pending_irq *pending_irqs; + /* Base address for guest GIC */ + paddr_t dbase; /* Distributor base address */ +#ifdef CONFIG_HAS_GICV3 + /* GIC V3 addressing */ + /* List of contiguous occupied by the redistributors */ + struct vgic_rdist_region { + paddr_t base; /* Base address */ + paddr_t size; /* Size */ + unsigned int first_cpu; /* First CPU handled */ + } *rdist_regions; + int nr_regions; /* Number of rdist regions */ + unsigned long int nr_lpis; + uint64_t rdist_propbase; + struct rb_root its_devices; /* Devices mapped to an ITS */ + spinlock_t its_devices_lock; /* Protects the its_devices tree */ + struct radix_tree_root pend_lpi_tree; /* Stores struct pending_irq's */ + rwlock_t pend_lpi_tree_lock; /* Protects the pend_lpi_tree */ + struct list_head vits_list; /* List of virtual ITSes */ + unsigned int intid_bits; + /* + * TODO: if there are more bool's being added below, consider + * a flags variable instead. + */ + bool rdists_enabled; /* Is any redistributor enabled? */ + bool has_its; +#endif +}; + +struct vgic_cpu { + /* + * SGIs and PPIs are per-VCPU, SPIs are domain global and in + * struct arch_domain. + */ + struct pending_irq pending_irqs[32]; + struct vgic_irq_rank *private_irqs; + + /* This list is ordered by IRQ priority and it is used to keep + * track of the IRQs that the VGIC injected into the guest. + * Depending on the availability of LR registers, the IRQs might + * actually be in an LR, and therefore injected into the guest, + * or queued in gic.lr_pending. + * As soon as an IRQ is EOI'd by the guest and removed from the + * corresponding LR it is also removed from this list. */ + struct list_head inflight_irqs; + /* lr_pending is used to queue IRQs (struct pending_irq) that the + * vgic tried to inject in the guest (calling gic_set_guest_irq) but + * no LRs were available at the time. + * As soon as an LR is freed we remove the first IRQ from this + * list and write it to the LR register. + * lr_pending is a subset of vgic.inflight_irqs. */ + struct list_head lr_pending; + spinlock_t lock; + + /* GICv3: redistributor base and flags for this vCPU */ + paddr_t rdist_base; + uint64_t rdist_pendbase; +#define VGIC_V3_RDIST_LAST (1 << 0) /* last vCPU of the rdist */ +#define VGIC_V3_LPIS_ENABLED (1 << 1) + uint8_t flags; +}; + struct sgi_target { uint8_t aff1; uint16_t list; From patchwork Fri Feb 9 14:38:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127855 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680111ljc; Fri, 9 Feb 2018 06:42:32 -0800 (PST) X-Google-Smtp-Source: AH8x227Ng14w4jZewKHTcRjLI4VBVbSbuAOC5caZEVkf8Dk9zmYxonPvk0txNEFYVQ71q49glwkV X-Received: by 10.107.138.20 with SMTP id m20mr3371203iod.192.1518187352469; Fri, 09 Feb 2018 06:42:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187352; cv=none; d=google.com; s=arc-20160816; b=JObFySXLQbLq+lJ96QcbWnoK0+iwifsOUL8H0itcQSlBPFKEPPCagkErz0pDImL303 BvkEMp3y3QTZxZY6sB8fTivgNnRVXoj51WCGLTpJXWNvEsui5kFS0Xzcnisg6ZeDXlvw 5HR27jN4HgaM0rP7kERiVMisTOW41d9JeVJ8/PaaHzjTLl5iEPyvrdsYUA38ta6M0r68 bRBpsiAFunVV8egDMWIkkBpUZGsHL5SpEZ5AvJoKp6vqVUwC/eoUr/ws9pTCLAmX1Gl/ gdv+7opzk0SKE2uSWNL1V+Vu24F3usjuvz1Ve1QfyTj5RaYRj6x3v39D8jpdLmhjp5tM 3JPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=V4De8keefaynCbLkw677L6zitVA2T+OXWJWLLu5KstE=; b=qKQVZbWkXM83My4zOuUqZaIe3Wlggf00K0pJMKKQBu5nEJ2odin3QL+VkRHVoYJobF CWby1iGaKwvZPxzsEJkAzY1fZMB4DQNoMID4YdIeuRiUCx/8f7nZj85LLP3ywsaw83e7 Pp44I2ktu/x/ipVEtTXKytRQmjIoNjwChFAFTlGzIcqLUlvovVSt4kloNc/93V7np6+i GhKjDium1Z1gvYMbw41hQard4fO4spqjxjhXzXs0DZ7fWJOUJxcv6pFMabDX4h4qc/dg c90IHVeYt4XLWtfWeeLElI2YJGgqP9lKzQrEi5eHxLulSwnqywlb3uYIYQKboWqOM1N9 WFgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BGuFWp5S; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:56 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:38:59 +0000 Message-Id: <20180209143937.28866-12-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 11/49] ARM: VGIC: reorder prototypes in vgic.h X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Currently vgic.h both contains prototypes used by Xen arch code outside of the actual VGIC (for instance vgic_vcpu_inject_irq()), and prototypes for functions used by the VGIC internally. Group them to later allow an easy split with one #ifdef. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/include/asm-arm/vgic.h | 73 ++++++++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 4e1c37f091..8c39ff1402 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -279,19 +279,8 @@ enum gic_sgi_mode; */ #define REG_RANK_INDEX(b, n, s) ((((n) >> s) & ((b)-1)) % 32) -/* - * In the moment vgic_num_irqs() just covers SPIs and the private IRQs, - * as it's mostly used for allocating the pending_irq and irq_desc array, - * in which LPIs don't participate. - */ -#define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) -extern int domain_vgic_init(struct domain *d, unsigned int nr_spis); -extern void domain_vgic_free(struct domain *d); -extern int vcpu_vgic_init(struct vcpu *v); extern struct vcpu *vgic_get_target_vcpu(struct vcpu *v, unsigned int virq); -extern int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, - bool level); extern void vgic_remove_irq_from_queues(struct vcpu *v, struct pending_irq *p); extern void gic_remove_from_lr_pending(struct vcpu *v, struct pending_irq *p); extern void vgic_clear_pending_irqs(struct vcpu *v); @@ -307,29 +296,40 @@ extern void register_vgic_ops(struct domain *d, const struct vgic_ops *ops); int vgic_v2_init(struct domain *d, int *mmio_count); int vgic_v3_init(struct domain *d, int *mmio_count); -bool vgic_evtchn_irq_pending(struct vcpu *v); -struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, - unsigned int virq); -int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, - struct irq_desc *desc, bool connect); - -extern int domain_vgic_register(struct domain *d, int *mmio_count); -extern int vcpu_vgic_free(struct vcpu *v); extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, enum gic_sgi_mode irqmode, int virq, const struct sgi_target *target); extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq); -/* Reserve a specific guest vIRQ */ -extern bool vgic_reserve_virq(struct domain *d, unsigned int virq); +void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, + paddr_t vbase, uint32_t aliased_offset); + +#ifdef CONFIG_HAS_GICV3 +struct rdist_region; +void vgic_v3_setup_hw(paddr_t dbase, + unsigned int nr_rdist_regions, + const struct rdist_region *regions, + unsigned int intid_bits); +#endif + +/*** Common VGIC functions used by Xen arch code ****/ /* - * Allocate a guest VIRQ - * - spi == 0 => allocate a PPI. It will be the same on every vCPU - * - spi == 1 => allocate an SPI + * In the moment vgic_num_irqs() just covers SPIs and the private IRQs, + * as it's mostly used for allocating the pending_irq and irq_desc array, + * in which LPIs don't participate. */ -extern int vgic_allocate_virq(struct domain *d, bool spi); +#define vgic_num_irqs(d) ((d)->arch.vgic.nr_spis + 32) +/* + * Allocate a guest VIRQ + * - is_spi == 0 => allocate a PPI. It will be the same on every vCPU + * - is_spi == 1 => allocate an SPI + */ +extern int vgic_allocate_virq(struct domain *d, bool is_spi); +/* Reserve a specific guest vIRQ */ +extern bool vgic_reserve_virq(struct domain *d, unsigned int virq); +extern void vgic_free_virq(struct domain *d, unsigned int virq); static inline int vgic_allocate_ppi(struct domain *d) { return vgic_allocate_virq(d, false /* ppi */); @@ -340,18 +340,21 @@ static inline int vgic_allocate_spi(struct domain *d) return vgic_allocate_virq(d, true /* spi */); } -extern void vgic_free_virq(struct domain *d, unsigned int virq); +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq); +int vgic_connect_hw_irq(struct domain *d, struct vcpu *v, unsigned int virq, + struct irq_desc *desc, bool connect); -void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, - paddr_t vbase, uint32_t aliased_offset); +bool vgic_evtchn_irq_pending(struct vcpu *v); -#ifdef CONFIG_HAS_GICV3 -struct rdist_region; -void vgic_v3_setup_hw(paddr_t dbase, - unsigned int nr_rdist_regions, - const struct rdist_region *regions, - unsigned int intid_bits); -#endif +int domain_vgic_register(struct domain *d, int *mmio_count); +int domain_vgic_init(struct domain *d, unsigned int nr_spis); +void domain_vgic_free(struct domain *d); +int vcpu_vgic_init(struct vcpu *vcpu); +int vcpu_vgic_free(struct vcpu *vcpu); + +int vgic_inject_irq(struct domain *d, struct vcpu *v, unsigned int virq, + bool level); #endif /* __ASM_ARM_VGIC_H__ */ From patchwork Fri Feb 9 14:39:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127826 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679660ljc; Fri, 9 Feb 2018 06:42:02 -0800 (PST) X-Google-Smtp-Source: AH8x227F+rdcBPUve0QuITgA3vLBkk/xHrzrViXGqoPo6LvqHODpMcMcuYB4TEn5Mm005P3Rrz/S X-Received: by 10.36.196.8 with SMTP id v8mr3517094itf.92.1518187322604; Fri, 09 Feb 2018 06:42:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187322; cv=none; d=google.com; s=arc-20160816; b=by7A7hEKEMq5PL1ONCiNn4Cqm6nHrIOdMW/aCHlyQLdC62wlsPXEuBuh230aOqoSis RR+qqpWUx4bgVZ5FrNn5foUY1YHHxeIT4qGayzp3+ULppIBMRU5I7GwwxDYB0ZTwUhhq rp90/ntQq0ArneYUYKEWq6ToXzGHyVxXXnvX3vAkPaGLPF1TdH80Y/OnIX+glaj1wmRX 3kx3jSWIfBujTpuDoElK/CSqRc950brSkTq4GiE+0f2jePIgkd4hpzEEvDt6mgl5KHcb bci8XcU88vNDoimaFje6ZPSD8OAYQz7QSToqZoEvsAnGWA4DOdLjLXIw+S5tvOiO70Ct llow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=xcHqvY9sQ3ShmbHRgbLrOK1rJ9hr4g8SxoOKIFXfgqg=; b=W03/B1djzDjxQIAzqCRywTcWDZrOKiYg9gMXHnbHj5gIGQ0Z6BQ1c1WwbHsR5v37VM 4lwms36eNJ4w0iE+OurSlcio0405RULyEXSnhpe2pbQsR+2QYNyHhxIqak1KZG9qyqbG EjY7CJbGQbnmSmuzsBc4rupHkVzVAaUNjDyzt4NTUwA0WkVamE5LbCx5XruAKovTqh33 7XrpjbKRAFYCMF2cVgS+kCNeMg2HyXpCUw/POjzdqpSyQg3MICG/MfixDhoFtW/1kexY CIUOScjpd+kpyxKsj8qnU7oPjKEWKdFe2Ab8oEpuapbSXTAF01eu2U3cJLXcA3iSI+KD 5xLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CvsjtKXB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:57 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:00 +0000 Message-Id: <20180209143937.28866-13-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 12/49] ARM: VGIC: introduce gic_get_nr_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-vgic.c | 10 +++++----- xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 1 + 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c92626e4ee 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include #include -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void gic_clear_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 968e46fabb..89873c1df4 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -47,6 +47,11 @@ void register_gic_ops(const struct gic_hw_operations *ops) gic_hw_ops = ops; } +int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + static void clear_cpu_lr_mask(void) { this_cpu(lr_mask) = 0ULL; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1d382b0ade..c1f027d703 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -222,6 +222,7 @@ enum gic_version { DECLARE_PER_CPU(uint64_t, lr_mask); extern enum gic_version gic_hw_version(void); +extern int gic_get_nr_lrs(void); /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type); From patchwork Fri Feb 9 14:39:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127824 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679640ljc; Fri, 9 Feb 2018 06:42:01 -0800 (PST) X-Google-Smtp-Source: AH8x226kGGnJsL7UanyOd+B8tLuUPuJj2JokY3I088cW/oNurfywLahtfpSBVu5Dwgm1GmhsOJmR X-Received: by 10.36.73.133 with SMTP id e5mr3585115itd.109.1518187321553; Fri, 09 Feb 2018 06:42:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187321; cv=none; d=google.com; s=arc-20160816; b=UQ8ZyEoUZWbuBUjN/gBbuCiRXP+cfhbuFijssC3VXQ3w/qatO5GqKyU9qXdG/P6mya GldMaz8Jz7AHNl2c15E4r+NZABqdV3lZ7buaE8cYIPxSrzhpkLAmRCRzt9wuP3xDmFfn 9hJf1490IqRLWneASTpfJW4IP4i0ijpC2VqVvBpDZrWrNDkMdkwqHcVzLFTzntbZaii/ qB9WJN5TGR8XxKd/M/tmBpJVM6qv7xo9jAycPpOAa/+EaU78YVCTDU44cr3rt1nhLu+n x7JlB4Whft3nwoN9Agloq+ipFDSn9vxGJPU++/c+iwQ3FuylCLoZPVN5vN5sML6/jgZF 2zKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Uzlc9KHaJTjf4iGqWxZWcvcIZKoFy2Y/uV7k2+kBi2A=; b=X9d2PWTqFaWneATuJrB+jl/u7VwSpYPTyinutMSbXbvbnDabDCE2rHVVLVmmfkn7SI x+H52O+HGzZt5IxEGsQh4tcf9zbnnK81als0CwAJAS9By3TcSbSzVX+eftdt06g2iCrZ xR8MBpmcuOY1hS1/MsNxGZwlkrsuuLpc8i8Z0P2cfQPxapIhkcKmDaIUe1/0i9zMj+gk p6zJvCILlk8Fj04qY/a3oZzznh1kEToY6Fp6KkpoJqDRkUjvCkqdPs5Iy6uSUsW99p93 ssvWwOgHiIzAOqL+kQqg07oc+UTEcXmTpRruQmjYTuvF/9QUGC2VCeeImH32EaLQC23t qG7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VOtomiuR; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:58 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:01 +0000 Message-Id: <20180209143937.28866-14-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 13/49] ARM: VGIC: Add hypervisor base address to vgic_v2_setup_hw() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC will need to know the hypervisor base address at some point, which is private to the hardware facing part of the VGIC so far. Add a parameter to vgic_v2_setup_hw() to pass this address on, so a VGIC implementation can make use of it. The current VGIC ignores this new parameter. TODO: add proper value for GICv2 on GICv3 emulation! Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 3 ++- xen/arch/arm/gic-v3.c | 3 ++- xen/arch/arm/vgic-v2.c | 3 ++- xen/include/asm-arm/vgic.h | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 2b271ba322..7a18abecfa 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -1207,7 +1207,8 @@ static int __init gicv2_init(void) if ( !gicv2.map_hbase ) panic("GICv2: Failed to ioremap for GIC Virtual interface\n"); - vgic_v2_setup_hw(dbase, cbase, csize, vbase, aliased_offset); + vgic_v2_setup_hw(dbase, cbase, csize, vbase, gicv2.map_hbase, + aliased_offset); /* Global settings: interrupt distributor */ spin_lock_init(&gicv2.lock); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index ea14ab4028..08d4703687 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1238,7 +1238,8 @@ static void __init gicv3_init_v2(void) printk("GICv3 compatible with GICv2 cbase %#"PRIpaddr" vbase %#"PRIpaddr"\n", cbase, vbase); - vgic_v2_setup_hw(dbase, cbase, csize, vbase, 0); + /* TODO: provide the proper HBASE address! */ + vgic_v2_setup_hw(dbase, cbase, csize, vbase, NULL, 0); } static void __init gicv3_ioremap_distributor(paddr_t dist_paddr) diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c index 646d1f3d12..96d543c005 100644 --- a/xen/arch/arm/vgic-v2.c +++ b/xen/arch/arm/vgic-v2.c @@ -47,7 +47,8 @@ static struct { } vgic_v2_hw; void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, - paddr_t vbase, uint32_t aliased_offset) + paddr_t vbase, void __iomem *hbase, + uint32_t aliased_offset) { vgic_v2_hw.enabled = true; vgic_v2_hw.dbase = dbase; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 8c39ff1402..85ad2aca79 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -302,7 +302,8 @@ extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq); void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, - paddr_t vbase, uint32_t aliased_offset); + paddr_t vbase, void __iomem *hbase, + uint32_t aliased_offset); #ifdef CONFIG_HAS_GICV3 struct rdist_region; From patchwork Fri Feb 9 14:39:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127820 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679570ljc; Fri, 9 Feb 2018 06:41:57 -0800 (PST) X-Google-Smtp-Source: AH8x2270xoF1v+7dRrln1qNgQ78IywIh0PjkuXhPZlWIa6Dfc5EEmO9esmUM5vo25r40q5MeroeG X-Received: by 10.107.160.21 with SMTP id j21mr3409942ioe.186.1518187317163; Fri, 09 Feb 2018 06:41:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187317; cv=none; d=google.com; s=arc-20160816; b=G1vvG2zChygPxeLXGAX6Y1gLJsCtoFvgQWro99a/R2mNE1XOBbGsGsQRKzpTedfSvz QU2udl23a/VEcLTs87Qg2IbeGNnubTiloCzzt+50ZANwLvG9j5yJVO5drPLxr7Gbsw0Z 3FkK31nI4SuTsRELpI1ccN7tU8oJewvUCC4+U8d+QMqutHjMIL065GSeCj3Jai/d2SaE 5XI58bV3/S607yYrkGWguYFwKGShGvFgSAWC4fd4/wB7RG9Td+TAbYoa+6SF8tQinOlC utjRVgvtcPYY24KwOU89NuYsOX6CbUigWmUXgrN33YR8n0bA+RfGLb+7RrSeeKc5rZie ivvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=HdL5sXwz5QgYeOwV60yB6EJq1Z5BnXxAU4HY2syzv84=; b=MPJ2NGe5wmXj8XWNjDXCNYn6+Wvnb9W4wGMi2AxSpTESYkI0pR4Fv4l0fbjokBOj8n qXas58Hk8azcTtR4zG0kaR4tJ68n6Fip0r2RY42X+QaHmYlagc6vW503aecBF6UiZcXV hQjERnhILM3KG+i3GQ1JZMFJ4rEJGssVeFK8PxWBN1vR0jSdMCKf8yrH1+tqONFv1bmS aZCxfzJ8H3frzSDuG2hGiZBfBxelAmQ97mK7+JiiRDp/vr9aFMhgV3mBNqAeMUNIgvUb miivCG4kQ79kS8yJclvzfihkgBss+6OoSR5wRXlZw7k0/PGlVkRIp1OjAqq4q8oOILjK vIRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XN2VWSBK; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:59 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:02 +0000 Message-Id: <20180209143937.28866-15-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 14/49] ARM: VGIC: extend GIC CPU interface definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC will shortly use more bits of the GICC_CTLR register, so add the respective definitions from the manual. Also add a missing definition for GICV_PMR_PRIORITY_MASK. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 2 +- xen/include/asm-arm/gic.h | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 7a18abecfa..2e35892881 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -358,7 +358,7 @@ static void gicv2_cpu_init(void) /* Finest granularity of priority */ writel_gicc(0x0, GICC_BPR); /* Turn on delivery */ - writel_gicc(GICC_CTL_ENABLE|GICC_CTL_EOI, GICC_CTLR); + writel_gicc(GICC_CTL_ENABLE0|GICC_CTL_EOI, GICC_CTLR); } static void gicv2_cpu_disable(void) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index c1f027d703..c4c68c7770 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -77,6 +77,7 @@ #define GICC_EOIR (0x0010) #define GICC_RPR (0x0014) #define GICC_HPPIR (0x0018) +#define GICC_ABPR (0x001c) #define GICC_APR (0x00D0) #define GICC_NSAPR (0x00E0) #define GICC_IIDR (0x00FC) @@ -102,8 +103,18 @@ #define GICD_TYPE_SEC 0x400 #define GICD_TYPER_DVIS (1U << 18) -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) +#define GICC_CTL_ENABLE0_SHIFT 0 +#define GICC_CTL_ENABLE0 (1U << GICC_CTL_ENABLE0_SHIFT) +#define GICC_CTL_ENABLE1_SHIFT 1 +#define GICC_CTL_ENABLE1 (1U << GICC_CTL_ENABLE1) +#define GICC_CTL_AC_SHIFT 2 +#define GICC_CTL_AC (1U << GICC_CTL_AC_SHIFT) +#define GICC_CTL_FIQEN_SHIFT 3 +#define GICC_CTL_FIQEN (1U << GICC_CTL_FIQEN_SHIFT) +#define GICC_CTL_CBPR_SHIFT 4 +#define GICC_CTL_CBPR (1U << GICC_CTL_CBPR_SHIFT) +#define GICC_CTL_EOI_SHIFT 9 +#define GICC_CTL_EOI (1U << GICC_CTL_EOI_SHIFT) #define GICC_IA_IRQ 0x03ff #define GICC_IA_CPU_MASK 0x1c00 @@ -127,6 +138,9 @@ #define GICH_MISR_VGRP1E (1 << 6) #define GICH_MISR_VGRP1D (1 << 7) +#define GICV_PMR_PRIORITY_SHIFT 3 +#define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) + /* * The minimum GICC_BPR is required to be in the range 0-3. We set * GICC_BPR to 0 but we must expect that it might be 3. This means we From patchwork Fri Feb 9 14:39:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127814 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679450ljc; Fri, 9 Feb 2018 06:41:50 -0800 (PST) X-Google-Smtp-Source: AH8x224mdOLMVjiOQnvfXsoEY7liMrXv8UVzXYxKN9BlQ1fVzkbTBoT1mtKEMn6WoaWiFmtKVThg X-Received: by 10.36.16.137 with SMTP id 131mr3676242ity.111.1518187309889; Fri, 09 Feb 2018 06:41:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187309; cv=none; d=google.com; s=arc-20160816; b=vjX5UWlhIWr07cnNoV94X0sEkbEDyHynEHNY5DRn8smz6INChPuaFLK5zRyUlZ0tjI heL/d7RVDdFTY5tYJRr/lYG+7Mge6QFLdM/LHpeL0D7TXEQL/7DoUVONUmupdZ1i6MNs u1E/PbZlZuT2IZWFc5BYBjkDO3MpGhtXowYYr2Dob7dPYAmF29okTjzPcwcXxjvV9ESv n0VkmizUSwxf64CbLJdgXjX6bLJve+6N0JYhDq0q1FwRILnet7KJNCbeSVWoxbOpMF56 xU3XpqSEVKFgP2MdkHpf3GzmVqf6ND9hwHUhjuNsbr1+Xl30oByyzCgUPsh9+OfRI69D ZgJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=VbeGceEsxicT3S6LTm9OfsKHg6Y3TEt0f79IyFudt8k=; b=WsgxeiaRZUWznHXuOghZWxnfcLHVwnAbQzFnBGpWUCAJ3/sx6KTIL5B6SEhrtLPRoO 7jKLqMuhQWdUK1Z3Dh7v9SocezxwGnuk9fDkbfUBqCXckUBOjlnkU+wNf2opJvXxSFPK 8VzyJzP9R0QAL+lxSBnuD8z4F5n7Vl2KYiDvoXVi6iuBKLJy/J+tNH7uLC/463lXKGPZ pniTY7EAcT4IbdRkLOFBf+lMlm3PR5J8tWwGQ940HiHKTF3y+25gplbRXfWUMvkyNMM4 uwyIimZ8WSYD+QURWOxLKsxMwQMJvRTRJYe0Bjg+Xh8aq5ajS/CUFr/Dq0ldWYayNoNt E/gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jfFyP6jL; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:00 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:03 +0000 Message-Id: <20180209143937.28866-16-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 15/49] ARM: GIC: Allow tweaking the active state of an IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When playing around with hardware mapped, level triggered virtual IRQs, there is the need to explicitly set the active state of an interrupt at some point in time. To prepare the GIC for that, we introduce a set_active_state() function to let the VGIC manipulate the state of an associated hardware IRQ. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 9 +++++++++ xen/arch/arm/gic-v3.c | 16 ++++++++++++++++ xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 5 +++++ 4 files changed, 35 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 2e35892881..5339f69fbc 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -235,6 +235,14 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } +static void gicv2_set_active_state(int irq, bool active) +{ + if (active) + writel_gicd(1U << (irq % 32), GICD_ISACTIVER + (irq / 32) * 4); + else + writel_gicd(1U << (irq % 32), GICD_ICACTIVER + (irq / 32) * 4); +} + static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type) { uint32_t cfg, actual, edgebit; @@ -1241,6 +1249,7 @@ const static struct gic_hw_operations gicv2_ops = { .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, + .set_active_state = gicv2_set_active_state, .set_irq_type = gicv2_set_irq_type, .set_irq_priority = gicv2_set_irq_priority, .send_SGI = gicv2_send_SGI, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 08d4703687..595eaef43a 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -475,6 +475,21 @@ static unsigned int gicv3_read_irq(void) return irq; } +static void gicv3_set_active_state(int irq, bool active) +{ + void __iomem *base; + + if ( irq >= NR_GIC_LOCAL_IRQS) + base = GICD + (irq / 32) * 4; + else + base = GICD_RDIST_SGI_BASE; + + if ( active ) + writel(1U << (irq % 32), base + GICD_ISACTIVER); + else + writel(1U << (irq % 32), base + GICD_ICACTIVER); +} + static inline uint64_t gicv3_mpidr_to_affinity(int cpu) { uint64_t mpidr = cpu_logical_map(cpu); @@ -1722,6 +1737,7 @@ static const struct gic_hw_operations gicv3_ops = { .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, + .set_active_state = gicv3_set_active_state, .set_irq_type = gicv3_set_irq_type, .set_irq_priority = gicv3_set_irq_priority, .send_SGI = gicv3_send_sgi, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 89873c1df4..dfc2108c4d 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -92,6 +92,11 @@ void gic_restore_state(struct vcpu *v) isb(); } +void gic_set_active_state(int irq, bool state) +{ + gic_hw_ops->set_active_state(irq, state); +} + /* desc->irq needs to be disabled before calling this function */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type) { diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index c4c68c7770..d330860580 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -238,6 +238,9 @@ DECLARE_PER_CPU(uint64_t, lr_mask); extern enum gic_version gic_hw_version(void); extern int gic_get_nr_lrs(void); +/* Force the state of an IRQ to active. */ +void gic_set_active_state(int irq, bool state); + /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type); @@ -347,6 +350,8 @@ struct gic_hw_operations { void (*deactivate_irq)(struct irq_desc *irqd); /* Read IRQ id and Ack */ unsigned int (*read_irq)(void); + /* Force the state of an IRQ to active */ + void (*set_active_state)(int irq, bool state); /* Set IRQ type */ void (*set_irq_type)(struct irq_desc *desc, unsigned int type); /* Set IRQ priority */ From patchwork Fri Feb 9 14:39:04 2018 Content-Type: text/plain; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:01 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:04 +0000 Message-Id: <20180209143937.28866-17-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 16/49] ARM: GIC: allow reading pending state of a hardware IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To synchronize level triggered interrupts which are mapped into a guest, we need to update the virtual line level at certain points in time. For a hardware mapped interrupt the GIC is the only place where we can easily access this information. Implement a gic_hw_operations member to return the pending state of a particular interrupt. Due to hardware limitations this only works for private interrupts of the current CPU, so there is not CPU field in the prototype. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 6 ++++++ xen/arch/arm/gic-v3.c | 13 +++++++++++++ xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 5 +++++ 4 files changed, 29 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5339f69fbc..30081640ac 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -514,6 +514,11 @@ static unsigned int gicv2_read_apr(int apr_reg) return readl_gich(GICH_APR); } +bool gicv2_read_pending_state(int irq) +{ + return readl_gicd(GICD_ISPENDR + (irq / 32) * 4) & (1U << (irq % 32)); +} + static void gicv2_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1261,6 +1266,7 @@ const static struct gic_hw_operations gicv2_ops = { .write_lr = gicv2_write_lr, .read_vmcr_priority = gicv2_read_vmcr_priority, .read_apr = gicv2_read_apr, + .read_pending_state = gicv2_read_pending_state, .make_hwdom_dt_node = gicv2_make_hwdom_dt_node, .make_hwdom_madt = gicv2_make_hwdom_madt, .get_hwdom_extra_madt_size = gicv2_get_hwdom_extra_madt_size, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 595eaef43a..2cbfeb8e03 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1081,6 +1081,18 @@ static unsigned int gicv3_read_apr(int apr_reg) } } +static bool gicv3_read_pending_state(int irq) +{ + void __iomem *base; + + if ( irq >= NR_GIC_LOCAL_IRQS) + base = GICD + (irq / 32) * 4; + else + base = GICD_RDIST_SGI_BASE; + + return readl(base + GICD_ISPENDR) & (1U << (irq % 32)); +} + static void gicv3_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1749,6 +1761,7 @@ static const struct gic_hw_operations gicv3_ops = { .write_lr = gicv3_write_lr, .read_vmcr_priority = gicv3_read_vmcr_priority, .read_apr = gicv3_read_apr, + .read_pending_state = gicv3_read_pending_state, .secondary_init = gicv3_secondary_cpu_init, .make_hwdom_dt_node = gicv3_make_hwdom_dt_node, .make_hwdom_madt = gicv3_make_hwdom_madt, diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index dfc2108c4d..ce9ab2367e 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -116,6 +116,11 @@ static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority) gic_hw_ops->set_irq_priority(desc, priority); } +bool gic_read_pending_state(int irq) +{ + return gic_hw_ops->read_pending_state(irq); +} + /* Program the GIC to route an interrupt to the host (i.e. Xen) * - needs to be called with desc.lock held */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index d330860580..d7fd18fd47 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -244,6 +244,9 @@ void gic_set_active_state(int irq, bool state); /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type); +/* Read the pending state of an interrupt from the distributor. */ +bool gic_read_pending_state(int irq); + /* Program the GIC to route an interrupt */ extern void gic_route_irq_to_xen(struct irq_desc *desc, unsigned int priority); extern int gic_route_irq_to_guest(struct domain *, unsigned int virq, @@ -376,6 +379,8 @@ struct gic_hw_operations { unsigned int (*read_vmcr_priority)(void); /* Read APRn register */ unsigned int (*read_apr)(int apr_reg); + /* Query the pending state of an interrupt at the distributor level. */ + bool (*read_pending_state)(int irq); /* Secondary CPU init */ int (*secondary_init)(void); /* Create GIC node for the hardware domain */ From patchwork Fri Feb 9 14:39:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127815 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679472ljc; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:02 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:05 +0000 Message-Id: <20180209143937.28866-18-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 17/49] ARM: timer: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM Generic Timer uses a level-sensitive interrupt semantic. We easily catch when the line goes high, as this triggers the hardware IRQ. However we have to sync the state of the interrupt condition at certain points to catch when the line goes low and we can remove the vtimer vIRQ from the vGIC (and the LR). The VGIC in Xen so far only implemented edge triggered vIRQs, really, so we need to add new functionality to re-sample the interrupt state. Signed-off-by: Andre Przywara --- xen/arch/arm/time.c | 34 ++++++++++++++++++++++++++++++++++ xen/arch/arm/traps.c | 1 + xen/include/xen/timer.h | 2 ++ 3 files changed, 37 insertions(+) diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index c11fcfeadd..98ebb4305d 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -263,6 +263,40 @@ static void vtimer_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) vgic_inject_irq(current->domain, current, current->arch.virt_timer.irq, true); } +/** + * vtimer_sync() - update the state of the virtual timer after a guest run + * @vcpu: The VCPU to sync the arch timer state + * + * After returning from a guest, update the state of the virtual interrupt + * line, to model the level triggered interrupt correctly. + * If the guest has handled a timer interrupt, the virtual interrupt line + * needs to be lowered explicitly. vgic_inject_irq() takes care of that. + */ +void vtimer_sync(struct vcpu *vcpu) +{ + struct vtimer *vtimer = &vcpu->arch.virt_timer; + bool level; + + vtimer->ctl = READ_SYSREG32(CNTV_CTL_EL0); + vtimer->cval = READ_SYSREG64(CNTV_CVAL_EL0); + + /* + * Technically we should mask with 0x7 here, to catch if the timer + * interrupt is masked. However Xen always masks the timer upon entering + * the hypervisor, leaving it up to the guest to un-mask it. + * So we would always read a "low" level, despite the condition being + * actually "high". Igoring the mask bit solves this (for now). + * Another possible check would be to compare the value of CNTVCT_EL0 + * against vtimer->cval and derive the interrupt state from that. + * + * TODO: The proper fix for this is to make vtimer vIRQ hardware mapped, + * but this requires reworking the arch timer to implement this. + */ + level = (vtimer->ctl & 0x5) == (CNTx_CTL_ENABLE | CNTx_CTL_PENDING); + + vgic_inject_irq(vcpu->domain, vcpu, vtimer->irq, level); +} + /* * Arch timer interrupt really ought to be level triggered, since the * design of the timer/comparator mechanism is based around that diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1cba7e584d..2d770a14a5 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,6 +2024,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); + vtimer_sync(current); gic_clear_lrs(current); } } diff --git a/xen/include/xen/timer.h b/xen/include/xen/timer.h index 4513260b0d..eddbbf3903 100644 --- a/xen/include/xen/timer.h +++ b/xen/include/xen/timer.h @@ -94,6 +94,8 @@ DECLARE_PER_CPU(s_time_t, timer_deadline); /* Arch-defined function to reprogram timer hardware for new deadline. */ int reprogram_timer(s_time_t timeout); +void vtimer_sync(struct vcpu *vcpu); + /* Calculate the aligned first tick time for a given periodic timer. */ s_time_t align_timer(s_time_t firsttick, uint64_t period); From patchwork Fri Feb 9 14:39:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127821 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679582ljc; Fri, 9 Feb 2018 06:41:58 -0800 (PST) X-Google-Smtp-Source: AH8x226OA9SDrLpZtK9fPN5VdVNQXy8eOe6J6K6YO/ElNPVH17eMk473lsBbwkEKSosZchl1IIcp X-Received: by 10.36.7.209 with SMTP id f200mr3503055itf.124.1518187318010; Fri, 09 Feb 2018 06:41:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187318; cv=none; d=google.com; s=arc-20160816; b=vxwk/wnWZjSh2Du0Yer0TIWrS1ODnkC2ktPLA1kkGaIbaADrjnUoGHBfUGoGjy+tt1 A7qJj5IPbkwscAkUFQTrTXHICgDeY2XHfsseUeXZ3UJEsGKkZWhKxWO8bGWqK6i0NDqp MxAKGRlo03zADpnaEySxwbQjrR9qZ2x+KK7vtvddty6tGTXBRDtl6z2wlITBs6N+NrAs moxNuWxtgsS96UvYaQ5CEQy7zq2fM8J+Z7k79TGFas1qKgk1O16eqWl1u9q9idPZ3rY/ dcm4nCmZlqG0Lf0bueO+fPMrD7uAntlGbEJUZrBvB6XfYQQ8XW1RA6U/fW3hPjYfENpz GFOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=/ElUmu1CY4xWn/Dy5dZx8pLx+S8TZyocnCGTu8KXJU4=; b=W6sfJjv6xFfpFU0x4ld2hpHC1Sxx9PLKEPQnJNP0Az5Z+9zdHkxDuvb8DLaRcA9Mkx aXB5qI8f7pH0gTIo2wyEz0ud9bpGwoka6NfPXSgxXC4om0p10bA6582rFRvSMzrVDDYj 3Ab4aVDN/rSLKWXyohkmcLx8ubTFvXKpmxh6BqoKEBngVGxCG6O3NqlNkwRcbQnF6PE0 BUmIXKkOog2nH7LZtNPBu8FvCnPvPygQdNKrC/l4gNLtJHi4SRMCJKSITwdR8I9shUzh BznmaBZJdij2oRBVa0mMI3Uj3pRbURcyabks3mpIaBUinQhsGByvCFTY1/r3be7R0mNI onsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A9QJYW4k; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:03 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:06 +0000 Message-Id: <20180209143937.28866-19-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 18/49] ARM: evtchn: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The event channel IRQ has level triggered semantics, however the current VGIC treats everything as edge triggered. To correctly process those IRQs, we have to lower the (virtual) IRQ line at some point in time, depending on whether ther interrupt condition still prevails. Check the per-VCPU evtchn_upcall_pending variable to make the interrupt line match its status, and call this function upon every hypervisor entry. Signed-off-by: Andre Przywara --- xen/arch/arm/domain.c | 7 +++++++ xen/arch/arm/traps.c | 1 + xen/include/asm-arm/event.h | 1 + 3 files changed, 9 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index e76cfdfe83..87bd493924 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -955,6 +955,13 @@ void vcpu_mark_events_pending(struct vcpu *v) vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + bool pending = vcpu_info(v, evtchn_upcall_pending); + + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, pending); +} + /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 2d770a14a5..f57ef2141a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2025,6 +2025,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); vtimer_sync(current); + vcpu_update_evtchn_irq(current); gic_clear_lrs(current); } } diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index e8c2a6cb44..87ef76e3d5 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -6,6 +6,7 @@ void vcpu_kick(struct vcpu *v); void vcpu_mark_events_pending(struct vcpu *v); +void vcpu_update_evtchn_irq(struct vcpu *v); void vcpu_block_unless_event_pending(struct vcpu *v); static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) From patchwork Fri Feb 9 14:39:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127813 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679434ljc; Fri, 9 Feb 2018 06:41:48 -0800 (PST) X-Google-Smtp-Source: AH8x2276Y1zSyfqQGlvN7BUiBdZnShjmrcWciT1Fg7aIgi4IJBoaqZF7booml1dIWBpw2ipM76Nr X-Received: by 10.107.133.75 with SMTP id h72mr3429057iod.227.1518187308441; Fri, 09 Feb 2018 06:41:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187308; cv=none; d=google.com; s=arc-20160816; b=h2P0YJzZw8gxnqeh+kOlRkIFyGWJr6EuX8/xv/D+hrl0TlnU9vr9YIYK0qnO0lc/f3 uRcOTeK7Kp4v1hZnvyhc8SjVnM8pTUp7RTcEuFghr7jrLIfUwKVlpmTo3FgNaBfBXCFs a3qx/Gnscctj2YBpyq198kV6PAuDszRElZhTXu5FFRU/UpgJGTYbIZVBLQK43M2s1eak JxAqfQGn3HEpByXPu90tHBDvTotgBjE6q1WUlSx18oCkHW+B0TeygY3udh/PtZH3GLpE o3z9zyzrmJrnz1GofTjX/TMkl9+j56wMowT172fY+CC6y+BN/JT2dFU9QHku9FIRZaDA J15g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=WruNtd5/JyrwsSpHf9giOv21US0JKHZAKsTKG9ZZMNA=; b=j+BQMBmhWtqMrw9qH6gmN6PzZVuakJ33AMSOaarKfpDL5bCEwNQPnObog+OePwaG5G nmrrmixBhQm4gRcNmC498295Q3b8ZF3w0bbQExHKYULF5Xx1vTcbiumfi6Ue0U5opdEx yc7Or6MgmIMBIa/OgI7EkaT5wp+g/v6J8pQgjUgioQPXfiemEsmzr0A1wQPQsd8qXKz/ InQczZCZsJESvb7zuLWx8NJnRu0vZF10pwNkOf+iBsPntuUTiDuxXD2T6867T5kbVsrS Y2ovh6tDx7TPQ2lmkXJjgX30Y89qBl06+rcRjhI7emHF+5pLlJi7NkitXzEtq+vMkjJ9 YUqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TWhwXWn0; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:04 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:07 +0000 Message-Id: <20180209143937.28866-20-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 19/49] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The emulated ARM SBSA UART is using level triggered IRQ semantics, however the current VGIC can only handle edge triggered IRQs, really. Disable the existing workaround for this problem in case we have the new VGIC in place, which can properly handle level triggered IRQs. Signed-off-by: Andre Przywara --- xen/arch/arm/vpl011.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 5dcf4bec18..197ece8873 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -54,6 +54,7 @@ static void vpl011_update_interrupt_status(struct domain *d) */ ASSERT(spin_is_locked(&vpl011->lock)); +#ifndef CONFIG_NEW_VGIC /* * TODO: PL011 interrupts are level triggered which means * that interrupt needs to be set/clear instead of being @@ -71,6 +72,9 @@ static void vpl011_update_interrupt_status(struct domain *d) vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); vpl011->shadow_uartmis = uartmis; +#else + vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, !!uartmis); +#endif } static uint8_t vpl011_read_data(struct domain *d) From patchwork Fri Feb 9 14:39:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127839 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679820ljc; Fri, 9 Feb 2018 06:42:10 -0800 (PST) X-Google-Smtp-Source: AH8x225KtMQ5k9RJiwFJqu2vRbNBa6FyqwyDF0xBbOd+m8ufheej/0rvuF1kVcz3JW+WRHjqGyLH X-Received: by 10.107.130.25 with SMTP id e25mr3572911iod.245.1518187330743; Fri, 09 Feb 2018 06:42:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187330; cv=none; d=google.com; s=arc-20160816; b=FIexsSydWzvHRa5q35uU9v8TKTKPOP6BjYrH7AWAdbVCjeqpsarSgjOBr+qahMmarS tHWvpVrvuKuuSmXbBxa5X9kYdotBk4SsIgK84j4bexyqcg0aI/T+oJIJNGU4dsTlVVHQ eNDD0mAKjgLpdJ4oO5eWVWVOq9t3vcFHalDLFarJeAfM+L7PNMuyTteh67pxZHWaphnK AilpF/VP+TzjFlGuY/deKWBqhX7CxSJDxVX/yvSnDcWPZkmb7Yaw0dH/Pvz8dw4jWUAV dVcOeKIslQNgH6hABbkKbotXGWs4R8Ec0n/EZUxPZU1c2qVD3wGOVlQypDV3DqxkJfZB zOSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=aCAHGnmWL7wB07D1my9WOrLsAFCuG5lS07JUrm7XTbA=; b=0+gyaMnoCYYHazMzTQ7FmOGIafsju/euunCLbD1j7aTVYMsy3rKckkSAYv1Jw+WA24 aaMBsXrZf3r/RMTTnDkf7j7jUO6ERW71fHlPmo0gC7CbJ8IL6wJX/kDMaCmqIZp0TclD 3LHhTlqtCmMkCgAPHTypDVUznwEiCHuaNOH8BALPG6GSHOhlt6DzGF7JlmdQtszLNyzC DOcNxP3w89wPbU5o3hPmmzObJuZqrI8qUssWP7OvKHGzgupY2MUEi4hyXZMXIWR6R5AJ r3kcATHGYpPMzGaER+39p/tACedWmmnqiexXbrp6svxp2c281fhabpY7Lsf4QVXH2X27 G4OQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d9KSHqk0; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:05 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:08 +0000 Message-Id: <20180209143937.28866-21-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 20/49] ARM: new VGIC: Add data structure definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add a new header file for the new and improved GIC implementation. The big change is that we now have a struct vgic_irq per IRQ instead of spreading all the information over various bitmaps in the ranks. We include this new header conditionally from within the old header file for the time being to avoid touching all the users. This is based on Linux commit b18b57787f5e, written by Christoffer Dall. Signed-off-by: Andre Przywara --- xen/include/asm-arm/arm_vgic.h | 269 +++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/domain.h | 4 + xen/include/asm-arm/vgic.h | 6 + 3 files changed, 279 insertions(+) create mode 100644 xen/include/asm-arm/arm_vgic.h diff --git a/xen/include/asm-arm/arm_vgic.h b/xen/include/asm-arm/arm_vgic.h new file mode 100644 index 0000000000..865e9ee5bc --- /dev/null +++ b/xen/include/asm-arm/arm_vgic.h @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __KVM_ARM_VGIC_H +#define __KVM_ARM_VGIC_H + +#include +#include +#include +#include + +#define VGIC_V3_MAX_CPUS 255 +#define VGIC_V2_MAX_CPUS 8 +#define VGIC_NR_IRQS_LEGACY 256 +#define VGIC_NR_SGIS 16 +#define VGIC_NR_PPIS 16 +#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) +#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) +#define VGIC_MAX_SPI 1019 +#define VGIC_MAX_RESERVED 1023 +#define VGIC_MIN_LPI 8192 + +#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) +#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ + (irq) <= VGIC_MAX_SPI) + +enum vgic_type { + VGIC_V2, /* Good ol' GICv2 */ + VGIC_V3, /* New fancy GICv3 */ +}; + +#define VGIC_V2_MAX_LRS (1 << 6) +#define VGIC_V3_MAX_LRS 16 +#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) + +enum vgic_irq_config { + VGIC_CONFIG_EDGE = 0, + VGIC_CONFIG_LEVEL +}; + +struct vgic_irq { + spinlock_t irq_lock; /* Protects the content of the struct */ + struct list_head lpi_list; /* Used to link all LPIs together */ + struct list_head ap_list; + + struct vcpu *vcpu; /* + * SGIs and PPIs: The VCPU + * SPIs and LPIs: The VCPU whose ap_list + * this is queued on. + */ + + struct vcpu *target_vcpu; /* + * The VCPU that this interrupt should + * be sent to, as a result of the + * targets reg (v2) or the affinity reg (v3). + */ + + u32 intid; /* Guest visible INTID */ + bool line_level; /* Level only */ + bool pending_latch; /* + * The pending latch state used to + * calculate the pending state for both + * level and edge triggered IRQs. + */ + bool active; /* not used for LPIs */ + bool enabled; + bool hw; /* Tied to HW IRQ */ + atomic_t refcount; /* Used for LPIs */ + u32 hwintid; /* HW INTID number */ + union + { + u8 targets; /* GICv2 target VCPUs mask */ + u32 mpidr; /* GICv3 target VCPU */ + }; + u8 source; /* GICv2 SGIs only */ + u8 priority; + enum vgic_irq_config config; /* Level or edge */ +}; + +struct vgic_register_region; +struct vgic_its; + +enum iodev_type { + IODEV_CPUIF, + IODEV_DIST, + IODEV_REDIST, + IODEV_ITS +}; + +struct vgic_io_device { + paddr_t base_addr; + union + { + struct vcpu *redist_vcpu; + struct vgic_its *its; + }; + const struct vgic_register_region *regions; + enum iodev_type iodev_type; + int nr_regions; +}; + +struct vgic_its { + /* The base address of the ITS control register frame */ + paddr_t vgic_its_base; + + bool enabled; + struct vgic_io_device iodev; + + /* These registers correspond to GITS_BASER{0,1} */ + u64 baser_device_table; + u64 baser_coll_table; + + /* Protects the command queue */ + spinlock_t cmd_lock; + u64 cbaser; + u32 creadr; + u32 cwriter; + + /* migration ABI revision in use */ + u32 abi_rev; + + /* Protects the device and collection lists */ + spinlock_t its_lock; + struct list_head device_list; + struct list_head collection_list; +}; + +struct vgic_dist { + bool ready; + bool initialized; + + /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ + u32 version; + + /* Do injected MSIs require an additional device ID? */ + bool msis_require_devid; + + int nr_spis; + + /* base addresses in guest physical address space: */ + paddr_t vgic_dist_base; /* distributor */ + union + { + /* either a GICv2 CPU interface */ + paddr_t vgic_cpu_base; + /* or a number of GICv3 redistributor regions */ + struct + { + paddr_t vgic_redist_base; + paddr_t vgic_redist_free_offset; + }; + }; + + /* distributor enabled */ + bool enabled; + + struct vgic_irq *spis; + unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ + + struct vgic_io_device dist_iodev; + + bool has_its; + + /* + * Contains the attributes and gpa of the LPI configuration table. + * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share + * one address across all redistributors. + * GICv3 spec: 6.1.2 "LPI Configuration tables" + */ + u64 propbaser; + + /* Protects the lpi_list and the count value below. */ + spinlock_t lpi_list_lock; + struct list_head lpi_list_head; + int lpi_list_count; +}; + +struct vgic_v2_cpu_if { + u32 vgic_hcr; + u32 vgic_vmcr; + u64 vgic_elrsr; /* Saved only */ + u32 vgic_apr; + u32 vgic_lr[VGIC_V2_MAX_LRS]; +}; + +struct vgic_v3_cpu_if { + u32 vgic_hcr; + u32 vgic_vmcr; + u32 vgic_sre; /* Restored only, change ignored */ + u32 vgic_elrsr; /* Saved only */ + u32 vgic_ap0r[4]; + u32 vgic_ap1r[4]; + u64 vgic_lr[VGIC_V3_MAX_LRS]; +}; + +struct vgic_cpu { + /* CPU vif control registers for world switch */ + union + { + struct vgic_v2_cpu_if vgic_v2; + struct vgic_v3_cpu_if vgic_v3; + }; + + unsigned int used_lrs; + struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; + + spinlock_t ap_list_lock; /* Protects the ap_list */ + + /* + * List of IRQs that this VCPU should consider because they are either + * Active or Pending (hence the name; AP list), or because they recently + * were one of the two and need to be migrated off this list to another + * VCPU. + */ + struct list_head ap_list_head; + + /* + * Members below are used with GICv3 emulation only and represent + * parts of the redistributor. + */ + struct vgic_io_device rd_iodev; + struct vgic_io_device sgi_iodev; + + /* Contains the attributes and gpa of the LPI pending tables. */ + u64 pendbaser; + + bool lpis_enabled; + + /* Cache guest priority bits */ + u32 num_pri_bits; + + /* Cache guest interrupt ID bits */ + u32 num_id_bits; +}; + +extern struct static_key_false vgic_v2_cpuif_trap; +extern struct static_key_false vgic_v3_cpuif_trap; + +#define vgic_initialized(k) ((k)->arch.vgic.initialized) +#define vgic_ready(k) ((k)->arch.vgic.ready) +#define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ + ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) + +bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr); +bool vgic_v3_emulate(struct cpu_user_regs *regs, union hsr hsr); + +void vgic_clear_pending_irqs(struct vcpu *v); + +void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, + paddr_t vbase, void __iomem *hbase, + uint32_t aliased_offset); +struct rdist_region; +void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions, + const struct rdist_region *regions, + unsigned int intid_bits); + +#endif /* __KVM_ARM_VGIC_H */ diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h index 968ffb0c81..e8f2917140 100644 --- a/xen/include/asm-arm/domain.h +++ b/xen/include/asm-arm/domain.h @@ -198,7 +198,11 @@ struct arch_vcpu union gic_state_data gic; uint64_t lr_mask; +#ifdef CONFIG_NEW_VGIC + struct vgic_cpu vgic_cpu; +#else struct vgic_cpu vgic; +#endif /* Timer registers */ uint32_t cntkctl; diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 85ad2aca79..96b99f5c85 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -18,6 +18,10 @@ #ifndef __ASM_ARM_VGIC_H__ #define __ASM_ARM_VGIC_H__ +#ifdef CONFIG_NEW_VGIC +#include +#else + #include #include #include @@ -313,6 +317,8 @@ void vgic_v3_setup_hw(paddr_t dbase, unsigned int intid_bits); #endif +#endif /* !CONFIG_NEW_VGIC */ + /*** Common VGIC functions used by Xen arch code ****/ /* From patchwork Fri Feb 9 14:39:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127831 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679726ljc; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:06 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:09 +0000 Message-Id: <20180209143937.28866-22-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 21/49] ARM: new VGIC: Add acccessor to new struct vgic_irq instance X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC implementation centers around a struct vgic_irq instance per virtual IRQ. Provide a function to retrieve the right instance for a given IRQ number and (in case of private interrupts) the right VCPU. This also includes the corresponding put function, which does nothing for private interrupts and SPIs, but handles the ref-counting for LPIs. This is based on Linux commit 64a959d66e47, written by Christoffer Dall. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 32 ++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic.c create mode 100644 xen/arch/arm/vgic/vgic.h diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c new file mode 100644 index 0000000000..3075091caa --- /dev/null +++ b/xen/arch/arm/vgic/vgic.c @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include +#include "vgic.h" + +/* + * Iterate over the VM's list of mapped LPIs to find the one with a + * matching interrupt ID and return a reference to the IRQ structure. + */ +static struct vgic_irq *vgic_get_lpi(struct domain *d, u32 intid) +{ + struct vgic_dist *dist = &d->arch.vgic; + struct vgic_irq *irq = NULL; + + spin_lock(&dist->lpi_list_lock); + + list_for_each_entry( irq, &dist->lpi_list_head, lpi_list ) + { + if ( irq->intid != intid ) + continue; + + /* + * This increases the refcount, the caller is expected to + * call vgic_put_irq() later once it's finished with the IRQ. + */ + vgic_get_irq_kref(irq); + goto out_unlock; + } + irq = NULL; + +out_unlock: + spin_unlock(&dist->lpi_list_lock); + + return irq; +} + +/* + * This looks up the virtual interrupt ID to get the corresponding + * struct vgic_irq. It also increases the refcount, so any caller is expected + * to call vgic_put_irq() once it's finished with this IRQ. + */ +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid) +{ + /* SGIs and PPIs */ + if ( intid <= VGIC_MAX_PRIVATE ) + return &vcpu->arch.vgic_cpu.private_irqs[intid]; + + /* SPIs */ + if ( intid <= VGIC_MAX_SPI ) + return &d->arch.vgic.spis[intid - VGIC_NR_PRIVATE_IRQS]; + + /* LPIs */ + if ( intid >= VGIC_MIN_LPI ) + return vgic_get_lpi(d, intid); + + WARN(); + return NULL; +} + +void vgic_put_irq(struct domain *d, struct vgic_irq *irq) +{ + struct vgic_dist *dist = &d->arch.vgic; + + if ( irq->intid < VGIC_MIN_LPI ) + return; + + spin_lock(&dist->lpi_list_lock); + if ( !atomic_dec_and_test(&irq->refcount) ) + { + spin_unlock(&dist->lpi_list_lock); + return; + }; + + list_del(&irq->lpi_list); + dist->lpi_list_count--; + spin_unlock(&dist->lpi_list_lock); + + xfree(irq); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h new file mode 100644 index 0000000000..7a15cfdd79 --- /dev/null +++ b/xen/arch/arm/vgic/vgic.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __XEN_ARM_VGIC_NEW_H__ +#define __XEN_ARM_VGIC_NEW_H__ + +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid); +void vgic_put_irq(struct domain *d, struct vgic_irq *irq); + +static inline void vgic_get_irq_kref(struct vgic_irq *irq) +{ + if ( irq->intid < VGIC_MIN_LPI ) + return; + + atomic_inc(&irq->refcount); +} + +#endif From patchwork Fri Feb 9 14:39:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127837 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679787ljc; Fri, 9 Feb 2018 06:42:08 -0800 (PST) X-Google-Smtp-Source: AH8x225HmkjY5CiGGUMVIbiHiI8ZvhHSwcyjlCPJUwGyu4NMbQoPv5pIHF4IVYs0QKOYPGKJmSvv X-Received: by 10.107.20.194 with SMTP id 185mr3183990iou.127.1518187328476; Fri, 09 Feb 2018 06:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187328; cv=none; d=google.com; s=arc-20160816; b=zhK7kh/aMdoU/k9L4GQmKGVyLER4nPHbqjbYHEJDDg/YPMr8+VJDJAaUZBdEMwiLjg J5MFJN0l+e+U3cvk46sXLr2Jw7DxameZZfTDgv1meS6c70nNoBdancm9h2CrAD4FtxNd Ctd2Ri0sVckK0K6PJG5TauIq4oNePF2MydozeitJmwGhoFdPIxS7SEVYchZxhL7ZmqyN BFIukt4fWyzKgH5J1ZLYmMwS1ed4QQUyzizwHTDC8i4Wf2bF1o61e9V57rwQNAvkq/3u fLoasplCT6ATBLdCjKXYtpq+RTV/Lh+4RGiGYtTy4phEZjVgN69TBi5hufTb/WMQh4pT OyJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=te2o17WRGuHjSLRFTpyXSz+6v7t3hI5FTeLLb5M2wCQ=; b=vUNkdqOme/ZdNx//kJQ303xGlulhq/we6eT3QhmAByzgGjTzbxWNajYB9ndVN6xTZ1 T4m0n6iW4ISLN5AvKsrCpNpJKROfA38D68XKKZQ5opzXhcLSra1fnkd+Kh8Jqjy9WoyC TpUR3+hZ8sZ7gSXkTzq8Pov04p4024vOmcPNxZVlurMdlMzlCvA1vAF7MqdwFI8273zP gmFfmlTgqpPQfh/PcnhZH+DIpoOIznuN4H91kHO8Wuj3NyIsVoKlL0IPtiCSi26Bre+G uShk0tmPxChgahsMSgu7Pb8Yx/6TmMAGJLEBD4vBiVqros8W+ecYXNIWo2vcb6QYIR8E Pxjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=FyUEoNVG; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:07 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:10 +0000 Message-Id: <20180209143937.28866-23-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 22/49] ARM: new VGIC: Implement virtual IRQ injection X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Provide a vgic_queue_irq_unlock() function which decides whether a given IRQ needs to be queued to a VCPU's ap_list. This should be called whenever an IRQ becomes pending or enabled, either as a result of a hardware IRQ injection, from devices emulated by Xen (like the architected timer) or from MMIO accesses to the distributor emulation. Also provides the necessary functions to allow to inject an IRQ to a guest. Since this is the first code that starts using our locking mechanism, we add some (hopefully) clear documentation of our locking strategy and requirements along with this patch. This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 224 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 10 +++ 2 files changed, 234 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 3075091caa..f517df6d00 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -21,6 +21,32 @@ #include #include "vgic.h" +/* + * Locking order is always: + * kvm->lock (mutex) + * its->cmd_lock (mutex) + * its->its_lock (mutex) + * vgic_cpu->ap_list_lock + * kvm->lpi_list_lock + * vgic_irq->irq_lock + * + * If you need to take multiple locks, always take the upper lock first, + * then the lower ones, e.g. first take the its_lock, then the irq_lock. + * If you are already holding a lock and need to take a higher one, you + * have to drop the lower ranking lock first and re-aquire it after having + * taken the upper one. + * + * When taking more than one ap_list_lock at the same time, always take the + * lowest numbered VCPU's ap_list_lock first, so: + * vcpuX->vcpu_id < vcpuY->vcpu_id: + * spin_lock(vcpuX->arch.vgic_cpu.ap_list_lock); + * spin_lock(vcpuY->arch.vgic_cpu.ap_list_lock); + * + * Since the VGIC must support injecting virtual interrupts from ISRs, we have + * to use the spin_lock_irqsave/spin_unlock_irqrestore versions of outer + * spinlocks for any lock that may be taken while injecting an interrupt. + */ + /* * Iterate over the VM's list of mapped LPIs to find the one with a * matching interrupt ID and return a reference to the IRQ structure. @@ -97,6 +123,204 @@ void vgic_put_irq(struct domain *d, struct vgic_irq *irq) xfree(irq); } +/** + * vgic_target_oracle - compute the target vcpu for an irq + * + * @irq: The irq to route. Must be already locked. + * + * Based on the current state of the interrupt (enabled, pending, + * active, vcpu and target_vcpu), compute the next vcpu this should be + * given to. Return NULL if this shouldn't be injected at all. + * + * Requires the IRQ lock to be held. + */ +static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); + + /* If the interrupt is active, it must stay on the current vcpu */ + if ( irq->active ) + return irq->vcpu ? : irq->target_vcpu; + + /* + * If the IRQ is not active but enabled and pending, we should direct + * it to its configured target VCPU. + * If the distributor is disabled, pending interrupts shouldn't be + * forwarded. + */ + if ( irq->enabled && irq_is_pending(irq) ) + { + if ( unlikely(irq->target_vcpu && + !irq->target_vcpu->domain->arch.vgic.enabled) ) + return NULL; + + return irq->target_vcpu; + } + + /* If neither active nor pending and enabled, then this IRQ should not + * be queued to any VCPU. + */ + return NULL; +} + +/* + * Only valid injection if changing level for level-triggered IRQs or for a + * rising edge. + */ +static bool vgic_validate_injection(struct vgic_irq *irq, bool level) +{ + switch (irq->config) + { + case VGIC_CONFIG_LEVEL: + return irq->line_level != level; + case VGIC_CONFIG_EDGE: + return level; + } + + return false; +} + +/* + * Check whether an IRQ needs to (and can) be queued to a VCPU's ap list. + * Do the queuing if necessary, taking the right locks in the right order. + * Returns true when the IRQ was queued, false otherwise. + * + * Needs to be entered with the IRQ lock already held, but will return + * with all locks dropped. + */ +bool vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags) +{ + struct vcpu *vcpu; + bool running; + + ASSERT(spin_is_locked(&irq->irq_lock)); + +retry: + vcpu = vgic_target_oracle(irq); + if ( irq->vcpu || !vcpu ) + { + /* + * If this IRQ is already on a VCPU's ap_list, then it + * cannot be moved or modified and there is no more work for + * us to do. + * + * Otherwise, if the irq is not pending and enabled, it does + * not need to be inserted into an ap_list and there is also + * no more work for us to do. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* + * We have to kick the VCPU here, because we could be + * queueing an edge-triggered interrupt for which we + * get no EOI maintenance interrupt. In that case, + * while the IRQ is already on the VCPU's AP list, the + * VCPU could have EOI'ed the original interrupt and + * won't see this one until it exits for some other + * reason. + */ + if ( vcpu ) + vcpu_unblock(vcpu); + return false; + } + + /* + * We must unlock the irq lock to take the ap_list_lock where + * we are going to insert this new pending interrupt. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* someone can do stuff here, which we re-check below */ + + spin_lock_irqsave(&vcpu->arch.vgic_cpu.ap_list_lock, flags); + spin_lock(&irq->irq_lock); + + /* + * Did something change behind our backs? + * + * There are two cases: + * 1) The irq lost its pending state or was disabled behind our + * backs and/or it was queued to another VCPU's ap_list. + * 2) Someone changed the affinity on this irq behind our + * backs and we are now holding the wrong ap_list_lock. + * + * In both cases, drop the locks and retry. + */ + + if ( unlikely(irq->vcpu || vcpu != vgic_target_oracle(irq)) ) + { + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags); + + spin_lock_irqsave(&irq->irq_lock, flags); + goto retry; + } + + /* + * Grab a reference to the irq to reflect the fact that it is + * now in the ap_list. + */ + vgic_get_irq_kref(irq); + list_add_tail(&irq->ap_list, &vcpu->arch.vgic_cpu.ap_list_head); + irq->vcpu = vcpu; + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic_cpu.ap_list_lock, flags); + + running = vcpu->is_running; + vcpu_unblock(vcpu); + if ( running && vcpu != current ) + smp_send_event_check_mask(cpumask_of(vcpu->processor)); + + return true; +} + +/** + * vgic_inject_irq - Inject an IRQ from a device to the vgic + * @d: The domain pointer + * @vcpu: The vCPU for PPIs + * @intid: The INTID to inject a new state to. + * @level: Edge-triggered: true: to trigger the interrupt + * false: to ignore the call + * Level-sensitive true: raise the input signal + * false: lower the input signal + * + * The VGIC is not concerned with devices being active-LOW or active-HIGH for + * level-sensitive interrupts. You can think of the level parameter as 1 + * being HIGH and 0 being LOW and all devices being active-HIGH. + */ +int vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, + bool level) +{ + struct vgic_irq *irq; + unsigned long flags; + + irq = vgic_get_irq(d, vcpu, intid); + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( !vgic_validate_injection(irq, level) ) + { + /* Nothing to see here, move along... */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + return 0; + } + + if ( irq->config == VGIC_CONFIG_LEVEL ) + irq->line_level = level; + else + irq->pending_latch = true; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 7a15cfdd79..5127739f0f 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,9 +17,19 @@ #ifndef __XEN_ARM_VGIC_NEW_H__ #define __XEN_ARM_VGIC_NEW_H__ +static inline bool irq_is_pending(struct vgic_irq *irq) +{ + if ( irq->config == VGIC_CONFIG_EDGE ) + return irq->pending_latch; + else + return irq->pending_latch || irq->line_level; +} + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); +bool vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Fri Feb 9 14:39:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127841 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679839ljc; Fri, 9 Feb 2018 06:42:12 -0800 (PST) X-Google-Smtp-Source: AH8x226BtNOqZW8CVxRtrjLibDus8q4ic9SZcTQFIgjeFTuPrSc57qbKBgeysYTCMdPkrr5MsyNh X-Received: by 10.36.124.84 with SMTP id a81mr3418858itd.97.1518187332785; Fri, 09 Feb 2018 06:42:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187332; cv=none; d=google.com; s=arc-20160816; b=vHV3elKyZs0KX3MmQnFqCcutzMQoGfLnKZG24PFQLfh8h+UVes+JryqK+0CYL8uLun oAMVkPSS7Ioa5aIpin7VChws3ZxaiLFRx5nUzWgy6fVwW22Jnb3bG2R4buBRaJXfhCjC P4rNPMiFkHDmefFDNN5DeTg8CMpWRqNXavcwh8y+voGhe/Kl5UazOSKJxVoZAcVxxcGi Z1LwBFUQGgUpi38LKeIROCYNxVAekNadQnuFL2O73dWgWiYKNMZJRbzbikokuGqIePk7 6yE/yFvXSz80UadXq9qyWHOV6q1LtK2zv7sqJ0qFWoxQ6Bvl0g8NwbFdBcbpw1g/AzM+ CmqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=DHtZJcIeUfwQkCgGoWcE/qdlIsgn2Oegs2IeayW/Nyc=; b=X9wetN/VTFtMnj/vQP57ysWoRcCqEcH2XjEh641OElfzARG6wvplPfs9vp/F6dlRgk hJ7MJhbwz8Z+4mGXxVH15Dmbtnyv4BvPpsP4fZkdKFx3Vxw7d0ZJwGkAk6a2rhPa1wX1 V1ocauArmJSohjN7vjEPZuuUETUK6bu4zjNkBE1q6S19vhxjAfwzhoHjOHIRLPf2Ijxy qRY+gI75yuimWVR6/asAyPuPQHBcofjSmUUTnsK8xeIMNS4lexX10x478gF8f7F2NmRT uCeBLefYzyS/f0YcbAcOiYY9LqtZH/uIap06KhDeL4Z/sLDOu66RtmsnYRkGzrDqJRkB xKeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CT905u/i; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:08 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:11 +0000 Message-Id: <20180209143937.28866-24-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 23/49] ARM: new VGIC: Add IRQ sorting X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Adds the sorting function to cover the case where you have more IRQs to consider than you have LRs. We consider their priorities. This pulls in Linux' list_sort.c , which is a merge sort implementation for linked lists. This is based on Linux commit 8e4447457965, written by Christoffer Dall. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 59 +++++++++++++++ xen/common/list_sort.c | 170 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/xen/list_sort.h | 11 +++ 3 files changed, 240 insertions(+) create mode 100644 xen/common/list_sort.c create mode 100644 xen/include/xen/list_sort.h diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index f517df6d00..a4efd1fd03 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -16,6 +16,7 @@ */ #include +#include #include #include @@ -163,6 +164,64 @@ static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) return NULL; } +/* + * The order of items in the ap_lists defines how we'll pack things in LRs as + * well, the first items in the list being the first things populated in the + * LRs. + * + * A hard rule is that active interrupts can never be pushed out of the LRs + * (and therefore take priority) since we cannot reliably trap on deactivation + * of IRQs and therefore they have to be present in the LRs. + * + * Otherwise things should be sorted by the priority field and the GIC + * hardware support will take care of preemption of priority groups etc. + * + * Return negative if "a" sorts before "b", 0 to preserve order, and positive + * to sort "b" before "a". + */ +static int vgic_irq_cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct vgic_irq *irqa = container_of(a, struct vgic_irq, ap_list); + struct vgic_irq *irqb = container_of(b, struct vgic_irq, ap_list); + bool penda, pendb; + int ret; + + spin_lock(&irqa->irq_lock); + spin_lock(&irqb->irq_lock); + + if ( irqa->active || irqb->active ) + { + ret = (int)irqb->active - (int)irqa->active; + goto out; + } + + penda = irqa->enabled && irq_is_pending(irqa); + pendb = irqb->enabled && irq_is_pending(irqb); + + if ( !penda || !pendb ) + { + ret = (int)pendb - (int)penda; + goto out; + } + + /* Both pending and enabled, sort by priority */ + ret = irqa->priority - irqb->priority; +out: + spin_unlock(&irqb->irq_lock); + spin_unlock(&irqa->irq_lock); + return ret; +} + +/* Must be called with the ap_list_lock held */ +static void vgic_sort_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_sort(NULL, &vgic_cpu->ap_list_head, vgic_irq_cmp); +} + /* * Only valid injection if changing level for level-triggered IRQs or for a * rising edge. diff --git a/xen/common/list_sort.c b/xen/common/list_sort.c new file mode 100644 index 0000000000..9c5cc58e43 --- /dev/null +++ b/xen/common/list_sort.c @@ -0,0 +1,170 @@ +/* + * list_sort.c: merge sort implementation for linked lists + * Copied from the Linux kernel (lib/list_sort.c) + * (without specific copyright notice there) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; If not, see . + */ +#include +#include + +#define MAX_LIST_LENGTH_BITS 20 + +/* + * Returns a list organized in an intermediate format suited + * to chaining of merge() calls: null-terminated, no reserved or + * sentinel head node, "prev" links not maintained. + */ +static struct list_head *merge(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *a, struct list_head *b) +{ + struct list_head head, *tail = &head; + + while ( a && b ) + { + /* if equal, take 'a' -- important for sort stability */ + if ( (*cmp)(priv, a, b) <= 0 ) + { + tail->next = a; + a = a->next; + } + else + { + tail->next = b; + b = b->next; + } + tail = tail->next; + } + tail->next = a?:b; + return head.next; +} + +/* + * Combine final list merge with restoration of standard doubly-linked + * list structure. This approach duplicates code from merge(), but + * runs faster than the tidier alternatives of either a separate final + * prev-link restoration pass, or maintaining the prev links + * throughout. + */ +static void merge_and_restore_back_links(void *priv, + int (*cmp)(void *priv, + struct list_head *a, + struct list_head *b), + struct list_head *head, + struct list_head *a, + struct list_head *b) +{ + struct list_head *tail = head; + u8 count = 0; + + while ( a && b ) + { + /* if equal, take 'a' -- important for sort stability */ + if ( (*cmp)(priv, a, b) <= 0 ) + { + tail->next = a; + a->prev = tail; + a = a->next; + } + else + { + tail->next = b; + b->prev = tail; + b = b->next; + } + tail = tail->next; + } + tail->next = a ? : b; + + do + { + /* + * In worst cases this loop may run many iterations. + * Continue callbacks to the client even though no + * element comparison is needed, so the client's cmp() + * routine can invoke cond_resched() periodically. + */ + if ( unlikely(!(++count)) ) + (*cmp)(priv, tail->next, tail->next); + + tail->next->prev = tail; + tail = tail->next; + } while ( tail->next ); + + tail->next = head; + head->prev = tail; +} + +/** + * list_sort - sort a list + * @priv: private data, opaque to list_sort(), passed to @cmp + * @head: the list to sort + * @cmp: the elements comparison function + * + * This function implements "merge sort", which has O(nlog(n)) + * complexity. + * + * The comparison function @cmp must return a negative value if @a + * should sort before @b, and a positive value if @a should sort after + * @b. If @a and @b are equivalent, and their original relative + * ordering is to be preserved, @cmp must return 0. + */ +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, struct list_head *b)) +{ + struct list_head *part[MAX_LIST_LENGTH_BITS+1]; /* sorted partial lists + -- last slot is a sentinel */ + int lev; /* index into part[] */ + int max_lev = 0; + struct list_head *list; + + if ( list_empty(head) ) + return; + + memset(part, 0, sizeof(part)); + + head->prev->next = NULL; + list = head->next; + + while ( list ) + { + struct list_head *cur = list; + list = list->next; + cur->next = NULL; + + for ( lev = 0; part[lev]; lev++ ) + { + cur = merge(priv, cmp, part[lev], cur); + part[lev] = NULL; + } + if ( lev > max_lev ) + { + if ( unlikely(lev >= ARRAY_SIZE(part)-1) ) + { + dprintk(XENLOG_DEBUG, "list too long for efficiency\n"); + lev--; + } + max_lev = lev; + } + part[lev] = cur; + } + + for ( lev = 0; lev < max_lev; lev++ ) + if ( part[lev] ) + list = merge(priv, cmp, part[lev], list); + + merge_and_restore_back_links(priv, cmp, head, part[max_lev], list); +} +EXPORT_SYMBOL(list_sort); diff --git a/xen/include/xen/list_sort.h b/xen/include/xen/list_sort.h new file mode 100644 index 0000000000..a60c589d4b --- /dev/null +++ b/xen/include/xen/list_sort.h @@ -0,0 +1,11 @@ +#ifndef _LINUX_LIST_SORT_H +#define _LINUX_LIST_SORT_H + +#include + +struct list_head; + +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)); +#endif From patchwork Fri Feb 9 14:39:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127818 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679538ljc; Fri, 9 Feb 2018 06:41:55 -0800 (PST) X-Google-Smtp-Source: AH8x2279OCbExJDZWK3FTjAsvcqCwzZu0L2OMGwDFwi8XJiTui2ARjRpWibfr1MypfdtBTxcIb4I X-Received: by 10.107.104.8 with SMTP id d8mr3223187ioc.119.1518187315062; Fri, 09 Feb 2018 06:41:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187315; cv=none; d=google.com; s=arc-20160816; b=Ow76rEcVG+yrh2qKQBsPYG6BflLpoaVosx6feL/+r5RM+lxKAhO4WIibI7Xdq8aRPm I8IyTYD8hHvkHbXhh0t7sIQ0/mv1HuFQb4XlcYGFun1wtjB7+DGFh7W/TKManNtYkKqg uXL8swlLmgzH8uxiKlPcg9NzIn6Uac53QB7WE14LDUHTrY0xxxaNQSy32WwZ68uEMSiB 1rva6/6TgxSRGSO9DfSek1WbHi+A+R4Q7jmzQrLIvAhJCSvi1LMKCM3IMR7qiW/KREMM vZqSNi+K5i11mb9aWih17QMiI2YF9NjBNUPpHiyTHHKRYICXPqB2EpwZ+5KG2LtDoVsR 9iPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=wfE1PlucApM3qZaqTSS1eBbX12eZ47ZvMwSkxgpWhgU=; b=mO49ePcL9lMu2DjiNve+DoVIw3+e470HV4TRPY1oWBGALCMxyBFpYXGrrxZQWqGI4K JnxnLLaHr2qFNpDTLIDYTiDPXTq4Nywuqkyaqyrrs+P0Jtj0+LpJuWxFa74S0UPayB5q H3inOxMrDBIt5T+0rHFzAGnrd2yT8toBvwOrEZBU171HrdQkJPqGzq9eAAAPcUj21oZX 9DKK+r78uJyXtCbqg0XwLvaPPxXAxA48ULz+Njp1wmO8Zj1TtDfZsAK2FGw/oGMYvS6E ptyGG589Wcq6jqRWzwtaGU8JOa9VdL1V8E6lNcDagnPKLwg0cJLiniKSsDrgPg/XNHBa JWTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QumgKZws; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id w69si1751878ith.131.2018.02.09.06.41.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:41:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QumgKZws; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qY-0000oC-9Y; Fri, 09 Feb 2018 14:40:14 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qX-0000l0-BD for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:13 +0000 X-Inumbo-ID: 10e1182a-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 10e1182a-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:43 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id 41so8460945wrc.9 for ; Fri, 09 Feb 2018 06:40:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=lOs5JkyXYBe4BLrNdmZxt5v92qlZ0SIVbJzDAiSeLxk=; b=QumgKZwsn7nAf3owKfUK9bBboS5leAVnhL5Q0J1/Vj+WB+ejp6H9IU66MB3jhM8QHB nFeRZgcQO6RfREDG0dkee3OGyJ7EqSrmh5lv6Y5BWMaxO+XA3cHzm44RoqRfbrhPJKiP ShKeCTuI7B1g8nH1Z4ksMPbYqUr/98pT7qXeA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=lOs5JkyXYBe4BLrNdmZxt5v92qlZ0SIVbJzDAiSeLxk=; b=Lq9qGes9xxvGS+XJc+OzFi5xWLWCleOKlF6ogn75e2hknbNGTvsZFu0WMogQgBeeok xg9Ta96LI+9PNIpVNba+2uX9UFmfp2BG836XThurwb9Vv9Z6u5DpMICvM/BJKjVU7Exk +uV68zqH3SQbGrXJu5uYmNsD6C1lC6lGJkO8Q26BkaUZBqju3hXo8ZuXc9wiCczsD4fc 6EJJYZEilNlR2eZYcyYgALY+vY5hhw1hjvWTNKvkXdgkw/CBm8l+7CoBdrKYv4EPtAap +d5sQp80M1Ln+4y1btZlfNoTQ85nk3wX7802jie27wW/2xjfY26LrUvZpP9IW4QxWgIp uUuw== X-Gm-Message-State: APf1xPD3qhnTTJke9wiiDRi0Z8TbDg/iYVq6cZUjol2Lo/uls6/T5lNY MqyJ8z5ypK8UxE1FuLQfk0mDOQ== X-Received: by 10.223.163.16 with SMTP id c16mr2827248wrb.21.1518187210498; Fri, 09 Feb 2018 06:40:10 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:09 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:12 +0000 Message-Id: <20180209143937.28866-25-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 24/49] ARM: new VGIC: Add IRQ sync/flush framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Implement the framework for syncing IRQs between our emulation and the list registers, which represent the guest's view of IRQs. This is done in kvm_vgic_flush_hwstate and kvm_vgic_sync_hwstate, which gets called on guest entry and exit. The code talking to the actual GICv2/v3 hardware is added in the following patches. This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 246 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 2 + 2 files changed, 248 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index a4efd1fd03..a1f77130d4 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -380,6 +380,252 @@ int vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, return 0; } +/** + * vgic_prune_ap_list - Remove non-relevant interrupts from the list + * + * @vcpu: The VCPU pointer + * + * Go over the list of "interesting" interrupts, and prune those that we + * won't have to consider in the near future. + */ +static void vgic_prune_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + struct vgic_irq *irq, *tmp; + unsigned long flags; + +retry: + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry_safe( irq, tmp, &vgic_cpu->ap_list_head, ap_list ) + { + struct vcpu *target_vcpu, *vcpuA, *vcpuB; + + spin_lock(&irq->irq_lock); + + BUG_ON(vcpu != irq->vcpu); + + target_vcpu = vgic_target_oracle(irq); + + if ( !target_vcpu ) + { + /* + * We don't need to process this interrupt any + * further, move it off the list. + */ + list_del(&irq->ap_list); + irq->vcpu = NULL; + spin_unlock(&irq->irq_lock); + + /* + * This vgic_put_irq call matches the + * vgic_get_irq_kref in vgic_queue_irq_unlock, + * where we added the LPI to the ap_list. As + * we remove the irq from the list, we drop + * also drop the refcount. + */ + vgic_put_irq(vcpu->domain, irq); + continue; + } + + if ( target_vcpu == vcpu ) + { + /* We're on the right CPU */ + spin_unlock(&irq->irq_lock); + continue; + } + + /* This interrupt looks like it has to be migrated. */ + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + /* + * Ensure locking order by always locking the smallest + * ID first. + */ + if ( vcpu->vcpu_id < target_vcpu->vcpu_id ) + { + vcpuA = vcpu; + vcpuB = target_vcpu; + } + else + { + vcpuA = target_vcpu; + vcpuB = vcpu; + } + + spin_lock_irqsave(&vcpuA->arch.vgic_cpu.ap_list_lock, flags); + spin_lock(&vcpuB->arch.vgic_cpu.ap_list_lock); + spin_lock(&irq->irq_lock); + + /* + * If the affinity has been preserved, move the + * interrupt around. Otherwise, it means things have + * changed while the interrupt was unlocked, and we + * need to replay this. + * + * In all cases, we cannot trust the list not to have + * changed, so we restart from the beginning. + */ + if ( target_vcpu == vgic_target_oracle(irq) ) + { + struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic_cpu; + + list_del(&irq->ap_list); + irq->vcpu = target_vcpu; + list_add_tail(&irq->ap_list, &new_cpu->ap_list_head); + } + + spin_unlock(&irq->irq_lock); + spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock); + spin_unlock_irqrestore(&vcpuA->arch.vgic_cpu.ap_list_lock, flags); + goto retry; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); +} + +static inline void vgic_fold_lr_state(struct vcpu *vcpu) +{ +} + +/* Requires the irq_lock to be held. */ +static inline void vgic_populate_lr(struct vcpu *vcpu, + struct vgic_irq *irq, int lr) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); +} + +static inline void vgic_clear_lr(struct vcpu *vcpu, int lr) +{ +} + +static inline void vgic_set_underflow(struct vcpu *vcpu) +{ +} + +/* Requires the ap_list_lock to be held. */ +static int compute_ap_list_depth(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + /* GICv2 SGIs can count for more than one... */ + if ( vgic_irq_is_sgi(irq->intid) && irq->source ) + count += hweight8(irq->source); + else + count++; + spin_unlock(&irq->irq_lock); + } + return count; +} + +/* Requires the VCPU's ap_list_lock to be held. */ +static void vgic_flush_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + if ( compute_ap_list_depth(vcpu) > gic_get_nr_lrs() ) + vgic_sort_ap_list(vcpu); + + list_for_each_entry( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + + if ( unlikely(vgic_target_oracle(irq) != vcpu) ) + goto next; + + /* + * If we get an SGI with multiple sources, try to get + * them in all at once. + */ + do + { + vgic_populate_lr(vcpu, irq, count++); + } while ( irq->source && count < gic_get_nr_lrs() ); + +next: + spin_unlock(&irq->irq_lock); + + if ( count == gic_get_nr_lrs() ) + { + if ( !list_is_last(&irq->ap_list, &vgic_cpu->ap_list_head) ) + vgic_set_underflow(vcpu); + break; + } + } + + vcpu->arch.vgic_cpu.used_lrs = count; + + /* Nuke remaining LRs */ + for ( ; count < gic_get_nr_lrs(); count++) + vgic_clear_lr(vcpu, count); +} + +/* + * gic_clear_lrs() - Update the VGIC state from hardware after a guest's run. + * @vcpu: the VCPU. + * + * Sync back the hardware VGIC state after the guest has run, into our + * VGIC emulation structures, It reads the LRs and updates the respective + * struct vgic_irq, taking level/edge into account. + * This is the high level function which takes care of the conditions, + * also bails out early if there were no interrupts queued. + * Was: kvm_vgic_sync_hwstate() + */ +void gic_clear_lrs(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + + /* An empty ap_list_head implies used_lrs == 0 */ + if ( list_empty(&vcpu->arch.vgic_cpu.ap_list_head) ) + return; + + if ( vgic_cpu->used_lrs ) + vgic_fold_lr_state(vcpu); + vgic_prune_ap_list(vcpu); +} + +/* + * gic_inject() - flush the emulation state into the hardware on guest entry + * + * Before we enter a guest, we have to translate the virtual GIC state of a + * VCPU into the GIC virtualization hardware registers, namely the LRs. + * This is the high level function which takes care about the conditions + * and the locking, also bails out early if there are no interrupts queued. + * Was: kvm_vgic_flush_hwstate() + */ +void gic_inject(void) +{ + /* + * If there are no virtual interrupts active or pending for this + * VCPU, then there is no work to do and we can bail out without + * taking any lock. There is a potential race with someone injecting + * interrupts to the VCPU, but it is a benign race as the VCPU will + * either observe the new interrupt before or after doing this check, + * and introducing additional synchronization mechanism doesn't change + * this. + */ + if ( list_empty(¤t->arch.vgic_cpu.ap_list_head) ) + return; + + ASSERT(!local_irq_is_enabled()); + + spin_lock(¤t->arch.vgic_cpu.ap_list_lock); + vgic_flush_lr_state(current); + spin_unlock(¤t->arch.vgic_cpu.ap_list_lock); +} /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 5127739f0f..47fc58b81e 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,8 @@ #ifndef __XEN_ARM_VGIC_NEW_H__ #define __XEN_ARM_VGIC_NEW_H__ +#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) + static inline bool irq_is_pending(struct vgic_irq *irq) { if ( irq->config == VGIC_CONFIG_EDGE ) From patchwork Fri Feb 9 14:39:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127850 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679967ljc; Fri, 9 Feb 2018 06:42:21 -0800 (PST) X-Google-Smtp-Source: AH8x224LXTFqyyVx5KLqkVdh/Z61DHiwEWR5r6gUwv6351ejz2vJUp4aU2w8srkQ99SUQDUl0lqM X-Received: by 10.107.151.72 with SMTP id z69mr3296309iod.185.1518187340973; Fri, 09 Feb 2018 06:42:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187340; cv=none; d=google.com; s=arc-20160816; b=Bwyum9KvlwJe8tty7HF8iUClYgN34m5PaFZmwMXQFd/viIMcL9z+x1bwyww0wIMVIY U8fw9zU4EOPn3dti/ZpHtoe1b22ES1g0NYOwd72OzC+BKStfzZsBKhmRozox8rdkq73b jix3dA6EDQHDoTihXmwN3ZECCwSCMmafuNOkDmbxXsTvhqtXXLYnQEhGoxIQEWl5YoZP VZMaKxlkIAt//PYdiiAcmQXF8V4ep4nAz3zEGbdF4j96Db4neL6MgaPBNrpJ1peQvBbl v9Imz99iI98LSFripXB1fKg5GrJ+0Ej2MJJUwOLSBX9BkhLB5qPVu2Z1JLZU4qAxDz1V 1f9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=5G0PWyutXot1BglpYanC2z4sXJjVW3ClFYqs0O7akQo=; b=hOpMqPbDgHW/ASeTwCnvpx4D5tdxtUVoN7ywS6yNwosoNRN/s9Ch2Y/xcv1LO4skHq 06rRl8Yn4X0peRRDTd3pQDUIgHTBLhZB1qz2ZpnhqaFFTgkUgD2mRxsgtPjfUWhSmc1j ic00IHY7fMRSPWCzO9XVq6tB69O1rZFAKCGodrDBHrKoYVeY+CmTacgm+XnxLk8m3kVN xUyKJjzEqzctG48orjwiOO9UadJwHwpCOK1rUYAuF4yWRinkFABSsbc+TRB1LaT06k7C ZCw5d3iNw9Wo5qq40/oMnUogIxc8OfxOBbcIL1Wp4qOHja2TQcIOzir07R+TMSgnXYA6 NHhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=F8TjLPhQ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:11 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:13 +0000 Message-Id: <20180209143937.28866-26-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 25/49] ARM: new VGIC: Add GICv2 world switch backend X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Processing maintenance interrupts and accessing the list registers are dependent on the host's GIC version. Introduce vgic-v2.c to contain GICv2 specific functions. Implement the GICv2 specific code for syncing the emulation state into the VGIC registers. This also adds the hook to let Xen setup the host GIC addresses. This is based on Linux commit 140b086dd197, written by Marc Zyngier. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-v2.c | 261 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 20 ++++ xen/arch/arm/vgic/vgic.h | 8 ++ 3 files changed, 289 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-v2.c diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c new file mode 100644 index 0000000000..10fc467ffa --- /dev/null +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -0,0 +1,261 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" + +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_LR0 0x100 + +#define GICH_LR_VIRTUALID (0x3ff << 0) +#define GICH_LR_PHYSID_CPUID_SHIFT (10) +#define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) +#define GICH_LR_PRIORITY_SHIFT 23 +#define GICH_LR_STATE (3 << 28) +#define GICH_LR_PENDING_BIT (1 << 28) +#define GICH_LR_ACTIVE_BIT (1 << 29) +#define GICH_LR_EOI (1 << 19) +#define GICH_LR_HW (1 << 31) + +static struct { + bool enabled; + paddr_t dbase; /* Distributor interface address */ + paddr_t cbase; /* CPU interface address & size */ + paddr_t csize; + paddr_t vbase; /* Virtual CPU interface address */ + void __iomem *hbase; /* Hypervisor control interface */ + + /* Offset to add to get an 8kB contiguous region if GIC is aliased */ + uint32_t aliased_offset; +} gic_v2_hw_data; + +void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, + paddr_t vbase, void __iomem *hbase, + uint32_t aliased_offset) +{ + gic_v2_hw_data.enabled = true; + gic_v2_hw_data.dbase = dbase; + gic_v2_hw_data.cbase = cbase; + gic_v2_hw_data.csize = csize; + gic_v2_hw_data.vbase = vbase; + gic_v2_hw_data.hbase = hbase; + gic_v2_hw_data.aliased_offset = aliased_offset; +} + +void vgic_v2_set_underflow(struct vcpu *vcpu) +{ + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, 1); +} + +/* + * transfer the content of the LRs back into the corresponding ap_list: + * - active bit is transferred as is + * - pending bit is + * - transferred as is in case of edge sensitive IRQs + * - set to the line-level (resample time) for level sensitive IRQs + */ +void vgic_v2_fold_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2; + int lr; + unsigned long flags; + + cpuif->vgic_hcr &= ~GICH_HCR_UIE; + + for ( lr = 0; lr < vgic_cpu->used_lrs; lr++ ) + { + u32 val = cpuif->vgic_lr[lr]; + u32 intid = val & GICH_LR_VIRTUALID; + struct vgic_irq *irq; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid); + + spin_lock_irqsave(&irq->irq_lock, flags); + + /* Always preserve the active bit */ + irq->active = !!(val & GICH_LR_ACTIVE_BIT); + + /* Edge is the only case where we preserve the pending bit */ + if ( irq->config == VGIC_CONFIG_EDGE && (val & GICH_LR_PENDING_BIT) ) + { + irq->pending_latch = true; + + if ( vgic_irq_is_sgi(intid) ) + { + u32 cpuid = val & GICH_LR_PHYSID_CPUID; + + cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; + irq->source |= (1 << cpuid); + } + } + + if ( irq->hw && irq->config == VGIC_CONFIG_LEVEL && + (val & GICH_LR_PENDING_BIT) ) + { + irq->line_level = gic_read_pending_state(irq->hwintid); + + if ( !irq->line_level ) + gic_set_active_state(irq->hwintid, true); + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } + + vgic_cpu->used_lrs = 0; +} + +/* + * Populates the particular LR with the state of a given IRQ: + * - for an edge sensitive IRQ the pending state is cleared in struct vgic_irq + * - for a level sensitive IRQ the pending state value is unchanged; + * it is dictated directly by the input level + * + * If @irq describes an SGI with multiple sources, we choose the + * lowest-numbered source VCPU and clear that bit in the source bitmap. + * + * The irq_lock must be held by the caller. + */ +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) +{ + u32 val = irq->intid; + + if ( irq_is_pending(irq) ) + { + val |= GICH_LR_PENDING_BIT; + + if ( irq->config == VGIC_CONFIG_EDGE ) + irq->pending_latch = false; + + if ( vgic_irq_is_sgi(irq->intid) ) + { + u32 src = ffs(irq->source); + + BUG_ON(!src); + val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; + irq->source &= ~(1 << (src - 1)); + if ( irq->source ) + irq->pending_latch = true; + } + } + + if ( irq->active ) + val |= GICH_LR_ACTIVE_BIT; + + if ( irq->hw ) + { + val |= GICH_LR_HW; + val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if ( irq->active && irq_is_pending(irq) ) + val &= ~GICH_LR_PENDING_BIT; + } + else + { + if ( irq->config == VGIC_CONFIG_LEVEL ) + val |= GICH_LR_EOI; + } + + /* + * Level-triggered mapped IRQs are special because we only observe + * rising edges as input to the VGIC. We therefore lower the line + * level here, so that we can take new virtual IRQs. See + * vgic_v2_fold_lr_state for more info. + */ + if ( irq->hw && irq->config == VGIC_CONFIG_LEVEL && + (val & GICH_LR_PENDING_BIT) ) + irq->line_level = false; + + /* The GICv2 LR only holds five bits of priority. */ + val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT; + + vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val; +} + +void vgic_v2_clear_lr(struct vcpu *vcpu, int lr) +{ + vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0; +} + +static void save_lrs(struct vcpu *vcpu, void __iomem *base) +{ + struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; + u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; + u64 elrsr; + int i; + + elrsr = readl_relaxed(base + GICH_ELRSR0); + if ( unlikely(used_lrs > 32) ) + elrsr |= ((u64)readl_relaxed(base + GICH_ELRSR1)) << 32; + + for ( i = 0; i < used_lrs; i++ ) + { + if ( elrsr & (1UL << i) ) + cpu_if->vgic_lr[i] &= ~GICH_LR_STATE; + else + cpu_if->vgic_lr[i] = readl_relaxed(base + GICH_LR0 + (i * 4)); + + writel_relaxed(0, base + GICH_LR0 + (i * 4)); + } +} + +void vgic_v2_save_state(struct vcpu *vcpu) +{ + u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; + + if ( used_lrs ) + { + save_lrs(vcpu, gic_v2_hw_data.hbase); + writel_relaxed(0, gic_v2_hw_data.hbase + GICH_HCR); + } +} + +void vgic_v2_restore_state(struct vcpu *vcpu) +{ + struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; + u64 used_lrs = vcpu->arch.vgic_cpu.used_lrs; + int i; + + if ( used_lrs ) + { + writel_relaxed(cpu_if->vgic_hcr, + gic_v2_hw_data.hbase + GICH_HCR); + for ( i = 0; i < used_lrs; i++ ) + writel_relaxed(cpu_if->vgic_lr[i], + gic_v2_hw_data.hbase + GICH_LR0 + (i * 4)); + } +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index a1f77130d4..f4f2a04a60 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -488,6 +488,7 @@ retry: static inline void vgic_fold_lr_state(struct vcpu *vcpu) { + vgic_v2_fold_lr_state(vcpu); } /* Requires the irq_lock to be held. */ @@ -495,14 +496,18 @@ static inline void vgic_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) { ASSERT(spin_is_locked(&irq->irq_lock)); + + vgic_v2_populate_lr(vcpu, irq, lr); } static inline void vgic_clear_lr(struct vcpu *vcpu, int lr) { + vgic_v2_clear_lr(vcpu, lr); } static inline void vgic_set_underflow(struct vcpu *vcpu) { + vgic_v2_set_underflow(vcpu); } /* Requires the ap_list_lock to be held. */ @@ -573,6 +578,11 @@ next: vgic_clear_lr(vcpu, count); } +static inline void vgic_save_state(struct vcpu *vcpu) +{ + vgic_v2_save_state(vcpu); +} + /* * gic_clear_lrs() - Update the VGIC state from hardware after a guest's run. * @vcpu: the VCPU. @@ -592,11 +602,18 @@ void gic_clear_lrs(struct vcpu *vcpu) if ( list_empty(&vcpu->arch.vgic_cpu.ap_list_head) ) return; + vgic_save_state(vcpu); + if ( vgic_cpu->used_lrs ) vgic_fold_lr_state(vcpu); vgic_prune_ap_list(vcpu); } +static inline void vgic_restore_state(struct vcpu *vcpu) +{ + vgic_v2_restore_state(vcpu); +} + /* * gic_inject() - flush the emulation state into the hardware on guest entry * @@ -625,7 +642,10 @@ void gic_inject(void) spin_lock(¤t->arch.vgic_cpu.ap_list_lock); vgic_flush_lr_state(current); spin_unlock(¤t->arch.vgic_cpu.ap_list_lock); + + vgic_restore_state(current); } + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 47fc58b81e..771ca6f046 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -41,4 +41,12 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) atomic_inc(&irq->refcount); } +void vgic_v2_fold_lr_state(struct vcpu *vcpu); +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); +void vgic_v2_clear_lr(struct vcpu *vcpu, int lr); +void vgic_v2_set_underflow(struct vcpu *vcpu); + +void vgic_v2_save_state(struct vcpu *vcpu); +void vgic_v2_restore_state(struct vcpu *vcpu); + #endif From patchwork Fri Feb 9 14:39:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127823 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679625ljc; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:12 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:14 +0000 Message-Id: <20180209143937.28866-27-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 26/49] ARM: new VGIC: Implement vgic_vcpu_pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Tell Xen whether a particular VCPU has an IRQ that needs handling in the guest. This is used to decide whether a VCPU is runnable. This is based on Linux commit 90eee56c5f90, written by Eric Auger. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index f4f2a04a60..9e7fb1edcb 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -646,6 +646,38 @@ void gic_inject(void) vgic_restore_state(current); } +static int vgic_vcpu_pending_irq(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + struct vgic_irq *irq; + bool pending = false; + unsigned long flags; + + if ( !vcpu->domain->arch.vgic.enabled ) + return false; + + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + pending = irq_is_pending(irq) && irq->enabled; + spin_unlock(&irq->irq_lock); + + if ( pending ) + break; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + return pending; +} + +int gic_events_need_delivery(void) +{ + return vgic_vcpu_pending_irq(current); +} + /* * Local variables: * mode: C From patchwork Fri Feb 9 14:39:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127816 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679514ljc; Fri, 9 Feb 2018 06:41:53 -0800 (PST) X-Google-Smtp-Source: AH8x226QsharA+mSVvL7Ah9779rQaeygQv78sSRabGhB36mq+Bn/BeKsS+471StZpaCssQNbNYzj X-Received: by 10.36.139.66 with SMTP id g63mr3928603ite.88.1518187313643; Fri, 09 Feb 2018 06:41:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187313; cv=none; d=google.com; s=arc-20160816; b=hF+g61KQmEF4bvPI8nlj76qL/bEq3ixOvhqdWFiuLWuWA41kuzPJeuwLFEkiBe7hE1 sMbQDmybuwqsdt6WEi3pJ9kF2E4SWFTytEj6zQpEUTG6u8x/74WQWBqImUOZW+iKl5lj nIJaj17JwXkFR/wkiSTBn6YndtiElKTICWsZBWAgCB/p3+oPYDW22k7KMh3sxSGfgiDz oYS1NJZ/vHfZ+cS2avHRGLs9ZT48KGjCRAIVAGzRyWUNSLzqMFafvL600vGiE1TFZGra qEwkvGlILWhnmD3zOeKQsXuScbgUomVDeMPUqUrUObGfQpp0ccPmSM2lgbbkj1Ryc1sJ 61Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=dmd+TzhXwCHfT9/IksZPVVq45Lu/UW/c4X69op/2TxY=; b=lEYSqAke1FvKAugeSG2TQcLTO+2b1IHs4CRmdLl5k7ZBN58QC3jPhnEbZ1aD/ZmfSO ixMk/c3Tn8TlIPulRJnHO2hn/MQoC4TdeQSZiEze4gpQJq7TCmJccMcTB8uUw1P78Qeo 8B1DL+f+vuq9xlN+irg4JJ8O0K/zc8T2LZoHNxlAGmVEilxuflDEckVStcC39jgwR4q3 4gVKw3Ei6+FLZwWvXgvNqxRbYwv9L/Kxgas4MtBBWvnhljPztgP1AwIKHhuHfb3KNNI5 1tZ2DbS592pPtkYkyoh6Gw3LJtIXuNWGe6Nsn74xzKFo1mh2qfFAn1bK6bW8Pn+RbYng qo6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Se8a1uxL; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:13 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:15 +0000 Message-Id: <20180209143937.28866-28-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 27/49] ARM: new VGIC: Add MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add an MMIO handling framework to the VGIC emulation: Each register is described by its offset, size (or number of bits per IRQ, if applicable) and the read/write handler functions. We provide initialization macros to describe each GIC register later easily. Separate dispatch functions for read and write accesses are connected to Xen's MMIO handling framework and binary-search for the responsible register handler based on the offset address within the region. The register handler prototype are courtesy of Christoffer Dall. This is based on Linux commit 4493b1c4866a, written by Marc Zyngier. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio.c | 192 ++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 145 +++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 4 + 3 files changed, 341 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio.c create mode 100644 xen/arch/arm/vgic/vgic-mmio.h diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c new file mode 100644 index 0000000000..3c70945466 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -0,0 +1,192 @@ +/* + * VGIC MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return 0; +} + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return -1UL; +} + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val) +{ + /* Ignore */ +} + +static int match_region(const void *key, const void *elt) +{ + const unsigned int offset = (unsigned long)key; + const struct vgic_register_region *region = elt; + + if ( offset < region->reg_offset ) + return -1; + + if ( offset >= region->reg_offset + region->len ) + return 1; + + return 0; +} + +const struct vgic_register_region * +vgic_find_mmio_region(const struct vgic_register_region *regions, + int nr_regions, unsigned int offset) +{ + return bsearch((void *)(uintptr_t)offset, regions, nr_regions, + sizeof(regions[0]), match_region); +} + +static bool check_region(const struct domain *d, + const struct vgic_register_region *region, + paddr_t addr, int len) +{ + int flags, nr_irqs = d->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + + switch (len) + { + case sizeof(u8): + flags = VGIC_ACCESS_8bit; + break; + case sizeof(u32): + flags = VGIC_ACCESS_32bit; + break; + case sizeof(u64): + flags = VGIC_ACCESS_64bit; + break; + default: + return false; + } + + if ( (region->access_flags & flags) && IS_ALIGNED(addr, len) ) + { + if ( !region->bits_per_irq ) + return true; + + /* Do we access a non-allocated IRQ? */ + return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs; + } + + return false; +} + +const struct vgic_register_region * +vgic_get_mmio_region(struct vcpu *vcpu, struct vgic_io_device *iodev, + paddr_t addr, int len) +{ + const struct vgic_register_region *region; + + region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions, + addr - iodev->base_addr); + if ( !region || !check_region(vcpu->domain, region, addr, len) ) + return NULL; + + return region; +} + +static int dispatch_mmio_read(struct vcpu *vcpu, mmio_info_t *info, + register_t *r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = 0; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + { + memset(r, 0, len); + return 0; + } + + switch (iodev->iodev_type) + { + case IODEV_CPUIF: + data = region->read(vcpu, addr, len); + break; + case IODEV_DIST: + data = region->read(vcpu, addr, len); + break; + case IODEV_REDIST: + data = region->read(iodev->redist_vcpu, addr, len); + break; + case IODEV_ITS: + data = region->its_read(vcpu->domain, iodev->its, addr, len); + break; + } + + memcpy(r, &data, len); + + return 1; +} + +static int dispatch_mmio_write(struct vcpu *vcpu, mmio_info_t *info, + register_t r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = r; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + return 0; + + switch (iodev->iodev_type) + { + case IODEV_CPUIF: + region->write(vcpu, addr, len, data); + break; + case IODEV_DIST: + region->write(vcpu, addr, len, data); + break; + case IODEV_REDIST: + region->write(iodev->redist_vcpu, addr, len, data); + break; + case IODEV_ITS: + region->its_write(vcpu->domain, iodev->its, addr, len, data); + break; + } + + return 1; +} + +struct mmio_handler_ops xen_io_gic_ops = { + .read = dispatch_mmio_read, + .write = dispatch_mmio_write, +}; + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h new file mode 100644 index 0000000000..375b70561d --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __KVM_ARM_VGIC_MMIO_H__ +#define __KVM_ARM_VGIC_MMIO_H__ + +struct vgic_register_region { + unsigned int reg_offset; + unsigned int len; + unsigned int bits_per_irq; + unsigned int access_flags; + union + { + unsigned long (*read)(struct vcpu *vcpu, paddr_t addr, + unsigned int len); + unsigned long (*its_read)(struct domain *d, struct vgic_its *its, + paddr_t addr, unsigned int len); + }; + union + { + void (*write)(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); + void (*its_write)(struct domain *d, struct vgic_its *its, + paddr_t addr, unsigned int len, + unsigned long val); + }; + unsigned long (*uaccess_read)(struct vcpu *vcpu, paddr_t addr, + unsigned int len); + union + { + void (*uaccess_write)(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); + int (*uaccess_its_write)(struct domain *d, struct vgic_its *its, + paddr_t addr, unsigned int len, + unsigned long val); + }; +}; + +extern struct mmio_handler_ops xen_io_gic_ops; + +#define VGIC_ACCESS_8bit 1 +#define VGIC_ACCESS_32bit 2 +#define VGIC_ACCESS_64bit 4 + +/* + * Generate a mask that covers the number of bytes required to address + * up to 1024 interrupts, each represented by bits. This assumes + * that is a power of two. + */ +#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1) + +/* + * (addr & mask) gives us the _byte_ offset for the INT ID. + * We multiply this by 8 the get the _bit_ offset, then divide this by + * the number of bits to learn the actual INT ID. + * But instead of a division (which requires a "long long div" implementation), + * we shift by the binary logarithm of . + * This assumes that is a power of two. + */ +#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \ + 8 >> LOG_2(bits)) + +/* + * Some VGIC registers store per-IRQ information, with a different number + * of bits per IRQ. For those registers this macro is used. + * The _WITH_LENGTH version instantiates registers with a fixed length + * and is mutually exclusive with the _PER_IRQ version. + */ +#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, ur, uw, bpi, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = bpi, \ + .len = bpi * 1024 / 8, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + .uaccess_read = ur, \ + .uaccess_write = uw, \ + } + +#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = 0, \ + .len = length, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, urd, uwr, length, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = 0, \ + .len = length, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + .uaccess_read = urd, \ + .uaccess_write = uwr, \ + } + +int kvm_vgic_register_mmio_region(struct domain *d, struct vcpu *vcpu, + struct vgic_register_region *reg_desc, + struct vgic_io_device *region, + int nr_irqs, bool offset_private); + +unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len); + +void vgic_data_host_to_mmio_bus(void *buf, unsigned int len, + unsigned long data); + +unsigned long extract_bytes(u64 data, unsigned int offset, + unsigned int num); + +u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, + unsigned long val); + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); + +/* Find the proper register handler entry given a certain address offset */ +const struct vgic_register_region * +vgic_find_mmio_region(const struct vgic_register_region *regions, + int nr_regions, unsigned int offset); + +#endif diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 771ca6f046..426b34d0ce 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -27,6 +27,10 @@ static inline bool irq_is_pending(struct vgic_irq *irq) return irq->pending_latch || irq->line_level; } +const struct vgic_register_region * +vgic_get_mmio_region(struct vcpu *vcpu, struct vgic_io_device *iodev, + paddr_t addr, int len); + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); From patchwork Fri Feb 9 14:39:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127819 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679545ljc; Fri, 9 Feb 2018 06:41:55 -0800 (PST) X-Google-Smtp-Source: AH8x225ncLebIuUaal+x17yUrxwPLudMHFLUcBfULDxFRdiLfkaSdBA/Ta3HhjJqHzhsjfHGxd8W X-Received: by 10.36.61.142 with SMTP id n136mr3842387itn.6.1518187315627; Fri, 09 Feb 2018 06:41:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187315; cv=none; d=google.com; s=arc-20160816; b=rPSFN7A1i9ZFjTGV/fo+FHy03w4+MwZFMwpV2UfmGS7wNQW+mhe8WBkW+b4GTH+Ufr 2tX1PmvBDQ2rHX51SiAIfVJX5yD9ZKgEsXERywLscZiwf8R0IJjq/f6efOzs06VbTIpy IwO9GO3rJscd2ORb3/oiyv6NDujd/Nomd3QYvauodVcRWv+7wwpTbjBE2J4YZNhOKDMP GZNfzsAe7SVCj+fXaWlzeAC2dk/jHYiBvXlSR9RaBtx3MmPKQ7xt1oBhg3tsOZrTPlPx jEIYrjDhi+SdglR7f42NP6U7nBb9G/Eo0YWhMGrtinUw6dSQe/ozpmoQbtcktkc+MgAg RzBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=WOMD2u4ZHA6gmyfhppSCCC5YUb0qkYr1J23N+4K1wCg=; b=rG66W5l5GeDWmTuqfc5dtakAl8rhAjmvWrHphVkh/Q/6vrmK2k5wYr7iyEIBV/dQN8 w3Q1VgISjEWmka3TYlb6dZmvmDWWDOKuto0CzGNXEWebDmU20KTc0FWZcmXmlVFqySHE zSGh7z74vSLCIw40PVbKFCdJi9wBFDiDoy2iBkXDtTvIrSU+ycJp+G7bUCrOnu0ZdD8y euAcOLt4pS9xgfBSmHsjSwU6K4t/YrJ2zYAj6k8I6r7K536emp1j20SIABOUfoueWenP uIoW4hrkrSVrhWFlKSRjGUB2po8/2Hifr5qhZyLbNXlnrGh3JyoxmB+gfjUvKD6roUhp Od3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ROxxNXc9; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:14 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:16 +0000 Message-Id: <20180209143937.28866-29-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 28/49] ARM: new VGIC: Add GICv2 MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers using the initializer macros provided by the VGIC MMIO framework. Provide a function to register the GICv2 distributor registers to the Xen MMIO framework. The actual handler functions are still stubs in this patch. This is based on Linux commit fb848db39661, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 83 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.c | 26 +++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 2 + xen/arch/arm/vgic/vgic.h | 2 + 4 files changed, 113 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio-v2.c diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c new file mode 100644 index 0000000000..ee685a5a07 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -0,0 +1,83 @@ +/* + * VGICv2 MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +static const struct vgic_register_region vgic_v2_dist_registers[] = { + REGISTER_DESC_WITH_LENGTH(GICD_CTLR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, + vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, + vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 2, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_SGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), +}; + +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev) +{ + dev->regions = vgic_v2_dist_registers; + dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers); + + return SZ_4K; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 3c70945466..59703a6909 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -182,6 +182,32 @@ struct mmio_handler_ops xen_io_gic_ops = { .write = dispatch_mmio_write, }; +int vgic_register_dist_iodev(struct domain *d, paddr_t dist_base_address, + enum vgic_type type) +{ + struct vgic_io_device *io_device = &d->arch.vgic.dist_iodev; + int ret = 0; + unsigned int len; + + switch (type) + { + case VGIC_V2: + len = vgic_v2_init_dist_iodev(io_device); + break; + default: + BUG_ON(1); + } + + io_device->base_addr = dist_base_address; + io_device->iodev_type = IODEV_DIST; + io_device->redist_vcpu = NULL; + + register_mmio_handler(d, &xen_io_gic_ops, dist_base_address, len, + io_device); + + return ret; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 375b70561d..10ac682296 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -137,6 +137,8 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); + /* Find the proper register handler entry given a certain address offset */ const struct vgic_register_region * vgic_find_mmio_region(const struct vgic_register_region *regions, diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 426b34d0ce..7747d3f3e0 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -49,6 +49,8 @@ void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_clear_lr(struct vcpu *vcpu, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +int vgic_register_dist_iodev(struct domain *d, paddr_t dist_base_address, + enum vgic_type); void vgic_v2_save_state(struct vcpu *vcpu); void vgic_v2_restore_state(struct vcpu *vcpu); From patchwork Fri Feb 9 14:39:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127840 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679834ljc; Fri, 9 Feb 2018 06:42:12 -0800 (PST) X-Google-Smtp-Source: AH8x226nS0tz6/Av3yupzta/DdjBzg70jyscPsocohkM9cXVlOhpYEIgL4aNcVh3/GkoRMnlY95c X-Received: by 10.36.181.93 with SMTP id j29mr3587650iti.99.1518187332505; Fri, 09 Feb 2018 06:42:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187332; cv=none; d=google.com; s=arc-20160816; b=bxiQSPZRNih83CCkPhWkolYcWuVukNEon3THl019FxXql67zFmPP174R3q8RYP7ESk 4ym12r3LF2s7qpPWh/KuywvUpubssgc4Rrjd5rTBEBm4zTj4HEkSGT4OS9aDbulPfBqP 3UcsFLuiHirzaofdUnma3Vnej6Vstur3YhyiMIBd6mBL34iPlHLRZiyUZ65EWKsr4Ve1 ygsmypCcL45x4/Ee4BBLtVwcIbWYSXqJj3NMNJ3307ftoHq8NZDEvIILsOihdNPo47WW R5VeWl4Lpd8r7rF/wvEvw1WUBU16RKGl3XhbDacQJg9a9sK5NN100yoaJ+dhJjRbpqKX JBqg== ARC-Message-Signature: i=1; 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[192.237.175.120]) by mx.google.com with ESMTPS id r22si1623519iod.154.2018.02.09.06.42.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Nbv9Log0; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qc-00011F-Iz; Fri, 09 Feb 2018 14:40:18 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qb-0000yG-KS for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:17 +0000 X-Inumbo-ID: 13f46fb8-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 13f46fb8-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:48 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id v65so1678776wrc.11 for ; Fri, 09 Feb 2018 06:40:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=EaguL9bdyPHtckpUHr5KVKvWPfGvs7Xp78K73WQjarE=; b=Nbv9Log0ay4V0lb4tELJAc7LToQgfFS+FOoRIzGDwmpn6dMDg9VhKa1IcSS3qqtL0t rojd3zNnVblG9qAeUP3kXuLquB24WUZky6wCREuBXRd0RH6G7MpIV8jRYa65lThL8bQ3 QlmbUDoabcs1pAljHEvLowotImwqoVGsuycaw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=EaguL9bdyPHtckpUHr5KVKvWPfGvs7Xp78K73WQjarE=; b=rqspc4eDpkwNiBZcpg+njffWUYejb6jDeSOosiPR+0PCMnW90tgIl3V1AScrksyw04 nNKnAvcnKgL85PNxxInXwdkxtRuRVl3gDAn2RhkMCTnxCociRWu7U62UgGfwFuNj8xtc TeALDfMQtkSptuEVjaKKnymsUGm7+x9WW9zNvFdr0++QjOH2LwGQGWcgo/oHR/ou406z K3TKQNiIUiEYSdqnKiCsHeOYMzooAhzBpVWbSxkFmKG4O3fSmzqNvbJ/5dGeoYPyNH3c kuMqxsjilDymB7XI0+Qz/BI+vib0z41kPZ9ptaLd/R9KGvQ434KNotQ3/WtkSoxIMEtf xmYg== X-Gm-Message-State: APf1xPAMxySvIPvJ4CEn8iF/aKF2IwajtsHl1xQzCoLLcCBKIS1u/Rdc 4DoFNmw42qtolqK1rS8RCyNwFw== X-Received: by 10.223.163.6 with SMTP id c6mr2877822wrb.265.1518187215826; Fri, 09 Feb 2018 06:40:15 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:15 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:17 +0000 Message-Id: <20180209143937.28866-30-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 29/49] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Those three registers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. Also they are handled in one function, as their implementation is pretty simple. When the guest enables the distributor, we kick all VCPUs to get potentially pending interrupts serviced. This is based on Linux commit 2b0cda878965, written by Marc Zyngier. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 48 +++++++++++++++++++++++++++++++++++++++- xen/arch/arm/vgic/vgic.c | 15 +++++++++++++ xen/arch/arm/vgic/vgic.h | 4 ++++ 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index ee685a5a07..0926b3243e 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -20,9 +20,55 @@ #include "vgic.h" #include "vgic-mmio.h" +static unsigned long vgic_mmio_read_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 value; + + switch (addr & 0x0c) + { + case GICD_CTLR: + value = vcpu->domain->arch.vgic.enabled ? GICD_CTL_ENABLE : 0; + break; + case GICD_TYPER: + value = vcpu->domain->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + value = (value >> 5) - 1; + value |= (vcpu->domain->max_vcpus - 1) << 5; + break; + case GICD_IIDR: + value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); + break; + default: + return 0; + } + + return value; +} + +static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_dist *dist = &vcpu->domain->arch.vgic; + bool was_enabled = dist->enabled; + + switch (addr & 0x0c) + { + case GICD_CTLR: + dist->enabled = val & GICD_CTL_ENABLE; + if ( !was_enabled && dist->enabled ) + vgic_kick_vcpus(vcpu->domain); + break; + case GICD_TYPER: + case GICD_IIDR: + /* Nothing to do */ + return; + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1, diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 9e7fb1edcb..dc5e011fa3 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -678,6 +678,21 @@ int gic_events_need_delivery(void) return vgic_vcpu_pending_irq(current); } +void vgic_kick_vcpus(struct domain *d) +{ + struct vcpu *vcpu; + + /* + * We've injected an interrupt, time to find out who deserves + * a good kick... + */ + for_each_vcpu( d, vcpu ) + { + if ( vgic_vcpu_pending_irq(vcpu) ) + vcpu_unblock(vcpu); + } +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 7747d3f3e0..82fe902e26 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,9 @@ #ifndef __XEN_ARM_VGIC_NEW_H__ #define __XEN_ARM_VGIC_NEW_H__ +#define PRODUCT_ID_KVM 0x4b /* ASCII code K */ +#define IMPLEMENTER_ARM 0x43b + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) @@ -36,6 +39,7 @@ struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, void vgic_put_irq(struct domain *d, struct vgic_irq *irq); bool vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, unsigned long flags); +void vgic_kick_vcpus(struct domain *d); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Fri Feb 9 14:39:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127858 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679822ljc; Fri, 9 Feb 2018 06:42:10 -0800 (PST) X-Google-Smtp-Source: AH8x225x38MHRv1ljDkFUQnWZEOyYp3mjMHrZXuihUnx7VbvT2a1OFD0eZBPGg00dM8LU+clVH5t X-Received: by 10.36.242.3 with SMTP id j3mr3687273ith.49.1518187330866; Fri, 09 Feb 2018 06:42:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187330; cv=none; d=google.com; s=arc-20160816; b=RkYl96qqVHeJCVYof9uAm56/tSVlqyBbrkX0F0FIu7Uw4YwCWctLr9UUddxS77tjOE WS/aOKQq1qnr2ztXtKQN8KxoOrVO+F2ekGCAqaPUahIaYQLsGXCcsI9PQlpYj9HxtBdb VV9wLUdz0M7ITOpunMmYmRCGf7Tvrarsl3pZCha2C2tg4dqeEpLSvpr6q17nAGkSJm4j 5uboFsuwUFAa/u81/9IpxIzX6eMF4in1QztcR6T09lvVRSpO2xCB2/Hj4twkqM4m5bPQ 98n2I3uBL4Psi1NUit/mCPD1Q/QfOa+mg4nLwOWLdl5GYtVZYBs3UE24+zAlWMK+y7Ii rJ5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=fR6UUmffpO/cAz8SaLFlGeYhjU2rNSfR/3S+/ttgMBk=; b=lnCE2Kvie954HCmiord5YNftfhIa5BPfA9MI1iLWQ78EApC7tfFa0HKBgXgE0B1RdL 1TA+hjMPmfLjHqawrKw77cwNeJq+Q162UdnH3FAEtbiNgogCUCohYqNWZtstwWBulA+g 8crZDVee2RuVYdLVcy+zYfFq2HfGyQdMG8WnvL3ssdhxltzxXVl4ocD6ALMUoP4ioE3f zRzC8sE1A9Lcm735ZruC7BT++iXZwICp+x42VNNg5pxZxGazT50+TriuWYnFaRv9T2oe hhVNsbfM4gLcGuXFIM+x27meFRfuQxZCSo24KBUohGR4Wdn3jHg71x+r+5r5nErTDzw7 v6bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d+cZ6aW7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b75si1713448itd.60.2018.02.09.06.42.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d+cZ6aW7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qd-00015u-Uu; Fri, 09 Feb 2018 14:40:19 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qc-000121-RY for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:18 +0000 X-Inumbo-ID: 149b368b-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 149b368b-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:49 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id o76so5348792wrb.7 for ; Fri, 09 Feb 2018 06:40:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=g88UZvbqFYupt2NXHX1P9U5zn8R80FglujmVgERCgV4=; b=d+cZ6aW7Sl1JvEf2G3BIvB+9ykFyiplxEhSJI0KVM5bsLOYGWTT68S6zWb7HCBF5Lz y7D7Cy5nanuu7+jy/Yjl8c/+hxvEf5qrS2+ZCd96WJEOlA9Y2RlkkodIP+2vjiYf2SZr GZ57AxLRTGjE+gLsrsVSOgvxBO+d+Fg+90J48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=g88UZvbqFYupt2NXHX1P9U5zn8R80FglujmVgERCgV4=; b=pnc13io34PlKpYvSwqgjdCZ4J/GQWtGRMprUyLUhVLGZVpaF1QZkRm1eemxv2UIxVB SUw+sxJEjCqWOsFOnLhOeX9+Xn3aLFoTQ97qImWrCCH02FP9pqmFZjCoxmr5IIN50CDf eoMw82h1o6uxvqjvoHFXQZ1dZDBnxwTtAtw8I2X/Mh3GYwdiY8tbyAQTm3D91PCzDbWu jVXTb7OK6r+Chx41wXq3yZ2rF9IsXM8NpLPZnABzzANKvSNKysMeJOLhNqgFQj6BjtdY XeyTM+KSwM6rZFh9V96SPJs7uYERBF/mH7mROCxiwezSHEHifq+DRcioT5T/aLqLHPp9 FgPg== X-Gm-Message-State: APf1xPDyXd/YGP4Io5P7sshAZQweyGIHf8NWNwCP8zbWJxf4Ip+k8Db9 tY0PzisHFS/+emCFQ5qEQUECPw== X-Received: by 10.223.145.102 with SMTP id j93mr840574wrj.254.1518187216865; Fri, 09 Feb 2018 06:40:16 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:16 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:18 +0000 Message-Id: <20180209143937.28866-31-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 30/49] ARM: new VGIC: Add ENABLE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As the enable register handlers are shared between the v2 and v3 emulation, their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 114 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ 3 files changed, 127 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 0926b3243e..eca6840ff9 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -74,10 +74,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 59703a6909..3d9fa02a10 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -39,6 +39,120 @@ void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, /* Ignore */ } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + u32 value = 0; + int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->enabled ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +static void vgic_handle_hardware_irq(irq_desc_t *desc, int irq_type, + bool enable) +{ + unsigned long flags; + +// irq_set_affinity(desc, cpumask_of(v_target->processor)); + spin_lock_irqsave(&desc->lock, flags); + if ( enable ) + { + gic_set_irq_type(desc, irq_type == VGIC_CONFIG_LEVEL ? + IRQ_TYPE_LEVEL_HIGH : IRQ_TYPE_EDGE_RISING); + desc->handler->enable(desc); + } + else + desc->handler->disable(desc); + spin_unlock_irqrestore(&desc->lock, flags); +} + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + irq_desc_t *desc; + int i; + unsigned long flags; + enum vgic_irq_config config; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->enabled = true; + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= 32); + + desc = irq_to_desc(irq->hwintid); + config = irq->config; + } + else + desc = NULL; + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + vgic_put_irq(vcpu->domain, irq); + + if ( desc ) + vgic_handle_hardware_irq(desc, config, true); + } +} + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + unsigned long flags; + irq_desc_t *desc; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->enabled = false; + + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + + if ( desc ) + vgic_handle_hardware_irq(desc, 0, false); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 10ac682296..9f34bd1aec 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -137,6 +137,17 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */ From patchwork Fri Feb 9 14:39:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127857 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679766ljc; Fri, 9 Feb 2018 06:42:08 -0800 (PST) X-Google-Smtp-Source: AH8x225TAd+4ZbCkZt8EOcg1KS5rW7co6SXrGMaG1vGIdQvuYtK3bN4vNgFR5ax8UzbEuAxuQxeD X-Received: by 10.36.146.196 with SMTP id l187mr3835194itd.115.1518187328076; Fri, 09 Feb 2018 06:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187328; cv=none; d=google.com; s=arc-20160816; b=HiL0/Hr6GU8ovbKF1174DcGSJ1tIpQDbaRuoazmFD9lutUIohMzhwTMb3UNRe073gp sDoB//XZLpTMsvmmoxIkaOTDdKYQ6A7aI1YvWal7llFJHP2OwxymFMwak0YMvLNmD1Ek Rkd+OAwq7BoR86jyADqLxDUteOaWlgAk2vl9yvhqthOvoywcztHnb17d4J1xFQWjmWw1 oiJrrsjBKoYj8y3Ul6ZghOkcR/rq9TlhY8e8RisBZKg/V8ELb/RouNjEumE6JCir1Lbj DhgF6pxTVoT7H2uihCR2jVdBvsAeDiQBxR3nS5h2yT6O8SU3tnLeYd2Qvh3XiLAN5HBh 4zwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=RMWImH2/Jkjoe90e2eUhSGmdkpvgy5AdXDt7HfE0PzM=; b=s4CHuHikNA46iNlK9T/iVVNdgW4L4Jhey5dJfL4PXdNhuYJ2MwAZ9fUlzA4Pf+rD0E MByTX712NiclDCQYeeZDiFSG4Sd10X/z1T/iffLzuM/LNUPvcfRZdIYh7rgAvxnpp1Zu nWpt2ITU5O1zMOD7S4mJo306fLR0U3Qa93i4YggWSsLSJEvJlmtiaRJjmQQ2NwnX5VnS zxN9q69QYxwkA0Nob/T4xbJ3rtDyRBWRHkZ2LLbOo0rKUo03w5Be5b9HtmbyFR+ndaEB tW1dNtCYDKjMmn4+MSwZPniavUs6rzNqg43eQpQ0MvWYvYf/9hnnj9XnoWqivXJOFs9O 5YTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=TZlGogoS; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:17 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:19 +0000 Message-Id: <20180209143937.28866-32-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 31/49] ARM: new VGIC: Add PENDING registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The pending register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. For level triggered interrupts the real line level is unaffected by this write, so we keep this state separate and combine it with the device's level to get the actual pending state. This is based on Linux commit 96b298000db4, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +-- xen/arch/arm/vgic/vgic-mmio.c | 62 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 +++++++ 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index eca6840ff9..ceb86900a0 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -80,10 +80,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_pending, vgic_mmio_write_spending, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 3d9fa02a10..9a65e39d78 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -153,6 +153,68 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + u32 value = 0; + int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq_is_pending(irq) ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + unsigned long flags; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = true; + + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + unsigned long flags; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->pending_latch = false; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 9f34bd1aec..209afbbb9a 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -148,6 +148,17 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */ From patchwork Fri Feb 9 14:39:20 2018 Content-Type: text/plain; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:18 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:20 +0000 Message-Id: <20180209143937.28866-33-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 32/49] ARM: new VGIC: Add ACTIVE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The active register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. Since activation/deactivation of an interrupt may happen entirely in the guest without it ever exiting, we need some extra logic to properly track the active state. For clearing the active state, we would basically have to halt the guest to make sure this is properly propagated into the respective VCPUs. This is not yet implemented in Xen. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 94 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 +++++ 3 files changed, 107 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index ceb86900a0..eba24d9866 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -86,10 +86,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_pending, vgic_mmio_write_cpending, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_active, vgic_mmio_write_sactive, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 9a65e39d78..ac3aa03fbc 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -215,6 +215,100 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + u32 value = 0; + int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->active ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +static void vgic_mmio_change_active(struct vcpu *vcpu, struct vgic_irq *irq, + bool new_active_state) +{ +} + +static void vgic_change_active_prepare(struct vcpu *vcpu, u32 intid) +{ +} + +static void vgic_change_active_finish(struct vcpu *vcpu, u32 intid) +{ +} + +static void __vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + vgic_mmio_change_active(vcpu, irq, false); + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + + spin_lock(&vcpu->domain->domain_lock); + vgic_change_active_prepare(vcpu, intid); + + __vgic_mmio_write_cactive(vcpu, addr, len, val); + + vgic_change_active_finish(vcpu, intid); + spin_unlock(&vcpu->domain->domain_lock); +} + +static void __vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + vgic_mmio_change_active(vcpu, irq, true); + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + + spin_lock(&vcpu->domain->domain_lock); + vgic_change_active_prepare(vcpu, intid); + + __vgic_mmio_write_sactive(vcpu, addr, len, val); + + vgic_change_active_finish(vcpu, intid); + spin_unlock(&vcpu->domain->domain_lock); +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 209afbbb9a..39e854232e 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -159,6 +159,17 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */ From patchwork Fri Feb 9 14:39:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127822 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679583ljc; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:19 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:21 +0000 Message-Id: <20180209143937.28866-34-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 33/49] ARM: new VGIC: Add PRIORITY registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The priority register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. There is a corner case when we change the priority of a pending interrupt which we don't handle at the moment. This is based on Linux commit dd238ec2b87b, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 ++-- xen/arch/arm/vgic/vgic-mmio.c | 47 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ xen/arch/arm/vgic/vgic.h | 2 ++ 4 files changed, 58 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index eba24d9866..0574ff9b16 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -92,8 +92,8 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_active, vgic_mmio_write_cactive, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, - VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, + 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index ac3aa03fbc..14570d9d8e 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -309,6 +309,53 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, spin_unlock(&vcpu->domain->domain_lock); } +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 8); + int i; + u64 val = 0; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (u64)irq->priority << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +/* + * We currently don't handle changing the priority of an interrupt that + * is already pending on a VCPU. If there is a need for this, we would + * need to make this VCPU exit and re-evaluate the priorities, potentially + * leading to this interrupt getting presented now to the guest (if it has + * been masked by the priority mask before). + */ +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 8); + int i; + unsigned long flags; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + /* Narrow the priority range to what we actually support */ + irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS); + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 39e854232e..30221096b9 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -170,6 +170,13 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */ diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 82fe902e26..b104f8e964 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -20,6 +20,8 @@ #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ #define IMPLEMENTER_ARM 0x43b +#define VGIC_PRI_BITS 5 + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) From patchwork Fri Feb 9 14:39:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127862 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp681266ljc; Fri, 9 Feb 2018 06:43:57 -0800 (PST) X-Google-Smtp-Source: AH8x227taP7WrsX20L9ZWT2Efo58bR9VCxnA5liUAJNXI1zudztllT1JtqFjv403SWCdaTvVWtbJ X-Received: by 10.36.104.149 with SMTP id v143mr3675772itb.2.1518187339170; Fri, 09 Feb 2018 06:42:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187339; cv=none; d=google.com; s=arc-20160816; b=NWu50JV+78lUz4Hj/kKi4hdtw9j38m5+dmrBtKTTM13NeinNnOs8IFAzmNFMVjRvgQ 5ZdmaJwffdIoLj6AlOVeA4lzHcFDECuJDv57r3FDbBhk5JDG9nEFHqWPxIXz3dQWlQrq rsTX4HQht+va+9JrTAp10V076gAyZgWIcnGInfCM+VtfXYpuXn9+2ta5SMxUneGsQgwP pcighfvk2WYU015eqepoCu4k7xUYLY1hGjMyeM+OIOqGQkIq4kMQc3P8a/CSGjJHkVSu g+Uz2QLnXGXOFwPcibLOey9p/RT3dPnHf5KsQirMMsF6U1CqJGAVfVado5oQNgzAed9f CC/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=C8ge/xmkNvDwi64/E/cuiCl2mUltz+pM4Bp5lnNPDmg=; b=kyMi9LzuG+IKkyXFPPmhuoEv4HwO/uNfK4Sk0HYYJG9mOoM2upNzodpvEGJunjqo8u aYYL8TEve9ZynMylGHmLd1fPF97z8K3C6KzBTITRrNV+JzMXrAmrO1sJB4/qkhMttBJZ nVte760S6Wj3R3CFsIEVvOk7ZIWAb9I/RZvbHGO6m+K2Bwn9aVDacZQow9JDuuPIypse fo7RUX1wGCroqzqAPDecL0TUPpsvU1Ly08nhlJbxTlY3EDNRgaEXw01mXr+gVJWOMDde IVZmBqgkG2BArVN3/EkMM2nW9ZyN3WmWet6PfjgA4qEx0AqLE8HmdJ+TO2FRdUj/vJ10 xiGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aJ5aOkc7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a129si1684224itd.14.2018.02.09.06.42.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aJ5aOkc7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qj-0001MM-3q; Fri, 09 Feb 2018 14:40:25 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qh-0001HQ-N4 for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:23 +0000 X-Inumbo-ID: 17145112-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 17145112-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:54 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id 41so8461480wrc.9 for ; Fri, 09 Feb 2018 06:40:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=yr3Zs5OL4GyhM2lueLOeEkZ6oBI8E+JFAq53kZ5YuAE=; b=aJ5aOkc7rdKWjEhJBlzZpjwkt8xlXJeIzPMVJOCHkmp2aKAlR4Mrg/dp/Q+gpqRlxx 1ChJrjjKwV67QUTzcRGAC7WoXzfzTL0GXwXL1olO2KdR5FkLTbSz9B9jBdGl3SjwHJSO Rjry/DYHvpCiXrDjqSX6l5gF9268MSutOnA5Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=yr3Zs5OL4GyhM2lueLOeEkZ6oBI8E+JFAq53kZ5YuAE=; b=rgpSz3qUg7wlyt9LK5Aq7oNKj75XpWMogPhRsa2rG+a5kSMuyvkSptyNBkjIJTkIdo 2OJF8iIW6D1cjfMZQ+aobHYXK68EdrJUCLMk0hxFrSL3Awjeu5JCKQzzzUwce6tK8fVe /kpK4oTyaH/KwvLJ8NmKj9pPAtJgSJju6Kn+AGwPMCrGRgUnGAvpN+h/vMalnS0vaLN1 tqvCfTAtVwYxWf27w0h3wKPKqs3iNJnbxNP/Pc5nQolSFAFnw8b9+0JBxdwjcYMrveQD NksaDQ1la/YA3sl5H10HF1DyI053XAnZNw0xi/8xZZJOcDImdMMyPEyC3fcUUUdFSSfe JJGw== X-Gm-Message-State: APf1xPAYRrg2jSaNX4NKJjhQOuIjpTdIyQsR40pX1Pwf74BWKzfHrdQZ YCmTUV2bQYpO3fgXIVRjtyF+fw== X-Received: by 10.223.171.24 with SMTP id q24mr2734015wrc.206.1518187221057; Fri, 09 Feb 2018 06:40:21 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:20 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:22 +0000 Message-Id: <20180209143937.28866-35-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 34/49] ARM: new VGIC: Add CONFIG registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The config register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This is based on Linux commit 79717e4ac09c, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 0574ff9b16..c0b88b347e 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -98,7 +98,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 2, + vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 4, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 14570d9d8e..626ce06986 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -356,6 +356,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 2); + u32 value = 0; + int i; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->config == VGIC_CONFIG_EDGE ) + value |= (2U << (i * 2)); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 2); + int i; + unsigned long flags; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq; + + /* + * The configuration cannot be changed for SGIs in general, + * for PPIs this is IMPLEMENTATION DEFINED. The arch timer + * code relies on PPIs being level triggered, so we also + * make them read-only here. + */ + if ( intid + i < VGIC_NR_PRIVATE_IRQS ) + continue; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( test_bit(i * 2 + 1, &val) ) + irq->config = VGIC_CONFIG_EDGE; + else + irq->config = VGIC_CONFIG_LEVEL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 30221096b9..b42ea1bd8a 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -177,6 +177,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */ From patchwork Fri Feb 9 14:39:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127843 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679872ljc; Fri, 9 Feb 2018 06:42:15 -0800 (PST) X-Google-Smtp-Source: AH8x225TW+Va1SIte/ypAiE/MfY5fyQU+N013Gd5RYh6sAIzru6DO2GK2ndXjCbEHlBOeBKtAXFW X-Received: by 10.107.168.217 with SMTP id e86mr3468126ioj.14.1518187334927; Fri, 09 Feb 2018 06:42:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187334; cv=none; d=google.com; s=arc-20160816; b=z7ac9FJbQZ3IdrrUnUxG3hzJZRky6DLWIbNIQMfULt1s4t88NEVyKXGZ5FHYVyzmYZ NWvQxQhIvStpuFUY2vMbJMpKD5PPybF52TYFS7MuwQA6M7Oj1xwvKnaXR9VwKzTjK5BN xLefhE6DMSoW+MqLyNtNRcD6QQy7Q4YKrWTo3xZwEv1SVl2b0Qq+grAzVIOTvyjOrU59 fwnbe8yidjhVx8RrZL3anhmsCTgVYIH28F8kseSpMknWm7yFFqzbPpvY62CFqXIkN6fF lAeTe1FKV1GbpR3lVnxxKiiwSZ7kWM0Zi+8Cp5elCqLhopHqk0d0rKaMJnQI1K305Pq7 orEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=8SS+br5lru+JEC4ZuQJ7ROjV/RFgDfNlYa6vrJTvejc=; b=FvUZITc0OXKOiFwWfOOZIWHwcDHWoPaa7pluRO0wdszu/Ld01oJqdcOsK3mfD3MU/O 9kZ5cxzlmc/z+H9+6mOyRyMiFbRl2gogLruU2dnZzW2be35UAImh0MTQ+qopgBE6bhvZ VnFW0Bt2UDOo/eVmWnMza9oTH4niuZJQKqTgiZD8XGbtvAYl3FopM9TxlTr7+u5AU4M9 9iAiDnNmT+KZf8PxBUCzFwxTJDLCI9AJKT9vf7V6bKfKmZ4RXuQw7nhcWpz9ESXXSRN6 GaBGCbIfHoxz8tbPo1Y4nS+fUgwP5Bz7zZVqiQOKzW/lgskm1byVcEUpAcDktBWIqGvm Dmrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KZ+PwiIX; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:21 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:23 +0000 Message-Id: <20180209143937.28866-36-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 35/49] ARM: new VGIC: Add TARGET registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The target register handlers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. We copy the old VGIC behaviour of assigning an IRQ to the first VCPU set in the target mask instead of making it possibly pending on multiple VCPUs. This is based on Linux commit 2c234d6f1826, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 52 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index c0b88b347e..c59f2c1ba7 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -66,6 +66,56 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 8); + int i; + u64 val = 0; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, + vcpu, intid + i); + + val |= (u64)irq->targets << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +static void vgic_mmio_write_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 8); + u8 cpu_mask = GENMASK(vcpu->domain->max_vcpus - 1, 0); + int i; + unsigned long flags; + + /* GICD_ITARGETSR[0-7] are read-only */ + if ( intid < VGIC_NR_PRIVATE_IRQS ) + return; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, + NULL, intid + i); + int target; + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->targets = (val >> (i * 8)) & cpu_mask; + target = irq->targets ? (ffs(irq->targets) - 1) : 0; + irq->target_vcpu = vcpu->domain->vcpu[target]; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -95,7 +145,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_priority, vgic_mmio_write_priority, NULL, NULL, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 8, + vgic_mmio_read_target, vgic_mmio_write_target, NULL, NULL, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, From patchwork Fri Feb 9 14:39:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127836 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679768ljc; Fri, 9 Feb 2018 06:42:08 -0800 (PST) X-Google-Smtp-Source: AH8x22556FDHCEJLP9xNT1fkXbejnCMG/oEGJkFjLhJWs1ZHph4eHPeVw4QK+reDipD+292/p6DE X-Received: by 10.107.13.143 with SMTP id 137mr3397028ion.265.1518187328077; Fri, 09 Feb 2018 06:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187328; cv=none; d=google.com; s=arc-20160816; b=NIx4hfyoBviIl6qJhznF+USasHdwx0SK+NgzuIU6wCPBR5oWH6HS/AUeZdUG+YsMVY i9Ejh7lF7flu8I9z07GOnDyxiAMfl9E0cGWHDX1AxvU5uAmTFVi/HUmjkQhKCYYRpigD UoSIS1NeJRE9b1ptZS99DIPSskG/mgufIhaIELQoZmQ8DPKXutoWpoT5jmcVa9s99s0g yOovLz/WRmxHcPYYAj3jlyFVJjRkjJ2LYP8/fRKA70gAoO+My3xSClTN/9I9kisPAtET 0Hodrdpoqtn9x7ymfUVYgBG1Zn1x8juhRTerFpddvjR4n4osl/Jg1mO2N0OK95ym9HG0 ukhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=slpj8S5EyctlQVHonH7ZNFwdp6+avaMU/Rqk1IMHfaw=; b=HR1cwXTKCMTCgDeNfjNgd2QaI8H4ZUr4JWsojgjzT9aoNX+DKx3zHizWgAa7OVp4Jp ywNiN8dOada04ZF9Ampf/iST+LJqDsKSIirNNPunj6vVy/HNJs3Syd+F0GrYG/6Ee/PX LpMbUueaEv55hrJczKbONGyEkxMMvhGVDICEdGGM8ENKdir/5VCJ7EL851GWcg/NBxN6 Eix46jsCzfStdrwhEIN77Xd1NPUjgR7P7QHg6oYOgh74/GIXWlwi6ZBaivHA9DmQM2yf OBwCTGjvIDN3NuAHkYAYxs9WXPcU4YFPAOOynC8CNJsoqqsSJDHM2nsiGIN9c7ayZgT2 vmRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IXrvk9uH; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:22 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:24 +0000 Message-Id: <20180209143937.28866-37-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 36/49] ARM: new VGIC: Add SGIR register handler X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Triggering an IPI via this register is v2 specific, so the implementation lives entirely in vgic-mmio-v2.c. This is based on Linux commit 55cc01fb9004, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 47 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index c59f2c1ba7..3f67b4659a 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -66,6 +66,51 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static void vgic_mmio_write_sgir(struct vcpu *source_vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct domain *d = source_vcpu->domain; + int nr_vcpus = d->max_vcpus; + int intid = val & 0xf; + int targets = (val >> 16) & 0xff; + int mode = (val >> 24) & 0x03; + struct vcpu *vcpu; + unsigned long flags; + + switch (mode) + { + case 0x0: /* as specified by targets */ + break; + case 0x1: + targets = (1U << nr_vcpus) - 1; /* all, ... */ + targets &= ~(1U << source_vcpu->vcpu_id); /* but self */ + break; + case 0x2: /* this very vCPU only */ + targets = (1U << source_vcpu->vcpu_id); + break; + case 0x3: /* reserved */ + return; + } + + for_each_vcpu(d, vcpu) + { + struct vgic_irq *irq; + + if ( !(targets & (1U << vcpu->vcpu_id)) ) + continue; + + irq = vgic_get_irq(d, vcpu, intid); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = true; + irq->source |= 1U << source_vcpu->vcpu_id; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + } +} + static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, paddr_t addr, unsigned int len) { @@ -151,7 +196,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_config, vgic_mmio_write_config, NULL, NULL, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 16, From patchwork Fri Feb 9 14:39:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127835 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679780ljc; Fri, 9 Feb 2018 06:42:08 -0800 (PST) X-Google-Smtp-Source: AH8x226z4C3s1Auo4xGXNLLmuT22WevCiaEDDSIAvgk9WeLcSO3EuObUQzP/3W4Sx3s+9qVHp6Og X-Received: by 10.36.4.82 with SMTP id 79mr3667974itb.89.1518187328379; Fri, 09 Feb 2018 06:42:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187328; cv=none; d=google.com; s=arc-20160816; b=B/93SI3+6rq4QIFJ1QV3cqLFcOoBx+wK09j1fZYacxrYG4hcMy3sIO/Z1TIjF38ROe ZZb1fM42FDWLxEOMIMnp28YSGrlMmRqpALaJcZSooOeEAJpboCz2O/2HMEG1bNzOEd1J Ny4ER6aCvPaOGDD79V6aCiwLSbNqiTlOewaKU6WvkIupW0g733VQMRdqHzWCyNceXxDo Swr7B/gSWEF4ukkVYGx5itkbQOSAczUiR0k6W2v/QnxOr4QuUr/zSvvXJII3MfEgrRss 2BR67fVfuQCxwpYKWZcfliM3Dh51JOCh71NNqrF0clheM4Qb+ZW902GeJOJoQHzJVBF7 XjqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=pgg8egc6r6/TSdXHYLZX/MaCVrvsespoA0c7b9A51d8=; b=xrsFq7FItoZEPwoLsYy6sVgFCPWQwbXC79OFPFIYE9JX6eWqRRub1Slepbo+IY/OXz SMUlTPFQ59bhp7A0gWyHD2dPu2hp86JjjevDmkk0fmflSr6LbMjBToL7O/92u1LZPCUz ROalHvjjxAIujAO8+yBrM8GlKpbM/Xjc7E3JnYxziZnrrufwQbafohT5SCtGujYeLXdj 0NaeU8ARBYdVHhHPArSedTn+zreK9kVZ4s2zzSAmicZXXyA2ojOPruYxOlaPBs5jWiYG wApS3xDq+7up/+EMqSNx2X0xWluVw9lbD0ubrD035Kdl6KTOi7stEY2JLVfkZ6Rr4F+/ klWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hmo0hL/M; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id t124si1666387itf.146.2018.02.09.06.42.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hmo0hL/M; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9ql-0001WP-Rd; Fri, 09 Feb 2018 14:40:27 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qk-0001Rd-KL for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:26 +0000 X-Inumbo-ID: 18eaef88-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 18eaef88-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:57 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id 111so5588577wrb.13 for ; Fri, 09 Feb 2018 06:40:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=2TDgL9PpUhytNU8lRsiKekfeJAkzR3w28LinIsqKmqc=; b=Hmo0hL/MPXR4yrTRyGYLmfKv6WKAmwSx70nQHIjFzxr/k2hTBhjBfh3Rh2EO3tdAoy 8quOX8E462NXCzTmQI98FZcwD34XOVpydm6CgLyhB3CLUbGbY5TgyyyEtW2UwO5FKSNq TD8Hw9PkhDtTqDnJLSSjnU26u+D18N1QHfpqY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=2TDgL9PpUhytNU8lRsiKekfeJAkzR3w28LinIsqKmqc=; b=LSTTr5x07DVMxJ1wisJcWgAkHRe7csDZdjvDSLDXdOG7xWoVjMVSPR2a4xzb97FUe9 PDcZ5r4Ae6r4y4D7cSLTPP5nj25+vPY9/gsW3VMjyEECq/9WMrX7KonijQn5ZFXSelZd RhGxTGjT98asZyLPk9vDuc5RkfrlDuJBem3qUMyToxSHf0Dq/YjRQtDxu2M4Y3Tccf0Y dshNi4lDMzWzCs5cf+vWYNrYhCdb9DuAbZcEd2gRoQjqqW5CBkZObEVRnmBFBv74qZeG Owl941G3w7hZrYp5cYOVSCimYkRLyTPL0jWw2I/gg4FAsJqrhbk7HgszXwe3RcY6fKpS ApKw== X-Gm-Message-State: APf1xPAPEXtxkQWjM/yFUoztjfwrSXabvwvWvV1WqvSEqsyEwdotiUGj 6Wyfv7k8KkqqZaTpVCNEemJEYA== X-Received: by 10.223.209.80 with SMTP id b16mr2758136wri.86.1518187224129; Fri, 09 Feb 2018 06:40:24 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:23 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:25 +0000 Message-Id: <20180209143937.28866-38-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 37/49] ARM: new VGIC: Add SGIPENDR register handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As this register is v2 specific, its implementation lives entirely in vgic-mmio-v2.c. This register allows setting the source mask of an IPI. This is based on Linux commit ed40213ef9b0, written by Andre Przywara. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 77 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 3f67b4659a..c62307c3aa 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -161,6 +161,79 @@ static void vgic_mmio_write_target(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_sgipend(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = addr & 0x0f; + int i; + u64 val = 0; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, + vcpu, intid + i); + + val |= (u64)irq->source << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + return val; +} + +static void vgic_mmio_write_sgipendc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = addr & 0x0f; + int i; + unsigned long flags; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, + vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source &= ~((val >> (i * 8)) & 0xff); + if ( !irq->source ) + irq->pending_latch = false; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + +static void vgic_mmio_write_sgipends(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = addr & 0x0f; + int i; + unsigned long flags; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, + vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source |= (val >> (i * 8)) & 0xff; + + if ( irq->source ) + { + irq->pending_latch = true; + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + } + else + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + } + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -199,10 +272,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), }; From patchwork Fri Feb 9 14:39:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127845 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679905ljc; Fri, 9 Feb 2018 06:42:16 -0800 (PST) X-Google-Smtp-Source: AH8x225+XbEmlo7v1BcOzo9fD2Hgq8E/ZzXKfdUzyGRXsFlmcgLNlBS3iPvuylduemDysElorXjV X-Received: by 10.107.180.70 with SMTP id d67mr3468115iof.73.1518187336680; Fri, 09 Feb 2018 06:42:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187336; cv=none; d=google.com; s=arc-20160816; b=XG+HfA8H58iU6Ix3Yj1I3hDJdr8B8P5iue7cF75LUdD8pswQKw0IIswHZs2d4dp9rA riCrAZZQrnwKN3s4iW6NlHgERmJz4pZC9xrxpmFG0VRqmKMve9UtcR5XlMtUH90mE5cB 0C2VN4Ig1XmjbBtmv5nG0iO0NFWsY1snzsWavdHCQkL04XOwwcrPkSJxe/Gk6rk2P0pk /VSLOcP2HfDB5wF2t8F5V5pJFXzi1/KI0xxrxLQySGLIBGPllgNzZ3l9n5v9XZ6fmiew BVy2+XpZQDzFKXdDmWeIJ/jDWoKRmkxSXi1iBMxg4lk/uOgpbrFvBaLHaswUJNCNrGYb ZkJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=K826P+ibaYSPT9xiH18JQxLGU+c/1G7+d0BHQ8kRCWc=; b=J5qD6Ee9Y6+B0PwR1PeSBZQNkCqWE8fN6+7GkyRjmyZNKMY7o+fO3o9Rj1mNZz0+y6 KgMnj+worG0pq7Et16f1rbVato/LhljyWLZz+PwcpmJ0zjUWS3DZ/M6Kdm9yzc+EcGVm h5cuJCaH9V+tRKnuF7nLvXhS7H8O40HODiA4GAqj+M/dRFYBwYKBFQ/74A63DCYuMy9/ 22TqVdhH9PIJKRLtxKYj/lLFMslQrM9m+CBYfPEW0ugIXZOa1z03lRtTVWKkRGvR0V5E R31TYlDJeCC7Ri+y30F3QZqs5Pf29cZU0hrLH2SwP+qimtHQCbyYOnkIkn8Zgg1mbfic 0tSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QxILZv6K; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:24 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:26 +0000 Message-Id: <20180209143937.28866-39-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 38/49] ARM: new VGIC: handle hardware mapped IRQs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The VGIC supports virtual IRQs to be connected to a hardware IRQ, so when a guest EOIs the virtual interrupt, it affects the state of that corresponding interrupt on the hardware side at the same time. Implement the interface that the Xen arch/core code expects to connect the virtual and the physical world. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index dc5e011fa3..8d5260a7db 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -693,6 +693,69 @@ void vgic_kick_vcpus(struct domain *d) } } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct irq_desc *desc = NULL; + struct vgic_irq *irq = vgic_get_irq(d, v, virq); + unsigned long flags; + + if ( !irq ) + return NULL; + + spin_lock_irqsave(&irq->irq_lock, flags); + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(d, irq); + + return desc; +} + +/* + * was: + * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) + * int kvm_vgic_unmap_phys_irq(struct vcpu *vcpu, unsigned int virt_irq) + */ +int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, + unsigned int virt_irq, struct irq_desc *desc, + bool connect) +{ + struct vgic_irq *irq = vgic_get_irq(d, vcpu, virt_irq); + unsigned long flags; + int ret = 0; + + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( connect ) /* assign a mapped IRQ */ + { + /* The VIRQ should not be already enabled by the guest */ + if ( !irq->hw && !irq->enabled ) + { + irq->hw = true; + irq->hwintid = desc->irq; + } + else + { + ret = -EBUSY; + } + } + else /* remove a mapped IRQ */ + { + irq->hw = false; + irq->hwintid = 0; + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + + return ret; +} + /* * Local variables: * mode: C From patchwork Fri Feb 9 14:39:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127844 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679894ljc; Fri, 9 Feb 2018 06:42:16 -0800 (PST) X-Google-Smtp-Source: AH8x2246cpOibzmC9VwBd7zRgNntT6qy/PZSQ4u2RYL5HQwtHUZaQ5qT1N2TloD4qgxIWk931PQT X-Received: by 10.36.225.9 with SMTP id n9mr3709414ith.87.1518187335938; Fri, 09 Feb 2018 06:42:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187335; cv=none; d=google.com; s=arc-20160816; b=HMFdpW9K13fet1wj5QlsJGBTgAbNaJhAs94+LEhIL19s/O13Az6NUBdIhBWhqDBTqR 1qnfkxoE1yvG2zm/oeBTPC/7Q5gH+w0n+aKO36Q6BKkcAktm1CBOsEBs8+7pkfTOsGk3 B2kF1VkGukO52mFDjH1lOcdlwlOXUq8oFumjnhkG5qsk8M58wB+vH9l6n+zUKR9xnh1T 7BY6W5bHRGtMuQrLG3f+fYE+erZ1tzaAM0i0mjGrxr5hlF2c6P3ZvblXRNynaBmaPP25 x+2NReoKv+EjAIbxHGTAZOnmyGII92UPzKzif+KOkNtifNE23an9S9lv2Wg5G+1fU73k 14dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=M4dfhSahno+TDmfqLAXdNgf28m0BfrusA1gGHn285+0=; b=BkAdPTW19FEXBz9UjBt1f74aCGNbCr4fSFJfmtEeGTl9rlhw5b1RvHieNiTZ7xZW8r HIAR35tG0WmkrnezGLmTRWHo85fYXn98WUENQFZEgUHR/wcTNirqp0SOdHBDSSJ5lJAh rDaOa8cUiibRH7oKbkdgB1hllyUo9QZ9lm4dEZRZjVBeOwwqAcbnnW+zywGuYciFhdQQ nbdoVdtD7DbihPhv3FrCmkrS/hlBiXCt8JBup+jiJLaa60/0fHwWgCSP9y1fLjpTjR02 iSsks4dPfXujkjETJhr/OJr+2YWS7WsMfxE97WRmA3uJagDmU5q6lDZlMzAw8IE2aXfU KuQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=JBJXBLxS; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:25 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:27 +0000 Message-Id: <20180209143937.28866-40-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 39/49] ARM: new VGIC: Add event channel IRQ handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen core/arch code relies on two abstracted functions to inject an event channel IRQ and to query its pending state. Implement those to query the state of the new VGIC implementation. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 8d5260a7db..b62cda7d2f 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -693,6 +693,26 @@ void vgic_kick_vcpus(struct domain *d) } } +void arch_evtchn_inject(struct vcpu *v) +{ + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); +} + +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct vgic_irq *irq; + bool pending; + + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + irq = vgic_get_irq(v->domain, v, v->domain->arch.evtchn_irq); + pending = irq_is_pending(irq); + vgic_put_irq(v->domain, irq); + + return pending; +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Fri Feb 9 14:39:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127830 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679711ljc; Fri, 9 Feb 2018 06:42:05 -0800 (PST) X-Google-Smtp-Source: AH8x224QognvLzOaY2Lfpffu3YqByOVHgJYtpOQt8VJ65Xf1/g7i8IounzlpCGBgYF6guYOOw3Il X-Received: by 10.107.17.27 with SMTP id z27mr3464800ioi.254.1518187325528; Fri, 09 Feb 2018 06:42:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187325; cv=none; d=google.com; s=arc-20160816; b=N40sGrexscYNZviWeKSCUhbIGg/ixAv3rKhChQYc6OJdgPKN3qkvxG95IqY6UQY2rg HNNcJK+L9oAhUeSJBqjMsfxvBdj8rFX7KzEqVyykRnw2MNCZBfC/pc0zE9C8KAO8Bez1 xYp5jOZd5GFHqGj2KDZuuTbaS7CzQrrI8n1qXVv1bcKzNq/6jgb/2D25Kqd+Z7+6LnMU vV3M9jktCYpyDoGEFQ5D7mV1ZuPTYcTUFOvz0fFG/l0XTRpTHSWW9WivCjI0zgxgy+9t 7ibqPrxmi5SqKMhpzVZcrq4oaZ2RDnnFaSci1WSZ1VFOEgceFRSawx7i4P0DcDKw1MFq TOZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=z3Go5d4RSh2i8I12sVG7jAkKHcBHOgKYDydcZEnVZBQ=; b=NuIca1B21d1FfjpwxDZIm8O62L4PgZJpAXjGG7uFMoY0ljWmuIVH1YOH8KgNkwiebL kKNcVvcchgpGpZPhZ61pUrPe8mAyS09rYtWzFIqFdp3jQxrbKTjpCEcSTdEl4OEfvE6Q BWDt0nSkSrfCYp7I9RC3GxPl1qQX021W2QSxeA7G3j8XmlOK0o07iuVhr+hda539GCh+ xsUFhgs1czFYj61PbHre1GJN57RQ2zGu5GFbBBYki6nXKk5yb0CC5xpkdFAjchw8YDCd Mhh3i79ST2ykFKhEf4OfnknbnwqOGwvB1H6Yik3h6EK8L8f9HrzuEiAsu5+VQ+rewecv w4nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NhP5tFQj; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:26 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:28 +0000 Message-Id: <20180209143937.28866-41-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 40/49] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To find an unused virtual IRQ number Xen uses a scheme to track used virtual IRQs. Implement this interface in the new VGIC to make the Xen core/arch code happy. This is actually somewhat VGIC agnostic, so is mostly a copy of the code from the old VGIC. But it has to live in the VGIC files, so we can't easily reuse the existing implementation. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index b62cda7d2f..3b475ed1a4 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -713,6 +713,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Fri Feb 9 14:39:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127846 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679913ljc; Fri, 9 Feb 2018 06:42:17 -0800 (PST) X-Google-Smtp-Source: AH8x224TCDb/t0JdqDTfSIVhYbc+KqdcNG9J4Wt2tIh48xb2Lc2MtJ/g/n/Debb3UY3ejDTuRB0+ X-Received: by 10.107.9.154 with SMTP id 26mr3273454ioj.52.1518187337132; Fri, 09 Feb 2018 06:42:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187337; cv=none; d=google.com; s=arc-20160816; b=w18Oz/QxlFUm6NxxsFzT8WnBvtl6dbWyYxTu7U0bLspSztyXi3NHFNAKt36vhoxXIC jvU5JItNMJvS4C06ym5hUMSyh3AjBcvByQMvKxuYJD5XZmphBYtcJe2iLCjuD2KMElLp tfZGSRpKgMc4le4th4hwpBTgGN7CR+rL2we0NaiBLSvf4GWJlT9PnG8pbmwwImYSnnm6 4ZdAnvzycAWf/OOFS24tIXcrTq4Vdx9MBkeDO/zDLOe5dJrARQVl2zP+sorjmPTUlbxk aLEAcQv7IwO+DLay+sHMQyakhhA7pYmoMXUxApQVuYMZEk93O1tw6w26oYwaqHnBvhF1 n3bA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Nvyvh/eXGUnm60PsAnB+mmOsgByQk12D2d9AajT+yXA=; b=aeN/qir/8n9ArwwKR/9nHnywueprGAEsP781W7BrBfboRIwOU7o9IelVfx+BKenDTd n2zXyCokCKQ0xFhriAUsx7+Vo2VTb5s4cFKycnXR6o9AJabTIg9BfPteS0sSbHK9uYho rbng6k31tTLpV/MW1laMP3MpY/Hnu8KtnL6qDlNBTsVO7kzGaJ/TPCmZYedT0G4kb9iM voOLFBj8KCbq3zZhMw6DBts4cwyNjvVEuQ5BiNHtZF21xM3sBdi/GPUhqTf3GjaiNaKt Zie2nbwfXmRULxt2N9cPvTJnb/RlNHAghA/iXgstzP/y9pfn8B5/XohVCQOtvfvdCKuG 3Emg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kyAuuI/+; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:27 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:29 +0000 Message-Id: <20180209143937.28866-42-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 41/49] ARM: new VGIC: dump virtual IRQ info X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When we dump guest state on the Xen console, we also print the state of IRQs that are on a VCPU. Add the code to dump the state of an IRQ handled by the new VGIC. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 3b475ed1a4..97ffdba5ad 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -757,6 +757,19 @@ void vgic_free_virq(struct domain *d, unsigned int virq) clear_bit(virq, d->arch.vgic.allocated_irqs); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct vgic_cpu *vgic_cpu = &v->arch.vgic_cpu; + struct vgic_irq *irq; + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + printk(" on CPU: %s %s irq %u: %spending, %sactive, %senabled\n", + irq->hw ? "hardware" : "virtual", + irq->config == VGIC_CONFIG_LEVEL ? "level" : "edge", + irq->intid, irq_is_pending(irq) ? "" : "not ", + irq->active ? "" : "not ", irq->enabled ? "" : "not "); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Fri Feb 9 14:39:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127849 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679965ljc; Fri, 9 Feb 2018 06:42:20 -0800 (PST) X-Google-Smtp-Source: AH8x227lI/pR0R8xCnCgcmi9nQNqBqGFndRmVmnXE5Q2lgCMrRggN3OHKGPKJaQ7zrErHqy+8fqg X-Received: by 10.107.180.146 with SMTP id d140mr3549959iof.166.1518187340807; Fri, 09 Feb 2018 06:42:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187340; cv=none; d=google.com; s=arc-20160816; b=GzhECdkjAibOduhjkdo64VZFYa+wnd1JjbIM13s1iBdYksbfFV5lGPysfbDS6h1xBS T4hmLX2lsK57x8bJUGyC8u7MIHWoRDpui7hjcd1Hmh0ax/XbMbFaiQGmEmDoLrNXeP+j dQWkVEG0PMeRrKVa52XhI/MyJg2uKoI5ihm1oJjDVSMmujW1bJ7u3WWYzYr2UwSiAqOM PDgQb/xE6QoD+yJ1kN1GpD9+Pu/ODBmdQV1ayPdVxpLoagaS4/bXyPT4LuiaXi7hOXWG 5sf/UIa4Efmbi+FtQh33kb9+W9aTeB2XBdG1hjQScvvR79XTynQbhqub57FjuuUdZulR TE7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=6EMdov2SQAXaXGWfUbxItLFx1o2dIVC2LJqVf5YSpP8=; b=MpLz0ZQ8+0hOJZdK0a0jNEjTtb2c+VqXyggcOqPZhi3jBT8v+QQO0jHyswGfvjCPGr rkBheAi87DxowCziac6OuRrVD3uSUBS+XP9DyR3xz3nn5sipA0hQvouPsVD9dANNOhBl zARz0PxeMBUDV60w0zmE82JjG1giHyt1JKLB4lGubTiGVDwalvALILlYY6xyNR2uVcXL p5DsymCCKo6ufgqFEuCJq6OiuazzxESY7pwKlPKrpyaWTcdSZP0QW67FaXn22hoNY8Wo vv9/PDZ3hzGsEZ6C1nSIlRx963V2E8/WclgQPUU1xzKP4M5anLuDBD79UntxqvLh3kiF 2eZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QkD7svwN; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:28 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:30 +0000 Message-Id: <20180209143937.28866-43-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 42/49] ARM: new VGIC: provide system register emulation stub X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen arch code traps system registers writes from the guest and will relay anything GIC related to the VGIC. Since this affects only GICv3 (which we don't yet emulate), provide a stub implementation of vgic_emulate() for now. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 97ffdba5ad..d91028bd43 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -790,6 +790,13 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, return desc; } +bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) +{ + ASSERT(current->domain->arch.vgic.version == GIC_V3); + + return false; +} + /* * was: * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) From patchwork Fri Feb 9 14:39:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127860 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp681152ljc; Fri, 9 Feb 2018 06:43:47 -0800 (PST) X-Google-Smtp-Source: AH8x227yr2ZIZ/KLWrPwUrm8cD9gbL3/1wl5f8XfxmXkR78XwOxJ2s7hTgc65dh/v8eZGo0QUEw8 X-Received: by 10.36.3.17 with SMTP id e17mr3881616ite.41.1518187337124; Fri, 09 Feb 2018 06:42:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187337; cv=none; d=google.com; s=arc-20160816; b=K9tUwBu80wEEvteoERq1ZlJf8UTx5DAkQdv/BWgEtuexHJzJ3lt1T9k3/xf6TdrjqL j413O4ZRopkqLS6KenTEv1ubOEiSdQD2mXNLkAuwWN2iImUMSMFl2N2jjquOLIU+up9a ULCpybDcJVqz6vNz7iq5Frmr++nozckWGu7UT2cMMrv7jSfF7Dqeaq9l09cJVCVxoSBw 35oPeK6UwSDyMyJfsBjyw8f9ge7UEQHiUfskKTepyBdJiUNUCeav8UXmNumC/7T/sMjq wymzOCPjqSw61QvbLmQAuiwGaXj2Bz+Bp0YLHQdvYucdFNs2XdorHH6NDi1kzJ7fjJxg xfDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=V28cUja4gnNh2/0hRVXoEx8ojwIQJFkYMBYyK04y1fM=; b=H4KBUaQtuYyoEIo1hymS9n+AIXooxMYUzokDfYhpmwsMG2yVevEqQzQS12t8OlPftM bmptGv4XL5e924NUlBUSbHgYvW7l4LUr0eYgbosvQFNjFhGaDGwZwrhB5zWWY+3vP1gG lZyixMvk5f8M5N+FNRtyWgxk/RZMjrncPmq3kp1KEZlj0m6Oo/FIWZSmaSF/tchgz7H6 M/D7QaxUSX5Y6SahPCN9Kz74rNwGAPuy8aZ3040hhzZlSM6ffcFHsm7pUcdHYj/bfl9i dfu9DOuC5vodtJu3qG0CZ22miNt3ZRog3mwHcdzAc/JKf4MerYxuCh7oI86CyXoBCGne xXTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A7yAi+2N; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v10si1588639iod.248.2018.02.09.06.42.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=A7yAi+2N; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qr-0001ro-GB; Fri, 09 Feb 2018 14:40:33 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qq-0001mu-B8 for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:32 +0000 X-Inumbo-ID: 1c9cfb62-0da7-11e8-ba59-bc764e045a96 Received: from mail-wm0-x242.google.com (unknown [2a00:1450:400c:c09::242]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 1c9cfb62-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:40:03 +0100 (CET) Received: by mail-wm0-x242.google.com with SMTP id r71so15884885wmd.1 for ; Fri, 09 Feb 2018 06:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=VeMhzqTQZrNPpar0j5t6sZXyIro2XcM77hiX99m3+14=; b=A7yAi+2NdEkTQNkjyq19hsk5rrTCbB8HbYkMR9qtq+h9ugDncz+UHhFuDE9uyAOrvr mQMpoeTgMoMfiYBIIIY8U+d39SL8iiCrOCIQoruQLgE1keoFEIiq+LICI0lqRfC91dui qHLI0YJGjS3oZ+rsP99UN3+gZ6vIEOgEE472g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=VeMhzqTQZrNPpar0j5t6sZXyIro2XcM77hiX99m3+14=; b=LjuBeRjFwCirg3lvgwvXvmIYpwuYwHdLQ5RjBYbN98wmrMeuhhw+he6ux7/PHhNwiv Nj5+DIPI0lJQggFGzIF9UsN02eUZpsUZc5paYzyC69iz9/rI5e3Ah37A15CbsxpBoT8E WizfOVfDuinsEtVgILj6qXXZ/GI2ty4Ym3nQVmCDv4L8JUl/TY+e5jQZusViSUjhOeUg je8bbzWsRVqt6Xr2z0gSY3+r+DXoeDybf3XiEtvzKjO/jBI6wgS+XQot5IvzJ9ZPzJod uJkRMdUq34SK4kh4xlXw7odhytzbsL9aq04k1V2DvP8BvYVJy9j3JjjGJ9jpZzmJlmER bOFg== X-Gm-Message-State: APf1xPBGqeEbJ0mCTxyuUQFjjsRu8OVE0Wy05Bsb9gEMISufRQ9cQ4Gv wzM9NGp8s0c4LipMRpw1Wa1xWg== X-Received: by 10.28.120.15 with SMTP id t15mr2296972wmc.34.1518187230377; Fri, 09 Feb 2018 06:40:30 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:29 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:31 +0000 Message-Id: <20180209143937.28866-44-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 43/49] ARM: new VGIC: Add preliminary stub implementations X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen core code requires an interrupt controller emulation to implement arch_move_irqs(), to move the affinity of an hardware mapped virtual IRQ to another core. In the moment we don't implement this physical-follow-virtual regime in our new VGIC, so just provide an empty stub implementation to make the linker happy. Similarily vgic_clear_pending_irqs() is required by the ARM code, although it is suspected that it is actually not necessary. Go with a stub for now. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index d91028bd43..77fa756329 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -770,6 +770,19 @@ void gic_dump_vgic_info(struct vcpu *v) irq->active ? "" : "not ", irq->enabled ? "" : "not "); } +void vgic_clear_pending_irqs(struct vcpu *v) +{ + /* + * TODO: It is unclear whether we really need this, so we might instead + * remove it on the caller site. + */ +} + +void arch_move_irqs(struct vcpu *v) +{ + /* TODO: implement this (?) */ +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Fri Feb 9 14:39:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127861 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp681167ljc; Fri, 9 Feb 2018 06:43:49 -0800 (PST) X-Google-Smtp-Source: AH8x227voMAtvFTgvnOptrnAo3k9536dPFkmioC8Ei5LQZBFHI22H1sLc4aO1IN3ZwkJykz2TAKm X-Received: by 10.36.19.5 with SMTP id 5mr3617297itz.11.1518187339229; Fri, 09 Feb 2018 06:42:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187339; cv=none; d=google.com; s=arc-20160816; b=YzWkU+cy15pahXayKLPp0LHjQjwfvs13ETEMSgAWQ0f4PMaU75XHv/xq8dChVNJce0 OG/+kPMCGpEvubjuujj8u5KdWEGsNfpciNSV0AG6vBOc9ioNuWD6dlfh2tyb0L6eGXnS 2GXQE3MSnzDIRvCxLpLrGfhnp53IkS5HbLNTGM9U5hRmVDvL6YWIXjENCcutL4o9hDhE QRkWXnjFHNbGt74R1Tui6pk5QMoQSk2dzezjsWp3ryYbeLRF53D5sUaUJfp8LaKE3zx3 6iTogSe/m3cEhh5zgagiIhmLeZ5+SrXl6YlMq43WNWLFMOHeYui0QGu2jCqvz958KPAB 7iyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=X/qNeRka59qF30+NPfA/+rnUImMyOjZmZ28xCCl8CCM=; b=KvS3C+pRxHtrA11egpzPC40o8R21VeI3XDWVR4w6UiTs1kVGCux6CsJwfrP0fuqdkJ dzE+HnFxBQQasB6Urvp8LE0QY3awyX11cnEOlzWQFU9DusERR8V+WCdLK9vl8L4dMQpU IJuEF14rg4YI6NmtoNJXZ4VYveua2usxR/tidt9066JEGqai6kijyPI+sPSIEgjtwYr3 Rz5Dwp/HLkTS/A1KXMfclC/tQSZrhTEE5/PQzoM91TH2EhHrulIzHxCHA/GJSrIKwN09 MKpAjNQjLnM+7eW6TGbK7AOCiMeKY8qebVT1oxTeGcjr1a6n/rdFW1Zx6hEk/z2lxrRG LSPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=M5ILwnlG; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:31 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:32 +0000 Message-Id: <20180209143937.28866-45-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 44/49] ARM: new VGIC: vgic-init: register VGIC X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch implements the function which is called by Xen when it wants to register the virtual GIC. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-init.c | 62 +++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 3 +++ 2 files changed, 65 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-init.c diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c new file mode 100644 index 0000000000..b5f1183a50 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-init.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include "vgic.h" + +/* CREATION */ + +/** + * domain_vgic_register: create a virtual GIC + * @d: domain pointer + * @mmio_count: pointer to add number of required MMIO regions + * + * was: kvm_vgic_create + */ +int domain_vgic_register(struct domain *d, int *mmio_count) +{ + switch ( d->arch.vgic.version ) + { +#ifdef CONFIG_HAS_GICV3 + case GIC_V3: + d->arch.max_vcpus = VGIC_V3_MAX_CPUS; + break; +#endif + case GIC_V2: + d->arch.max_vcpus = VGIC_V2_MAX_CPUS; + break; + } + + if ( d->max_vcpus > d->arch.max_vcpus ) + return -E2BIG; + + d->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index b104f8e964..205ce10ffa 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -20,6 +20,9 @@ #define PRODUCT_ID_KVM 0x4b /* ASCII code K */ #define IMPLEMENTER_ARM 0x43b +#define VGIC_ADDR_UNDEF (-1) +#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) + #define VGIC_PRI_BITS 5 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) From patchwork Fri Feb 9 14:39:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127852 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680061ljc; Fri, 9 Feb 2018 06:42:28 -0800 (PST) X-Google-Smtp-Source: AH8x226SSlOp4p4E35arV/CJNtcPUIDNjwbFCkBZ+8PfVNoQOIpkw0Q335MitpAn+rwkBbSzWWlw X-Received: by 10.36.236.134 with SMTP id g128mr3810840ith.38.1518187348464; Fri, 09 Feb 2018 06:42:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187348; cv=none; d=google.com; s=arc-20160816; b=vMbyiRvSgpWPss6aV0j/piRkArASXgOZR5KGbw+ILjMnsotZeCVAi8w886KgLWP5qf La5iAMS5EZkQBaftGdQZk0tW55ABztCRX+MPPofilbzA1FAsVVV0dSJi307G0mpnhLGD uxVUoyV+w1BVzTH8UxA0R/d+eQ6U2yfex4CVL1OovwK8WqLl2v7B+Hu2mJr/xKBr+C7s wBMrv7iUYfpEbkIWOK0OSJ6zNhCDWU22jrzOzYURFTst8vq3ODYV0ENz5A2+U7aPYjNV bByzB/pMztL7b9xYqolCPKUQjkU/5HPwRsx1Nb7foBdzLTneYqx24TEnJJM6ED6lnoUf zz0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Qi1cz9NUkTTWt+1SptHS7AwCrSvIE/SZTnhNDsAVuic=; b=iw87j8gQpFLKeqF08LBA1q6kbI36IQXM5MelpeEZcmmvFv9mD9tfKa6xIrGxt46Wzq GKSNKQHrMrDRs1o4FrM1Q7WMidGTf3neJWQ5v5KPGLq+H7s8tX59p2ApiCoGaLFDnE6g dRV9on8quJXmiUOaNtJ5nLUBpYSrscx+/dIoo36k77BA7j0P4cHIEL1J24mQ5TG23ep7 dIt1YS3t24iSK09ayotbFWmHFv8f+nVOSgfmJl3tj3GNcpzUQLupQLgpv+4unSF9cf22 BQ0tsHavaLx/SD7tOiKZLhuZbfZGRJwJx/RsyNveCb53MNe6EUJ9Hp2I3LlGo8I+DU83 09zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IDoHgdQB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:32 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:33 +0000 Message-Id: <20180209143937.28866-46-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 45/49] ARM: new VGIC: vgic-init: implement vgic_init X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch allocates and initializes the data structures used to model the vgic distributor and virtual cpu interfaces. At that stage the number of IRQs and number of virtual CPUs is frozen. This is based on Linux commit ad275b8bb1e6, written by Eric Auger. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-init.c | 197 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 197 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c index b5f1183a50..0cd2dfc600 100644 --- a/xen/arch/arm/vgic/vgic-init.c +++ b/xen/arch/arm/vgic/vgic-init.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -19,6 +20,77 @@ #include "vgic.h" +/* + * Initialization rules: there are multiple stages to the vgic + * initialization, both for the distributor and the CPU interfaces. The basic + * idea is that even though the VGIC is not functional or not requested from + * user space, the critical path of the run loop can still call VGIC functions + * that just won't do anything, without them having to check additional + * initialization flags to ensure they don't look at uninitialized data + * structures. + * + * Distributor: + * + * - vgic_early_init(): initialization of static data that doesn't + * depend on any sizing information or emulation type. No allocation + * is allowed there. + * + * - vgic_init(): allocation and initialization of the generic data + * structures that depend on sizing information (number of CPUs, + * number of interrupts). Also initializes the vcpu specific data + * structures. Can be executed lazily for GICv2. + * + * CPU Interface: + * + * - kvm_vgic_vcpu_early_init(): initialization of static data that + * doesn't depend on any sizing information or emulation type. No + * allocation is allowed there. + */ + +/** + * vgic_vcpu_early_init() - Initialize static VGIC VCPU data structures + * @vcpu: The VCPU whose VGIC data structures whould be initialized + * + * Only do initialization, but do not actually enable the VGIC CPU interface + * yet. + */ +static void vgic_vcpu_early_init(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + int i; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + spin_lock_init(&vgic_cpu->ap_list_lock); + + /* + * Enable and configure all SGIs to be edge-triggered and + * configure all PPIs as level-triggered. + */ + for ( i = 0; i < VGIC_NR_PRIVATE_IRQS; i++ ) + { + struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; + + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->intid = i; + irq->vcpu = NULL; + irq->target_vcpu = vcpu; + irq->targets = 1U << vcpu->vcpu_id; + atomic_set(&irq->refcount, 0); + if ( vgic_irq_is_sgi(i) ) + { + /* SGIs */ + irq->enabled = 1; + irq->config = VGIC_CONFIG_EDGE; + } + else + { + /* PPIs */ + irq->config = VGIC_CONFIG_LEVEL; + } + } +} + /* CREATION */ /** @@ -52,6 +124,131 @@ int domain_vgic_register(struct domain *d, int *mmio_count) return 0; } +/* INIT/DESTROY */ + +/** + * domain_vgic_init: initialize the dist data structures + * @d: domain pointer + * @nr_spis: number of SPIs + */ +int domain_vgic_init(struct domain *d, unsigned int nr_spis) +{ + struct vgic_dist *dist = &d->arch.vgic; + int i, ret; + + /* Limit the number of virtual SPIs supported to (1020 - 32) = 988 */ + if ( nr_spis > (1020 - NR_LOCAL_IRQS) ) + return -EINVAL; + + dist->nr_spis = nr_spis; + dist->spis = xzalloc_array(struct vgic_irq, nr_spis); + if ( !dist->spis ) + return -ENOMEM; + + /* + * In the following code we do not take the irq struct lock since + * no other action on irq structs can happen while the VGIC is + * not initialized yet: + * If someone wants to inject an interrupt or does a MMIO access, we + * require prior initialization in case of a virtual GICv3 or trigger + * initialization when using a virtual GICv2. + */ + for ( i = 0; i < nr_spis; i++ ) + { + struct vgic_irq *irq = &dist->spis[i]; + + irq->intid = i + VGIC_NR_PRIVATE_IRQS; + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->vcpu = NULL; + irq->target_vcpu = NULL; + atomic_set(&irq->refcount, 0); + if ( dist->version == GIC_V2 ) + irq->targets = 0; + else + irq->mpidr = 0; + } + + INIT_LIST_HEAD(&dist->lpi_list_head); + spin_lock_init(&dist->lpi_list_lock); + + if ( dist->version == GIC_V2 ) + ret = vgic_v2_map_resources(d); + else + ret = -ENXIO; + + if ( ret ) + return ret; + + /* allocated_irqs() is used by Xen to find available vIRQs */ + d->arch.vgic.allocated_irqs = + xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d))); + if ( !d->arch.vgic.allocated_irqs ) + return -ENOMEM; + + /* vIRQ0-15 (SGIs) are reserved */ + for ( i = 0; i < NR_GIC_SGI; i++ ) + set_bit(i, d->arch.vgic.allocated_irqs); + + return 0; +} + +/** + * vcpu_vgic_init() - Register VCPU-specific KVM iodevs + * was: kvm_vgic_vcpu_init() + * Xen: adding vgic_vx_enable() call + * @vcpu: pointer to the VCPU being created and initialized + */ +int vcpu_vgic_init(struct vcpu *vcpu) +{ + int ret = 0; + + vgic_vcpu_early_init(vcpu); + + if ( gic_hw_version() == GIC_V2 ) + vgic_v2_enable(vcpu); + else + ret = -ENXIO; + + return ret; +} + +void domain_vgic_free(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + int i, ret; + + for ( i = 0; i < dist->nr_spis; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(d, NULL, 32 + i); + + if ( !irq->hw ) + continue; + + ret = release_guest_irq(d, irq->hwintid); + if ( ret ) + dprintk(XENLOG_G_WARNING, + "d%u: Failed to release virq %u ret = %d\n", + d->domain_id, 32 + i, ret); + } + + dist->ready = false; + dist->initialized = false; + + xfree(dist->spis); + xfree(dist->allocated_irqs); + dist->nr_spis = 0; +} + +int vcpu_vgic_free(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + + return 0; +} + /* * Local variables: * mode: C From patchwork Fri Feb 9 14:39:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127854 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680090ljc; 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[192.237.175.120]) by mx.google.com with ESMTPS id v11si1622293itf.94.2018.02.09.06.42.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XO6mS0f+; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qw-0002CE-PW; Fri, 09 Feb 2018 14:40:38 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qv-000279-Iw for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:37 +0000 X-Inumbo-ID: 1ea3aa9f-0da7-11e8-ba59-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 1ea3aa9f-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:40:06 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id g1so15784855wmg.2 for ; Fri, 09 Feb 2018 06:40:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=rWYP3bJJQnf1syaBdarbmjRBmnA3VhYwNl74VtTc5Sg=; b=XO6mS0f+Ex2UWMKTZfGRgiCZTKnmSm5R2urPQeg56wvVkEaSsC3RU0z7QmsmHD4imR +3T0CE1kDF/tsK4qvJW5kGncKzCbRIPiWUX20Wy+KLHtIK43aQTmZ6jc5O5QQw/zC6jZ d3FAQEgSFyA7Dms4BHAGn/3/HV2xQP5/LnOlc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=rWYP3bJJQnf1syaBdarbmjRBmnA3VhYwNl74VtTc5Sg=; b=jjGhRZHPzZn+y0MrgwbKfQ9WiQL7C3y7/V0pqHooeVldx8yXN2/xv4Am8m5lmkMo92 j0QPCWI88G3rPZqKWXIitUP334MduATEAqknMwBQZuVAUD2qZA3HcKisJCLxclOWdMN4 HsH3lcYZk2crZuPUnT7e6HmHwKpmrtangZZ4M14nJ9lTRhQpzbBt75iVbpW0n9GKeWun YETMBKncw4VTmRfgqZqUeDby5tmUZ+TNUfvkKfzR+dveLqmbHH+CLqpDmAlk+jWC11b0 0qEenYssws62VAZ3UCuTCuyHbAfRVUuzcI59mZdOG9Apu4FQWNICmUylBtWBwlHftcTl 6Iqw== X-Gm-Message-State: APf1xPBgvrfNqBgz+s1TADqhELIODh+0FIcg2jHaX/2o/b3XZ5v5RW/l NLPc+YZYNhQYlYjo/zvIeoy13jc5ung= X-Received: by 10.28.158.77 with SMTP id h74mr2141903wme.38.1518187233622; Fri, 09 Feb 2018 06:40:33 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:33 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:34 +0000 Message-Id: <20180209143937.28866-47-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 46/49] ARM: new VGIC: vgic-init: implement map_resources X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" map_resources is the last initialization step needed before the first VCPU is run. At that stage the code stores the MMIO base addresses used. Also it registers the respective register frames with the MMIO framework. This is based on Linux commit cbae53e663ea, written by Eric Auger. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-v2.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 66 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index 10fc467ffa..b5026bb050 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -202,6 +202,71 @@ void vgic_v2_clear_lr(struct vcpu *vcpu, int lr) vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0; } +int vgic_v2_map_resources(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + paddr_t cbase, csize; + paddr_t vbase; + int ret; + + /* + * The hardware domain gets the hardware address. + * Guests get the virtual platform layout. + */ + if ( is_hardware_domain(d) ) + { + d->arch.vgic.vgic_dist_base = gic_v2_hw_data.dbase; + /* + * For the hardware domain, we always map the whole HW CPU + * interface region in order to match the device tree (the "reg" + * properties is copied as it is). + * Note that we assume the size of the CPU interface is always + * aligned to PAGE_SIZE. + */ + cbase = gic_v2_hw_data.cbase; /* was: dist->vgic_cpu_base */ + csize = gic_v2_hw_data.csize; + vbase = gic_v2_hw_data.vbase; /* was: kvm_vgic_global_state.vcpu_base */ + } + else + { + d->arch.vgic.vgic_dist_base = GUEST_GICD_BASE; + /* + * The CPU interface exposed to the guest is always 8kB. We may + * need to add an offset to the virtual CPU interface base + * address when in the GIC is aliased to get a 8kB contiguous + * region. + */ + BUILD_BUG_ON(GUEST_GICC_SIZE != SZ_8K); + cbase = GUEST_GICC_BASE; + csize = GUEST_GICC_SIZE; + vbase = gic_v2_hw_data.vbase + gic_v2_hw_data.aliased_offset; + } + + + ret = vgic_register_dist_iodev(d, dist->vgic_dist_base, VGIC_V2); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to register VGIC MMIO regions\n"); + return ret; + } + + /* + * Map the gic virtual cpu interface in the gic cpu interface + * region of the guest. + */ + ret = map_mmio_regions(d, gaddr_to_gfn(cbase), csize / PAGE_SIZE, + maddr_to_mfn(vbase)); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to remap VGIC CPU to VCPU\n"); + return ret; + } + + dist->ready = true; + + return 0; +} + static void save_lrs(struct vcpu *vcpu, void __iomem *base) { struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2; diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 205ce10ffa..adb04f2f52 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -58,6 +58,7 @@ void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_clear_lr(struct vcpu *vcpu, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +int vgic_v2_map_resources(struct domain *d); int vgic_register_dist_iodev(struct domain *d, paddr_t dist_base_address, enum vgic_type); From patchwork Fri Feb 9 14:39:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127856 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680137ljc; Fri, 9 Feb 2018 06:42:34 -0800 (PST) X-Google-Smtp-Source: AH8x2277jLnQylKcsFY1bidX8n27VuqUDQzwcddeAm/BW/7Jeq79dxVKC8r8EuJIcsX0cnxsImHX X-Received: by 10.36.239.130 with SMTP id i124mr3755677ith.27.1518187354611; Fri, 09 Feb 2018 06:42:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187354; cv=none; d=google.com; s=arc-20160816; b=D7nyxGhVOaCVnneM7EGxzJ1uu3Bwi57cNxtkDyR/2aMY3mh7oeC9xP3do2TDKvUV7j manip/w39fNVt36Ot9QmEO9UMjsWba83l/FbFsAS/x9udqjP0T4OjQwmUjHfr+G2Lpm/ 9qqu8vgsfVDCvkla5sZhW8sqxmiBahHWuLM8MCq+sMnZJnpMDIPdssApKUDexG1z7NIw YJbq/5MugFXMQ0aaoZgniptufrfRLUfqeOZek06i45va+dlmYP88Gym8g44gP1QHDBbT 7FQMr9fhNe/WmR2AgdXME+L79hSqZbypOtddNnYygVy9IJ6Wmd3rsCdidu/HiSsmeNcz 0qPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=M1sEy5GP2+knfPN0e74FZYLnKUFpk7jEFI6K4xl9/gA=; b=0UZ4uF3oaP8vimeQjrUQLC2XGmNSkAvBJ35N62abBghfYJOOJyMiw4xV6HBuigH0rA BMGJzu8MHzN8H0rQ9nau5ePKLnpy0kyVs2m0FYDd/vZjKbxgvUtii/4nfBBG20q7XKZj pQYJE3heVJowkn+r1jonrkHz39xNGdrDnGXdllMfi7GejnTf/rnbVzqvL/kFsFAHxLxK OSeSRlp3J9zsFRrNLvSUBfArl2j63krvLoNsU0Ea92UslqxeGWXYGtRReNg9sJeHxEtJ CmO17jNMVB6oo6BJD/G8MCcb2aNtkQJOCdOsWOIw41rd4XrzQx+J/0NI/eWOTvKO49hj SEZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=EbNTa69P; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:34 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:35 +0000 Message-Id: <20180209143937.28866-48-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 47/49] ARM: new VGIC: Add vgic_v2_enable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. This is based on Linux commit f7b6985cc3d0, written by Eric Auger. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-v2.c | 13 +++++++++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 14 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index b5026bb050..16e9c8dbf0 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -202,6 +202,19 @@ void vgic_v2_clear_lr(struct vcpu *vcpu, int lr) vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0; } +void vgic_v2_enable(struct vcpu *vcpu) +{ + /* + * By forcing VMCR to zero, the GIC will restore the binary + * points to their reset values. Anything else resets to zero + * anyway. + */ + vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0; + + /* Get the show on the road... */ + vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN; +} + int vgic_v2_map_resources(struct domain *d) { struct vgic_dist *dist = &d->arch.vgic; diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index adb04f2f52..e28c002a9e 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -58,6 +58,7 @@ void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_clear_lr(struct vcpu *vcpu, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +void vgic_v2_enable(struct vcpu *vcpu); int vgic_v2_map_resources(struct domain *d); int vgic_register_dist_iodev(struct domain *d, paddr_t dist_base_address, enum vgic_type); From patchwork Fri Feb 9 14:39:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127833 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679744ljc; Fri, 9 Feb 2018 06:42:07 -0800 (PST) X-Google-Smtp-Source: AH8x224OxkqBU9k0x0t4b3szuOWAu2GAycLhNJVPUGUbg0vBUjqj2yZhhvGNMs5zdCYnR34SbIGr X-Received: by 10.36.13.5 with SMTP id 5mr3715821itx.68.1518187327112; Fri, 09 Feb 2018 06:42:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187327; cv=none; d=google.com; s=arc-20160816; b=W1CEY0gM1+97lAXkmxXcMwpc+4df3bJJKThstVk0RqHLwRIDr1ZpqatLLSxOmH4l1i +eWoKxBATUEHwRp6I/mWhbMrcIjjgIcRY5ZpYH4UpvILsoUDtTkcL1W+M6/pOP7CCod1 irmpdlc52NE1A/iTAuiIysL0cKRe6z0iRRYIEaP5Eo8eI0cdLVleQ+2v3gxFdBWSlhq9 RssbdudDJ75GBl9NO+QUIaY3BMRVG2wibHIHed3WwrKE5b8c0yiZcWz7y5Rk4xCXmydQ 9oT+ufO/2hTNuNQHy43v1WkAcE+HXD+RUdKjTXd7UdzqYldjtoH4hqlm5sJtE1Wj/xRv VWaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=pJAuWXq1KUZ+5VMQUb7aEmSdFwIPcQBKGZ1i0lSw9k8=; b=NMBq6r+tGQ1RhlDvtGpshNyncjNKqGgXBv2LIdThTAtOdTEuzFiUotxfuB0mBFqH6N gFBrpFvsPICpVGeVL1uNbiVGqNr8YxDLUzhRZE7zI3WVfrm7xihmehHqhHykQrpVu1og X2BYRsZQq7txuKfaAso3mXemmqLJH78Sf3621khPNcmh1FdhOfoG6SKxvilKJWyqNNa+ IYXwtH9l8JX4aDODm2ATmSUSQI5NU2mxLAoRs3L71idljNHxFcKH4n6A464Kr28ut78z p9JEWvnX7xZn4X/stfNDfs2fNExZbiCCLE0z302ZOcl+5pZ4Shv6rSwrFp7HU8piSV1+ Od3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=kTYgMy2l; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:35 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:36 +0000 Message-Id: <20180209143937.28866-49-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 48/49] ARM: allocate two pages for struct vcpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we allocate exactly one page for struct vcpu on ARM, also have a check in place to prevent it growing beyond 4KB. As the struct includes the state of all 32 private (per-VCPU) interrupts, we are at 3840 bytes on arm64 at the moment already. Growing the per-IRQ VGIC structure even slightly makes the VCPU quickly exceed the 4K limit. The new VGIC will need more space per virtual IRQ. I spent a few hours trying to trim this down, but couldn't get it below 4KB, even with the nasty hacks piling up to save some bytes here and there. It turns out that beyond efficiency, maybe, there is no real technical reason this struct has to fit in one page, so lifting the limit to two pages seems like the most pragmatic solution. Signed-off-by: Andre Przywara --- xen/arch/arm/domain.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 87bd493924..4dd34393f1 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -502,10 +502,13 @@ void dump_pageframe_info(struct domain *d) struct vcpu *alloc_vcpu_struct(void) { struct vcpu *v; - BUILD_BUG_ON(sizeof(*v) > PAGE_SIZE); - v = alloc_xenheap_pages(0, 0); - if ( v != NULL ) + + BUILD_BUG_ON(sizeof(*v) > 2 * PAGE_SIZE); + v = alloc_xenheap_pages(1, 0); + if ( v != NULL ) { clear_page(v); + clear_page((void *)v + PAGE_SIZE); + } return v; } From patchwork Fri Feb 9 14:39:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127859 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp680114ljc; Fri, 9 Feb 2018 06:42:32 -0800 (PST) X-Google-Smtp-Source: AH8x224ZzrI/qeJsyQP+uiGWZIvlc1HbIxO5oo5734QKXq35V3XZxDst7TMlHPLIxY2SbPGkGscw X-Received: by 10.36.47.78 with SMTP id j75mr3640087itj.129.1518187352643; Fri, 09 Feb 2018 06:42:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187352; cv=none; d=google.com; s=arc-20160816; b=XTFpXMrpRiOwgn1Nlk33GTMW9oarkYnByg8wMlwWdvGKxuKKhjAJ4gDYhxUJI3wWCt KiDYy280YhLqFcH/HlUPMZcUyMQsOdn1x9Uh1HpRRZF1nWoAg5pLXdwa9KvJ8vwgykv2 Oe/RldDViqa68QD3xLBJqH+HVs0SmchvULv5SUhK3oChnYpXXsejuqv8fUJU+Q7jj/xA yHAvVxa3zE3nyO/F/WNc9p3oi/+OlerbkSFyOCyF2ZLz3A4jWttKXu/hGkHWEl4ZW0FM ffHIgstTaFg/kS9qvzBTag/C38vw7zhF8LUZXpt0KiQwiD3Xy7xJvR9jAsll/1fvdqrP Fqzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=EgzE8yBf7IzXJ/oFx/y7YxbOd2+2aNJROSOHJZIbkdo=; b=ifbLKpFaoD1R95Tz6lPNjCul7lk0TL1NnNujlJa0AMqC4l6MvSFGOYDn5VUHD3r7A9 daQ8xcDppp7QrZmucekkBRDfiCI5Ge9w1gZgJB4tQiz4/ImBdxoW9EeOFWSxNPb3s+/N HKGkq15YjBmcZxPHhfyJcBi/zWsVA1EoTG2CzJOGPwYo2k9ATut+bTnrxlBVsqM3oWTp oGWjllhtWa3UXnyDWpx+cupRsWBZVq7lBFArhMn3OiRMAzgZt5IgTch9whFIoB1Gisgn 8GXuAo3p3V97SThle/I8UtDQeyjHO9tB82NpMb0Q1PCd/pWkdoISHURPSVMP2R+77Ygr sjhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Nu/JYKwj; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:36 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:37 +0000 Message-Id: <20180209143937.28866-50-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 49/49] ARM: VGIC: wire new VGIC(-v2) files into Xen build system X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we have both the old VGIC prepared to cope with a sibling and the code for the new VGIC in place, lets add a Kconfig option to enable the new code and wire it into the Xen build system. This will add a compile time option to use either the "old" or the "new" VGIC. In the moment this is restricted to a vGIC-v2. To make the build system happy, we provide a temporary dummy implementation of vgic_v3_setup_hw() to allow building for now. Signed-off-by: Andre Przywara --- xen/arch/arm/Kconfig | 6 +++++- xen/arch/arm/Makefile | 10 +++++++++- xen/arch/arm/vgic/vgic.c | 8 ++++++++ xen/common/Makefile | 1 + 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2782ee6589..aad19927ce 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -48,7 +48,11 @@ config HAS_GICV3 config HAS_ITS bool prompt "GICv3 ITS MSI controller support" if EXPERT = "y" - depends on HAS_GICV3 + depends on HAS_GICV3 && !NEW_VGIC + +config NEW_VGIC + bool + prompt "Use new VGIC implementation" config SBSA_VUART_CONSOLE bool "Emulated SBSA UART console support" diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 41d7366527..2a3ec94a18 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,7 +16,6 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o -obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o @@ -47,10 +46,19 @@ obj-y += sysctl.o obj-y += time.o obj-y += traps.o obj-y += vcpreg.o +ifeq ($(CONFIG_NEW_VGIC),y) +obj-y += vgic/vgic.o +obj-y += vgic/vgic-v2.o +obj-y += vgic/vgic-mmio.o +obj-y += vgic/vgic-mmio-v2.o +obj-y += vgic/vgic-init.o +else +obj-y += gic-vgic.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o obj-$(CONFIG_HAS_ITS) += vgic-v3-its.o +endif obj-y += vm_event.o obj-y += vtimer.o obj-$(CONFIG_SBSA_VUART_CONSOLE) += vpl011.o diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 77fa756329..690ae892e0 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -853,6 +853,14 @@ int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, return ret; } +void vgic_v3_setup_hw(paddr_t dbase, + unsigned int nr_rdist_regions, + const struct rdist_region *regions, + unsigned int intid_bits) +{ + /* Dummy implementation to allow building without actual vGICv3 support. */ +} + /* * Local variables: * mode: C diff --git a/xen/common/Makefile b/xen/common/Makefile index 3a349f478b..92a1d1fa58 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -19,6 +19,7 @@ obj-y += keyhandler.o obj-$(CONFIG_KEXEC) += kexec.o obj-$(CONFIG_KEXEC) += kimage.o obj-y += lib.o +obj-$(CONFIG_NEW_VGIC) += list_sort.o obj-$(CONFIG_LIVEPATCH) += livepatch.o livepatch_elf.o obj-y += lzo.o obj-$(CONFIG_HAS_MEM_ACCESS) += mem_access.o